CN1117395C - 半导体组件的制造方法及半导体组件 - Google Patents
半导体组件的制造方法及半导体组件 Download PDFInfo
- Publication number
- CN1117395C CN1117395C CN95192144A CN95192144A CN1117395C CN 1117395 C CN1117395 C CN 1117395C CN 95192144 A CN95192144 A CN 95192144A CN 95192144 A CN95192144 A CN 95192144A CN 1117395 C CN1117395 C CN 1117395C
- Authority
- CN
- China
- Prior art keywords
- distribution
- semiconductor element
- supporter
- semiconductor
- external connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 290
- 238000004519 manufacturing process Methods 0.000 title claims description 84
- 239000000758 substrate Substances 0.000 claims abstract description 65
- 238000007789 sealing Methods 0.000 claims abstract description 18
- 238000009826 distribution Methods 0.000 claims description 198
- 238000000034 method Methods 0.000 claims description 102
- 229910052751 metal Inorganic materials 0.000 claims description 49
- 239000002184 metal Substances 0.000 claims description 49
- 239000000463 material Substances 0.000 claims description 35
- 229920005989 resin Polymers 0.000 claims description 25
- 239000011347 resin Substances 0.000 claims description 25
- 230000008569 process Effects 0.000 claims description 23
- 239000003518 caustics Substances 0.000 claims description 19
- 241000283216 Phocidae Species 0.000 claims description 17
- 230000015572 biosynthetic process Effects 0.000 claims description 13
- 238000009413 insulation Methods 0.000 claims description 10
- 230000004888 barrier function Effects 0.000 claims description 7
- 238000003466 welding Methods 0.000 claims description 6
- 238000010023 transfer printing Methods 0.000 claims description 4
- 241001671982 Pusa caspica Species 0.000 claims description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 153
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 abstract description 145
- 239000011889 copper foil Substances 0.000 abstract description 107
- 229910052759 nickel Inorganic materials 0.000 abstract description 72
- 229910000679 solder Inorganic materials 0.000 abstract description 49
- 229920000647 polyepoxide Polymers 0.000 abstract description 25
- 239000003822 epoxy resin Substances 0.000 abstract description 24
- 230000010354 integration Effects 0.000 abstract description 2
- 239000003513 alkali Substances 0.000 abstract 1
- 229920001721 polyimide Polymers 0.000 description 60
- 239000011241 protective layer Substances 0.000 description 51
- 238000009740 moulding (composite fabrication) Methods 0.000 description 47
- 229910052802 copper Inorganic materials 0.000 description 46
- 239000010949 copper Substances 0.000 description 46
- 239000004642 Polyimide Substances 0.000 description 37
- 230000007797 corrosion Effects 0.000 description 34
- 238000005260 corrosion Methods 0.000 description 34
- 239000010410 layer Substances 0.000 description 34
- 230000005540 biological transmission Effects 0.000 description 25
- 238000007747 plating Methods 0.000 description 24
- 239000000243 solution Substances 0.000 description 23
- 238000005253 cladding Methods 0.000 description 22
- 238000003475 lamination Methods 0.000 description 21
- 238000012545 processing Methods 0.000 description 20
- 238000011161 development Methods 0.000 description 19
- 239000011248 coating agent Substances 0.000 description 18
- 238000000576 coating method Methods 0.000 description 18
- 239000007788 liquid Substances 0.000 description 17
- 238000005516 engineering process Methods 0.000 description 16
- 229910052737 gold Inorganic materials 0.000 description 14
- 239000010931 gold Substances 0.000 description 14
- 239000000853 adhesive Substances 0.000 description 13
- 230000001070 adhesive effect Effects 0.000 description 13
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 13
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 11
- 238000009713 electroplating Methods 0.000 description 11
- 238000004080 punching Methods 0.000 description 11
- 229910000365 copper sulfate Inorganic materials 0.000 description 10
- 239000003566 sealing material Substances 0.000 description 10
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 9
- 238000002788 crimping Methods 0.000 description 9
- 238000007639 printing Methods 0.000 description 9
- 239000010935 stainless steel Substances 0.000 description 9
- 229910001220 stainless steel Inorganic materials 0.000 description 9
- 229910052718 tin Inorganic materials 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 239000004020 conductor Substances 0.000 description 8
- 230000008878 coupling Effects 0.000 description 8
- 238000010168 coupling process Methods 0.000 description 8
- 238000005859 coupling reaction Methods 0.000 description 8
- 238000004090 dissolution Methods 0.000 description 8
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 6
- 238000005520 cutting process Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 239000011888 foil Substances 0.000 description 6
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 5
- 239000002131 composite material Substances 0.000 description 5
- 230000009477 glass transition Effects 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 5
- 238000003672 processing method Methods 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 239000007767 bonding agent Substances 0.000 description 4
- 238000009434 installation Methods 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- OFNHPGDEEMZPFG-UHFFFAOYSA-N phosphanylidynenickel Chemical compound [P].[Ni] OFNHPGDEEMZPFG-UHFFFAOYSA-N 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- 239000001569 carbon dioxide Substances 0.000 description 3
- 229910002092 carbon dioxide Inorganic materials 0.000 description 3
- 229920001971 elastomer Polymers 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 241000218202 Coptis Species 0.000 description 2
- 235000002991 Coptis groenlandica Nutrition 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000001351 cycling effect Effects 0.000 description 2
- 238000000280 densification Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000806 elastomer Substances 0.000 description 2
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 229910000906 Bronze Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 239000010974 bronze Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000005266 casting Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- BCAARMUWIRURQS-UHFFFAOYSA-N dicalcium;oxocalcium;silicate Chemical compound [Ca+2].[Ca+2].[Ca]=O.[O-][Si]([O-])([O-])[O-] BCAARMUWIRURQS-UHFFFAOYSA-N 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 125000003700 epoxy group Chemical group 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- -1 nickel Chemical class 0.000 description 1
- 150000002815 nickel Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920005575 poly(amic acid) Polymers 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 238000011536 re-plating Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 239000003351 stiffener Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/4985—Flexible insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68377—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29339—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
- H01L2224/32057—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/325—Material
- H01L2224/32501—Material at the bonding interface
- H01L2224/32503—Material at the bonding interface comprising an intermetallic compound
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
- H01L2224/8381—Soldering or alloying involving forming an intermetallic compound at the bonding interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01027—Cobalt [Co]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/0665—Epoxy resin
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
- H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15182—Fan-in arrangement of the internal vias
- H01L2924/15183—Fan-in arrangement of the internal vias in a single layer of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15182—Fan-in arrangement of the internal vias
- H01L2924/15184—Fan-in arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/203—Ultrasonic frequency ranges, i.e. KHz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
本发明提供一种能适应半导体高度集成化的半导体组件基片。在电解铜箔上镀镍层,形成配线,在铜箔上装配LSI芯片,由引线连接LSI端子与配线,并采用环氧树脂密封半导体。用碱腐蚀方法溶解只除去铜箔,露出镍层,在对铜溶解性小的镍剥离液中除去镍层,使配线露出。涂敷焊料保护层,设置图形并使连接端子露出,在该配线露出处溶融配置焊料球,通过焊料球与外部配线板连接。
Description
技术领域
本发明涉及一种半导体组件的制造方法及半导体组件。
背景技术
随着半导体集成化的提高,输入输出端子数目正在增加。从而需要具有许多输入输出端子的半导体组件。通常,输入输出端子有两种形式:一种是组件周围一列配置,另一种是不仅在周围而且布至组件内部的多列配置。QFP(Qund Flat Package)是前者的代表,当要使其实现多端子化时,必须缩小端子间距。然而当间距小于0.5mm时,在与配线板的连接方面需要很复杂的技术。作为后者的阵列式有可能以比较大的间距配置端子,故适合于多针化。
以往,作为阵列式配置,通常是拥有连接针的PGA(Pin Grid Array),但其与配线板的连接为插入型,不适合于表面安装。于是,人们正在开发一种可表面安装的、被称为BGA(Ball Grid Array)的半导体组件。作为BGA的类型有:(1)陶瓷型、(2)印刷电路板型及(3)使用TAB(tapeautomated bonding)的条型。这当中,若与过去的PGA相比,陶瓷型的母板与组件的距离变短,从而出现因母板与组件间的热应力差而造成的组件翅曲这一严重问题。另外,在印刷电路板型中也存在基片翅曲、耐湿性、可靠性以及基片过厚等问题。故而人们正提出可应用TAB技术的条型BGA。
作为与组件尺寸更加小型化相适应的一种技术,人们提出了一种与半导体芯片几乎同等大小的、所谓的芯片尺度组件(CSP:Chip Sizepackage)。这是一种不是在半导体芯片周围、而是在其安装区域内拥有可连接外部配线基片的连接部件的半导体组件。
作为具体的例子有以下两种:将凸出的聚酰亚胺膜与半导体芯片表面粘接,通过金属引线和芯片相接,然后浇注环氧树脂等进行密封(NIKKEIMATERIALS & TECHNOLOGY 94.4,N0.140,P18-19);在临时基片上、相当于与半导体芯片及外部配线基片连接部位置,设置金属凸块,将半导体芯片倒焊后,用该临时基片自动传送模制而成(Smallest F1ip-Chip-LivePackage CSP;The Second VLSI Package Workshop of Japan,P46-50,1994)。
另外,如前所述,在BGA和CSP领域,人们正在研究开发一种利用聚酰亚胺带作为基片的组件。这种情况下,作为聚酰亚胺带,通常是通过粘接料层使铜箔与聚酰亚胺带作成层压板,但从耐热和耐湿性的角度出发,人们更希望在铜箔上直接形成聚酰亚胺层,即所谓的双层片状基材。双层片状基材的制造方法大致可分为以下两种:①在铜箔上涂敷聚酰亚胺的前体聚酰胺酸后使其垫固;②利用真空成膜法和无电镀法,在固化了的聚酰亚胺膜上形成金属薄膜。若采用激光加工技术除去所需部分(相当于第2连接功能部)的聚酰亚胺除去,而形成抵达铜箔的凹部时,最好使聚酰亚胺膜尽量地薄。反之,若将双层片状基材加工处理成引线框架状时,如膜厚度过薄,则会出现缺乏操作性及框架的刚性。
如上所述,作为能适应小型化、高集成化发展的半导体组件,正提出种种方案,但人们期待着更进一步的改进,以满足性能、特性及生产等全方位的要求。
本发明提供一种半导体组件的制造方法及半导体组件,它可生产性能良好、安全稳定地制造能适应小型化、高集成化发展的半导体组件。
发明内容
本申请的第一发明为一种半导体组件的制造方法,其特征在于,该制造方法包括步骤:
A.在导电性临时支撑体的单面设置配线;
B.在设置配线的导电性临时支撑体上已设置配线的一面,形成绝缘性支撑体;
C.除去导电性临时支撑体,将配线转印至绝缘支撑体;
D.除去预设置配线外部连接端子处的绝缘性支撑体,并设置外部连接端子所用透孔;
E.在转印有配线的绝缘性支撑体上装配半导体元件,接通半导体元件端子与配线;
G.用树脂密封半导体元件;
H.在外部连接端子所用透孔中接通配线,形成外部连接端子。
在第一发明中,可以依A-H的顺序进行,也可将D工艺放在B前进行。例如,B的工艺过程也可用下述工艺进行,即将预先设有外部连接端子所用透孔的绝缘膜绝缘性支撑体与已设置配线的导电性临时支撑体设有配线的一面相粘合。
本申请的第二发明为一种半导体组件制造方法,其特征在于,该制造方法包括步骤:
A.在导电性临时支撑体的单面设置配线;
B.在已设有配线的导电性临时支撑体上装配半导体元件,接通半导体元件端子与配线;
C.用树脂密封半导体元件;
D.在导电性临时支撑体的、与装有半导体元件相对应的另一面上预设置配线的外部连接端子处,设置形成与导电性临时支撑体清除条件不同的金属图形。
E.除去已形成金属图形以外的导电性临时支撑体。
作为金属图形,最好是焊锡,也可以是在镍层上面加上金层。
本申请的第三发明为一种半导体组件的制造方法,其特征在于,该制造方法包括步骤:
A.在绝缘性支撑体的单面设置多组配线;
B.除去预设置配线外部连接端子处的绝缘性支撑体,并设置外部连接端子所用透孔;
C.在已设置多组配线的绝缘性支撑体上装配半导体元件,用焊线接通半导体元件端子与配线;
D.用树脂密封半导体元件;
E.在外部连接端子所用透孔中接通配线,形成外部连接端子;
F.分离每个半导体组件;
所述外部连接端子设置在所述配线上与所述半导体元件端子接通的位置的内侧。
在第三发明中,制造工序最好是依A-F顺序进行,但也可将B放在5前进行。即可以在设有外部连接端子所用透孔的绝缘性支撑体上设置多组配线。
本申请的第四发明为一种半导体组件的制造方法,其特征在于,该制造方法包括步骤:
A.除去预设置配线外部连接端子处的绝缘性支撑体,并设置外部连接端子所用透孔;
B.在绝缘性支撑体的单面设置多组配线;
C.在已设置多组配线的绝缘性支撑体上装配半导体元件,用焊线接通半导体元件端子与配线;
D.用树脂密封半导体元件;
E.在外部连接端子所用透孔中接通配线,形成外部连接端子;
F.分离每个半导体组件;
所述外部连接端子设置在所述配线上与所述半导体元件端子接通的位置的内侧。
作为金属图形,最好是焊锡,也可以是在镍层上面加上金层。
本申请的第五发明为一种半导体组件的制造方法,其特征在于,该制造方法包括步骤:
A.在导电性临时支撑体的单面设置多组配线;
B.为使配置在导电性临时支撑体上多组配线达到所定的单元个数,切断分离导电性临时支撑体,并将设有配线的、已分离的导电性临时支撑体固定在框架;
C.在设有配线的导电性临时支撑体上装配半导体元件,并接通半导体元件端子与配线;
D.用树脂密封半导体元件;
E.除去导电性临时支撑体、露出配线;
F.在预设置已露出配线的外部连接端子处之外,形成绝缘层;
G.在未形成配线绝缘层处,设置外部连接端子;
H.分离每个半导体组件。
B所定的单元个数可是1个,但为提高生产效率也可是多个。
本申请的第六发明为一种半导体组件的制造方法,其特征在于,该制造方法包括步骤:
A.在绝缘性支撑体的单面设置多组配线;
B.除去预设置配线外部连接端子处的绝缘性支撑体,形成外部连接端子所用透孔;
C.为使配置在绝缘性支撑体上多组配线达到所定的单元个数,切断分离绝缘性支撑体,将设有配线的、已分离的绝缘性支撑体固定于框架;
D.在已设有配线的绝缘性支撑体上装配半导体元件,接通半导体元件端子与配线;
E.用树脂密封半导体元件;
F.在外部连接端子所用透孔中接通配线,形成外部连接端子;
G.分离每个半导体组件。
上述制造工艺,可依A-G的顺序进行,也可像第五发明那样,将B放在A前进行。
本申请的第七发明为一种半导体组件的制造方法,其特征在于,该半导体组件中的配线在单层配线情况下具有如下两种功能:配线的一面与半导体元件相连的第1连接功能,以及配线的另一面与外部的配线相连的第2连接功能,具有所述构成配线的半导体组件的制造方法包括以下A、B、C和D步骤:
A.将具有耐热性金属箔的绝缘基材的金属箔加工成配线图形;
B.后续工艺中,在第2连接功能部位,设置可从绝缘基材侧抵达配线图形的凹部;
C.在与配线图形面及配线图形相邻近的绝缘基材面上所需的位置上,粘合所需部分已被开孔的框架基材;
D.装配半导体元件,接通半导体元件端子与配线,用树脂密封半导体元件。
在第七发明中,工艺可依A-D顺序进行,也可将B放在A前进行,即可以在绝缘基片上设置抵达金属箔的凹部,然后将金属箔加工成配线图形。
本申请的第八发明为一种半导体组件的制造方法,其特征在于,该半导体组件中的配线在单层配线的情况下具有如下两种功能:配线的一面与半导体元件相连的第1连接功能,以及配线的另一面与外部配线相连的第2连接功能,具有所述构成配线的半导体组件的制造方法包括以下A、B、C、D和E步骤:
A.将具有耐热性金属箔的绝缘基材的金属箔加工成多组配线图形;
B.后续工艺中,在第2连接功能部位,设置可从绝缘基材侧抵达配线图形的凹部;
C.在与配线图形面及配线图形相邻的绝缘基材面上所需的位置,粘合所需部分已被开孔的第2绝缘基材,形成绝缘支撑体;
D.为使配置在绝缘支撑体上多组配线达到所定的单元个数,切断绝缘支撑体,并将设有配线的、已分离的绝缘支撑体固定在框架;
E.装配半导体元件,接通半导体元件端子与配线,用树脂密封半导体元件。
第八发明中,工艺可依A-E顺序,也可像第八发明那样,将B工艺放在A前进行。
本申请的第九发明为一种半导体组件的制造方法,
A.在支撑体的单面设置多组配线;
B.在已形成配线的支撑体上装配多个半导体元件,通过线焊接接通半导体元件端子与配线;
C.通过一体地形成树脂来密封接通的多组半导体元件和配线;
D.除去所需除去的支撑体部分,使所设定的配线部分露出,
E.形成与露出的配线电连接的外部连接端子;
F.分离每个半导体组件;
所述外部连接端子设置在所述配线上与所述半导体元件端子接通的位置的内侧。
作为支撑体,也可用金属箔,待树脂密封后,除去支撑体,从而使配线图形露出。
另外,支撑体为绝缘基材时,也可以在树脂密封后,除去绝缘基材的预定部分,形成抵达配线图形的、非贯通凹部。
本申请的第十发明为一种半导体组件的制造方法,其特征在于,该制造方法包括:
A.除去所需除去的支撑体部分,使所设定的配线部分露出;
B.在支撑体的单面设置多组配线;
C.在已形成配线的支撑体上装配多个半导体元件,通过线焊接接通半导体元件端子与配线;
D.通过一体地形成树脂来密封接通的多组半导体元件和配线,
E.形成与露出的配线电连接的外部连接端子;
F.分离每个半导体组件;
所述外部连接端子设置在所述配线上与所述半导体元件端子接通的位置的内侧。
作为支撑体,也可用金属箔,待树脂密封后,除去支撑体,从而使配线图形露出。
另外,支撑体为绝缘基材时,也可以在树脂密封后,除去绝缘基材的预定部分,形成抵达配线图形的、非贯通凹部。
本申请的第十一发明为一种用于安装半导体元件的框架的制造方法,其特征在于,所述框架由多个半导体元件安装基片部、连接多个半导体元件安装基片部的连接部以及位置对合标识部组成,所述制造方法包括:
(a)在导电性临时基片上设置半导体元件安装部的配线的工艺过程;
(b)向树脂基材上转印配线的工艺过程;
(c)用腐蚀方法除去导电性临时基片的工艺过程,当除去(c)的导电性临时基片时,保留其一部分,以作为连接部的一部分。
在本发明中,半导体元件可以使用LSI芯片、IC芯片等普通的元件。
在使半导体元件端子与配线相连的方法上,既可使用导线连接,也可采用如凸块形连接和各向异性薄片等的普通手段。
本发明在半导体元件进行树脂密封后,对密封树脂固化物进行加热处理,故可制造出不变形的半导体组件。
加热处理的温度最好是在密封树脂固化物的玻璃化转变温度±20℃的范围内,其理由是:在玻璃化转变温度±20℃的范围内,树脂固化物具有最好的塑性,易消除残留应变,若加热处理温度未达到玻璃化转变温度-20℃时,树脂固化物会成为玻璃态的弹性体,松驰效应变低,而当温度超过玻璃化转变温度+20℃时,树脂固化物会成为橡胶弹性体,同样具有降低消除应变效果的趋势。
在以密封树脂固化物的玻璃化转变温度±20℃的温度下进行加热处理后,以5℃/分钟的降温速度冷却至室温,这样可进一步确保防止半导体组件的翅曲和变形。
加热处理及/或冷却工序,最好在密封树脂固化物的上下两面用刚性平板、以具有可防止密封树脂固化物翅曲和变形的作用力压制的状态下进行。
本发明的半导体组件具有如下结构:在单层配线情况下,配线具有其一面与半导体芯片相连的第1连接功能,以及该配线的另一面可与外部配线相连的第2连接功能。
与外部配线相连的外部连接端子,可以使用焊锡凸块及金属凸块等。
从高密度化出发,外部连接端子最好设置在由导线等将半导体元件端子与配线接通位置的内侧(扇入型)。这样,在装配着半导体元件的下面,外部连接端子呈格子状布置,从高密度化方向看,是人们所期望的。
附图说明
以下将对附图作简要说明:
图1为说明本发明中半导体组件制造方法的一实施例的剖面图。
图2为说明本发明中半导体组件制造方法的一实施例的剖面图。
图3为说明本发明中半导体组件制造方法的一实施例的剖面图。
图4为说明本发明中半导体组件制造方法的一实施例的剖面图。
图5为说明本发明中半导体组件制造方法的一实施例的剖面图。
图6为说明本发明中半导体组件制造方法的一实施例的剖面图。
图7为说明本发明中半导体组件制造方法的一实施例的剖面图。
图8为说明本发明中半导体组件制造方法的一实施例的剖面图。
图9为说明本发明中半导体组件制造方法的一实施例的剖面图。
图10为说明本发明中半导体组件制造方法的一实施例的剖面图。
图11为说明本发明中半导体组件制造方法的一实施例的剖面图。
图12为说明本发明中半导体组件制造方法的一实施例的剖面图。
图13为说明本发明中半导体组件制造方法的一实施例的剖面图。
图14为说明本发明中半导体组件制造方法的一实施例的剖面图。
图15为说明本发明中半导体组件制造方法的一实施例的剖面图。
图16为说明本发明中半导体组件制造方法的一实施例的剖面图。
图17为说明本发明中半导体组件制造方法的一实施例的剖面图。
图18为说明本发明中半导体组件制造方法的一实施例的剖面图。
图19为说明本发明中半导体组件制造方法的一实施例的剖面图。
图20为说明本发明中半导体组件制造方法的一实施例的剖面图。
图21为说明本发明中半导体组件制造方法的一实施例的剖面图。
图22为说明本发明中半导体组件制造方法的一实施例的剖面图。
图23为说明本发明中半导体组件制造方法的一实施例的剖面图。
图24为说明本发明中半导体组件制造方法的一实施例的剖面图。
图25为说明本发明中半导体组件制造方法的一实施例的剖面图。
具体实施方式
结合图1,对本发明的第1实施例进行说明。
在厚度为0.035mm的电解铜箔1的单面上电镀厚度为0.001mm的镍层(图1中省略)。然后,对感光性干膜保护层(日立化成工业株式会社制造、商品名:″PHOTEC HN340″)进行层压,配线图形经曝光、显影,形成电镀保护层。接着,在硫酸铜液中进行电解镀铜。下一步进行厚度为0.003mm的镀镍、纯度在99.9%以上、厚度在0.0003mm以上的镀金。然后,剥离电镀保护层,形成配线2(图1a)。这样将LSI芯片3装配在已设有配线2的铜箔1上(图1b)。在粘接LSI芯片时,使用半导体专用的银焊料4。而后将LSI端子与配线2通过导线100相连接(图1c)。如此形成之后,将该件放入自动传送模中,采用专用于半导体密封的环氧树脂(日立化成工业株式会社制造、商品名:“CL-7700”)进行密封5(图1d)。此后,利用碱腐蚀方法只将铜箔1溶解除去,露出镍层。在对铜溶解性低的镍剥离液中除去镍层,露出配线部(图1e)。接着,涂敷焊料保护层6,并以能使连接用端子部呈露出状态地设置图形。在该配线露出处,设置焊料球7,并使之溶融(图1f)。通过该焊料球7与外部的配线相连接。
结合图2,对本发明的第2实施例进行说明。
用与图1同样的方法,制成拥有配线2的铜箔1(图2a)。装配LSI芯片3,在LSI芯片端子部设置金属凸块8,将所述金属凸块8与配线2的端子部经加热加压相连接(图2b)。然后在LSI芯片下部充填液态环氧树脂并使之固化9(图2c)。如此形成之后,将该件放入自动传送模中,采用半导体专用密封环氧树脂(日立化成工业株式会社制造、商品名:“CL-7700”)进行密封10(图2d)。此后,利用碱腐蚀方法只将铜箔1溶解除去,露出镍层。在对铜溶解性低的镍剥离液中除去镍层,露出配线部(图2e)。然后,涂敷焊料保护层6,并以能使连接用端子部呈露出状态地设置图形。在该配线露出处,设置焊料球7,并使之溶融(图2f)。通过该焊料球7与外部的配线相连接。
结合图3,对本发明第3实施例进行说明。
在厚度为0.035mm的电解铜箔1的单面电镀厚度为0.001mm的镍层(图3中省略)。然后对感光性干膜保护层(日立化成工业株式会社制造、商品名:“PHOTEC HN340")进行层压,配线图形经曝光、显影,形成电镀保护层。接着,在硫酸铜液体中进行电解镀铜,设置第1配线13。而后使电镀保护层剥离,在第1配线13的表面进行氧化和还原处理。作为粘接树脂,使用聚酰亚胺类粘接膜(日立化成工业株式会社制造、商品名:“AS2210”)12,让配线13处于内侧,与新的铜箔层叠粘接。(用通常的光刻法在铜箔11上设置形成直径为0.1mm的孔穴。利用板镀法在孔穴内和铜箔整个表面进行镀铜)。利用铜箔及光刻法设置第2配线11。用准分子激光除去LSI装配部位的树脂(聚酰亚胺类粘接膜12),使端子部露出。在该端子部,进行厚度为0.003mm的镀镍、纯度99.9%以上、厚度为0.0003mm以上的镀金(图3a)。这样,在设有双层配线的铜箔1上装配LSI芯片。粘接LSI芯片时,使用半导体专用的银焊料(图3b)。然后,用导线100将LSI端子部与配线13连接(图3c)。如此形成之后,将该件放入自动传送模中,用半导体专用密封环氧化树脂(日立化成工业株式会社制造、商品名“CL-7700”)进行密封5。此后,利用碱腐蚀方法只将铜箔1溶解除去,露出镍层。在对铜溶解性低的镍剥离液中除去镍层,露出配线(图3e)。然后,涂敷焊料保护层,以使连接用端子部呈露出状态地设置图形。在该配线的露出处,设置焊料球7、使之溶融(图3f)。通过该焊料球7与外部的配线相连接。
结合图4,对本发明的第4实施例进行说明。
在厚度为0.1mm的SUS(不锈钢)板14上,对感光性干膜保护层(日立化成工业株式会社制造、商品名“PHOTEC HN 340”)进行层压,配线图形经曝光、显影,形成电镀保护层。此后,在硫酸铜液中进行电解镀铜。下一步,进行厚度为0.003mm镀镍、纯度在99.9%以上、厚度为0.0003mm以上的镀金。然后,剥离电镀保护层,形成配线2(图4a)。这样,在设有配线2的SUS板14上装配半导体芯片103(图4b)。粘接半导体芯片时,采用半导体专用银焊料4。然后,通过导线100将半导体端子部与配线2连接(图4c)。如此形成之后,将该件放入自动传送模中,用半导体专用密封环氧树脂(日立化成工业株式会社制造、商品名:“CL-7700”)进行密封5(图4d)。此后,将SUS板14机械剥离除去,露出配线部(图4e)。然后,涂敷焊料保护层,以使连接用端子部呈露出状地设置图形。在该配线的露出处,设置焊料球7,并使之溶融(图4f)。通过该焊料球7与外部配线相连接。
结合图5,对本发明第5实施例进行说明。
在厚度为0.035mm的电解铜箔1上,对感光性干膜保护层(日立化成工业株式会社制造、商品名:"PHOTEC HN340")进行层压,配线图形经曝光、显影,形成电镀保护层。接着,在进行镍的图纹电镀15之后,在硫酸铜液中进行电解镀铜。下一步,进行厚度为0.003mm的镍层、纯度99.9%以上、厚度在0.0003mm以上的镀金。然后剥离电镀保护层,形成配线2(图5a)。在如此设有配线2的铜箔1上装配半导体芯片103(图5b)。粘接半导体芯片时,利用半导体专用银焊料4。然后,通过导线100将半导体端子和配线2连接(图5c)。如此形成之后,将该件放入自动传送模中,采用半导体专用密封环氧树脂(日立化成工业株式会社制造、商品名:“CL-7700”)进行密封5(图5d)。此后,利用碱腐蚀方法将铜箔1除去,露出镍层的配线部(图5e)。然后,涂敷焊料保护层6,以使连接用端子部呈露出状地设置图形。在该配线露出处,设置并溶融焊球7(图5f)。通过该焊球7与外部配线相连接。
结合图6,对本发明第6实施例进行说明。
在厚度为0.035mm的电解铜箔1上,对感光性干膜保护层(日立化成工业株式会社制造、商品名:"PHOTEC HN340")进行层压,配线图形经曝光、显影,形成电镀保护层。接着,进行纯度99.9%以上、厚度在0.0003mm以上的镀金,以及厚度大于0.003mm的镀镍。进而在硫酸铜液中进行电解镀铜,剥离电镀保护层,形成配线2(图6a)。这样,在已设置有配线2的铜箔1的配线面上粘接聚酰亚胺膜片16,利用激光使配线2的连接用端子部露出(图6b),并利用腐蚀方法将铜箔1除去(图6c)。另外,不使用聚酰亚胺而用感光性薄膜16,不使用激光也可使连接用端子部露出。接着,在聚酰亚胺膜16的配线图形面上装配LSI芯片3。粘接LSI芯片时,利用半导体专用银焊料4。然后,通过导线100将半导体端子与配线2相连接(图6d)。如此形成之后,将该件放入自动传送模中,用半导体密封专用环氧树脂(日立化成工业株式会社制造、商品名:“CL-7700”)进行密封5(图6e)。此后,在连接用端子部设置并溶融焊料球7(图6f)。通过该焊料球7与外部配线相连接。
结合图7,对本发明第7实施例进行说明。
在厚度为0.035mm的电解铜箔1的平面上,电镀厚度为0.001mm的镍层(图7中省略)。然后对感光性干膜保护层(日立化成工业株式会社制造、商品名:“PHOTEC HN340”)进行层压,配线图形经曝光显影,形成电镀保护层。接着,在硫酸铜液中进行电解镀铜。进而进行厚度为0.003mm的镀镍,以及厚度大于0.0003mm、纯度在99.9%以上的镀金。此后,剥离电镀保护层,形成配线2(图7a)。这样,在设有配线2的铜箔上装配LSI芯片3。粘接LSI芯片时,采用半导体专用银焊料4。然后,通过导线100将半导体端子与配线2连接(图7b)。如此形成之后,将该件放入自动传送膜中,采用半导体密封专用环氧树脂(日立化成工业株式会社制造、商品名:“CL-7700”)进行密封5(图7c)。此后,用碱腐蚀方法只将铜箔1溶解除去,使镍层露出。在对铜溶解性低的镍剥离液中除去镍层,露出配线(图7d)。然后,粘接使连接用端子开口的聚酰亚胺薄膜16(图7e),并在该配线露出处设置并溶融焊料球7(图7f)。通过该焊料球7与外部配线连接。
结合图8,对本发明第8实施例进行说明。
在厚度为0.035mm的电解铜箔1上,对感光性干膜保护层(日立化成工业株式会社制造、商品名:“PHOTEC HN340”)进行层压,配线图形经曝光、显影,形成电镀保护层。接着,进行纯度在99.9%以上、厚度为0.0003mm的镀金,以及厚度在0.003mm以上的镀镍。在硫酸铜液中电解镀铜,并剥离电镀保护层,形成配线2(图8a)。在如此设置有配线2的铜箔1的配线一面,采用丝网印刷方法涂敷液态密封树脂17,并使配线2的接线用端子部呈露出状地设置绝缘层(图8b)。待液态密封树脂固化后,利用腐蚀方法将铜箔1除去(图8c)。然后,在已固化的液态密封树脂16具有配线图形的一面装配LSI芯片3。粘接LSI芯片时,使用半导体专用银焊料4。此后,用导线100将半导体端子与配线2相连接(8d)。如此形成之后,将该件放入自动传送模中,采用半导体专用密封环氧树脂(日立化成工业株式会社制造、商品名:“CL-7700”)进行密封5(图8e)。此后,在配线2的连接端子处设置并溶融焊料球7(图8f)。通过该焊料球7与外部配线相连接。
结合图9,对本发明第9实施例进行说明。
在厚度为0.035mm的电解铜箔1的单面电镀厚度0.001mm的镍层(图9中省略)。此后,对感光性干膜保护层(日立化成工业株式会社制造、商品名:“PHOTEC HN340”),进行层压,配线图形经曝光、显影,形成电镀保护层。接着,在硫酸铜液中电解镀铜。然后,进行厚度为0.003mm的镍电镀,以及纯度在99.9%以上、厚度在0.0003mm以上的镀金。此后,剥离电镀保护层,形成配线2(图9a)。这样,在设有配线2的铜箔1上装配LSI芯片3。粘接LSI芯片时,利用半导体专用的银焊料4。然后,通过导线100将半导体端子与配线2连接(图9b)。如此形成之后,将该件放入自动传送模中,用半导体密封专用环氧树脂(日立化成工业株式会社制造、商品名:“CL-7700”)进行密封5(图9c)。此后,利用碱腐蚀方法仅将铜箔1溶解除去,使镍层露出。在对铜溶解性低的镍剥离液中除去镍层,露出配线(图9d)。然后,采用丝网印刷方法涂敷液态密封树脂17,使配线2的连接用端子部呈露出状态而形成液态密封树脂17的绝缘层(图9e)。在使用液态密封树脂17固化后,在该配线2连接用端子部,设置并溶融焊料球7(图9f)。通过该焊料球7与外部配线相连接。
结合图10,对本发明第10实施例进行说明。
在厚度为0.035mm的电解铜箔1的单面,电镀厚度为0.001mm的镍层(图10中省略)。对感光性干膜保护层(日立化成工业株式会社制造、商品名:“PHOTEC HN340”)进行层压,经曝光、显影,形成配线图形及位置对合标识的电镀保护层。在硫酸铜液中进行电解镀铜。然后,继续进行厚度为0.003mm的镀镍,以及纯度在99.9%以上、厚度在0.0003mm以上的镀金。接着,剥离电镀保护层,形成配线2及位置对合标识18后(图10a),仅在位置对合标识18处,用SUS板进行夹压,使铜箔1的背面形成突出的位置对合标识(图10b)。在如此已设置有配线2和位置对合标识18的铜箔1上,装配LSI芯片3(图10c)。粘接LSI芯片3时,采用半导体专用银焊料4。此后,通过导线100将半导体端子部与配线2连接(图10d)。如此形成之后,将该件放入自动传送模中,用半导体密封专用环氧树脂(日立化成工业株式会社制造、商品名:CL-7700)进行密封5(图10e)。在铜箔背面再次对感光性干膜保护层进行压层,利用位置对合标识18形成腐蚀图形。此后,将铜箔1及镍层进行腐蚀处理,由铜箔1形成凸块7,并实现配线部的露出(图10f)。接着,涂敷焊料保护层8,并使凸块7呈露出状形成绝缘层(图10g)。通过该凸块7与外部配线连接。
结合图11,对本发明第11实施例进行说明。
在厚度为0.035mm的电解铜箔1上,对感光性干膜保护层(日立化成工业株式会社制造,商品名:“PHOTEC HN340”)进行层压,使多组配线图形经显影,形成电镀保护层。接着,进行纯度在99.9%以上、厚度0.0003mm的镀金,以及厚度在0.003mm以上的镀镍层。然后,在硫酸铜液中电解镀铜,剥离保护层,形成多组配线2(图11a)。这样,在已设有多组配线2的铜箔1的配线面上粘接聚酰亚胺膜19,并利用激光加工使配线2的连接端子部露出(图11b),用腐蚀方法除去铜箔1(图11c)。这样,在一片聚酰亚胺膜片上形成多组配线2后,装配LSI芯片3。在粘接LSI芯片时,利用半导体专用芯片连接条4′。此后,通过导线100将半导体端子与配线2连接(图11d)。如此形成之后,将该件放入自动传送模中,用半导体密封用环氧树脂(日立化成工业株式会社制造、商品名:“CL-7700”)分别进行密封5(图11e)。然后,在配线2的连接端子部,设置、溶融焊料球7(图11f)。通过该焊料球7与外部配线相连接。最后,将用聚酰亚胺薄膜相连的组件冲压取出(图11g)。
结合图12,对本发明第12实施例进行说明。
在厚度为0.07mm、带有粘接剂的聚酰亚胺薄膜20上,用冲压的方法使其预成为连接端子的部分形成开口(图12a)。然后,在粘接厚度0.035mm的铜箔21后(图12b),对感光性干膜保护层(日立化成株式会社制造、商品名:"PHDTEC HN340")进行层压,多组配线图形经曝光、显影,形成腐蚀保护层。接着,将铜箔腐蚀,剥离保护层,形成多组配线2(图12c)。这样,在1片聚酰亚胺膜片上形成多组配线图形后,装配LSI芯片3。粘接LSI芯片3时,利用半导体专用芯片连接条4′。此后,通过导线100将半导体端子与配线2连接(图12d)。如此形成之后,将该件放入自动传送模中,用半导体专用密封环氧树脂(日立化成工业株式会社制造、商品名:“CL-7700”)分别进行密封5(图12e)。此后,在配线的连接端子部,设置并溶融焊料球7(图12f)。通过该焊料球7与外部配线相连接。最后,将用聚酰亚胺薄膜相连的组件冲压取出(图12g)。
结合图13、图14和图15,对本发明第13实施例进行说明。
在厚度为0.035mm的电解铜箔1的一面电镀厚度为0.001mm的镍层(图13中省略)。对感光性干膜保护层(日立化成工业株式会社制造、商品名:“PHOTEC HN340”)进行层压,经曝光、显影,形成多组配线图形的电镀保护层。然后在硫酸铜溶液中电解镀铜,接着进行厚度0.003mm的镀镍,纯度在99.9%以上、厚度在0.0003mm以上的镀金,剥离电镀保护层,形成配线2(图13a)。再接着,将形成有配线2的铜箔1分为单元个数后,利用聚酰亚胺粘接膜将其粘贴在另外准备好的、不锈钢制成的框架22(厚度0.135mm)上(图13b)。框架可以用磷青铜等铜合金、铜箔、镍箔及镍合金箔制成。而粘接方法还可以利用金属间共晶的方法,以及利用超音波的粘接方法等。另外,如图14所示,事先检查铜箔1上的配线,只要选择品质良好的配线23与框架22相粘接即可。在图14中,1为电解铜箔,22为框架,24为品质不良的配线,25是位置对合用孔穴。另外,在本实施例中,在分离后的铜箔上具有一个配线,但也可使分离后的铜箔上具有多组配线。作为将框架22与带有配线的铜箔进行粘合的位置关系,有如图15(a)和(b)所示的种种可能。图15为框架22的平面图,26是框架的开口部、27是带有配线的铜箔的安装位置、28是用来固定箔的粘接剂。然后,安装LSI芯片3,并通过导线100将半导体端子部与配线2相连接(图13c)。安装LSI芯片时,利用半导体专用芯片连接条4′。这里,也可以不用连接条4′,使用芯片连接用银焊料。另外,在安装半导体芯片时,选用了普通的导线连接,但也可以采用倒装片等其他方法。如此形成之后,将该件放入自动传送模中,采用半导体密封专用环氧树脂(日立化成工业株式会社、制造商品名“CL-7700”)进行密封5(图13d)。然后,利用碱腐蚀方法只将铜箔1溶解除去,使镍层露出。再在对铜溶解性低的镍剥离液中除去镍层,露出配线部分。此后,涂敷焊料保护层6,以使连接端子呈露出状设置图形。在该配线露出部,设置、溶融焊料球7(图13e)。此后,利用剪断机切断,并除掉框架22不要的切片101,分割成各个半导体组件(图13f)。通过所述焊料球7与外部配线相连接。本实施例是以板的形式操作,可高效率地制造半导体组件。
结合图16,对本发明第14实施例进行说明。
在厚度为0.07mm的、带有粘接剂的聚酰亚胺薄膜29上,用冲压的方法使其预成为连接端子的部分形成开口。然后,与厚度0.035mm的铜箔相粘接,对感光性干膜保护层(日立化成工业株式会社制造、商品名:“PHOTEC HN340”)进行层压,多组配线图形经曝光、显影,形成腐蚀保护层。接着,腐蚀铜箔,剥离保护层,形成多组配线2(图16a)。这里也可采用将聚酰亚胺直接涂到铜箔上的材料(日立化成工业株式会社制造、商品名:50001),形成连接端子部及配线2。开口部的形成也可用钻孔加工、准分子激光等激光加工和印刷等方法,以及使用对聚酰亚胺具有感光性能的材料来通过曝光、显影而形成。不使用聚酰亚胺,也可以使用密封树脂的材料。
如上所述,在一片聚酰亚胺薄膜上形成多组配线图形后,将带有配线的薄膜分成数个单元,并通过粘合聚酰亚胺用粘接剂28,粘接在另已准备好的不锈钢制的框架22(厚0.135mm)上(图16b)。然后,装配LSI芯片3,通过导线100将半导体端子部与配线2连接(图16c)。在安装LSI芯片时,利用了芯片连接条4′。如此形成之后,将该件放入自动传送模中,采用半导体密封专用的环氧树脂(日立化成工业株式会社制造、商品名:“CL-7700”)进行密封5(图16d)。接着,在最初设置的、预成为连接端子的开口部配置、溶融焊料球7(图16e)。通过该焊料球7与外部配线相连接。最后,将以薄膜连的组件冲压取出,分割成各个组件(图16f)。
结合图17,对本发明第13实施例进行说明。
在金属箔31上直接设置绝缘材料32,在这种双层柔性基材(图17a)的金属箔上设置一定的保护层图案,用众所周知的腐蚀法形成所需的多组配线图形33,剥离保护层(图17b)。作为金属箔,除电解铜箔、压伸铜箔或铜合金箔等单一箔外,在经后续工艺可除去的载体箔上设有铜薄层的复合金属箔等也是适用的。具体地讲,在厚度18μm的电解铜箔的单面,形成厚度0.2μm左右的镍磷镀层后,继续电镀厚度为5μm左右的铜薄层,这种复合金属箔也是可应用的。这种情况下,当在铜薄层上形成聚酰亚胺层后,通过腐蚀除去铜箔及镍磷层,而露出铜薄层。即,在本申请的发明中,既可以在使铜薄层全部露出后再对铜薄层进行配线加工,也可以将载体箔(铜箔/镍薄层)作为引导框架结构体的一部分加以利用。
另外,作为绝缘基材,从工艺耐热性等观点来看,聚酰亚胺材料是很一般的。这种场合下,若聚酰亚胺和铜箔的热膨胀系数不相同,在焊料的软溶过程中,基材的翅曲就会显著。因此,作为聚酰亚胺,最好是使用含有70摩尔%以上的聚酰亚胺,该聚酰亚胺具有下列[化学式1]的循环单元。
然后,后续处理中,在成为与外部基板连接部的位置上,设置达到铜箔的凹部34(图17c)。凹部的加工方法无特殊限定,除准分子激光、二氧化碳激光以及YAG激光等激光加工外,也可应用液体腐蚀方法。
然后,将框架基材37与配线图形面相粘接,所述基材37是对所设定部分(开孔部35)用冲孔加工等方法而成,并带有粘接材料36(图17d)。在这种情况下,对框架基材无特殊限定,象聚酰亚胺膜及铜箔等金属箔均可适用。这里假设双层柔性基材聚酰亚胺层厚度25μm,且粘接框架基材为聚酰亚胺膜,那么,为了确保框架整体的刚度,薄膜厚度必须在50-70μm左右。而且,对形成薄膜基材层的区域也无特殊限定,也可在装配半导体芯片的那部分设置框架基材层。具体地讲,在以导线连接方式装配芯片的情况下,只要最小限度地露出导线连接用端子部38,其他区域也可全部设置框架基材层。之后,装配半导体芯片39,用金线40将半导体芯片与配线图形间连通(图17e)。另外,作为半导体芯片的安装方式,在采用倒焊方式的情况下,也可在配线图形的一定位置(与半导体芯片外部连接所用电极的位置相对应)设置金属凸块,通过该金属凸块,使半导体芯片与波线图形相连通。然后,将该件放入自动传送模中,用树脂密封材料41进行密封(图17f)。这时树脂密封材料无特殊限定,比如可以采用含有直径在10-20μm的二氧化硅、含水量在5-80%范围的环氧类树脂等。然后形成与外部基板的连接部42。作为连接部42的形成方法,既可采取在图17c的工序后预先通过电解电镀法形成较聚酰亚胺膜要厚一些的凸块的方法,也可采取在树脂密封后由焊锡印刷法形成焊料凸块的方法。最后,由框架切断组件,得到所需的组件(图17g)。
以下对图17的第15实施例进行更具体的说明。
具体例1
在单面拥有厚度12μm电解铜箔的双层柔性基材(日立化成工业株式会社制造、商品名:“MCF5000I”)的铜箔面上,对干膜保护层(日立化成工业株式会社)制造、商品名:“PHOTEC HK 815”)进行层压,经曝光、显影,得到所需的抗腐蚀图形。然后,用氯化铁溶液对铜箔腐蚀后,用氢氧化钾溶液剥离抗腐蚀图形,从而得到所需的配线图形。接着,采用准分子激光加工机(住友重型机械工业株式会社制造、“INDEX200”)在一定的位置,仅以一定的数量形成从绝缘基材一侧到达配线图形背面的凹部(直径300μm)。准分子激光加工条件为:能量密度250mJ/cm2,缩小率3.0,振荡频率200Hz,照射脉冲数为300。然后,制造粘接片,所述粘接片为:在厚度50μm的聚酰亚胺薄膜(宇部兴产制造、商品名:“UPILEXS”)的单面具有厚度10μm的聚酰亚胺类的粘接材料(日立化成工业株式会社制造、商品名:“AS2250”)。用冲孔加工方法除去所设定区域,该设定区域包括后续工序中设置导线连接端子的区域。这样,通过粘接材料,使聚酰亚胺薄膜与带有配线图形的双层柔性基材经加热而压接。压接条件为:压力20kgf/cm2,温度180℃,加热加压时间60分钟。然后,由无电解镍及镀金法,在导线连接端子处进行镀镍/金。镀层厚度分别为3μm、0.3μm。然后,利用装配半导体芯片的芯片连接材料(日立化成工业株式会社制造、商品名:“HM-1”)装配半导体芯片。装配条件为:冲压压力5kgf/cm2,粘接温度380℃,压接时间5秒钟。此后,通过导线连接接通半导体芯片的外部电极与配线图形。此后,冲压加工成引导框架状,放入自动传送膜中,采用半导体专用密封环氧树脂(日立化成工业株式会社制造、商品名:“CL-7700”),在温度185℃、用90秒的时间进行密封。接着,在前述的凹部印刷涂敷一定量的焊料,利用红外线软溶炉使焊料溶融,形成与外部连接的凸块。最后,将组件冲压取出,得到所需的组件。
结合图18,对本发明第16实施例进行说明。
在金属箔31上直接配置绝缘材料32,在这种双层柔性基材(图18a)的金属箔上设置一定的保护层图形,用众所周知的腐蚀方法形成所需的多组配线图形33,并剥离保护层图形(图18b)。作为金属箔,除了电解铜箔、冲压铜箔或合金铜箔等单一箔外,在经后续工序可被除去的载体箔上设有铜薄层的复合金属箔等也是适用的。具体地讲,在厚度18μm的电解铜箔的单面上,设置厚度0.2μm左右的镍磷镀层后,接着再电镀厚度约为5μm的铜薄层,这种复合金属箔是可以使用的。这种情况下,在铜薄层上形成聚酰亚胺层后,通过腐蚀除去铜箔及镍磷层,露出铜薄层。即,在本申请发明中,既可以在使铜薄层全部露出后再对铜薄层进行配线加工,也可以将载体箔(铜箔/镍薄层)作为引导框架构造体的一部分加以利用。另外,从工艺耐热性等观点来看,聚酰亚胺作为绝缘材料是很一般的。这种情况下,若聚酰亚胺和铜箔的热膨胀系数不同,则在焊料的软溶过程中,基材的翅曲就会明显。因此,作为聚酰亚胺,最好是使用含70摩尔%以上的聚酰亚胺,该聚酰亚胺具有上述化学式1的循环单元。
然后,经后续工序,在将成为与外部基板连接部的位置,设置达到铜箔的凹部34(图18c)。凹部的加工方法无特殊限定,除准分子激光、二氧化碳激光及YAG激光加工方法外,也可采用液体腐蚀方法。
作为第2绝缘基材,将框架基材37与配线图形面相粘接,该框架基材37是对所设定的部分(开口部35)用冲孔加工而成,并带有粘接材料36(图18d)。这里,假设双层柔性基材聚酰亚胺层厚度为25μm,若考虑用后处理法来固定框架,则粘接聚酰亚胺薄膜的厚度必须在50-70μm左右。尤其,粘接聚酰亚胺的区域范围并无特别的限制,也可通过将其设置在装配半导体芯片的部位,像CSP那样,在半导体芯片下面形成外部连接端子。具体地讲,在以导线连接方式装配芯片时,只要最小限度地使导线连接端子38露出,其他区域可全部粘接聚酰亚胺膜。将如此得到的绝缘基板分离成各个配线图形(图18e),并固定在已特别准备好的、如SUS等的框架43上(图18f)。然后,装配半导体芯片39,并用金线40将半导体芯片和配线图形间接通(图18g)。另外,作为半导体芯片的安装方式,在采用倒焊时,也可在配线图形的一定位置(与半导体芯片外部连接所用电极的位置相对应)设置金属凸块,通过该金属凸块,使半导体芯片与波线图形相接通。然后,放入自动传送模中,用树脂密封材料41进行密封(图18h)在这种情况下,树脂密封材料无特殊限定,比如可以使用含水量在5-80%、含有直径10-20μm的二氧化硅的环氧类树脂等。接着,形成与外部基板的连接部42。作为该连接部42的形成方法,既可采用在图18c的工序后预先通过电解电镀法形成较聚酰亚胺膜要厚一些的凸块的方法,也可采取在树脂密封后由焊锡印刷法形成焊料凸块的方法等。最后由框架切断组件,得到所需的组件(图18i)。
以下对图18中的第16实施例进行更具体的说明。
具体例2
在单面具有厚度12μm的电解铜箔的双层柔性基材(日立化成工业株式会社制造、商品名:“MCF5000I”)铜箔面上,对干膜保护层(日立化成工业株式会社制造、商品名:“PHOTEC HK815”)进行层压,经曝光、显影,得到所需的保护层图形。然后,用氯化铁溶液对铜箔腐蚀加工,用氢氧化钾溶液剥离保护层图形,从而得到所设定的配线图形。然后用准分子激光加工机(住友重型机械工业株式会社制造、商品名:“INDEX200”)、在一定的位置、以一定的数量,形成从绝缘基材一侧达到配线图纹背面的凹部(直径为300μm)。准分子激光的加工条件为:能量密度250mJ/cm2,缩小率3.0,振荡频率200Hz,照射脉冲数300。此后,制造粘接片,该粘接片为:在厚度50μm的聚酰亚胺薄膜(宇部兴产制造、商品名:“UPILEXS”)的单面上,设有厚度10μm的聚酰亚胺类的粘接材料(日立化成工业株式会社制造、商品名:“AS2250”)。用冲孔加工方法除去所设定区域,该设定区域包括在后续工序中设置导线连接端子的区域。这样,通过粘接材料,使聚酰亚胺薄膜与带有配线图形的双层柔性基材经加热而压接。压接条件为:压力20kgf/cm2,温度180℃,加热加压时间为60分钟。然后,由无电解镍及镀金法,在导线连接端子部进行镀镍/金。镀层厚度分别为3μm和0.3μm。将如此得到的基板分离为各配线图形,并固定在另已准备好的SUS框架上。然后,用专用于装配半导体芯片的芯片连接材料(日立化成工业株式会社制造、商品名:“HM-1”)装配半导体芯片。装配条件为:冲压压力5kgf/cm2,粘接温度380℃,压接时间为5秒。经由导线连接使半导体芯片的外部电极部与配线图形相连接。此后,冲压加工呈引导框架状,放入自动传送模中,用半导体专用密封环氧树脂(日立化成工业株式会社制造、商品名:“CL-7700”),在185℃、90秒钟的条件下进行密封。然后,在前述的凹部处印刷涂敷一定量的焊料,用红外线软溶炉使焊料溶融,形成与外部连接用的凸块。最后,将组件部冲压取出,得到所需的组件。
结合图19、图20和图21,对本发明的第17实施例进行说明。
在支撑体51上,设置多组所需的配线图形52(图19a)。作为该支撑件,除电解铜箔等金属箔外,聚酰亚胺薄膜等绝缘基材也是适用的。
使用绝缘基材时有如下两种方法。第1种方法是,在绝缘基材的设定部位,设置达到配线图形的、未贯通的凹部,在配线图形的露出部位形成外部连接端子。未贯通凹部可利用准分子激光和二氧化碳激光加工形成。第2种方法是,在附带有粘接材料的绝缘基材上预先进行打孔加工,与电解铜箔等进行层压后,对铜箔进行腐蚀加工。
另一方面,在使用金属箔时,首先由光致抗蚀膜等形成保护层图形,然后以金属箔作为阴板,用电镀法形成配线图形。这种情况下,可在通常的电解铜箔和电解铜箔上设置与铜箔的化学腐蚀条件不同的金属(镍、金、锡等)薄层。还有,作为配线图形,铜是可以的,但如前述当以电解铜箔作为支撑体使用时,需要利用与铜箔的腐蚀条件不同的金属作为配线图形,或者,必须在图形镀铜之前就设置一种图形薄层,它能成为铜箔腐蚀的保护层。
然后,利用芯片连接材料53装配半导体元件54,接通半导体元件端子与配线图形(图19b),利用自动传送注模法和树脂密封材56,将多组半导体元件和配线图形一起密封(19c)。树脂密封材料无特殊的限制,比如,可以使用含水量在5-80%、含有直径10-20μm的二氧化硅的环氧树脂。而且,本发明中,半导体元件的安装方式并不限定为正面焊,比如倒焊的方式也是可以的。具体地讲,在配线图形52上的一定位置,用电镀法形成用于倒焊半导体元件凸块,此后即可使半导体元件的外部连接部与凸块接通。如图20和图21所示,这对后续工序易于分离组件是有效的。其中,图20中具有多个组件,在各组件的分界部设置槽沟59。槽宽和槽深等可通过自动传送模的加工尺寸来控制。另外,在图21中,使用格状中间板60进行自动传送注膜,所述格状中间板60是预先将各组件的相应部分刻槽而形成。然后,当支撑体为金属箔时,利用化学腐蚀等方法除去支撑体,在所设的位置形成外部连接端子57(图19d)。使用绝缘基材作为支撑体时,如前所述,可利用激光等方法有选择地除去所设定部分的绝缘基材。最后,将一起密封的基板切断分离成单元58。而且,为了保护配线图形,也可以在配线图形的露出面上设置焊料保护层。
以下对第17实施例进行具体说明。
具体例3
在边长250mm、厚度35μm的四方形电解铜箔的光泽面上,对感光性干膜保护层(日立化成工业株式会社制造、商品名:"PHOTECHN640")进行层压,经曝光、显影,形成所需的保护层图形(最少线/间距=50μm/50μm)。然后,由电镀法形成300个(4区块/250mm×250mm、75个/每区块)同样的配线图形,所述配线图形由厚度0.2μm的镍、30μm的铜、5μm的镍及1μm的软金的镀层构成。接着,利用溶液温度为35℃、浓度为3wt%的氢氧化钾溶液剥离保护层图形,并在85℃温度下干燥15分钟,待切成各块后,采用安装半导体元件的芯片连接材(日立化成工业株式会社制造、商品名:“HM-1”)粘接半导体元件。其粘接条件为:冲压压力5kgf/cm2,温度380℃及压接时间5秒钟。然后,用导线接通半导体元件外部端子与镀金端子部(第2连接部),并放入自动传送模中,用半导体密封用环氧树脂(日立化成工业株式会社制造、商品名:“CL-7700”)在185℃、90秒钟的条件下,将75个(相当于1块)配线图形一起密封,由此将各配线图形转印至密封材上。然后,采用碱腐蚀方法(Meltex株式会社制造、商品名:“A工艺方法”)腐蚀除去电解铜箔的所需部分。腐蚀液的温度为40℃,喷射压力为1.2kgf/cm2。利用印刷法在外部连接端子部位形成焊料图形,利用红外线软溶炉使焊料溶融,从而形成用于外部连接的凸块。最后,利用金刚石割刀分离各组件部分,得到所需的组件。
具体例4
在边长为250mm、厚35μm的四方形电解铜箔的光泽面上,对感光性干膜保护层(日立化成工业株式会社制造、商品名:“PHOTECHN640”)进行层压,经曝光、显影,形成所需的保护层图形(最少线/间距=50μm/50μm)。接着,利用电镀法形成300个(4块/250mm×250mm、75个/块)同样的配线图形,所述配线图形由厚度0.2μm的镍、30μm铜、5μm的镍及1μm的软金的镀层构成。然后,利用温度为35℃、浓度3wt%的氢氧化钾溶液,剥离保护层图形,在85℃温度下干燥15分钟后,切断各块,此后利用安装半导体元件的芯片连接材(日立化成工业株式会社制造、商品名:“HM-1”)粘接半导体元件。粘接条件为:冲压压力5kgf/cm2,温度38℃及压接时间5秒钟。然后用导线将半导体元件的外部端子与镀金端子部分(第2连接部)相连通。用已将相当于组件区域位置(15mm×15mm)刻去而成的格状不锈钢板作为中间板,放入自动传送模中,采用半导体密封专用环氧树脂(日立化成工业株式会制造、商品名:“CL-7700”)在温度185℃、时间90秒钟的条件下,将75个(相当于1块)配线图形一起密封,从而将各配线图形转印至密封材上。为使各组件易于从中间板分离,在中间板的格子部设置12°的锥度。然后,采用碱腐蚀方法(Meltex株式会社制造、商品名:“A工艺过程”)除去电解铜箔的所需部分。各组件保持在格子状中间板里。腐蚀液的温度为40℃,压力为1.2kgf/cm2。最后,用印刷法在外部连接端子部位设置焊料图形,并利用红外线软溶炉使焊料溶融,从而形成用于外部连接的凸块,将各组件从中间板部分离,得到所需的组件。
结合图22,对本发明第18实施例进行说明。
在导电性临时支撑体61(图22a)上设置多组所需的保护层图形62(图22b)。并由电镀法在临时支撑体的露出部分设置配线图形63。这种情况下,临时支撑体无特殊限制,比如,也可以在通常的电解铜箔和电解铜箔面上,设置与铜箔具有不同化学腐蚀条件的金属(镍、金、焊锡等)的薄层。另外,作为配线图形可以使用铜,但也可如前所述,当电解铜箔作为临时支撑体使用时,可将与铜箔具有不同腐蚀条件的金属作为配线图形使用,或者,在图形镀铜之前,就必须先设置图形薄层,它为铜箔腐蚀时的保护层。关于临时支撑体的厚度,在对后续工序的可操作性以及安装半导体元件时的尺寸无影响的情况下,并无特别的限制。然后,将临时支撑体作为阴极,在进行金丝连接所需的电镀(通常为镍/金)64之后,除去保护层图形(图22c)。而且,在本发明中,半导体元件的安装方式并不限于正焊方式,如倒焊方式也是适用的。具体地讲,采用电镀法在配线图形63上所需位置设置形成用于倒焊连接的凸块后,即可将半导体元件的外部连接部与凸块接通。
然后,用芯片连接材66粘接半导体元件65,并接通半导体元件的外部连接端子与配线图形(图22d)。此后,将其放入自动传送模中,用树脂密封材料68进行密封(图22e)。此种情况下,树脂密封材料无特别限定,比如,可以使用含水量为5-80wt%、含有直径10-20μm二氧化硅的环氧树脂。
此后,在相当于外部连接端子处,设置所需的金属图形69(图22f)。此种情况下,作为适用的金属,只要在腐蚀除去导电性临时支撑体条件下不被腐蚀即可,比如焊锡、金、镍/金等均可适用。另外,作为形成金属图形的方法,可采用众所周知的电镀法和焊锡印刷法等。而且,当用焊锡印刷法形成金属图形69的情况下,可以利用软溶过程来形成焊锡凸块70。这时,通过调节图形69的厚度,可控制软溶后的焊锡凸块70的高度。然后,以金属图形作为腐蚀保护层,除去临时支撑体所设定的部分,使配线图形露出。
最后,利用冲压加工,或者切割加工法等,分割各组件71(图22g)。尤其,在对露出的配线图形未用镍等耐腐蚀金属进行保护情况下,也可利用众所周知的焊料保护层来覆盖外部连接端子之外的区域。而且,在使用锡作为金属图形时,对软溶工艺并无特别的限定,在分割各组件的前、后均可使用,或者在向外部配线基板上安装各组件时,亦可使用。
以下对第18实施例进行具体说明。
具体例5
在厚度70μm的电解铜箔的光泽面上,对感光干膜保护层(日立化成工业株式会社制造、商品名:“PHOTEC HN640”)进行层压,经曝光、显影,形成所需的保护层图形(最少线/间距=50μm/50μm)。然后,用电镀法形成由厚度0.2μm的镍、30μm的铜、5μm的镍及1μm的软金组成的配线图形。接着,用溶液温度35℃、浓度3wt%的氢氧化钾溶液剥离保护层图形,在85℃下干燥15分钟后,用安装半导体元件的芯片连接材(日立化成工株式会社制造、商品名:“HM-1”)粘接半导体元件。粘接条件为:冲压压力5kgf/cm,温度380℃及压接时间5秒钟。在用导线接通半导体外部端子与镀金端子部(第2连接部)后,将其放入自动传送模中,使用半导体密封专用的环氧树脂(日立化成工业株式会社制造、商品名:“CL-7700”),在185℃、用90秒的时间进行密封,将配线图形转印至密封材上。然后,在电解铜箔上对感光干膜保护层(日立化成工业株式会社制造、商品名:“PHOTECHN340”)进行层压,经曝光、显影,形成所需的保护层图形,然后,用电镀方法设置厚度40um的焊锡垫片(直经为0.3mmφ),设置间距为1.0mm)。此后,在剥离干膜保护层后,利用碱腐蚀方法(Metex株式会社制造、商品名:“A工艺方法”)腐蚀除去欲清除部分的电解铜箔。腐蚀液的温度为40℃,喷射压力1.2kgf/cm2。最后,利用红外线软溶炉使焊锡熔融,形成用于外部连接的凸块。
结合图23、图24和图25,对本发明第19实施例进行说明。
利用图23说明安装半导体所用框架的构成。89为半导体安装基板,它由绝缘基材和配线构成。通过基板和连结部90形成多个连接。在连接部90上设有基准位置销孔91。不使用销孔91,也可使用图像识别中的识别标记。在后续工艺中,将以这些基准位置来定位。尤其用树脂对半导体进行浇注时,将洞内的销子插入销孔91以对合位置。
利用图24和图25作进一步说明。在作为导电性临时基板的、厚度0.070mm的电解铜箔81的单面上,用电镀形成厚度0.001mm的镍层(图24、25中省略)。然后对感光性干膜保护层(日立化成工业株式会社制造、商品名:“PHOTEC HN340”)进行层压,经曝光、显影,形成多组配线图形的电镀保护层。此时的曝光量为70mJ/cm2。接着,在众所周知的硫酸铜液中进行电解镀铜,并剥离保护层,形成多组配线82(图24a、图25a)。这里,如图25a所示,也可以考虑在连结部形成镀铜82,由此可以进一步提高已完成的框架的刚度。图24a和图25a所表示的构成,通过下述工艺也可得到:预先准备好由铜/镍薄层/铜这三层组成的基材,并用通常的腐蚀工艺在所述基材的一面形成配线。另外,也可以将这样得到的铜箔81/镍薄层(图中未示)/铜配线82(及82′)的构成作成铜箔/镍配线、镍箔/铜配线等无镍薄层的双层结构。也就是说,金属种类的选择并不限制本实施例的种类,但也有如下选择的适宜标准:当在后续工艺中腐蚀除去临时基板的一部分时(图24c,图25c),应能使配线有选择地保留。而且,为了成为框架连结部的组成材料,导电性临时基板最好是厚一些,由于后面还有将其一部分腐蚀除去的工序,所以必须选择适当的厚度。作为导电性临时基板的厚度,这取决于材质,比如,使用铜箔时,最好能在0.03-0.3mm左右。然后,在设有多组配线82的铜箔81上的配线一面,粘接聚酰亚胺粘接剂83。这里的聚酰亚胺粘接剂83,并不限于该种材料,比如,也可以利用环氧类粘接膜、在聚酰亚胺膜上涂敷粘贴剂的薄膜等。接着,利用准分子激光加工,形成外部连接端子用孔穴84(图24b、图25b)。为了后续工序中工艺简化,在安装半导体前,预先设置连接端子是合适的。另外,作为形成该孔穴84的方法,此外还可在薄膜上采用钻孔和冲压加工手段预先形成外部连接端子用孔穴84,然后再将该薄膜粘接。而且,这里也可以在孔穴84中充填作为连接端子用的焊锡等金属(相当于图24f、图25f的88),但在后面的半导体安装工序、树脂密封工艺中,金属突起有时会形成障碍,故最好还是在后续工序中形成。作为半导体元件安装基板部的外部连接端子用孔穴(或端子),最好能以阵列状形式设置在安装半导体元件一面的背面。
然后,腐蚀除去电解铜箔的一部分,所述电解铜箔为形成配线图形那部分的临时基板。作为该腐蚀液,在本实施例构成的情况下,可以选择较镍相比、铜的溶解速度显著高的腐蚀液和腐蚀条件。在本实施例中,作为腐蚀液是碱腐蚀剂(Meltex株式会社制造、商品名:“A工艺法”),腐蚀条件比如溶液温度为40℃,喷射压力为1.2kgf/cm2。这里所示的溶液的种类和条件只是个例子而已。通过该工序使基板部的镍薄层露出。在只腐蚀该镍薄层时,可以选择与铜相比、对镍的溶解速度阴显高的腐蚀液和腐蚀条件。在本实施例中,是利用镍腐蚀剂(Meltex株式会社制造、商品名:“Melstrip N950”)有选择性地进行腐蚀清除。腐蚀液的温度为40℃,喷射压力为1.2kgf/cm2。这里所示的溶液的种类和条件也只是一例而已。经过这样的工序,保留了连接部的临时基板,并得到具有一定刚度的半导体安装用框架(图24c、图25c)。在本实施例中,在该框架的铜配线端子部进行无电解镍--金电镀(图中省略)。为了在后续工序中导线连接芯片,这是必要的,根据需要也可进行这样的表面处理。
然后,装配半导体芯片85。粘接半导体芯片时,使用了半导体用芯片焊接条86(日立化工株式会社制造、商品名:“HM-1”)。这里,在芯片下面无配线时,也可以使用芯片焊接用的银焊料来粘接。此后,利用导线100连接半导体端子与配线(图24d、图25d)。与半导体端子的连接,也可以采用其他方法,如采用倒焊的倒装片连接,以及利用各向异性导电性反粘结剂的粘接。如此形成之后,将该件放入自动传送模中,用半导体密封用环氧树脂(日立化成工业株式会社制造、商品名:“CL-7700”)分别进行密封87(图24e、图25e)。此后,在配线82的连接端子处设置的连接用孔穴中,溶融、形成焊料球88(图24f、图25f)。该焊料球88将成为所谓的外部连接端子。将由连结部102相连的多部半导体装置冲压取出,得到各个半导体装置(图24g、25g)。
在本实施例中,通过采用半导体安装支框架及半导体装置制造方法,在使用聚酰亚胺条等薄膜基板的BGA、CSP等半导体装置制造中,可获得具有足够刚度的框架,并通过利用该框架,可以高精度、高效率地制造半导体装置。
根据本发明,可生产性良好、且稳定地制造能适应半导体芯片高度集成化要求的半导体组件。
Claims (13)
1.一种半导体组件制造方法,其特征在于,该制造方法包括步骤:
A.在导电性临时支撑体的单面设置配线;
B.在设置配线的导电性临时支撑体上已设置配线的一面,形成绝缘性支撑体;
C.除去导电性临时支撑体,将配线转印至绝缘支撑体;
D.除去预设置配线外部连接端子处的绝缘性支撑体,并设置外部连接端子所用透孔;
E.在转印有配线的绝缘性支撑体上装配半导体元件,接通半导体元件端子与配线;
G.用树脂密封半导体元件;
H.在外部连接端子所用透孔中接通配线,形成外部连接端子。
2.一种半导体组件的制造方法,其特征在于,该制造方法包括步骤:
A.在导电性临时支撑体的单面设置配线;
B.在已设有配线的导电性临时支撑体上装配半导体元件,接通半导体元件端子与配线;
C.用树脂密封半导体元件;
D.在导电性临时支撑体的、与装有半导体元件相对应的另一面上预设置配线的外部连接端子处,设置形成与导电性临时支撑体清除条件不同的金属图形。
E.除去已形成金属图形以外的导电性临时支撑体。
3.一种半导体组件的制造方法,其特征在于,该制造方法包括步骤:
A.在绝缘性支撑体的单面设置多组配线;
B.除去预设置配线外部连接端子处的绝缘性支撑体,并设置外部连接端子所用透孔;
C.在已设置多组配线的绝缘性支撑体上装配半导体元件,用焊线接通半导体元件端子与配线;
D.用树脂密封半导体元件;
E.在外部连接端子所用透孔中接通配线,形成外部连接端子;
F.分离每个半导体组件;
所述外部连接端子设置在所述配线上与所述半导体元件端子接通的位置的内侧。
4.一种半导体组件的制造方法,其特征在于,该制造方法包括步骤:
A.除去预设置配线外部连接端子处的绝缘性支撑体,并设置外部连接端子所用透孔;
B.在绝缘性支撑体的单面设置多组配线;
C.在已设置多组配线的绝缘性支撑体上装配半导体元件,用焊线接通半导体元件端子与配线;
D.用树脂密封半导体元件;
E.在外部连接端子所用透孔中接通配线,形成外部连接端子;
F.分离每个半导体组件;
所述外部连接端子设置在所述配线上与所述半导体元件端子接通的位置的内侧。
5.一种半导体组件的制造方法,其特征在于,该制造方法包括步骤:
A.在导电性临时支撑体的单面设置多组配线;
B.为使配置在导电性临时支撑体上多组配线达到所定的单元个数,切断分离导电性临时支撑体,并将设有配线的、已分离的导电性临时支撑体固定在框架;
C.在设有配线的导电性临时支撑体上装配半导体元件,并接通半导体元件端子与配线;
D.用树脂密封半导体元件;
E.除去导电性临时支撑体、露出配线;
F.在预设置已露出配线的外部连接端子处之外,形成绝缘层;
G.在未形成配线绝缘层处,设置外部连接端子;
H.分离每个半导体组件。
6.一种半导体组件的制造方法,其特征在于,该制造方法包括步骤:
A.在绝缘性支撑体的单面设置多组配线;
B.除去预设置配线外部连接端子处的绝缘性支撑体,形成外部连接端子所用透孔;
C.为使配置在绝缘性支撑体上多组配线达到所定的单元个数,切断分离绝缘性支撑体,将设有配线的、已分离的绝缘性支撑体固定于框架;
D.在已设有配线的绝缘性支撑体上装配半导体元件,接通半导体元件端子与配线;
E.用树脂密封半导体元件;
F.在外部连接端子所用透孔中接通配线,形成外部连接端子;
G.分离每个半导体组件。
7.一种半导体组件的制造方法,其特征在于,该半导体组件中的配线在单层配线情况下具有如下两种功能:配线的一面与半导体元件相连的第1连接功能,以及配线的另一面与外部的配线相连的第2连接功能,具有所述构成配线的半导体组件的制造方法包括以下A、B、C和D步骤:
A.将具有耐热性金属箔的绝缘基材的金属箔加工成配线图形;
B.后续工艺中,在第2连接功能部位,设置可从绝缘基材侧抵达配线图形的凹部;
C.在与配线图形面及配线图形相邻近的绝缘基材面上所需的位置上,粘合所需部分已被开孔的框架基材;
D.装配半导体元件,接通半导体元件端子与配线,用树脂密封半导体元件。
8.一种半导体组件的制造方法,其特征在于,该半导体组件中的配线在单层配线的情况下具有如下两种功能:配线的一面与半导体元件相连的第1连接功能,以及配线的另一面与外部配线相连的第2连接功能,具有所述构成配线的半导体组件的制造方法包括以下A、B、C、D和E步骤:
A.将具有耐热性金属箔的绝缘基材的金属箔加工成多组配线图形;
B.后续工艺中,在第2连接功能部位,设置可从绝缘基材侧抵达配线图形的凹部;
C.在与配线图形面及配线图形相邻的绝缘基材面上所需的位置,粘合所需部分已被开孔的第2绝缘基材,形成绝缘支撑体;
D.为使配置在绝缘支撑体上多组配线达到所定的单元个数,切断绝缘支撑体,并将设有配线的、已分离的绝缘支撑体固定在框架;
E.装配半导体元件,接通半导体元件端子与配线,用树脂密封半导体元件。
9.一种半导体组件的制造方法,其特片在于,该制造方法包括步骤:
A.在支撑体的单面设置多组配线;
B.在已形成配线的支撑体上装配多个半导体元件,通过线焊接接通半导体元件端子与配线;
C.通过一体地形成树脂来密封接通的多组半导体元件和配线;
D.除去所需除去的支撑体部分,使所设定的配线部分露出,
E.形成与露出的配线电连接的外部连接端子;
F.分离每个半导体组件;
所述外部连接端子设置在所述配线上与所述半导体元件端子接通的位置的内侧。
10.一种半导体组件的制造方法,其特片在于,该制造方法包括步骤:
A.除去所需除去的支撑体部分,使所设定的配线部分露出;
B.在支撑体的单面设置多组配线;
C.在已形成配线的支撑体上装配多个半导体元件,通过线焊接接通半导体元件端子与配线;
D.通过一体地形成树脂来密封接通的多组半导体元件和配线,
E.形成与露出的配线电连接的外部连接端子;
F.分离每个半导体组件;
所述外部连接端子设置在所述配线上与所述半导体元件端子接通的位置的内侧。
11.如权利要求1至权利要求10中的任何一项所述的半导体组件的制造方法,其特征在于,在对所述半导体元件进行所述树脂密封后,对密封树脂固化物进行加热处理。
12.如权利要求1至权利要求11中的任何一项所述的方法制造的半导体组件。
13.一种用于安装半导体元件的框架的制造方法,其特征在于,所述框架由多个半导体元件安装基片部、连接多个半导体元件安装基片部的连接部以及位置对合标识部组成,所述制造方法包括:
(a)在导电性临时基片上设置半导体元件安装部的配线的工艺过程;
(b)向树脂基材上转印配线的工艺过程;
(c)用腐蚀方法除去导电性临时基片的工艺过程,当除去(c)的导电性临时基片时,保留其一部分,以作为连接部的一部分。
Applications Claiming Priority (12)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP48760/94 | 1994-03-18 | ||
JP4876094 | 1994-03-18 | ||
JP48760/1994 | 1994-03-18 | ||
JP273469/94 | 1994-11-08 | ||
JP273469/1994 | 1994-11-08 | ||
JP27346994 | 1994-11-08 | ||
JP768395 | 1995-01-20 | ||
JP7683/95 | 1995-01-20 | ||
JP7683/1995 | 1995-01-20 | ||
JP5620295 | 1995-03-15 | ||
JP56202/95 | 1995-03-15 | ||
JP56202/1995 | 1995-03-15 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNA031378625A Division CN1516251A (zh) | 1994-03-18 | 1995-03-17 | 半导体组件的制造方法及半导体组件 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1144016A CN1144016A (zh) | 1997-02-26 |
CN1117395C true CN1117395C (zh) | 2003-08-06 |
Family
ID=27454766
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN95192144A Expired - Fee Related CN1117395C (zh) | 1994-03-18 | 1995-03-17 | 半导体组件的制造方法及半导体组件 |
CNA031378625A Pending CN1516251A (zh) | 1994-03-18 | 1995-03-17 | 半导体组件的制造方法及半导体组件 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNA031378625A Pending CN1516251A (zh) | 1994-03-18 | 1995-03-17 | 半导体组件的制造方法及半导体组件 |
Country Status (6)
Country | Link |
---|---|
US (5) | US5976912A (zh) |
EP (4) | EP1213754A3 (zh) |
JP (3) | JP3247384B2 (zh) |
KR (2) | KR100437437B1 (zh) |
CN (2) | CN1117395C (zh) |
WO (1) | WO1995026047A1 (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101740410B (zh) * | 2008-11-13 | 2011-10-05 | 南茂科技股份有限公司 | 芯片封装结构的制程 |
CN101740424B (zh) * | 2008-11-13 | 2011-10-05 | 南茂科技股份有限公司 | 芯片封装结构的制程 |
Families Citing this family (417)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1213754A3 (en) * | 1994-03-18 | 2005-05-25 | Hitachi Chemical Co., Ltd. | Fabrication process of semiconductor package and semiconductor package |
JP4029910B2 (ja) * | 1994-03-18 | 2008-01-09 | 日立化成工業株式会社 | 半導体パッケ−ジの製造法及び半導体パッケ−ジ |
US6465743B1 (en) * | 1994-12-05 | 2002-10-15 | Motorola, Inc. | Multi-strand substrate for ball-grid array assemblies and method |
US5677566A (en) * | 1995-05-08 | 1997-10-14 | Micron Technology, Inc. | Semiconductor chip package |
US6376921B1 (en) | 1995-11-08 | 2002-04-23 | Fujitsu Limited | Semiconductor device, method for fabricating the semiconductor device, lead frame and method for producing the lead frame |
US6072239A (en) * | 1995-11-08 | 2000-06-06 | Fujitsu Limited | Device having resin package with projections |
US6329711B1 (en) * | 1995-11-08 | 2001-12-11 | Fujitsu Limited | Semiconductor device and mounting structure |
US6159770A (en) * | 1995-11-08 | 2000-12-12 | Fujitsu Limited | Method and apparatus for fabricating semiconductor device |
JP3445895B2 (ja) * | 1996-02-28 | 2003-09-08 | 日立化成工業株式会社 | 半導体パッケ−ジ用チップ支持基板 |
US6001671A (en) * | 1996-04-18 | 1999-12-14 | Tessera, Inc. | Methods for manufacturing a semiconductor package having a sacrificial layer |
US6821821B2 (en) * | 1996-04-18 | 2004-11-23 | Tessera, Inc. | Methods for manufacturing resistors using a sacrificial layer |
DE69735588T2 (de) * | 1996-05-27 | 2007-01-11 | Dai Nippon Printing Co., Ltd. | Herstellung eines bauteils für eine halbleiterschaltung |
US5776798A (en) | 1996-09-04 | 1998-07-07 | Motorola, Inc. | Semiconductor package and method thereof |
DE19640304C2 (de) * | 1996-09-30 | 2000-10-12 | Siemens Ag | Chipmodul insbesondere zur Implantation in einen Chipkartenkörper |
JP3608205B2 (ja) | 1996-10-17 | 2005-01-05 | セイコーエプソン株式会社 | 半導体装置及びその製造方法並びに回路基板 |
US6962829B2 (en) * | 1996-10-31 | 2005-11-08 | Amkor Technology, Inc. | Method of making near chip size integrated circuit package |
US5866949A (en) * | 1996-12-02 | 1999-02-02 | Minnesota Mining And Manufacturing Company | Chip scale ball grid array for integrated circuit packaging |
US5990545A (en) * | 1996-12-02 | 1999-11-23 | 3M Innovative Properties Company | Chip scale ball grid array for integrated circuit package |
US6635514B1 (en) * | 1996-12-12 | 2003-10-21 | Tessera, Inc. | Compliant package with conductive elastomeric posts |
US5907769A (en) * | 1996-12-30 | 1999-05-25 | Micron Technology, Inc. | Leads under chip in conventional IC package |
JP2982729B2 (ja) * | 1997-01-16 | 1999-11-29 | 日本電気株式会社 | 半導体装置 |
SG63803A1 (en) * | 1997-01-23 | 1999-03-30 | Toray Industries | Epoxy-resin composition to seal semiconductors and resin-sealed semiconductor device |
US6583444B2 (en) * | 1997-02-18 | 2003-06-24 | Tessera, Inc. | Semiconductor packages having light-sensitive chips |
KR100237328B1 (ko) * | 1997-02-26 | 2000-01-15 | 김규현 | 반도체 패키지의 구조 및 제조방법 |
JPH10284525A (ja) * | 1997-04-03 | 1998-10-23 | Shinko Electric Ind Co Ltd | 半導体装置の製造方法 |
KR100568571B1 (ko) * | 1997-05-09 | 2006-04-07 | 시티즌 도케이 가부시키가이샤 | 반도체 패키지의 제조 방법 및 집합 회로 기판 |
FR2764111A1 (fr) * | 1997-06-03 | 1998-12-04 | Sgs Thomson Microelectronics | Procede de fabrication de boitiers semi-conducteurs comprenant un circuit integre |
JP3639088B2 (ja) * | 1997-06-06 | 2005-04-13 | 株式会社ルネサステクノロジ | 半導体装置及び配線テープ |
US6173490B1 (en) * | 1997-08-20 | 2001-01-16 | National Semiconductor Corporation | Method for forming a panel of packaged integrated circuits |
JP2954110B2 (ja) * | 1997-09-26 | 1999-09-27 | 九州日本電気株式会社 | Csp型半導体装置及びその製造方法 |
US5888850A (en) * | 1997-09-29 | 1999-03-30 | International Business Machines Corporation | Method for providing a protective coating and electronic package utilizing same |
US6028354A (en) | 1997-10-14 | 2000-02-22 | Amkor Technology, Inc. | Microelectronic device package having a heat sink structure for increasing the thermal conductivity of the package |
DE69839896D1 (de) * | 1997-10-29 | 2008-09-25 | Hitachi Chemical Co Ltd | Siloxanmodifizierte Polyamidharzzusammensetzungsklebefolie, CSP Leiterplatte und Folie und hergestelltes Halbleiterbauelement |
JPH11163022A (ja) * | 1997-11-28 | 1999-06-18 | Sony Corp | 半導体装置、その製造方法及び電子機器 |
JP3819574B2 (ja) | 1997-12-25 | 2006-09-13 | 三洋電機株式会社 | 半導体装置の製造方法 |
JPH11186432A (ja) * | 1997-12-25 | 1999-07-09 | Canon Inc | 半導体パッケージ及びその製造方法 |
JPH11233684A (ja) * | 1998-02-17 | 1999-08-27 | Seiko Epson Corp | 半導体装置用基板、半導体装置及びその製造方法並びに電子機器 |
TW434760B (en) * | 1998-02-20 | 2001-05-16 | United Microelectronics Corp | Interlaced grid type package structure and its manufacturing method |
JP3481117B2 (ja) * | 1998-02-25 | 2003-12-22 | 富士通株式会社 | 半導体装置及びその製造方法 |
US6326239B1 (en) * | 1998-04-07 | 2001-12-04 | Denso Corporation | Mounting structure of electronic parts and mounting method of electronic parts |
US6933594B2 (en) * | 1998-06-10 | 2005-08-23 | Asat Ltd. | Leadless plastic chip carrier with etch back pad singulation |
US6989294B1 (en) | 1998-06-10 | 2006-01-24 | Asat, Ltd. | Leadless plastic chip carrier with etch back pad singulation |
US6294100B1 (en) | 1998-06-10 | 2001-09-25 | Asat Ltd | Exposed die leadless plastic chip carrier |
US7270867B1 (en) | 1998-06-10 | 2007-09-18 | Asat Ltd. | Leadless plastic chip carrier |
US6872661B1 (en) | 1998-06-10 | 2005-03-29 | Asat Ltd. | Leadless plastic chip carrier with etch back pad singulation and die attach pad array |
US8330270B1 (en) | 1998-06-10 | 2012-12-11 | Utac Hong Kong Limited | Integrated circuit package having a plurality of spaced apart pad portions |
US7226811B1 (en) | 1998-06-10 | 2007-06-05 | Asat Ltd. | Process for fabricating a leadless plastic chip carrier |
US6635957B2 (en) | 1998-06-10 | 2003-10-21 | Asat Ltd. | Leadless plastic chip carrier with etch back pad singulation and die attach pad array |
US7271032B1 (en) | 1998-06-10 | 2007-09-18 | Asat Ltd. | Leadless plastic chip carrier with etch back pad singulation |
US7247526B1 (en) | 1998-06-10 | 2007-07-24 | Asat Ltd. | Process for fabricating an integrated circuit package |
US6498099B1 (en) * | 1998-06-10 | 2002-12-24 | Asat Ltd. | Leadless plastic chip carrier with etch back pad singulation |
US6229200B1 (en) | 1998-06-10 | 2001-05-08 | Asat Limited | Saw-singulated leadless plastic chip carrier |
US7049177B1 (en) | 2004-01-28 | 2006-05-23 | Asat Ltd. | Leadless plastic chip carrier with standoff contacts and die attach pad |
US6585905B1 (en) * | 1998-06-10 | 2003-07-01 | Asat Ltd. | Leadless plastic chip carrier with partial etch die attach pad |
JP2000156435A (ja) * | 1998-06-22 | 2000-06-06 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US6143981A (en) | 1998-06-24 | 2000-11-07 | Amkor Technology, Inc. | Plastic integrated circuit package and method and leadframe for making the package |
DE19830159A1 (de) * | 1998-07-06 | 2000-01-20 | Siemens Ag | Chipmodul mit einem Substrat als Träger für eine ein- oder mehrlagige hochdichte Verdrahtung (High Density Interconnect) |
US6092281A (en) | 1998-08-28 | 2000-07-25 | Amkor Technology, Inc. | Electromagnetic interference shield driver and method |
JP4073098B2 (ja) * | 1998-11-18 | 2008-04-09 | 三洋電機株式会社 | 半導体装置の製造方法 |
JP3169919B2 (ja) * | 1998-12-21 | 2001-05-28 | 九州日本電気株式会社 | ボールグリッドアレイ型半導体装置及びその製造方法 |
KR20000071383A (ko) | 1999-02-26 | 2000-11-25 | 마쯔노고오지 | 배선층 전사용 복합재와 그 제조방법 및 장치 |
US20020145207A1 (en) * | 1999-03-05 | 2002-10-10 | Anderson Sidney Larry | Method and structure for integrated circuit package |
US6784541B2 (en) | 2000-01-27 | 2004-08-31 | Hitachi, Ltd. | Semiconductor module and mounting method for same |
JP4078033B2 (ja) * | 1999-03-26 | 2008-04-23 | 株式会社ルネサステクノロジ | 半導体モジュールの実装方法 |
US6310390B1 (en) | 1999-04-08 | 2001-10-30 | Micron Technology, Inc. | BGA package and method of fabrication |
JP3521325B2 (ja) * | 1999-07-30 | 2004-04-19 | シャープ株式会社 | 樹脂封止型半導体装置の製造方法 |
JP3544895B2 (ja) * | 1999-07-30 | 2004-07-21 | シャープ株式会社 | 樹脂封止型半導体装置及びその製造方法 |
JP3462806B2 (ja) * | 1999-08-06 | 2003-11-05 | 三洋電機株式会社 | 半導体装置およびその製造方法 |
US6350664B1 (en) * | 1999-09-02 | 2002-02-26 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method of manufacturing the same |
WO2001020661A1 (fr) * | 1999-09-10 | 2001-03-22 | Nitto Denko Corporation | Plaquette semi-conductrice dotee d'un film anisotrope et procede de fabrication correspondant |
JP2001156212A (ja) | 1999-09-16 | 2001-06-08 | Nec Corp | 樹脂封止型半導体装置及びその製造方法 |
KR20010037247A (ko) * | 1999-10-15 | 2001-05-07 | 마이클 디. 오브라이언 | 반도체패키지 |
US6329220B1 (en) | 1999-11-23 | 2001-12-11 | Micron Technology, Inc. | Packages for semiconductor die |
JP3706533B2 (ja) | 2000-09-20 | 2005-10-12 | 三洋電機株式会社 | 半導体装置および半導体モジュール |
US7173336B2 (en) * | 2000-01-31 | 2007-02-06 | Sanyo Electric Co., Ltd. | Hybrid integrated circuit device |
EP1122778A3 (en) * | 2000-01-31 | 2004-04-07 | Sanyo Electric Co., Ltd. | Circuit device and manufacturing method of circuit device |
US7091606B2 (en) * | 2000-01-31 | 2006-08-15 | Sanyo Electric Co., Ltd. | Circuit device and manufacturing method of circuit device and semiconductor module |
JP3778773B2 (ja) * | 2000-05-09 | 2006-05-24 | 三洋電機株式会社 | 板状体および半導体装置の製造方法 |
US6656765B1 (en) | 2000-02-02 | 2003-12-02 | Amkor Technology, Inc. | Fabricating very thin chip size semiconductor packages |
DE10008203B4 (de) * | 2000-02-23 | 2008-02-07 | Vishay Semiconductor Gmbh | Verfahren zum Herstellen elektronischer Halbleiterbauelemente |
US6562660B1 (en) * | 2000-03-08 | 2003-05-13 | Sanyo Electric Co., Ltd. | Method of manufacturing the circuit device and circuit device |
SG106050A1 (en) * | 2000-03-13 | 2004-09-30 | Megic Corp | Method of manufacture and identification of semiconductor chip marked for identification with internal marking indicia and protection thereof by non-black layer and device produced thereby |
JP2001267459A (ja) * | 2000-03-22 | 2001-09-28 | Mitsubishi Electric Corp | 半導体装置 |
JP2001339011A (ja) * | 2000-03-24 | 2001-12-07 | Shinko Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2001308095A (ja) * | 2000-04-19 | 2001-11-02 | Toyo Kohan Co Ltd | 半導体装置およびその製造方法 |
US7042068B2 (en) | 2000-04-27 | 2006-05-09 | Amkor Technology, Inc. | Leadframe and semiconductor package made using the leadframe |
JP3883784B2 (ja) * | 2000-05-24 | 2007-02-21 | 三洋電機株式会社 | 板状体および半導体装置の製造方法 |
WO2001093327A1 (en) * | 2000-06-02 | 2001-12-06 | Tyco Electronics Amp Gmbh | Semiconductor component, electrically conductive structure therefor, and process for production thereof |
US6611053B2 (en) * | 2000-06-08 | 2003-08-26 | Micron Technology, Inc. | Protective structure for bond wires |
TW506236B (en) * | 2000-06-09 | 2002-10-11 | Sanyo Electric Co | Method for manufacturing an illumination device |
TW507482B (en) * | 2000-06-09 | 2002-10-21 | Sanyo Electric Co | Light emitting device, its manufacturing process, and lighting device using such a light-emitting device |
US6790760B1 (en) * | 2000-07-21 | 2004-09-14 | Agere Systems Inc. | Method of manufacturing an integrated circuit package |
US6541310B1 (en) * | 2000-07-24 | 2003-04-01 | Siliconware Precision Industries Co., Ltd. | Method of fabricating a thin and fine ball-grid array package with embedded heat spreader |
KR100414479B1 (ko) * | 2000-08-09 | 2004-01-07 | 주식회사 코스타트반도체 | 반도체 패키징 공정의 이식성 도전패턴을 갖는 테이프 및그 제조방법 |
US6559537B1 (en) * | 2000-08-31 | 2003-05-06 | Micron Technology, Inc. | Ball grid array packages with thermally conductive containers |
US6909178B2 (en) * | 2000-09-06 | 2005-06-21 | Sanyo Electric Co., Ltd. | Semiconductor device and method of manufacturing the same |
US6624005B1 (en) | 2000-09-06 | 2003-09-23 | Amkor Technology, Inc. | Semiconductor memory cards and method of making same |
CN1265451C (zh) * | 2000-09-06 | 2006-07-19 | 三洋电机株式会社 | 半导体装置及其制造方法 |
TW511422B (en) | 2000-10-02 | 2002-11-21 | Sanyo Electric Co | Method for manufacturing circuit device |
JP4589519B2 (ja) * | 2000-11-09 | 2010-12-01 | ルネサスエレクトロニクス株式会社 | 半導体回路部品の製造方法 |
JP4354109B2 (ja) * | 2000-11-15 | 2009-10-28 | Okiセミコンダクタ株式会社 | 半導体装置及びその製造方法 |
US7434305B2 (en) | 2000-11-28 | 2008-10-14 | Knowles Electronics, Llc. | Method of manufacturing a microphone |
US8617934B1 (en) | 2000-11-28 | 2013-12-31 | Knowles Electronics, Llc | Methods of manufacture of top port multi-part surface mount silicon condenser microphone packages |
EP1346411A2 (en) | 2000-12-01 | 2003-09-24 | Broadcom Corporation | Thermally and electrically enhanced ball grid array packaging |
US6770959B2 (en) * | 2000-12-15 | 2004-08-03 | Silconware Precision Industries Co., Ltd. | Semiconductor package without substrate and method of manufacturing same |
US6906414B2 (en) | 2000-12-22 | 2005-06-14 | Broadcom Corporation | Ball grid array package with patterned stiffener layer |
US7161239B2 (en) | 2000-12-22 | 2007-01-09 | Broadcom Corporation | Ball grid array package enhanced with a thermal and electrical connector |
US20020079572A1 (en) * | 2000-12-22 | 2002-06-27 | Khan Reza-Ur Rahman | Enhanced die-up ball grid array and method for making the same |
US7132744B2 (en) | 2000-12-22 | 2006-11-07 | Broadcom Corporation | Enhanced die-up ball grid array packages and method for making the same |
TW473947B (en) * | 2001-02-20 | 2002-01-21 | Siliconware Precision Industries Co Ltd | Substrate structure of semiconductor packaging article |
TW548843B (en) * | 2001-02-28 | 2003-08-21 | Fujitsu Ltd | Semiconductor device and method for making the same |
US6545345B1 (en) | 2001-03-20 | 2003-04-08 | Amkor Technology, Inc. | Mounting for a package containing a chip |
TW530455B (en) | 2001-04-19 | 2003-05-01 | Sanyo Electric Co | Switch circuit device of compound semiconductor |
US7259448B2 (en) * | 2001-05-07 | 2007-08-21 | Broadcom Corporation | Die-up ball grid array package with a heat spreader and method for making the same |
KR100868419B1 (ko) | 2001-06-07 | 2008-11-11 | 가부시끼가이샤 르네사스 테크놀로지 | 반도체장치 및 그 제조방법 |
KR100434201B1 (ko) | 2001-06-15 | 2004-06-04 | 동부전자 주식회사 | 반도체 패키지 및 그 제조 방법 |
KR100378285B1 (en) | 2001-06-15 | 2003-03-29 | Dongbu Electronics Co Ltd | Semiconductor package and fabricating method thereof |
JP2003007917A (ja) * | 2001-06-19 | 2003-01-10 | Sanyo Electric Co Ltd | 回路装置の製造方法 |
JP4761662B2 (ja) * | 2001-07-17 | 2011-08-31 | 三洋電機株式会社 | 回路装置の製造方法 |
DE10153615C1 (de) * | 2001-10-31 | 2003-07-24 | Osram Opto Semiconductors Gmbh | Verfahren zur Herstellung von elektronischen Bauteilen |
US6873059B2 (en) | 2001-11-13 | 2005-03-29 | Texas Instruments Incorporated | Semiconductor package with metal foil attachment film |
JP3920629B2 (ja) * | 2001-11-15 | 2007-05-30 | 三洋電機株式会社 | 半導体装置 |
US6664615B1 (en) | 2001-11-20 | 2003-12-16 | National Semiconductor Corporation | Method and apparatus for lead-frame based grid array IC packaging |
JP4173346B2 (ja) * | 2001-12-14 | 2008-10-29 | 株式会社ルネサステクノロジ | 半導体装置 |
US6879039B2 (en) | 2001-12-18 | 2005-04-12 | Broadcom Corporation | Ball grid array package substrates and method of making the same |
US6861750B2 (en) * | 2002-02-01 | 2005-03-01 | Broadcom Corporation | Ball grid array package with multiple interposers |
US6825108B2 (en) | 2002-02-01 | 2004-11-30 | Broadcom Corporation | Ball grid array package fabrication with IC die support structures |
US7550845B2 (en) * | 2002-02-01 | 2009-06-23 | Broadcom Corporation | Ball grid array package with separated stiffener layer |
JP3666591B2 (ja) * | 2002-02-01 | 2005-06-29 | 株式会社トッパンNecサーキットソリューションズ | 半導体チップ搭載用基板の製造方法 |
US6876553B2 (en) | 2002-03-21 | 2005-04-05 | Broadcom Corporation | Enhanced die-up ball grid array package with two substrates |
US7196415B2 (en) | 2002-03-22 | 2007-03-27 | Broadcom Corporation | Low voltage drop and high thermal performance ball grid array package |
DE10213296B9 (de) * | 2002-03-25 | 2007-04-19 | Infineon Technologies Ag | Elektronisches Bauteil mit einem Halbleiterchip, Verfahren zu seiner Herstellung und Verfahren zur Herstellung eines Nutzens |
US6608366B1 (en) | 2002-04-15 | 2003-08-19 | Harry J. Fogelson | Lead frame with plated end leads |
SG109495A1 (en) * | 2002-04-16 | 2005-03-30 | Micron Technology Inc | Semiconductor packages with leadfame grid arrays and components and methods for making the same |
EP1357606A1 (en) * | 2002-04-22 | 2003-10-29 | Scientek Corporation | Image sensor semiconductor package |
EP1357595A1 (en) * | 2002-04-22 | 2003-10-29 | Scientek Corporation | Ball grid array semiconductor package with resin coated core |
DE10224124A1 (de) * | 2002-05-29 | 2003-12-18 | Infineon Technologies Ag | Elektronisches Bauteil mit äußeren Flächenkontakten und Verfahren zu seiner Herstellung |
DE10237084A1 (de) * | 2002-08-05 | 2004-02-19 | Osram Opto Semiconductors Gmbh | Verfahren zum Herstellen eines elektrischen Leiterrahmens und Verfahren zum Herstellen eines oberflächenmontierbaren Halbleiterbauelements |
DE10240461A1 (de) * | 2002-08-29 | 2004-03-11 | Infineon Technologies Ag | Universelles Gehäuse für ein elektronisches Bauteil mit Halbleiterchip und Verfahren zu seiner Herstellung |
US7732914B1 (en) | 2002-09-03 | 2010-06-08 | Mclellan Neil | Cavity-type integrated circuit package |
JP2004119729A (ja) * | 2002-09-26 | 2004-04-15 | Sanyo Electric Co Ltd | 回路装置の製造方法 |
US7723210B2 (en) | 2002-11-08 | 2010-05-25 | Amkor Technology, Inc. | Direct-write wafer level chip scale package |
US6905914B1 (en) | 2002-11-08 | 2005-06-14 | Amkor Technology, Inc. | Wafer level package and fabrication method |
JP2004165279A (ja) * | 2002-11-11 | 2004-06-10 | Mitsui Mining & Smelting Co Ltd | 電子部品実装用フィルムキャリアテープ |
US6798047B1 (en) | 2002-12-26 | 2004-09-28 | Amkor Technology, Inc. | Pre-molded leadframe |
JP3897704B2 (ja) | 2003-01-16 | 2007-03-28 | 松下電器産業株式会社 | リードフレーム |
TWI241000B (en) * | 2003-01-21 | 2005-10-01 | Siliconware Precision Industries Co Ltd | Semiconductor package and fabricating method thereof |
JP4245370B2 (ja) * | 2003-02-21 | 2009-03-25 | 大日本印刷株式会社 | 半導体装置の製造方法 |
US6750545B1 (en) | 2003-02-28 | 2004-06-15 | Amkor Technology, Inc. | Semiconductor package capable of die stacking |
TW587325B (en) * | 2003-03-05 | 2004-05-11 | Advanced Semiconductor Eng | Semiconductor chip package and method for manufacturing the same |
JP3772984B2 (ja) * | 2003-03-13 | 2006-05-10 | セイコーエプソン株式会社 | 電子装置及びその製造方法、回路基板並びに電子機器 |
US6794740B1 (en) | 2003-03-13 | 2004-09-21 | Amkor Technology, Inc. | Leadframe package for semiconductor devices |
JP3918936B2 (ja) * | 2003-03-13 | 2007-05-23 | セイコーエプソン株式会社 | 電子装置及びその製造方法、回路基板並びに電子機器 |
JP2004281538A (ja) * | 2003-03-13 | 2004-10-07 | Seiko Epson Corp | 電子装置及びその製造方法、回路基板並びに電子機器 |
WO2004097896A2 (en) * | 2003-04-26 | 2004-11-11 | Freescale Semiconductor, Inc. | A packaged integrated circuit having a heat spreader and method therefor |
AU2003231137A1 (en) * | 2003-04-29 | 2004-11-26 | Semiconductor Components Industries L.L.C. | Method of making a low profile packaged semiconductor device |
KR100629887B1 (ko) * | 2003-05-14 | 2006-09-28 | 이규한 | 금속 칩스케일 반도체패키지 및 그 제조방법 |
JP2004349316A (ja) * | 2003-05-20 | 2004-12-09 | Renesas Technology Corp | 半導体装置及びその製造方法 |
US6894376B1 (en) * | 2003-06-09 | 2005-05-17 | National Semiconductor Corporation | Leadless microelectronic package and a method to maximize the die size in the package |
JP3897115B2 (ja) * | 2003-07-09 | 2007-03-22 | 信越化学工業株式会社 | 半導体素子の封止方法 |
DE10334576B4 (de) * | 2003-07-28 | 2007-04-05 | Infineon Technologies Ag | Verfahren zum Herstellen eines Halbleiterbauelements mit einem Kunststoffgehäuse |
US20050023682A1 (en) * | 2003-07-31 | 2005-02-03 | Morio Nakao | High reliability chip scale package |
US6903449B2 (en) * | 2003-08-01 | 2005-06-07 | Micron Technology, Inc. | Semiconductor component having chip on board leadframe |
JP3838572B2 (ja) * | 2003-09-03 | 2006-10-25 | 松下電器産業株式会社 | 固体撮像装置およびその製造方法 |
US7033517B1 (en) | 2003-09-15 | 2006-04-25 | Asat Ltd. | Method of fabricating a leadless plastic chip carrier |
US7009286B1 (en) | 2004-01-15 | 2006-03-07 | Asat Ltd. | Thin leadless plastic chip carrier |
US7872686B2 (en) * | 2004-02-20 | 2011-01-18 | Flextronics International Usa, Inc. | Integrated lens and chip assembly for a digital camera |
US7732259B2 (en) * | 2004-02-26 | 2010-06-08 | Infineon Technologies Ag | Non-leaded semiconductor package and a method to assemble the same |
US11081370B2 (en) * | 2004-03-23 | 2021-08-03 | Amkor Technology Singapore Holding Pte. Ltd. | Methods of manufacturing an encapsulated semiconductor device |
JP5004410B2 (ja) * | 2004-04-26 | 2012-08-22 | Towa株式会社 | 光素子の樹脂封止成形方法および樹脂封止成形装置 |
DE102004020580A1 (de) * | 2004-04-27 | 2005-11-17 | Infineon Technologies Ag | Verfahren zur Herstellung eines BGA-Chipmoduls und BGA-Chipmodul |
US7091581B1 (en) | 2004-06-14 | 2006-08-15 | Asat Limited | Integrated circuit package and process for fabricating the same |
US7411289B1 (en) | 2004-06-14 | 2008-08-12 | Asat Ltd. | Integrated circuit package with partially exposed contact pads and process for fabricating the same |
US7482686B2 (en) | 2004-06-21 | 2009-01-27 | Braodcom Corporation | Multipiece apparatus for thermal and electromagnetic interference (EMI) shielding enhancement in die-up array packages and method of making the same |
US7411281B2 (en) | 2004-06-21 | 2008-08-12 | Broadcom Corporation | Integrated circuit device package having both wire bond and flip-chip interconnections and method of making the same |
US7432586B2 (en) * | 2004-06-21 | 2008-10-07 | Broadcom Corporation | Apparatus and method for thermal and electromagnetic interference (EMI) shielding enhancement in die-up array packages |
WO2006004671A2 (en) * | 2004-06-25 | 2006-01-12 | Tessera, Inc. | Microelectronic package structure with spherical contact pins |
JP4596846B2 (ja) * | 2004-07-29 | 2010-12-15 | 三洋電機株式会社 | 回路装置の製造方法 |
US7135781B2 (en) * | 2004-08-10 | 2006-11-14 | Texas Instruments Incorporated | Low profile, chip-scale package and method of fabrication |
US7632747B2 (en) * | 2004-08-19 | 2009-12-15 | Micron Technology, Inc. | Conductive structures for microfeature devices and methods for fabricating microfeature devices |
US7786591B2 (en) | 2004-09-29 | 2010-08-31 | Broadcom Corporation | Die down ball grid array package |
US7595225B1 (en) | 2004-10-05 | 2009-09-29 | Chun Ho Fan | Leadless plastic chip carrier with contact standoff |
JP5128047B2 (ja) * | 2004-10-07 | 2013-01-23 | Towa株式会社 | 光デバイス及び光デバイスの生産方法 |
CN101053079A (zh) | 2004-11-03 | 2007-10-10 | 德塞拉股份有限公司 | 堆叠式封装的改进 |
US7358119B2 (en) * | 2005-01-12 | 2008-04-15 | Asat Ltd. | Thin array plastic package without die attach pad and process for fabricating the same |
US7394151B2 (en) * | 2005-02-15 | 2008-07-01 | Alpha & Omega Semiconductor Limited | Semiconductor package with plated connection |
DE102005007486B4 (de) * | 2005-02-17 | 2011-07-14 | Infineon Technologies AG, 81669 | Halbleiterbauteil mit oberflächenmontierbarem Gehäuse, Montageanordnung und Verfahren zur Herstellung desselben |
US7589407B2 (en) * | 2005-04-11 | 2009-09-15 | Stats Chippac Ltd. | Semiconductor multipackage module including tape substrate land grid array package stacked over ball grid array package |
US7298052B2 (en) * | 2005-04-22 | 2007-11-20 | Stats Chippac Ltd. | Micro chip-scale-package system |
US7588992B2 (en) * | 2005-06-14 | 2009-09-15 | Intel Corporation | Integrated thin-film capacitor with etch-stop layer, process of making same, and packages containing same |
US7556984B2 (en) * | 2005-06-17 | 2009-07-07 | Boardtek Electronics Corp. | Package structure of chip and the package method thereof |
US20060289976A1 (en) * | 2005-06-23 | 2006-12-28 | Intel Corporation | Pre-patterned thin film capacitor and method for embedding same in a package substrate |
US7985357B2 (en) * | 2005-07-12 | 2011-07-26 | Towa Corporation | Method of resin-sealing and molding an optical device |
US7348663B1 (en) | 2005-07-15 | 2008-03-25 | Asat Ltd. | Integrated circuit package and method for fabricating same |
US7803667B2 (en) * | 2005-07-21 | 2010-09-28 | Chipmos Technologies Inc. | Manufacturing process for a quad flat non-leaded chip package structure |
US7851270B2 (en) * | 2005-07-21 | 2010-12-14 | Chipmos Technologies Inc. | Manufacturing process for a chip package structure |
US7851262B2 (en) * | 2005-07-21 | 2010-12-14 | Chipmos Technologies Inc. | Manufacturing process for a chip package structure |
US7795079B2 (en) * | 2005-07-21 | 2010-09-14 | Chipmos Technologies Inc. | Manufacturing process for a quad flat non-leaded chip package structure |
TWI255561B (en) * | 2005-07-21 | 2006-05-21 | Chipmos Technologies Inc | Manufacturing process for chip package without core |
US20090068797A1 (en) * | 2005-07-21 | 2009-03-12 | Chipmos Technologies Inc. | Manufacturing process for a quad flat non-leaded chip package structure |
US7803666B2 (en) * | 2005-07-21 | 2010-09-28 | Chipmos Technologies Inc. | Manufacturing process for a Quad Flat Non-leaded chip package structure |
US7790514B2 (en) * | 2005-07-21 | 2010-09-07 | Chipmos Technologies Inc. | Manufacturing process for a chip package structure |
TWI305389B (en) * | 2005-09-05 | 2009-01-11 | Advanced Semiconductor Eng | Matrix package substrate process |
JP2007081232A (ja) * | 2005-09-15 | 2007-03-29 | Renesas Technology Corp | 半導体装置の製造方法 |
US7410830B1 (en) | 2005-09-26 | 2008-08-12 | Asat Ltd | Leadless plastic chip carrier and method of fabricating same |
US7572681B1 (en) | 2005-12-08 | 2009-08-11 | Amkor Technology, Inc. | Embedded electronic component package |
US20070138240A1 (en) * | 2005-12-15 | 2007-06-21 | Aleksandra Djordjevic | Method for forming leadframe assemblies |
US8058101B2 (en) | 2005-12-23 | 2011-11-15 | Tessera, Inc. | Microelectronic packages and methods therefor |
JP2007207921A (ja) | 2006-01-31 | 2007-08-16 | Stanley Electric Co Ltd | 表面実装型光半導体デバイスの製造方法 |
US8461694B1 (en) | 2006-04-28 | 2013-06-11 | Utac Thai Limited | Lead frame ball grid array with traces under die having interlocking features |
US8310060B1 (en) | 2006-04-28 | 2012-11-13 | Utac Thai Limited | Lead frame land grid array |
US8492906B2 (en) | 2006-04-28 | 2013-07-23 | Utac Thai Limited | Lead frame ball grid array with traces under die |
US8487451B2 (en) | 2006-04-28 | 2013-07-16 | Utac Thai Limited | Lead frame land grid array with routing connector trace under unit |
US8460970B1 (en) | 2006-04-28 | 2013-06-11 | Utac Thai Limited | Lead frame ball grid array with traces under die having interlocking features |
JP4799385B2 (ja) * | 2006-05-11 | 2011-10-26 | パナソニック株式会社 | 樹脂封止型半導体装置の製造方法およびそのための配線基板 |
US8183680B2 (en) | 2006-05-16 | 2012-05-22 | Broadcom Corporation | No-lead IC packages having integrated heat spreader for electromagnetic interference (EMI) shielding and thermal enhancement |
US7902660B1 (en) | 2006-05-24 | 2011-03-08 | Amkor Technology, Inc. | Substrate for semiconductor device and manufacturing method thereof |
JP2007317822A (ja) * | 2006-05-25 | 2007-12-06 | Sony Corp | 基板処理方法及び半導体装置の製造方法 |
US8092102B2 (en) * | 2006-05-31 | 2012-01-10 | Flextronics Ap Llc | Camera module with premolded lens housing and method of manufacture |
US7638867B2 (en) * | 2006-06-02 | 2009-12-29 | Intel Corporation | Microelectronic package having solder-filled through-vias |
US7968998B1 (en) | 2006-06-21 | 2011-06-28 | Amkor Technology, Inc. | Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package |
TWI314774B (en) * | 2006-07-11 | 2009-09-11 | Siliconware Precision Industries Co Ltd | Semiconductor package and fabrication method thereof |
US9281218B2 (en) * | 2006-08-30 | 2016-03-08 | United Test And Assembly Center Ltd. | Method of producing a semiconductor package |
US8101464B2 (en) | 2006-08-30 | 2012-01-24 | Micron Technology, Inc. | Microelectronic devices and methods for manufacturing microelectronic devices |
US8125077B2 (en) * | 2006-09-26 | 2012-02-28 | Utac Thai Limited | Package with heat transfer |
US8013437B1 (en) | 2006-09-26 | 2011-09-06 | Utac Thai Limited | Package with heat transfer |
MY143209A (en) * | 2006-10-06 | 2011-03-31 | Hitachi Chemical Co Ltd | Liquid resin composition for electronic part sealing, and electronic part apparatus utilizing the same |
US7704800B2 (en) * | 2006-11-06 | 2010-04-27 | Broadcom Corporation | Semiconductor assembly with one metal layer after base metal removal |
KR100814830B1 (ko) * | 2006-11-22 | 2008-03-20 | 삼성에스디아이 주식회사 | 플라즈마 표시 장치 및 이의 구동방법 |
US9761435B1 (en) | 2006-12-14 | 2017-09-12 | Utac Thai Limited | Flip chip cavity package |
US9711343B1 (en) | 2006-12-14 | 2017-07-18 | Utac Thai Limited | Molded leadframe substrate semiconductor package |
US20080188020A1 (en) * | 2007-02-05 | 2008-08-07 | Kuo Wei-Min | Method of LED packaging on transparent flexible film |
US7927920B2 (en) * | 2007-02-15 | 2011-04-19 | Headway Technologies, Inc. | Method of manufacturing electronic component package, and wafer and substructure used for manufacturing electronic component package |
JP4605177B2 (ja) * | 2007-04-20 | 2011-01-05 | 日立化成工業株式会社 | 半導体搭載基板 |
US7816176B2 (en) * | 2007-05-29 | 2010-10-19 | Headway Technologies, Inc. | Method of manufacturing electronic component package |
US8365397B2 (en) | 2007-08-02 | 2013-02-05 | Em Research, Inc. | Method for producing a circuit board comprising a lead frame |
US7790512B1 (en) | 2007-11-06 | 2010-09-07 | Utac Thai Limited | Molded leadframe substrate semiconductor package |
US20090196999A1 (en) * | 2007-12-12 | 2009-08-06 | Rohm And Haas Electronic Materials Llc | Adhesion promotion |
US8488046B2 (en) | 2007-12-27 | 2013-07-16 | Digitaloptics Corporation | Configurable tele wide module |
JP5110441B2 (ja) * | 2008-01-15 | 2012-12-26 | 大日本印刷株式会社 | 半導体装置用配線部材、半導体装置用複合配線部材、および樹脂封止型半導体装置 |
US8063470B1 (en) | 2008-05-22 | 2011-11-22 | Utac Thai Limited | Method and apparatus for no lead semiconductor package |
US20100084748A1 (en) * | 2008-06-04 | 2010-04-08 | National Semiconductor Corporation | Thin foil for use in packaging integrated circuits |
US8375577B2 (en) * | 2008-06-04 | 2013-02-19 | National Semiconductor Corporation | Method of making foil based semiconductor package |
US7836586B2 (en) * | 2008-08-21 | 2010-11-23 | National Semiconductor Corporation | Thin foil semiconductor package |
US9947605B2 (en) * | 2008-09-04 | 2018-04-17 | UTAC Headquarters Pte. Ltd. | Flip chip cavity package |
JP5629969B2 (ja) * | 2008-09-29 | 2014-11-26 | 凸版印刷株式会社 | リードフレーム型基板の製造方法と半導体装置の製造方法 |
CN101740404B (zh) * | 2008-11-05 | 2011-09-28 | 矽品精密工业股份有限公司 | 一种半导体封装件的结构以及其制法 |
TWI414048B (zh) * | 2008-11-07 | 2013-11-01 | Advanpack Solutions Pte Ltd | 半導體封裝件與其製造方法 |
CN101740406B (zh) * | 2008-11-20 | 2012-12-26 | 南茂科技股份有限公司 | 四方扁平无引脚封装的制造方法 |
KR101030356B1 (ko) * | 2008-12-08 | 2011-04-20 | 삼성전기주식회사 | 반도체 패키지의 제조 방법 |
TWI372454B (en) * | 2008-12-09 | 2012-09-11 | Advanced Semiconductor Eng | Quad flat non-leaded package and manufacturing method thereof |
KR20100071485A (ko) * | 2008-12-19 | 2010-06-29 | 삼성전기주식회사 | 웨이퍼 레벨 패키지의 제조방법 |
JP5058144B2 (ja) * | 2008-12-25 | 2012-10-24 | 新光電気工業株式会社 | 半導体素子の樹脂封止方法 |
TWI393193B (zh) * | 2009-01-15 | 2013-04-11 | Chipmos Technologies Inc | 晶片封裝結構的製程 |
TWI387015B (zh) * | 2009-01-15 | 2013-02-21 | Chipmos Technologies Inc | 晶片封裝結構的製程 |
US9899349B2 (en) | 2009-01-29 | 2018-02-20 | Semiconductor Components Industries, Llc | Semiconductor packages and related methods |
US10199311B2 (en) | 2009-01-29 | 2019-02-05 | Semiconductor Components Industries, Llc | Leadless semiconductor packages, leadframes therefor, and methods of making |
US8071427B2 (en) * | 2009-01-29 | 2011-12-06 | Semiconductor Components Industries, Llc | Method for manufacturing a semiconductor component and structure therefor |
US10163766B2 (en) | 2016-11-21 | 2018-12-25 | Semiconductor Components Industries, Llc | Methods of forming leadless semiconductor packages with plated leadframes and wettable flanks |
US8569877B2 (en) * | 2009-03-12 | 2013-10-29 | Utac Thai Limited | Metallic solderability preservation coating on metal part of semiconductor package to prevent oxide |
US20100289132A1 (en) * | 2009-05-13 | 2010-11-18 | Shih-Fu Huang | Substrate having embedded single patterned metal layer, and package applied with the same, and methods of manufacturing of the substrate and package |
US8367473B2 (en) * | 2009-05-13 | 2013-02-05 | Advanced Semiconductor Engineering, Inc. | Substrate having single patterned metal layer exposing patterned dielectric layer, chip package structure including the substrate, and manufacturing methods thereof |
US9449900B2 (en) | 2009-07-23 | 2016-09-20 | UTAC Headquarters Pte. Ltd. | Leadframe feature to minimize flip-chip semiconductor die collapse during flip-chip reflow |
JP5428667B2 (ja) * | 2009-09-07 | 2014-02-26 | 日立化成株式会社 | 半導体チップ搭載用基板の製造方法 |
TWI425603B (zh) * | 2009-09-08 | 2014-02-01 | Advanced Semiconductor Eng | 晶片封裝體 |
US20110061234A1 (en) * | 2009-09-15 | 2011-03-17 | Jun-Chung Hsu | Method For Fabricating Carrier Board Having No Conduction Line |
US8334584B2 (en) * | 2009-09-18 | 2012-12-18 | Stats Chippac Ltd. | Integrated circuit packaging system with quad flat no-lead package and method of manufacture thereof |
US8551820B1 (en) * | 2009-09-28 | 2013-10-08 | Amkor Technology, Inc. | Routable single layer substrate and semiconductor package including same |
US8101470B2 (en) * | 2009-09-30 | 2012-01-24 | National Semiconductor Corporation | Foil based semiconductor package |
US8803300B2 (en) * | 2009-10-01 | 2014-08-12 | Stats Chippac Ltd. | Integrated circuit packaging system with protective coating and method of manufacture thereof |
US8796561B1 (en) | 2009-10-05 | 2014-08-05 | Amkor Technology, Inc. | Fan out build up substrate stackable package and method |
US8786062B2 (en) | 2009-10-14 | 2014-07-22 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and process for fabricating same |
US20110084372A1 (en) | 2009-10-14 | 2011-04-14 | Advanced Semiconductor Engineering, Inc. | Package carrier, semiconductor package, and process for fabricating same |
US7943424B1 (en) * | 2009-11-30 | 2011-05-17 | Alpha & Omega Semiconductor Incorporated | Encapsulation method for packaging semiconductor components with external leads |
US8937381B1 (en) | 2009-12-03 | 2015-01-20 | Amkor Technology, Inc. | Thin stackable package and method |
US9355940B1 (en) | 2009-12-04 | 2016-05-31 | Utac Thai Limited | Auxiliary leadframe member for stabilizing the bond wire process |
US8368189B2 (en) * | 2009-12-04 | 2013-02-05 | Utac Thai Limited | Auxiliary leadframe member for stabilizing the bond wire process |
US9691734B1 (en) | 2009-12-07 | 2017-06-27 | Amkor Technology, Inc. | Method of forming a plurality of electronic component packages |
DE102009060480A1 (de) * | 2009-12-18 | 2011-06-22 | Schweizer Electronic AG, 78713 | Leiterstrukturelement und Verfahren zum Herstellen eines Leiterstrukturelements |
JP2011134960A (ja) * | 2009-12-25 | 2011-07-07 | Hitachi Chem Co Ltd | 半導体装置、その製造法、半導体素子接続用配線基材、半導体装置搭載配線板及びその製造法 |
TWI392066B (zh) * | 2009-12-28 | 2013-04-01 | 矽品精密工業股份有限公司 | 封裝結構及其製法 |
US8569894B2 (en) | 2010-01-13 | 2013-10-29 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with single sided substrate design and manufacturing methods thereof |
JP5232185B2 (ja) * | 2010-03-05 | 2013-07-10 | 株式会社東芝 | 半導体装置の製造方法 |
US8575732B2 (en) * | 2010-03-11 | 2013-11-05 | Utac Thai Limited | Leadframe based multi terminal IC package |
TWI453844B (zh) * | 2010-03-12 | 2014-09-21 | 矽品精密工業股份有限公司 | 四方平面無導腳半導體封裝件及其製法 |
US8420508B2 (en) * | 2010-03-17 | 2013-04-16 | Stats Chippac Ltd. | Integrated circuit packaging system with bump contact on package leads and method of manufacture thereof |
TWI411075B (zh) | 2010-03-22 | 2013-10-01 | Advanced Semiconductor Eng | 半導體封裝件及其製造方法 |
US8871571B2 (en) | 2010-04-02 | 2014-10-28 | Utac Thai Limited | Apparatus for and methods of attaching heat slugs to package tops |
US8324511B1 (en) | 2010-04-06 | 2012-12-04 | Amkor Technology, Inc. | Through via nub reveal method and structure |
US8373279B2 (en) * | 2010-04-23 | 2013-02-12 | Infineon Technologies Ag | Die package |
TWI527175B (zh) | 2010-04-28 | 2016-03-21 | 先進封裝技術私人有限公司 | 半導體封裝件、基板及其製造方法 |
CN101819951B (zh) * | 2010-05-07 | 2012-01-25 | 日月光半导体制造股份有限公司 | 基板及应用其的半导体封装件与其制造方法 |
US8294276B1 (en) | 2010-05-27 | 2012-10-23 | Amkor Technology, Inc. | Semiconductor device and fabricating method thereof |
US8482111B2 (en) | 2010-07-19 | 2013-07-09 | Tessera, Inc. | Stackable molded microelectronic packages |
US9159708B2 (en) | 2010-07-19 | 2015-10-13 | Tessera, Inc. | Stackable molded microelectronic packages with area array unit connectors |
US8440554B1 (en) | 2010-08-02 | 2013-05-14 | Amkor Technology, Inc. | Through via connected backside embedded circuit features structure and method |
JP2012069919A (ja) * | 2010-08-25 | 2012-04-05 | Toshiba Corp | 半導体装置の製造方法 |
JP5242644B2 (ja) * | 2010-08-31 | 2013-07-24 | 株式会社東芝 | 半導体記憶装置 |
TWI429048B (zh) | 2010-08-31 | 2014-03-01 | Advanpack Solutions Pte Ltd | 半導體承載元件的製造方法及應用其之半導體封裝件的製造方法 |
US8435834B2 (en) | 2010-09-13 | 2013-05-07 | Stats Chippac, Ltd. | Semiconductor device and method of forming bond-on-lead interconnection for mounting semiconductor die in FO-WLCSP |
US8487445B1 (en) | 2010-10-05 | 2013-07-16 | Amkor Technology, Inc. | Semiconductor device having through electrodes protruding from dielectric layer |
KR101075241B1 (ko) | 2010-11-15 | 2011-11-01 | 테세라, 인코포레이티드 | 유전체 부재에 단자를 구비하는 마이크로전자 패키지 |
US8791501B1 (en) | 2010-12-03 | 2014-07-29 | Amkor Technology, Inc. | Integrated passive device structure and method |
US20120146206A1 (en) | 2010-12-13 | 2012-06-14 | Tessera Research Llc | Pin attachment |
JP5049382B2 (ja) | 2010-12-21 | 2012-10-17 | パナソニック株式会社 | 発光装置及びそれを用いた照明装置 |
US8390130B1 (en) | 2011-01-06 | 2013-03-05 | Amkor Technology, Inc. | Through via recessed reveal structure and method |
KR101128063B1 (ko) | 2011-05-03 | 2012-04-23 | 테세라, 인코포레이티드 | 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리 |
US8618659B2 (en) | 2011-05-03 | 2013-12-31 | Tessera, Inc. | Package-on-package assembly with wire bonds to encapsulation surface |
TWI453872B (zh) * | 2011-06-23 | 2014-09-21 | 矽品精密工業股份有限公司 | 半導體封裝件及其製法 |
WO2013006209A2 (en) * | 2011-07-03 | 2013-01-10 | Eoplex Limited | Lead carrier with thermally fused package components |
CN102244061A (zh) * | 2011-07-18 | 2011-11-16 | 江阴长电先进封装有限公司 | Low-k芯片封装结构 |
JP2013023766A (ja) * | 2011-07-26 | 2013-02-04 | Hitachi Chemical Co Ltd | テープキャリア付半導体実装用導電基材の表面処理方法、ならびにこの処理方法を用いてなるテープキャリア付半導体実装用導電基材および半導体パッケージ |
US8872318B2 (en) | 2011-08-24 | 2014-10-28 | Tessera, Inc. | Through interposer wire bond using low CTE interposer with coarse slot apertures |
US8836136B2 (en) | 2011-10-17 | 2014-09-16 | Invensas Corporation | Package-on-package assembly with wire bond vias |
CN103999484B (zh) | 2011-11-04 | 2017-06-30 | 美商楼氏电子有限公司 | 作为声学设备中的屏障的嵌入式电介质和制造方法 |
US8552548B1 (en) | 2011-11-29 | 2013-10-08 | Amkor Technology, Inc. | Conductive pad on protruding through electrode semiconductor device |
CN102683315B (zh) * | 2011-11-30 | 2015-04-29 | 江苏长电科技股份有限公司 | 滚镀四面无引脚封装结构及其制造方法 |
CN102376672B (zh) * | 2011-11-30 | 2014-10-29 | 江苏长电科技股份有限公司 | 无基岛球栅阵列封装结构及其制造方法 |
JP6165411B2 (ja) * | 2011-12-26 | 2017-07-19 | 富士通株式会社 | 電子部品及び電子機器 |
US8946757B2 (en) | 2012-02-17 | 2015-02-03 | Invensas Corporation | Heat spreading substrate with embedded interconnects |
US9349706B2 (en) | 2012-02-24 | 2016-05-24 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
US8372741B1 (en) | 2012-02-24 | 2013-02-12 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
US9312194B2 (en) | 2012-03-20 | 2016-04-12 | Stats Chippac Ltd. | Integrated circuit packaging system with terminals and method of manufacture thereof |
US9324641B2 (en) | 2012-03-20 | 2016-04-26 | Stats Chippac Ltd. | Integrated circuit packaging system with external interconnect and method of manufacture thereof |
US8569112B2 (en) * | 2012-03-20 | 2013-10-29 | Stats Chippac Ltd. | Integrated circuit packaging system with encapsulation and leadframe etching and method of manufacture thereof |
US9129943B1 (en) | 2012-03-29 | 2015-09-08 | Amkor Technology, Inc. | Embedded component package and fabrication method |
US9048298B1 (en) | 2012-03-29 | 2015-06-02 | Amkor Technology, Inc. | Backside warpage control structure and fabrication method |
US9040346B2 (en) * | 2012-05-03 | 2015-05-26 | Infineon Technologies Ag | Semiconductor package and methods of formation thereof |
US9449905B2 (en) | 2012-05-10 | 2016-09-20 | Utac Thai Limited | Plated terminals with routing interconnections semiconductor device |
US9029198B2 (en) | 2012-05-10 | 2015-05-12 | Utac Thai Limited | Methods of manufacturing semiconductor devices including terminals with internal routing interconnections |
US8835228B2 (en) | 2012-05-22 | 2014-09-16 | Invensas Corporation | Substrate-less stackable package with wire-bond interconnect |
US9006034B1 (en) | 2012-06-11 | 2015-04-14 | Utac Thai Limited | Post-mold for semiconductor package having exposed traces |
JP6029873B2 (ja) * | 2012-06-29 | 2016-11-24 | 新光電気工業株式会社 | 配線基板、配線基板の製造方法及び半導体装置の製造方法 |
US9391008B2 (en) | 2012-07-31 | 2016-07-12 | Invensas Corporation | Reconstituted wafer-level package DRAM |
US9502390B2 (en) | 2012-08-03 | 2016-11-22 | Invensas Corporation | BVA interposer |
US9078063B2 (en) | 2012-08-10 | 2015-07-07 | Knowles Electronics, Llc | Microphone assembly with barrier to prevent contaminant infiltration |
CN104854695A (zh) * | 2012-09-07 | 2015-08-19 | 联达科技控股有限公司 | 具有印刷形成的端子焊盘的引线载体 |
US9911685B2 (en) | 2012-11-09 | 2018-03-06 | Amkor Technology, Inc. | Land structure for semiconductor package and method therefor |
KR20140060390A (ko) | 2012-11-09 | 2014-05-20 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지의 랜드 및 그 제조 방법과 이를 이용한 반도체 패키지 및 그 제조 방법 |
US8975738B2 (en) | 2012-11-12 | 2015-03-10 | Invensas Corporation | Structure for microelectronic packaging with terminals on dielectric mass |
TWI508238B (zh) | 2012-12-17 | 2015-11-11 | Princo Corp | 晶片散熱系統 |
US8878353B2 (en) | 2012-12-20 | 2014-11-04 | Invensas Corporation | Structure for microelectronic packaging with bond elements to encapsulation surface |
US9136254B2 (en) | 2013-02-01 | 2015-09-15 | Invensas Corporation | Microelectronic package having wire bond vias and stiffening layer |
JP5592526B2 (ja) * | 2013-04-08 | 2014-09-17 | ルネサスエレクトロニクス株式会社 | 樹脂封止型半導体装置の製造方法 |
CN103325753A (zh) * | 2013-05-16 | 2013-09-25 | 华天科技(西安)有限公司 | 一种基于无框架csp封装背面植球塑封封装件及其制作工艺 |
US9034696B2 (en) | 2013-07-15 | 2015-05-19 | Invensas Corporation | Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation |
US9023691B2 (en) | 2013-07-15 | 2015-05-05 | Invensas Corporation | Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation |
US8883563B1 (en) | 2013-07-15 | 2014-11-11 | Invensas Corporation | Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation |
US9167710B2 (en) | 2013-08-07 | 2015-10-20 | Invensas Corporation | Embedded packaging with preformed vias |
US9685365B2 (en) | 2013-08-08 | 2017-06-20 | Invensas Corporation | Method of forming a wire bond having a free end |
US20150076714A1 (en) | 2013-09-16 | 2015-03-19 | Invensas Corporation | Microelectronic element with bond elements to encapsulation surface |
US9087815B2 (en) | 2013-11-12 | 2015-07-21 | Invensas Corporation | Off substrate kinking of bond wire |
US9082753B2 (en) | 2013-11-12 | 2015-07-14 | Invensas Corporation | Severing bond wire by kinking and twisting |
US9263394B2 (en) | 2013-11-22 | 2016-02-16 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US9583456B2 (en) | 2013-11-22 | 2017-02-28 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US9379074B2 (en) | 2013-11-22 | 2016-06-28 | Invensas Corporation | Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects |
US10242953B1 (en) | 2015-05-27 | 2019-03-26 | Utac Headquarters PTE. Ltd | Semiconductor package with plated metal shielding and a method thereof |
US9583411B2 (en) | 2014-01-17 | 2017-02-28 | Invensas Corporation | Fine pitch BVA using reconstituted wafer with area array accessible for testing |
US9401287B2 (en) * | 2014-02-07 | 2016-07-26 | Altera Corporation | Methods for packaging integrated circuits |
US9214454B2 (en) | 2014-03-31 | 2015-12-15 | Invensas Corporation | Batch process fabrication of package-on-package microelectronic assemblies |
US10242934B1 (en) | 2014-05-07 | 2019-03-26 | Utac Headquarters Pte Ltd. | Semiconductor package with full plating on contact side surfaces and methods thereof |
US10103037B2 (en) | 2014-05-09 | 2018-10-16 | Intel Corporation | Flexible microelectronic systems and methods of fabricating the same |
US10381326B2 (en) | 2014-05-28 | 2019-08-13 | Invensas Corporation | Structure and method for integrated circuits packaging with increased density |
US9646917B2 (en) | 2014-05-29 | 2017-05-09 | Invensas Corporation | Low CTE component with wire bond interconnects |
US9412714B2 (en) | 2014-05-30 | 2016-08-09 | Invensas Corporation | Wire bond support structure and microelectronic package including wire bonds therefrom |
US20160005679A1 (en) * | 2014-07-02 | 2016-01-07 | Nxp B.V. | Exposed die quad flat no-leads (qfn) package |
BR112015015380A2 (pt) * | 2014-07-11 | 2017-07-11 | Intel Corp | dispositivos eletrônicos inclináveis e estiráveis e métodos |
US9390993B2 (en) * | 2014-08-15 | 2016-07-12 | Broadcom Corporation | Semiconductor border protection sealant |
US20160064299A1 (en) * | 2014-08-29 | 2016-03-03 | Nishant Lakhera | Structure and method to minimize warpage of packaged semiconductor devices |
US9899330B2 (en) * | 2014-10-03 | 2018-02-20 | Mc10, Inc. | Flexible electronic circuits with embedded integrated circuit die |
US9735084B2 (en) | 2014-12-11 | 2017-08-15 | Invensas Corporation | Bond via array for thermal conductivity |
US20160218021A1 (en) * | 2015-01-27 | 2016-07-28 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and method of manufacturing the same |
US9888579B2 (en) | 2015-03-05 | 2018-02-06 | Invensas Corporation | Pressing of wire bond wire tips to provide bent-over tips |
US9633883B2 (en) * | 2015-03-20 | 2017-04-25 | Rohinni, LLC | Apparatus for transfer of semiconductor devices |
US10002843B2 (en) * | 2015-03-24 | 2018-06-19 | Advanced Semiconductor Engineering, Inc. | Semiconductor substrate structure, semiconductor package and method of manufacturing the same |
US9502372B1 (en) | 2015-04-30 | 2016-11-22 | Invensas Corporation | Wafer-level packaging using wire bond wires in place of a redistribution layer |
US9761554B2 (en) | 2015-05-07 | 2017-09-12 | Invensas Corporation | Ball bonding metal wire bond wires to metal pads |
KR101637189B1 (ko) * | 2015-06-12 | 2016-07-20 | 주식회사 에스에프에이반도체 | 반도체 패키지 제조방법 |
US9794661B2 (en) | 2015-08-07 | 2017-10-17 | Knowles Electronics, Llc | Ingress protection for reducing particle infiltration into acoustic chamber of a MEMS microphone package |
US10206288B2 (en) | 2015-08-13 | 2019-02-12 | Palo Alto Research Center Incorporated | Bare die integration with printed components on flexible substrate |
US10490528B2 (en) | 2015-10-12 | 2019-11-26 | Invensas Corporation | Embedded wire bond wires |
US9490222B1 (en) | 2015-10-12 | 2016-11-08 | Invensas Corporation | Wire bond wires for interference shielding |
US10332854B2 (en) | 2015-10-23 | 2019-06-25 | Invensas Corporation | Anchoring structure of fine pitch bva |
US10181457B2 (en) | 2015-10-26 | 2019-01-15 | Invensas Corporation | Microelectronic package for wafer-level chip scale packaging with fan-out |
US9805955B1 (en) | 2015-11-10 | 2017-10-31 | UTAC Headquarters Pte. Ltd. | Semiconductor package with multiple molding routing layers and a method of manufacturing the same |
US10043779B2 (en) | 2015-11-17 | 2018-08-07 | Invensas Corporation | Packaged microelectronic device for a package-on-package device |
US9659848B1 (en) | 2015-11-18 | 2017-05-23 | Invensas Corporation | Stiffened wires for offset BVA |
CN105489542B (zh) * | 2015-11-27 | 2019-06-14 | 矽力杰半导体技术(杭州)有限公司 | 芯片封装方法及芯片封装结构 |
US10165677B2 (en) * | 2015-12-10 | 2018-12-25 | Palo Alto Research Center Incorporated | Bare die integration with printed components on flexible substrate without laser cut |
DE102015122282A1 (de) * | 2015-12-18 | 2017-06-22 | Infineon Technologies Ag | Elektronisches Bauteil und Verfahren zu dessen Herstellung |
US9984992B2 (en) | 2015-12-30 | 2018-05-29 | Invensas Corporation | Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces |
US10276477B1 (en) | 2016-05-20 | 2019-04-30 | UTAC Headquarters Pte. Ltd. | Semiconductor package with multiple stacked leadframes and a method of manufacturing the same |
US9935075B2 (en) | 2016-07-29 | 2018-04-03 | Invensas Corporation | Wire bonding method and apparatus for electromagnetic interference shielding |
JP6610497B2 (ja) * | 2016-10-14 | 2019-11-27 | オムロン株式会社 | 電子装置およびその製造方法 |
US10141215B2 (en) | 2016-11-03 | 2018-11-27 | Rohinni, LLC | Compliant needle for direct transfer of semiconductor devices |
US10471545B2 (en) | 2016-11-23 | 2019-11-12 | Rohinni, LLC | Top-side laser for direct transfer of semiconductor devices |
US10504767B2 (en) | 2016-11-23 | 2019-12-10 | Rohinni, LLC | Direct transfer apparatus for a pattern array of semiconductor device die |
KR102040296B1 (ko) * | 2016-12-19 | 2019-11-04 | 삼성에스디아이 주식회사 | 필름형 반도체 밀봉 부재, 이를 이용하여 제조된 반도체 패키지 및 그 제조 방법 |
US10299368B2 (en) | 2016-12-21 | 2019-05-21 | Invensas Corporation | Surface integrated waveguides and circuit structures therefor |
KR102052199B1 (ko) * | 2016-12-23 | 2019-12-04 | 삼성에스디아이 주식회사 | 필름형 반도체 밀봉 부재, 이를 이용하여 제조된 반도체 패키지 및 그 제조 방법 |
US10062588B2 (en) | 2017-01-18 | 2018-08-28 | Rohinni, LLC | Flexible support substrate for transfer of semiconductor devices |
CN108346587A (zh) * | 2017-01-25 | 2018-07-31 | 新加坡有限公司 | 芯片封装器件及封装方法 |
US10128169B1 (en) | 2017-05-12 | 2018-11-13 | Stmicroelectronics, Inc. | Package with backside protective layer during molding to prevent mold flashing failure |
US10847384B2 (en) | 2017-05-31 | 2020-11-24 | Palo Alto Research Center Incorporated | Method and fixture for chip attachment to physical objects |
US10643863B2 (en) | 2017-08-24 | 2020-05-05 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and method of manufacturing the same |
TWM555065U (zh) * | 2017-09-05 | 2018-02-01 | 恆勁科技股份有限公司 | 電子封裝件及其封裝基板 |
US10410905B1 (en) | 2018-05-12 | 2019-09-10 | Rohinni, LLC | Method and apparatus for direct transfer of multiple semiconductor devices |
US11094571B2 (en) | 2018-09-28 | 2021-08-17 | Rohinni, LLC | Apparatus to increase transferspeed of semiconductor devices with micro-adjustment |
JP7348532B2 (ja) * | 2018-09-28 | 2023-09-21 | 日亜化学工業株式会社 | 発光モジュール及びその製造方法 |
US20200203242A1 (en) * | 2018-12-19 | 2020-06-25 | Texas Instruments Incorporated | Low cost reliable fan-out fan-in chip scale package |
JP7335036B2 (ja) | 2019-03-29 | 2023-08-29 | ラピスセミコンダクタ株式会社 | 半導体パッケージの製造方法 |
CN110233113A (zh) * | 2019-06-17 | 2019-09-13 | 青岛歌尔微电子研究院有限公司 | 一种芯片的封装方法 |
CN113035722A (zh) | 2019-12-24 | 2021-06-25 | 维谢综合半导体有限责任公司 | 具有选择性模制的用于镀覆的封装工艺 |
CN113035721A (zh) | 2019-12-24 | 2021-06-25 | 维谢综合半导体有限责任公司 | 用于侧壁镀覆导电膜的封装工艺 |
CN111341672B (zh) * | 2020-05-15 | 2020-10-20 | 深圳市汇顶科技股份有限公司 | 半导体封装方法及其封装结构 |
US11887916B2 (en) | 2020-09-09 | 2024-01-30 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor devices and methods of manufacturing semiconductor devices |
CN117976551A (zh) * | 2024-04-02 | 2024-05-03 | 新恒汇电子股份有限公司 | 一种可回收载带的智能卡及其制备方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59208756A (ja) * | 1983-05-12 | 1984-11-27 | Sony Corp | 半導体装置のパツケ−ジの製造方法 |
Family Cites Families (62)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3878555A (en) * | 1970-05-14 | 1975-04-15 | Siemens Ag | Semiconductor device mounted on an epoxy substrate |
US3748543A (en) * | 1971-04-01 | 1973-07-24 | Motorola Inc | Hermetically sealed semiconductor package and method of manufacture |
US4376287A (en) * | 1980-10-29 | 1983-03-08 | Rca Corporation | Microwave power circuit with an active device mounted on a heat dissipating substrate |
US4602271A (en) * | 1981-07-22 | 1986-07-22 | International Business Machines Corporation | Personalizable masterslice substrate for semiconductor chips |
FR2524707B1 (fr) * | 1982-04-01 | 1985-05-31 | Cit Alcatel | Procede d'encapsulation de composants semi-conducteurs, et composants encapsules obtenus |
JPS5943554A (ja) * | 1982-09-03 | 1984-03-10 | Toshiba Corp | 樹脂封止半導体装置 |
JPS59231825A (ja) | 1983-06-14 | 1984-12-26 | Toshiba Corp | 半導体装置 |
JPS60160624A (ja) | 1984-01-31 | 1985-08-22 | Sharp Corp | 半導体チツプの絶縁分離方法 |
US4688150A (en) * | 1984-06-15 | 1987-08-18 | Texas Instruments Incorporated | High pin count chip carrier package |
JPS61177759A (ja) | 1985-02-04 | 1986-08-09 | Hitachi Micro Comput Eng Ltd | 半導体装置 |
JPS61222151A (ja) * | 1985-03-27 | 1986-10-02 | Ibiden Co Ltd | 半導体搭載用プリント配線板の製造方法 |
JPS6223091A (ja) | 1985-07-24 | 1987-01-31 | 株式会社日立製作所 | 表示制御装置 |
US4700473A (en) | 1986-01-03 | 1987-10-20 | Motorola Inc. | Method of making an ultra high density pad array chip carrier |
US4969257A (en) * | 1987-09-04 | 1990-11-13 | Shinko Electric Industries, Co., Ltd. | Transfer sheet and process for making a circuit substrate |
JPH081988B2 (ja) | 1987-09-30 | 1996-01-10 | 日立化成工業株式会社 | 配線板の製造法 |
US4890383A (en) * | 1988-01-15 | 1990-01-02 | Simens Corporate Research & Support, Inc. | Method for producing displays and modular components |
JPH01289273A (ja) | 1988-05-17 | 1989-11-21 | Matsushita Electric Ind Co Ltd | 配線基板 |
EP0351581A1 (de) | 1988-07-22 | 1990-01-24 | Oerlikon-Contraves AG | Hochintegrierte Schaltung sowie Verfahren zu deren Herstellung |
JPH02153542A (ja) * | 1988-12-05 | 1990-06-13 | Matsushita Electric Ind Co Ltd | 集積回路装置の製造方法 |
FR2645680B1 (fr) * | 1989-04-07 | 1994-04-29 | Thomson Microelectronics Sa Sg | Encapsulation de modules electroniques et procede de fabrication |
US5077633A (en) | 1989-05-01 | 1991-12-31 | Motorola Inc. | Grounding an ultra high density pad array chip carrier |
WO1993017457A1 (en) * | 1989-07-01 | 1993-09-02 | Ryo Enomoto | Substrate for mounting semiconductor and method of producing the same |
JP2840317B2 (ja) | 1989-09-06 | 1998-12-24 | 新光電気工業株式会社 | 半導体装置およびその製造方法 |
JP2781020B2 (ja) * | 1989-09-06 | 1998-07-30 | モトローラ・インコーポレーテッド | 半導体装置およびその製造方法 |
JP2840316B2 (ja) * | 1989-09-06 | 1998-12-24 | 新光電気工業株式会社 | 半導体装置およびその製造方法 |
JPH03178152A (ja) | 1989-12-06 | 1991-08-02 | Sony Chem Corp | モールドicおよびその製造方法 |
US5250470A (en) * | 1989-12-22 | 1993-10-05 | Oki Electric Industry Co., Ltd. | Method for manufacturing a semiconductor device with corrosion resistant leads |
JPH0426545A (ja) | 1990-05-18 | 1992-01-29 | Sumitomo Metal Ind Ltd | 半導体磁器及びその製造方法 |
US5173766A (en) | 1990-06-25 | 1992-12-22 | Lsi Logic Corporation | Semiconductor device package and method of making such a package |
JP2737373B2 (ja) | 1990-07-12 | 1998-04-08 | 富士通株式会社 | リードフレーム及び集積回路の製造方法 |
JP3094430B2 (ja) | 1990-08-10 | 2000-10-03 | 株式会社ブリヂストン | 履帯用ゴムパッド |
US5399903A (en) | 1990-08-15 | 1995-03-21 | Lsi Logic Corporation | Semiconductor device having an universal die size inner lead layout |
US5258330A (en) * | 1990-09-24 | 1993-11-02 | Tessera, Inc. | Semiconductor chip assemblies with fan-in leads |
US5148265A (en) | 1990-09-24 | 1992-09-15 | Ist Associates, Inc. | Semiconductor chip assemblies with fan-in leads |
JP2897409B2 (ja) | 1990-11-15 | 1999-05-31 | 凸版印刷株式会社 | Icパッケージ |
US5216278A (en) * | 1990-12-04 | 1993-06-01 | Motorola, Inc. | Semiconductor device having a pad array carrier package |
JP3094459B2 (ja) | 1990-12-28 | 2000-10-03 | ソニー株式会社 | 電界放出型カソードアレイの製造方法 |
JPH04241445A (ja) | 1991-01-16 | 1992-08-28 | Nec Corp | 半導体集積回路装置 |
JP2962586B2 (ja) * | 1991-03-05 | 1999-10-12 | 新光電気工業株式会社 | 半導体装置とその製造方法及びこれに用いる接合体 |
US5153385A (en) | 1991-03-18 | 1992-10-06 | Motorola, Inc. | Transfer molded semiconductor package with improved adhesion |
US5218759A (en) * | 1991-03-18 | 1993-06-15 | Motorola, Inc. | Method of making a transfer molded semiconductor device |
JP2570498B2 (ja) * | 1991-05-23 | 1997-01-08 | モトローラ・インコーポレイテッド | 集積回路チップ・キャリア |
JPH0582667A (ja) | 1991-09-24 | 1993-04-02 | Mitsubishi Electric Corp | リード付き配線基板 |
JPH05109922A (ja) * | 1991-10-21 | 1993-04-30 | Nec Corp | 半導体装置 |
JPH05129473A (ja) * | 1991-11-06 | 1993-05-25 | Sony Corp | 樹脂封止表面実装型半導体装置 |
JP2994510B2 (ja) | 1992-02-10 | 1999-12-27 | ローム株式会社 | 半導体装置およびその製法 |
US5313365A (en) * | 1992-06-30 | 1994-05-17 | Motorola, Inc. | Encapsulated electronic package |
JP2632762B2 (ja) | 1992-07-29 | 1997-07-23 | 株式会社三井ハイテック | 半導体素子搭載用基板の製造方法 |
EP0582052A1 (en) * | 1992-08-06 | 1994-02-09 | Motorola, Inc. | Low profile overmolded semiconductor device and method for making the same |
JPH06244231A (ja) * | 1993-02-01 | 1994-09-02 | Motorola Inc | 気密半導体デバイスおよびその製造方法 |
US6262477B1 (en) * | 1993-03-19 | 2001-07-17 | Advanced Interconnect Technologies | Ball grid array electronic package |
US5355283A (en) * | 1993-04-14 | 1994-10-11 | Amkor Electronics, Inc. | Ball grid array with via interconnection |
US5454161A (en) * | 1993-04-29 | 1995-10-03 | Fujitsu Limited | Through hole interconnect substrate fabrication process |
JPH0758161A (ja) | 1993-08-10 | 1995-03-03 | Nippon Steel Corp | フィルムキャリヤ及びこのフィルムキャリヤを用いた半導体装置 |
US5467252A (en) * | 1993-10-18 | 1995-11-14 | Motorola, Inc. | Method for plating using nested plating buses and semiconductor device having the same |
EP1213754A3 (en) * | 1994-03-18 | 2005-05-25 | Hitachi Chemical Co., Ltd. | Fabrication process of semiconductor package and semiconductor package |
US5579207A (en) * | 1994-10-20 | 1996-11-26 | Hughes Electronics | Three-dimensional integrated circuit stacking |
US5537738A (en) * | 1995-02-10 | 1996-07-23 | Micron Display Technology Inc. | Methods of mechanical and electrical substrate connection |
US5612256A (en) * | 1995-02-10 | 1997-03-18 | Micron Display Technology, Inc. | Multi-layer electrical interconnection structures and fabrication methods |
US5766053A (en) * | 1995-02-10 | 1998-06-16 | Micron Technology, Inc. | Internal plate flat-panel field emission display |
JPH0913991A (ja) | 1995-06-27 | 1997-01-14 | Kubota Corp | 過給器付きディーゼルエンジンのガバナ装置 |
KR20100051672A (ko) | 2007-07-25 | 2010-05-17 | 고쿠리츠다이가쿠호진 히로시마다이가쿠 | 고형화된 세정제 조성물 및 이의 제조방법 |
-
1995
- 1995-03-17 EP EP02003791A patent/EP1213754A3/en not_active Withdrawn
- 1995-03-17 CN CN95192144A patent/CN1117395C/zh not_active Expired - Fee Related
- 1995-03-17 KR KR10-2003-7017172A patent/KR100437437B1/ko not_active IP Right Cessation
- 1995-03-17 CN CNA031378625A patent/CN1516251A/zh active Pending
- 1995-03-17 JP JP52453795A patent/JP3247384B2/ja not_active Expired - Fee Related
- 1995-03-17 US US08/716,362 patent/US5976912A/en not_active Expired - Lifetime
- 1995-03-17 EP EP95912471A patent/EP0751561A4/en not_active Withdrawn
- 1995-03-17 EP EP02003794A patent/EP1213756A3/en not_active Withdrawn
- 1995-03-17 KR KR1019960705146A patent/KR100437436B1/ko not_active IP Right Cessation
- 1995-03-17 WO PCT/JP1995/000492 patent/WO1995026047A1/ja not_active Application Discontinuation
- 1995-03-17 EP EP02003792A patent/EP1213755A3/en not_active Withdrawn
-
2000
- 2000-01-19 US US09/487,682 patent/US6365432B1/en not_active Expired - Fee Related
-
2001
- 2001-10-23 US US10/008,616 patent/US6746897B2/en not_active Expired - Fee Related
-
2002
- 2002-01-08 US US10/042,408 patent/US20020094606A1/en not_active Abandoned
-
2003
- 2003-11-10 US US10/705,706 patent/US7187072B2/en not_active Expired - Fee Related
-
2008
- 2008-03-17 JP JP2008067673A patent/JP4862848B2/ja not_active Expired - Fee Related
-
2011
- 2011-05-02 JP JP2011103182A patent/JP5104978B2/ja not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59208756A (ja) * | 1983-05-12 | 1984-11-27 | Sony Corp | 半導体装置のパツケ−ジの製造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101740410B (zh) * | 2008-11-13 | 2011-10-05 | 南茂科技股份有限公司 | 芯片封装结构的制程 |
CN101740424B (zh) * | 2008-11-13 | 2011-10-05 | 南茂科技股份有限公司 | 芯片封装结构的制程 |
Also Published As
Publication number | Publication date |
---|---|
CN1516251A (zh) | 2004-07-28 |
KR20040028799A (ko) | 2004-04-03 |
CN1144016A (zh) | 1997-02-26 |
JP3247384B2 (ja) | 2002-01-15 |
KR100437436B1 (ko) | 2004-07-16 |
EP1213756A2 (en) | 2002-06-12 |
US5976912A (en) | 1999-11-02 |
EP1213755A3 (en) | 2005-05-25 |
US20040110319A1 (en) | 2004-06-10 |
EP1213755A2 (en) | 2002-06-12 |
WO1995026047A1 (en) | 1995-09-28 |
EP0751561A4 (en) | 1997-05-07 |
EP1213754A2 (en) | 2002-06-12 |
EP1213754A3 (en) | 2005-05-25 |
KR100437437B1 (ko) | 2004-06-25 |
US6365432B1 (en) | 2002-04-02 |
EP0751561A1 (en) | 1997-01-02 |
JP4862848B2 (ja) | 2012-01-25 |
US6746897B2 (en) | 2004-06-08 |
EP1213756A3 (en) | 2005-05-25 |
US20020094606A1 (en) | 2002-07-18 |
US7187072B2 (en) | 2007-03-06 |
US20020039808A1 (en) | 2002-04-04 |
JP2011146751A (ja) | 2011-07-28 |
JP2008153708A (ja) | 2008-07-03 |
JP5104978B2 (ja) | 2012-12-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1117395C (zh) | 半导体组件的制造方法及半导体组件 | |
CN1227957C (zh) | 电路装置的制造方法及电路装置 | |
CN1173400C (zh) | 板状体和半导体器件的制造方法 | |
CN1244139C (zh) | 半导体器件和半导体组件 | |
CN1198332C (zh) | 布线基片、半导体器件和布线基片的制造方法 | |
CN1251318C (zh) | 半导体芯片、半导体装置和它们的制造方法以及使用它们的电路板和仪器 | |
CN1216419C (zh) | 布线基板、具有布线基板的半导体装置及其制造和安装方法 | |
CN1873935A (zh) | 配线基板的制造方法及半导体器件的制造方法 | |
CN1882224A (zh) | 配线基板及其制造方法 | |
CN1779951A (zh) | 半导体器件及其制造方法 | |
CN1266752C (zh) | 电路装置的制造方法 | |
CN1677657A (zh) | 半导体器件及其制造方法 | |
CN1197150C (zh) | 半导体装置、安装基板及其制造方法、电路基板和电子装置 | |
JP2003309242A (ja) | リードフレーム部材とリードフレーム部材の製造方法、及び該リードフレーム部材を用いた半導体パッケージとその製造方法 | |
CN1739323A (zh) | 多层布线板及其制造方法 | |
CN1469461A (zh) | 半导体器件和制造半导体器件的方法 | |
CN1835212A (zh) | 电子装置用基板及其制造方法以及电子装置及其制造方法 | |
JP4029910B2 (ja) | 半導体パッケ−ジの製造法及び半導体パッケ−ジ | |
CN1245854C (zh) | 安装底板及其制造方法以及电子电路元件的安装方法 | |
CN1288591A (zh) | 半导体装置和制造方法及其安装构造和安装方法 | |
CN1784119A (zh) | 柔性布线基板及其制造方法、半导体装置和电子设备 | |
CN1348215A (zh) | 散热基板及半导体模块 | |
JP3352084B2 (ja) | 半導体素子搭載用基板及び半導体パッケージ | |
JP3337467B2 (ja) | 半導体パッケージの製造法及び半導体パッケージ | |
JP3685205B2 (ja) | 半導体パッケージ及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C17 | Cessation of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20030806 Termination date: 20130317 |