CN110233113A - 一种芯片的封装方法 - Google Patents

一种芯片的封装方法 Download PDF

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Publication number
CN110233113A
CN110233113A CN201910522476.4A CN201910522476A CN110233113A CN 110233113 A CN110233113 A CN 110233113A CN 201910522476 A CN201910522476 A CN 201910522476A CN 110233113 A CN110233113 A CN 110233113A
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China
Prior art keywords
chip
substrate
release
packaging method
lead
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Pending
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CN201910522476.4A
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English (en)
Inventor
尹保冠
佘飞
田德文
宋青林
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Qingdao Geer Microelectronics Research Institute Co Ltd
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Qingdao Geer Microelectronics Research Institute Co Ltd
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Publication date
Application filed by Qingdao Geer Microelectronics Research Institute Co Ltd filed Critical Qingdao Geer Microelectronics Research Institute Co Ltd
Priority to CN201910522476.4A priority Critical patent/CN110233113A/zh
Publication of CN110233113A publication Critical patent/CN110233113A/zh
Priority to PCT/CN2019/123551 priority patent/WO2020253146A1/zh
Priority to US17/620,345 priority patent/US20220367209A1/en
Pending legal-status Critical Current

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    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Abstract

本发明公开了一种芯片的封装方法，包括以下步骤；提供基板，基板上形成有贯通其相对两侧的开口槽；提供离型基材，将所述离型基材粘接在基板的一侧，并覆盖所述开口槽；提供芯片，将芯片贴装在位于开口槽位置的离型基材上；对基板上远离所述离型基材的一侧进行封装，形成将芯片封装并固定在基板上的封装层；去除离型基材，得到芯片的封装结构。本公开的封装方法，不但提高了芯片与基板之间封装的可靠性，还可以减小芯片占用的空间，尤其是多个芯片堆叠时的厚度，从而降低了整个封装的厚度，这利于电子产品的轻薄化发展。

Description

一种芯片的封装方法
技术领域
本发明涉及封装领域，更具体地，涉及一种芯片的封装工艺。
背景技术
随着电子产品的小型化、轻薄化发展，厂商对芯片的封装提出了更高的要求。SIP封装(System In a Package系统级封装)是将多种功能芯片，包括处理器、存储器等功能芯片集成在一个封装内，从而实现一个基本完整的功能。
例如对于底部芯片较小而顶部芯片较大的封装结构，当底部芯片焊线之后，粘接支撑部以将顶部芯片支撑起来。这种封装结构，在利用注塑或者线上膜(film on wire，简称FOW)工艺进行封装的时候，由于顶部芯片与支撑部之间的区域狭小，经常会发生填充不完全的问题，造成封装的可靠性差。
对于存储器产品，为了增加存储容量，减小封装尺寸，常采用芯片堆叠的封装方式。两个芯片或者更多个芯片在厚度方向上通过支撑部或者线上膜工艺堆叠起来并进行封装，这种封装结构不利于现代电子产品的轻薄化发展。
发明内容
本发明的一个目的是提供一种芯片的封装方法的新技术方案。
根据本发明的第一方面，提供了一种芯片的封装方法，包括以下步骤；
S100：提供基板，基板上形成有贯通其相对两侧的开口槽；
S200：提供离型基材，将所述离型基材粘接在基板的一侧，并覆盖所述开口槽；
S300：提供芯片，将芯片贴装在位于开口槽位置的离型基材上；
S400：对基板上远离所述离型基材的一侧进行封装，形成将芯片封装并固定在基板上的封装层；
S500：去除离型基材，得到芯片的封装结构。
可选地，所述芯片的顶面与基板的顶面齐平，或者低于所述基板的顶面；在所述步骤S400后，还包括减薄所述封装层的步骤。
可选地，所述步骤S300中，所述芯片以其引脚朝向离型基材的方式贴装在离型基材上；所述步骤S500之后，还包括在基板上进行重新布线的步骤。
可选地，在进行重新布线的步骤之后，还包括切割得到多个独立的封装结构的步骤。
可选地，在所述步骤300中，将芯片通过引线导通到基板上；所述步骤S400中，将芯片及其引线封装并固定在基板上；
之后还包括在封装层上贴装另一芯片，并将该另一芯片通过引线导通到基板上的步骤；以及包括对该另一芯片进行再次封装的步骤，形成将该另一芯片封装在基板上的另一封装层。
可选地，所述步骤S300中，第一芯片以其引脚朝向离型基材的方式贴装在离型基材上，第二芯片以其引脚远离所述离型基材的方式贴装在第一芯片上，且第二芯片的引脚通过引线导通到基板上；
在所述步骤S400中，将第一芯片、第二芯片及第二芯片的引线封装并固定在基板上；
在所述步骤S500之后，还包括将第一芯片的引脚通过引线导通到基板上的步骤，以及包括从基板的另一侧对第一芯片及其引线进行再次封装的步骤。
可选地，通过点胶工艺从基板的另一侧对第一芯片及其引线进行再次封装。
可选地，所述第一芯片与第二芯片的尺寸相同。
可选地，所述步骤S400中，通过注塑的工艺或者线上膜的工艺进行封装。
可选地，所述离型基材为胶带，或者热解膜，或者光解膜，或者为包含离型层的基板。
根据本公开的一个实施例，可以将芯片封装在基板的开口槽位置，这不但提高了芯片与基板之间封装的可靠性，还可以减小芯片占用的空间，尤其是多个芯片堆叠时的厚度，从而降低了整个封装的厚度，这利于电子产品的轻薄化发展。
通过以下参照附图对本发明的示例性实施例的详细描述，本发明的其它特征及其优点将会变得清楚。
附图说明
被结合在说明书中并构成说明书的一部分的附图示出了本发明的实施例，并且连同其说明一起用于解释本发明的原理。
图1a至图1f是本发明第一实施方式的封装工艺流程图。
图2a至图2g是本发明第二实施方式的封装工艺流程图。
图3a至图3g是本发明第三实施方式的封装工艺流程图。
具体实施方式
现在将参照附图来详细描述本发明的各种示例性实施例。应注意到：除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不限制本发明的范围。
以下对至少一个示例性实施例的描述实际上仅仅是说明性的，决不作为对本发明及其应用或使用的任何限制。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为说明书的一部分。
在这里示出和讨论的所有例子中，任何具体值应被解释为仅仅是示例性的，而不是作为限制。因此，示例性实施例的其它例子可以具有不同的值。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步讨论。
本发明提供了一种芯片的封装方法，包括以下步骤；提供基板，基板上形成有贯通其相对两侧的开口槽；提供离型基材，将所述离型基材粘接在基板的一侧，并覆盖所述开口槽；提供芯片，将芯片贴装在位于开口槽位置的离型基材上；从基板上远离所述离型基材的一侧进行封装，将芯片封装并固定在基板上；去除离型基材，得到芯片的封装结构。
采用这种的封装方法，可以将芯片封装在基板的开口槽位置，这不但提高了芯片与基板之间封装的可靠性，还可以减小芯片占用的空间，尤其是多个芯片堆叠时的厚度，从而降低了整个封装的厚度，这利于电子产品的轻薄化发展。
下面以三种封装方式为例，对本发明的封装工艺进行详尽的描述，这三种封装方式可以适用于不同芯片的封装。
图1a至图1f示出了本发明封装方法的第一实施方式。
参考图1a，提供具有开口槽10a的基板，该基板选用电路板1a，其内部形成有用于走线的电路布图。开口槽10a的尺寸及形状可以根据芯片的类型而定。将胶带2a粘接在电路板1a的其中一侧，并使胶带2a覆盖住开口槽10a的一侧开口。
参考图1b，将第一芯片3a贴装在胶带2a上位于开口槽10a的位置。第一芯片3a位于开口槽10a内，并通过胶带2a的胶层进行粘接。其中，第一芯片3a的高度可以大于电路板1a的厚度，也可以等于或者小于电路板1a的厚度。之后，通过引线将第一芯片3a的引脚导通到电路板1a的相应位置。
参考图1c，从电路板1a远离胶带2a的一侧对第一芯片3a进行封装，例如可以通过注塑的工艺或者线上膜(FOW)工艺对第一芯片3a进行封装，以得到第一封装层4a。对于芯片封装领域的技术人员而言，注塑的工艺或者线上膜(FOW)工艺属于常规的手段，对此不再具体说明。
该第一封装层4a将第一芯片3a及其引线同时封装在电路板1a上；同时第一封装层4a会填充在第一芯片3a与开口槽10a之间的间隙内，从而将第一芯片3a与电路板1a牢牢地结合在一起。
参考图1d，在第一封装层4a的表面贴装第二芯片5a，并将第二芯片5a的引脚通过引线导通到电路板1a上。第二芯片5a可以通过本领域技术人员所熟知的方式粘接在第一封装层4a的顶部表面，第二芯片5a的尺寸大于第一芯片3a的尺寸以及开口槽10a的尺寸，这属于典型的顶部芯片大、底部芯片小的封装结构。采用这样的结构设计，不用担心悬空导致的芯片在焊线过程中震动造成的一系列问题。
参考图1e，对第二芯片5a进行二次封装，得到第二封装层6a。该第二封装层6a可以通过注塑的工艺形成，通过第二封装层6a将第二芯片5a及其引线，以及第一封装层4a同时封装在电路板1a上。第二封装层6a与第一封装层4a可以采用相同的材质及工艺，在此不再具体说明。
参考图1f，将胶带2a揭开，从而得到芯片的封装结构。由于胶带2a仅靠其自身较弱的粘性粘接在电路板1a、第一芯片3a、第一封装层4a上，因此可直接将胶带2a撕下。
对于本领域的技术人员而言，还可以选用热解膜、光解膜，或者为包含离型层的基板作为芯片的暂时载体。例如当选用热解膜时，可以通过加热的方式去除热解膜；当选用光解膜时，可以通过照射的方式去除光解膜。当选用包含离型层的基板作为临时载体时，可根据离型层的类型选择不同的方式去除，离型层例如可以选择热解材质或者光解材质，在此不再具体说明。
对于本领域的技术人员而言，还可以包括切割的步骤，将上述得到的封装结构根据设计需要进行切割，得到独立的封装。
另外，上述步骤可以应用到大规模的生产线上，以同时制作大量的封装，在此不再具体说明
图2a至图2g示出了本发明封装方法的第二实施方式。
参考图2a，提供具有开口槽10b的基板，该基板选用电路板1b，其内部形成有用于走线的电路布图。开口槽10b的尺寸及形状可以根据芯片的类型而定。将热解膜2b粘接在电路板1b的其中一侧，并使热解膜2b覆盖住开口槽10b的一侧。
参考图2b，将第一芯片3b贴装在热解膜2b上位于开口槽10b的位置，且第一芯片3b的引脚朝向热解膜2b的方向。第一芯片3b位于开口槽10b内，并通过热解膜2b的胶层进行粘接。其中，第一芯片3b的高度可以大于电路板1b的厚度，也可以等于或者小于电路板1b的厚度。
参考图2c，将第二芯片5b贴装在第一芯片3b的顶部。第二芯片5b的尺寸与第一芯片3b的尺寸可以相同。第二芯片5b以其引脚远离热解膜2b的方式贴装在第一芯片3b的顶部表面。之后，通过引线将第二芯片5b的引脚导通到电路板1b的相应位置。
第一芯片3b可以位于电路板1b的开口槽10b内，即第一芯片3b的厚度小于电路板1b的厚度。这样第二芯片5b可以至少部分地位于开口槽10b内，使得两个芯片以嵌入电路板1b的方式进行堆叠。
参考图2d，从电路板1b远离热解膜2b的一侧对第一芯片3b、第二芯片5b进行封装，例如可以通过注塑的工艺或者线上膜(FOW)工艺对第一芯片3b、第二芯片5b进行封装，以得到第一封装层4b。对于芯片封装领域的技术人员而言，注塑的工艺或者线上膜(FOW)工艺属于常规的手段，对此不再具体说明。
该第一封装层4b将第一芯片3b、第二芯片5b及第二芯片5b的引线同时封装在电路板1b上；同时第一封装层4b会填充在芯片与开口槽10b之间的间隙内，从而将芯片与电路板1b牢牢地结合在一起。
参考图2e，将热解膜2b去除，从而得到芯片的封装结构。例如可通过加热的方式轻易地将热解膜2b从电路板1b、第一芯片3b、第一封装层4b上去除。
对于本领域的技术人员而言，还可以选用光解膜，或者为包含离型层的基板作为芯片的暂时载体，在此不再具体说明。
参考图2f，由于去除了热解膜2b，从而将第一芯片3b的下表面暴露出来，此时可以通过引线将第一芯片3b下表面的引脚导通到电路板1b的相应位置上。
参考图2g，从电路板1b的下表面对第一芯片3b及其引线进行再次封装，以得到第二封装层6b。例如可通过点胶、注塑或者线上膜的工艺进行再次封装。对于芯片封装领域的技术人员而言，点胶、注塑的工艺或者线上膜(FOW)工艺属于常规的手段，对此不再具体说明。
该第二封装层6b将第一芯片3b的下表面及其引线同时封装在电路板1b的下表面上，从而将芯片与电路板1b牢牢地结合在一起。
之后，还可以在电路板1b下表面的相应位置进行植锡球，以便于该封装与外部电路的导通，在此不再具体说明。
本实施例的这种嵌入式芯片堆叠的封装结构，相比于传统的芯片堆叠封装结构，封装厚度有大幅度的减小，以满足封装超薄化的需求。
图3a至图3g示出了本发明封装方法的第三实施方式。
参考图3a，提供具有开口槽10c的基板1c，开口槽10c的尺寸及形状可以根据芯片的类型而定。开口槽10c可以设置有多个，图3a示出了两个开口槽10c的示意图。将热解膜2c粘接在基板1c的其中一侧，并使热解膜2c覆盖住开口槽10c的一侧。
参考图3b，将芯片3c贴装在热解膜2c上位于开口槽10c的位置，且芯片3c的引脚朝向热解膜2c的方向。芯片3c位于开口槽10c内，并通过热解膜2c的胶层进行粘接。其中，芯片3c的高度可以大于基板1c的厚度，也可以等于或者小于基板1c的厚度。
参考图3c，从基板1c远离热解膜2c的一侧对芯片3c进行封装，例如可以通过注塑的工艺或者线上膜(FOW)工艺对芯片3c进行封装，以得到封装层4c。对于芯片封装领域的技术人员而言，注塑的工艺或者线上膜(FOW)工艺属于常规的手段，对此不再具体说明。
该封装层4c将芯片3c封装在基板1c上；同时封装层4c会填充在芯片3c与开口槽10c之间的间隙内，从而将芯片3c与基板1c牢牢地结合在一起。
参考图3d，优选地，可以对封装层4c的外表面进行减薄。例如可以通过研磨的方式进行减薄，减薄的厚度可以根据实际需要进行。例如可以设计芯片3c的厚度低于或者等于基板1c的厚度，此时可以将封装层4c减薄至将基板1c的表面露出。
参考图3e，将热解膜2c去除，从而得到芯片的封装结构。例如可通过加热的方式轻易地将热解膜2c从基板1c、芯片3c、封装层4c上去除。
对于本领域的技术人员而言，还可以选用光解膜，或者为包含离型层的基板作为芯片的暂时载体，在此不再具体说明。
参考图3f，由于去除了热解膜2b，从而将芯片3c的下表面暴露出来。可通过重新布线的工艺(RDL制程)在基板1c上进行电路的走线及引出。例如可以在基板1c制作导电线路7c及走线层；最终可在基板1c、芯片3c上形成植锡球8c，以便于该封装与外部电路的导通。这种在基板上重新布线的制程属于本领域技术人员的公知常识，在此不再具体说明。
参考图3g，沿着相应的位置切割基板1c，从而可得到多个独立的芯片封装。
本实施例的封装工艺属于面板级的扇出型封装，芯片封装在基板的开口槽内，使得封装的翘曲度可控；且采用粘接的工艺放置芯片，芯片的定位精度高；重新布线的制程可采用PCB加工工艺，设备和材料匹配性高，加工成本低。
虽然已经通过例子对本发明的一些特定实施例进行了详细说明，但是本领域的技术人员应该理解，以上例子仅是为了进行说明，而不是为了限制本发明的范围。本领域的技术人员应该理解，可在不脱离本发明的范围和精神的情况下，对以上实施例进行修改。本发明的范围由所附权利要求来限定。

Claims (10)

1.一种芯片的封装方法，其特征在于，包括以下步骤；
S100：提供基板，基板上形成有贯通其相对两侧的开口槽；
S200：提供离型基材，将所述离型基材粘接在基板的一侧，并覆盖所述开口槽；
S300：提供芯片，将芯片贴装在位于开口槽位置的离型基材上；
S400：对基板上远离所述离型基材的一侧进行封装，形成将芯片封装并固定在基板上的封装层；
S500：去除离型基材，得到芯片的封装结构。
2.根据权利要求1所述的芯片的封装方法，其特征在于，所述芯片的顶面与基板的顶面齐平，或者低于所述基板的顶面；在所述步骤S400后，还包括减薄所述封装层的步骤。
3.根据权利要求1所述的芯片的封装方法，其特征在于，所述步骤S300中，所述芯片以其引脚朝向离型基材的方式贴装在离型基材上；所述步骤S500之后，还包括在基板上进行重新布线的步骤。
4.根据权利要求3所述的芯片的封装方法，其特征在于，在进行重新布线的步骤之后，还包括切割得到多个独立的封装结构的步骤。
5.根据权利要求1所述的芯片的封装方法，其特征在于，在所述步骤300中，将芯片通过引线导通到基板上；所述步骤S400中，将芯片及其引线封装并固定在基板上；
之后还包括在封装层上贴装另一芯片，并将该另一芯片通过引线导通到基板上的步骤；以及包括对该另一芯片进行再次封装的步骤，形成将该另一芯片封装在基板上的另一封装层。
6.根据权利要求1所述的芯片的封装方法，其特征在于，所述步骤S300中，第一芯片以其引脚朝向离型基材的方式贴装在离型基材上，第二芯片以其引脚远离所述离型基材的方式贴装在第一芯片上，且第二芯片的引脚通过引线导通到基板上；
在所述步骤S400中，将第一芯片、第二芯片及第二芯片的引线封装并固定在基板上；
在所述步骤S500之后，还包括将第一芯片的引脚通过引线导通到基板上的步骤，以及包括从基板的另一侧对第一芯片及其引线进行再次封装的步骤。
7.根据权利要求6所述的芯片的封装方法，其特征在于，通过点胶工艺从基板的另一侧对第一芯片及其引线进行再次封装。
8.根据权利要求6所述的芯片的封装方法，其特征在于，所述第一芯片与第二芯片的尺寸相同。
9.根据权利要求1所述的芯片的封装方法，其特征在于，所述步骤S400中，通过注塑的工艺或者线上膜的工艺进行封装。
10.根据权利要求1所述的芯片的封装方法，其特征在于，所述离型基材为胶带，或者热解膜，或者光解膜，或者为包含离型层的基板。
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