CN103915414A - 倒装芯片晶片级封装及其方法 - Google Patents

倒装芯片晶片级封装及其方法 Download PDF

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CN103915414A
CN103915414A CN201310749734.5A CN201310749734A CN103915414A CN 103915414 A CN103915414 A CN 103915414A CN 201310749734 A CN201310749734 A CN 201310749734A CN 103915414 A CN103915414 A CN 103915414A
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tube core
flip
electronic packaging
group
chip
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CN103915414B (zh
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T.迈尔
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Infineon Technologies AG
Intel Deutschland GmbH
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Infineon Technologies AG
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    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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Abstract

本公开涉及倒装芯片晶片级封装及其方法，其中一种电子封装包括：倒装芯片部件，具有耦合到倒装芯片基底的第一管芯；第二管芯，堆叠在第一管芯上；密封化合物，形成在第一管芯和第二管芯周围；一组贯穿密封剂通孔TEV，提供贯穿密封化合物至倒装芯片基底的从电子封装的第一侧到电子封装的第二侧的一组电连接；和再分布层，在电子封装的第一侧上把第二管芯上的一组接触电连接到所述一组TEV。

Description

倒装芯片晶片级封装及其方法
技术领域
本公开涉及制造电子设备的装置和方法，更具体地，涉及电子封装及其制造方法。
背景技术
在制造集成电路(IC)时，称为芯片或管芯的IC通常在分布以及与其它电子组件集成之前被封装。这种封装通常包括把芯片密封在材料中并且在封装的外侧上提供电接触以提供到芯片的接口。除其他事项外，芯片封装还可提供防止污染物的保护，提供机械支撑，分散热量，并且减小热机械应力。
因为IC加工和IC封装之间的关系，IC封装也必须通常随着半导体工业的快速进步而发展。特别地，对封装IC和其它电子设备以使其更小、更快并且更加可靠的期望一直没有间断过。
发明内容
在本公开的第一方面，一种电子封装包括：倒装芯片部件，具有耦合到倒装芯片基底的第一管芯；第二管芯，堆叠在第一管芯上；密封化合物，形成在第一管芯和第二管芯周围；一组贯穿密封剂通孔（TEV)，提供贯穿密封化合物至倒装芯片基底的从电子封装的第一侧到电子封装的第二侧的一组电连接；和再分布层，在电子封装的第一侧上把第二管芯上的一组接触电连接到所述一组TEV。
在本公开的另一方面，提供一种用于制造电子封装的方法。所述方法包括：提供具有耦合到倒装芯片基底的第一管芯的倒装芯片部件；把第一管芯粘合到第二管芯；在第一管芯和第二管芯周围形成密封化合物；钻出从电子封装的第一侧到位于电子封装的第二侧的倒装芯片基底的一组贯穿密封剂通孔（TEV)；采用导电材料填充所述一组TEV；以及施加再分布层，所述再分布层在电子封装的第一侧上把第二管芯上的一组接触电连接到所述一组TEV。
在本公开的又一方面，一种存储器装置包括：倒装芯片部件，具有耦合到倒装芯片基底的第一管芯；第二管芯，堆叠在第一管芯上；密封化合物，形成在第一管芯和第二管芯周围；一组贯穿密封剂通孔(TEV)，提供贯穿密封化合物至倒装芯片基底的从电子封装的第一侧到电子封装的第二侧的一组电连接；和再分布层，在电子封装的第一侧上把第二管芯上的一组接触电连接到所述一组TEV。第一管芯和/或第二管芯包括存储器功能。
在本公开的再又一方面，一种电子封装包括第一电子封装和第二电子封装。第二电子封装包括：倒装芯片部件，具有耦合到倒装芯片基底的第一管芯；第二管芯，堆叠在第一管芯上；密封化合物，形成在第一管芯和第二管芯周围；一组贯穿密封剂通孔(TEV)，提供贯穿密封化合物至倒装芯片基底的从电子封装的第一侧到电子封装的第二侧的一组电连接；和再分布层，在电子封装的第一侧上把第二管芯上的一组接触电连接到所述一组TEV。第一电子封装与第二电子封装堆叠在一起以形成层叠封装(PoP)电子封装。
附图说明
为了进一步阐明本发明的以上和其它优点和特征，本发明更具体的描述将会通过参照在附图中示出的本发明的特定实施例提供。应该理解的是，这些附图仅描述本发明的典型实施例，并且因此不被视为限制其范围。本发明将通过使用附图采用另外的特征和细节进行描述和解释，其中：
图1是倒装芯片引线接合封装。
图2是倒装芯片晶片级封装。
图3图示用于制造图2中示出的倒装芯片晶片级封装的方法。
图4-13描述用于制造图2中示出的倒装芯片晶片级封装的工艺流程。
图14-23描述用于制造图2中示出的倒装芯片晶片级封装的替代的工艺流程。
图24是具有三芯片配置的倒装芯片晶片级封装。
具体实施方式
现在将参照附图，其中相同结构将会具有相同标号。应该理解，附图是本发明的示例性实施例的概略性和示意性表示，而非限制本发明，附图未必按照比例绘制。
芯片(替代地，在这里称为管芯)通常在分布以及与其它电子组件集成之前被封装。这种封装通常包括把芯片密封在材料中并且在封装的外侧上提供电接触以提供到芯片的接口。除其他事项外，芯片封装还可提供防止污染物的保护，提供机械支撑，分散热量，并且减小热机械应力。
在单一芯片封装内堆叠多个芯片是越来越普遍的封装要求，以便减小例如总体组件尺寸、功能电路速度和总体成本。
图1是倒装芯片引线接合封装10。倒装芯片引线接合封装10包括两个芯片1、3，布置芯片1、3以使得芯片1堆叠在芯片3上面。芯片3借助于凸点底部填充层9耦合到分层基底11。分层基底11又耦合到焊球13。以这种方式，芯片3以物理方式以及以电方式间接耦合到一些焊球13，从而一个子集的焊球13形成用于芯片3的电接口。同样地，芯片1借助于接合引线5电耦合到分层基底11。以这种方式，芯片1间接地电耦合到一些焊球13，从而一个子集的焊球13形成用于芯片1的电气接口。密封化合物7在芯片1、3、接合引线5和凸点底部填充层9周围模制成型。密封化合物7通常形成在分层基底11上面。以这种方式，倒装芯片引线接合封装10形成具有借助于焊球13提供的接口的整体封装。
尽管倒装芯片引线接合封装10和其它引线接合封装提供用于封装生产的方法，但是工业中正在发生的进步已朝着更低的封装轮廓和增加的电性能推进。
贯穿硅通孔(TSV)提供用于堆叠目的的贯穿半导体晶片的连接。TSV可提供更好的电性能和更低的轮廓。然而，成本和可靠的供应链管理通常可能会限制工业内的广泛的TSV使用。
图2是倒装芯片晶片级封装10’。 倒装芯片晶片级封装10’包括倒装芯片部件18，倒装芯片部件18包括耦合到倒装芯片基底11’的管芯3’。如图所示，管芯3’借助于凸点底部填充层9’耦合到倒装芯片基底11’。
管芯1’布置在管芯3’上面，并且密封化合物7’形成在管芯1’和管芯3’周围。在形成密封化合物7’之前，可通过在管芯1’和管芯3’之间施加粘合剂15(诸如，管芯附着膜(DAF))把管芯1’粘合到管芯3’。例如，粘合剂15可通过把粘合剂层叠、打印或分配到管芯之一上并且随后在固化之前把其余管芯放置在粘合剂上的方式被施加。
一组贯穿密封剂通孔(TEV)19提供贯穿倒装芯片晶片级封装10’的密封化合物7’的电气连接。另外，再分布层17把TEV 19电连接到管芯1’。倒装芯片晶片级封装10’还包括粘合到倒装芯片基底11’的焊球13’，并且可包括覆盖再分布层17和TEV 19以保护否则会露出的部件16’的保护层16。倒装芯片晶片级封装10’可还包括第二管芯和再分布层之间的介电层。
可根据标准半导体制造工艺加工管芯1’和管芯3’。也就是说，通常在晶锭生长之后，它被切成晶片。晶片的区域可经受沉积、去除、图案化和掺杂工艺。一旦晶片已被处理，晶片通常被安装并且切成个体管芯。特别地，管芯3’被进一步处理并且被提供作为倒装芯片部件18的一部分。也就是说，使用倒装芯片技术处理管芯3’，以使得管芯3’耦合到倒装芯片基底11’，由此形成倒装芯片部件18。
密封化合物7’通常由塑料材料组成，但如果需要，可使用其它材料，诸如，陶瓷和金属和硅或玻璃。特别地，热固性模塑化合物是基于环氧树脂的一种类型的塑料材料。这些类型的化合物已在历史上被用在电子封装应用中。热塑性塑料(诸如，高纯度含氟聚合物)是可被用作密封化合物7’的另一类型的塑料材料。
通过钻出贯穿密封化合物7’的孔并且随后采用导电材料填充钻出的孔，形成TEV 19。例如，可采用机械钻头、激光或者通过化学蚀刻执行钻出TEV孔。
管芯1’上的接触可按照各种方式布置。然而，如图2中所述，布置管芯1’，以使其接触布置为与管芯3’上的接触相对。以这种方式，再分布层17能够被直接施加在管芯1’上方并且由此连接到管芯1’上的接触。优选地使用薄膜技术施加再分布层17。除其他技术之外，薄膜淀积可以例如经由溅射、电镀或化学气相沉积(CVD) 被实现。
根据倒装芯片晶片级封装10’建立的电子封装还可包括一个或多个下面的特征或者与一个或多个下面的特征组合。管芯1’和/或管芯3’可包括存储器功能。例如，倒装芯片晶片级封装10’可实现动态随机存取存储器(DRAM)。电子封装可包括第一电子封装和第二电子封装，根据倒装芯片晶片级封装10’建立所述第一电子封装和第二电子封装中的至少一个；第一电子封装可与第二电子封装堆叠在一起以形成层叠封装(PoP)电子封装。以这种方式，如图1中所绘制的管芯1’和管芯3’由第一电子封装和第二电子封装替换，而倒装芯片晶片级封装10’的其余结构保持相对不变。
倒装芯片晶片级封装10’可包括堆叠在倒装芯片部件18的管芯3’上的另外的管芯。也就是说，除了管芯1’和管芯3’之外，倒装芯片晶片级封装10’可包括更多的管芯，从而倒装芯片晶片级封装10’中的管芯的总数是三个或更多。
可构造倒装芯片晶片级封装10’，以使得第二管芯上的一组接触和电子封装的第一侧的表面之间的距离小于大约20μm。这种配置减小封装尺寸并且可减小总体电子组件尺寸。
以下具体参照图3-23讨论关于晶片级封装10’的制造的进一步细节。图3图示用于制造图2中示出的倒装芯片晶片级封装的方法，而图4-13描述用于制造图2中示出的倒装芯片晶片级封装10’的工艺流程，并且图14-23描述用于制造图2中示出的倒装芯片晶片级封装10’的替代的工艺流程。
参照图3，提供用于制造电子封装的方法30。在图4中，提供具有可剥离的带子（tape）35的模具载体33。例如，粘性箔可被用作可剥离的带子35并且例如通过层叠而被施加到模具载体33的上面。
在图5中，管芯1’借助于可剥离的带子35粘合到模具载体33。优选地，管芯1’被正面向下放置在可剥离的带子35上。也就是说，布置管芯1’，以使得其上面的电接触朝向模具载体33。可根据标准半导体制造工艺加工管芯1’和管芯3’。也就是说，通常在晶锭生长之后，它被切成晶片。晶片的区域可经受沉积、去除、图案化和掺杂工艺。一旦晶片已被处理，晶片通常被安装并且切成个体管芯。特别地，管芯3’被进一步处理并且被提供作为倒装芯片部件18的一部分。也就是说，使用倒装芯片技术处理管芯3’，以使得管芯3’耦合到倒装芯片基底11’，由此形成倒装芯片部件18。
在图6中，粘合剂15随后被施加于管芯1’的一侧。优选地，粘合剂15被施加于管芯1’的与管芯1’粘合到模具载体33’的一侧相反的一侧，或者更简单地，粘合剂15优选地被施加于管芯1’的背面。通过在管芯1’和管芯3’之间施加粘合剂15(诸如，管芯附着膜(DAF))，管芯1’可粘合到管芯3。例如，粘合剂15可通过层叠、打印或分配粘合剂的方式被施加。
方法30随后包括：如图7中所示，提供21具有耦合到倒装芯片基底11’的管芯3’的倒装芯片部件18，并且把管芯3’粘合23到管芯1’。由于如以上参照图6所讨论，管芯1’的背面已经具有施加于其上的粘合剂15，所以管芯3’可借助于先前提供的粘合剂15粘合到管芯1’。以这种方式，倒装芯片部件18通过管芯1’和管芯3’的粘合而粘合到模具载体33。如果需要，则粘合剂15可通过增加能量固化。例如，可增加化学品、热或紫外(UV)光以使粘合剂15固化。
方法30还包括：如图8中所示，在管芯1’和管芯3’周围形成25密封化合物37。密封化合物7’通常由塑料材料组成，但如果期望，可使用其它材料，诸如陶瓷和金属。特别地，热固性模塑化合物是基于环氧树脂的一种类型的塑料材料。这些类型的化合物已在历史上被用在电子封装应用中。热塑性塑料(诸如，高纯度含氟聚合物)是可被用作密封化合物7’的另一类型的塑料材料。需要注意的是，可使倒装芯片基底11’的露出侧保留不被密封化合物7’覆盖。为了不采用密封化合物7’覆盖倒装芯片基底11’，可使用压缩模塑工具中的顶箔，或者可采用注入模塑技术。另一可能性将会是在模塑之后把附着的模具化合物向下研磨至基底接触。
在图9中，在已形成密封化合物37之后，剥离模具载体33。作为剥离模具载体33的一部分，也可去除粘合剂35，并且可施加并且构造介电层39。例如，通过旋涂和光刻法或者通过层叠和激光构造，可执行介电层39的施加。也可在稍后施加介电层39，或者能够与TEV钻孔同时构造介电层39。
方法30还包括：如图10中所示，钻出27从电子封装的第一侧到位于电子封装的第二侧的倒装芯片基底11’的一组贯穿密封剂通孔(TEV)19。通过如图10中所示钻出贯穿密封化合物7’(并且可能贯穿介电材料，如果以前未构造的话)的孔并且随后如图11中所示采用导电材料填充钻出的孔，形成TEV 19。例如，可采用机械钻头、激光或者通过化学蚀刻执行钻出TEV孔。在执行钻孔时，倒装芯片基底11’上的通孔止动器可被用于提供钻孔的停止点。
方法30随后包括：如图11中所示，采用导电材料填充29 TEV 19，并且施加31再分布层17，由此在电子封装10’的第一侧上把管芯1’上的一组接触电连接到TEV 19。采用导电材料填充29 TEV 19并且施加31再分布层17可在不同部分中执行，或者可在单一步骤中同时发生。再分布层17电连接TEV 19与焊球位置，并且也可在给定平面中提供片上连接和多个芯片之间的连接。
在图12中，可在再分布层17上面施加焊接止动器或背面保护(BSP)，诸如保护层16，由此例如对电子封装10’给予一致的黑色背面，保护再分布层17，并且保护TEV 19。可使用旋涂、层叠、喷涂或打印工艺施加这个焊接止动器或BSP。
最后，在图13中，焊球13’被施加或粘合到倒装芯片基底11’，并且如果各封装还未分开，则各封装可在此时分开。焊球13’可以是例如传统的焊球、半球、聚合物核心球或焊盘栅阵列(LGA)，并且可例如经由焊接到倒装芯片基底11’而粘合到倒装芯片基底11’。
除了产生更小、更高效的封装之外，倒装芯片晶片级封装10’允许在加工过程之间单独测试并且预烧（burning-in）倒装芯片部件18。也就是说，在继续制造倒装芯片晶片级封装10’之前，可单独加工、测试并且预烧倒装芯片部件18。
参照图14-23，示出替代的工艺流程。在图14中，提供具有可剥离的带子35的模具载体33。也就是说，可剥离的带子35被施加于模具载体33。例如，粘性箔可被用作可剥离的带子35并且层叠到模具载体33。
在图15中，倒装芯片部件18经由先前施加的可剥离的带子35粘合到模具载体33。更具体地，倒装芯片基底11’经由可剥离的带子35粘合到模具载体33。
类似于此前描述的工艺流程，在图16中，管芯1’随后借助于粘合剂15附着于管芯3’。粘合剂15被施加于管芯3’的一侧，或者替代地被施加于管芯1’的一侧。优选地，粘合剂15被施加于管芯3’的与管芯3’粘合到倒装芯片基底11’的一侧相反的一侧，或者更简单地，粘合剂15优选地被施加于管芯3’的背面。通过在管芯1’和管芯3’之间施加粘合剂15(诸如，管芯附着膜(DAF))，管芯1’可粘合到管芯3’。例如，粘合剂15可通过层叠、打印或分配粘合剂的方式被施加。管芯1’和管芯3’随后借助于先前施加的粘合剂15粘合在一起。以这种方式，管芯1’通过管芯1’和管芯3’的粘合而粘合到模具载体33。如果需要，则粘合剂15可通过附加能量而被固化。例如，可附加化学品、热或紫外(UV)光以使粘合剂15固化。优选地，如图中所示布置管芯1’和管芯3’，以使各接触彼此相对。
如图17中所示，在管芯1’和管芯3’上以及在管芯1’和管芯3’周围形成密封化合物7’，并且去除模具载体33以及可去除的粘合剂35。密封化合物7’通常由塑料材料组成，但如果需要，可使用其它材料，诸如陶瓷和金属。特别地，热固性模塑化合物是基于环氧树脂的一种类型的塑料材料。这些类型的化合物已在历史上被用在电子封装应用中。热塑性塑料(诸如，高纯度含氟聚合物)是可被用作密封化合物7’的另一类型的塑料材料。
在图18中，通过例如研磨密封化合物37直至管芯1’的接头露出并且密封化合物7’与管芯1’的表面形成基本上较平坦的表面，管芯1’的接触或施加的接头可随后露出。替代地，通过激光钻穿密封化合物7’，接触或施加的接头可露出。作为另一选择，可使管芯1’的具有接触的一侧保留相对地不被密封化合物7’覆盖。为了不采用密封化合物7’覆盖倒装芯片基底11’，可使用压缩模塑工具中的顶箔，或者可采用注入模塑技术。
在图19中，施加并且至少部分地构造介电层39。例如，通过旋涂或者通过层叠和激光构造，可执行介电层39的施加。也可在稍后施加介电层39，或者能够与TEV钻孔同时构造介电层39。
在图20中，钻出TEV 19，并且在图21中，采用导电材料填充TEV 19。TEV 19从电子封装的第一侧前进到位于电子封装的第二侧的倒装芯片基底11’。通过钻出贯穿密封化合物7’(并且可能贯穿介电层39)的孔并且随后采用导电材料填充钻出的孔，形成TEV 19。例如，可采用机械钻头、激光器或者通过化学蚀刻执行钻出TEV孔。在执行钻孔时，倒装芯片基底11’上的通孔止动器可被用于提供用于打钻的停止点。
在图21中，施加再分布层17以便把TEV 19电连接到管芯1’。采用导电材料填充29 TEV 19并且施加31再分布层17可在不同部分中执行，或者可在单一步骤中同时发生。再分布层17电连接TEV 19与焊球位置，并且也可在给定平面中提供片上连接和多个芯片之间的连接。
在图22中，可在再分布层17上面施加焊接止动器或背面保护(BSP)，诸如保护层16，由此例如对电子封装10’给予一致的黑色背面，保护再分布层17，并且保护TEV 19。可使用旋涂、层叠或打印过程施加这个焊接止动器或BSP。
最后，在图23中，焊球13’被施加或粘合到倒装芯片基底11’，并且如果各封装还未分开，则各封装可在此时分开。如以上所讨论，焊球13’可以是例如传统的焊球、半球或焊盘栅阵列(LGA)，并且可例如经焊接到倒装芯片基底11’而粘合到倒装芯片基底11’。
可根据以上描述配置另外的管芯。例如，如图24中所示，可构造倒装芯片晶片级封装240，以使得管芯41和43与管芯3’堆叠在一起。以这种方式，多个管芯可被引入到这种电子封装中。特别地，并非经由粘合剂15把单一管芯粘合到管芯3’，而是可把多个管芯粘合到管芯3’。
在不背离本发明的精神或本质特性的情况下，本发明可实现为其它特定形式。所描述的实施例应在所有方面被视为仅是说明性的，而非限制性的。本发明的范围因此由所附权利要求指示，而非由前面的描述指示。落在权利要求的等同物的含义和范围内的所有变化将被包括在其范围内。 

Claims (21)

1.一种电子封装，包括：
倒装芯片部件，具有耦合到倒装芯片基底的第一管芯；
第二管芯，堆叠在第一管芯上；
密封化合物，形成在第一管芯和第二管芯周围；
一组贯穿密封剂通孔TEV，提供贯穿密封化合物至倒装芯片基底的从电子封装的第一侧到电子封装的第二侧的一组电连接；和
再分布层，在电子封装的第一侧上把第二管芯上的一组接触电连接到所述一组TEV。
2.根据权利要求1所述的电子封装，还包括：一组另外的管芯，堆叠在倒装芯片部件的第一管芯上。
3.根据权利要求1所述的电子封装，其中所述第一管芯的一组接触布置为与第二管芯的一组接触相对。
4.根据权利要求1所述的电子封装，其中所述再分布层是薄膜层。
5.根据权利要求1所述的电子封装，还包括：保护层，覆盖再分布层和TEV。
6.根据权利要求1所述的电子封装，还包括：焊球，粘合到倒装芯片基底。
7.根据权利要求1所述的电子封装，其中所述第二管芯上的一组接触和电子封装的第一侧的表面之间的距离小于大约20μm。
8.根据权利要求1所述的电子封装，还包括：介电层，位于第二管芯和再分布层之间。
9.一种用于制造电子封装的方法，所述方法包括：
提供具有耦合到倒装芯片基底的第一管芯的倒装芯片部件；
把第一管芯粘合到第二管芯；
在第一管芯和第二管芯周围形成密封化合物；
钻出从电子封装的第一侧到位于电子封装的第二侧的倒装芯片基底的一组贯穿密封剂通孔TEV；
采用导电材料填充所述一组TEV；以及
施加再分布层，所述再分布层在电子封装的第一侧上把第二管芯上的一组接触电连接到所述一组TEV。
10.根据权利要求9所述的方法，还包括：施加覆盖再分布层和TEV的保护层。
11.根据权利要求9所述的方法，还包括：把焊球粘合到倒装芯片基底。
12.根据权利要求9所述的方法，还包括：单独测试并且预烧倒装芯片部件。
13.根据权利要求9所述的方法，还包括：
采用可剥离的粘合剂把第二管芯粘合到模具载体；以及
从第二管芯去除模具载体。
14.根据权利要求9所述的方法，还包括：
采用可剥离的粘合剂把倒装芯片部件粘合到模具载体；以及
从倒装芯片部件去除模具载体。
15.根据权利要求14所述的方法，还包括：把一组接头耦合到第二管芯上的一组接触上。
16.根据权利要求13所述的方法，其中所述接头包括铜。
17.根据权利要求14所述的方法，还包括：
在第二管芯上方形成密封化合物；以及
使接头露出。
18.根据权利要求17所述的方法，其中使接头露出包括：研磨密封化合物直至接头露出，其中所述密封化合物形成基本上较平坦的表面。
19.根据权利要求17所述的方法，其中使接头露出包括：对密封化合物进行激光钻孔。
20.一种存储器装置，包括：
倒装芯片部件，具有耦合到倒装芯片基底的第一管芯；
第二管芯，堆叠在第一管芯上；
密封化合物，形成在第一管芯和第二管芯周围；
一组贯穿密封剂通孔TEV，提供贯穿密封化合物至倒装芯片基底的从电子封装的第一侧到电子封装的第二侧的一组电连接；和
再分布层，在电子封装的第一侧上把第二管芯上的一组接触电连接到所述一组TEV，
其中由第一管芯和第二管芯构成的组中的至少一个包括存储器功能。
21.一种电子封装，包括：
第一电子封装；和
第二电子封装，包括：
       倒装芯片部件，具有耦合到倒装芯片基底的第一管芯；
       第二管芯，堆叠在第一管芯上；
       密封化合物，形成在第一管芯和第二管芯周围；
       一组贯穿密封剂通孔TEV，提供贯穿密封化合物至倒装芯片基底的从电子封装的第一侧到电子封装的第二侧的一组电连接；和
       再分布层，在电子封装的第一侧上把第二管芯上的一组接触电连接到所述一组TEV，
其中所述第一电子封装与第二电子封装堆叠在一起以形成层叠封装PoP电子封装。
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DE102013113469B4 (de) 2023-04-27
TW201605009A (zh) 2016-02-01
TW201444048A (zh) 2014-11-16
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US8729714B1 (en) 2014-05-20
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