CN102194705A - 具有保护性中介层的嵌入式裸片 - Google Patents

具有保护性中介层的嵌入式裸片 Download PDF

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Publication number
CN102194705A
CN102194705A CN2011100682079A CN201110068207A CN102194705A CN 102194705 A CN102194705 A CN 102194705A CN 2011100682079 A CN2011100682079 A CN 2011100682079A CN 201110068207 A CN201110068207 A CN 201110068207A CN 102194705 A CN102194705 A CN 102194705A
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China
Prior art keywords
nude film
intermediary layer
substrate
lamination
layer
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Granted
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CN2011100682079A
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CN102194705B (zh
Inventor
吴亚伯
吴嘉洛
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Kaiwei International Co
Marvell International Ltd
Marvell Asia Pte Ltd
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Mawier International Trade Co Ltd
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Publication of CN102194705A publication Critical patent/CN102194705A/zh
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
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Abstract

本公开涉及具有保护性中介层的嵌入式裸片，本公开的实施方式提供一种衬底，该衬底具有(i)第一叠层、(ii)第二叠层和(iii)布置于第一叠层与第二叠层之间的芯材料；以及附接至该第一叠层的裸片，该裸片具有键合至裸片的有源侧的表面的中介层，该表面包括(i)电介质材料和(ii)用以路由裸片的电信号的键合焊盘，中介层具有形成于其中的通孔，该通孔电耦合至键合焊盘以进一步路由裸片的电信号，其中裸片和中介层嵌入在衬底的芯材料中。可能描述和/或要求保护其他实施方式。

Description

具有保护性中介层的嵌入式裸片
与相关申请的交叉引用
本公开要求对提交于2010年3月18日的编号为61/315,319的美国临时专利申请的优先权，除可能存在的任何与本说明书不一致的章节之外，出于所有目的将该专利申请整体并入本文。
技术领域
本公开的实施方式涉及集成电路领域，并且更具体地涉及具有保护性中介层(interposer)的嵌入式裸片的技术、结构和配置。
背景技术
在此提供的背景技术描述是为了一般性地呈现本公开的上下文的目的。就在此背景技术部分中所描述的程度上的当前提名发明人的工作以及在提交时不作为现有技术的描述方面，都不被明示或者暗示地承认其为本公开的现有技术。
集成电路器件(比如晶体管)一般形成在裸片上，所述裸片耦合至衬底以形成封装体组件。在一些新兴的封装技术中，形成衬底以在该衬底上嵌入裸片。然而，裸片可能包括诸如低k电介质之类的电介质材料，这些材料容易遭受由应力或其他机械力所造成的裂缝、分层或者其他产量/可靠性缺陷。因此，与裸片在衬底内的嵌入相关联的应力或其他机械力可能会破坏电介质材料，从而导致裸片的产量/可靠性较低。
发明内容
在一个实施方式中，本公开包括一种方法，该方法包括：提供一种裸片，所述裸片具有键合至该裸片的有源侧的表面的中介层，该表面包括(i)电介质材料和(ii)用以路由裸片的电信号的键合焊盘，该中介层具有形成于其中的通孔，所述通孔电耦合至键合焊盘以进一步路由裸片的电信号；将裸片附接至衬底的一层；以及形成衬底的一个或多个附加层以将裸片嵌入衬底。
在另一实施方式中，本公开包括一种衬底，该衬底具有(i)第一叠层、(ii)第二叠层以及(iii)布置于第一叠层与第二叠层之间的芯材料；以及附接至第一叠层的裸片，所述裸片具有键合至该裸片的有源侧的表面的中介层，所述表面包括(i)电介质材料和(ii)用以路由裸片的电信号的键合焊盘，所述中介层具有形成于其中的通孔，该通孔电耦合至键合焊盘以进一步路由裸片的电信号，其中裸片和中介层嵌入在衬底的芯材料中。
附图说明
通过结合附图的以下详细描述将很容易理解本公开的实施方式。为了便于这一说明，相似参考编号指示相似结构元件。本文的实施方式通过举例方式而不是通过在附图中进行限制的方式来示出。
图1示意性地示出一种使用中介层来保护嵌入在衬底中的裸片的示例封装体组件。
图2示意性地示出在被耦合在一起之前的裸片和中介层。
图3示意性地示出在将裸片和中介层附接至衬底的一层后的封装体组件。
图4至图8示意性地示出在形成衬底的用以将裸片嵌入衬底的一个或多个附加层后的封装体组件。
图9是一种用于制造本文所述封装体组件的方法的工艺流程图。
具体实施方式
本公开的实施方式描述针对嵌入于衬底中的裸片和中介层的技术、结构和配置。在以下详细描述中，对构成本文一部分的随附附图做出了参考，在附图中自始至终以相似编号指示相似部件。可以利用其他实施方式以及做出结构或逻辑改变而不偏离本公开的范围。因此，以下详细描述并非以限制意义做出，并且实施方式的范围是由所附权利要求及其等同体来定义的。
描述可以使用基于透视的描述，比如上/下、之上/之下和/或顶部/底部。这样的描述仅用来帮助进行讨论，而并非旨在将本文所描述的实施方式的应用约束到任何特定取向。
针对本公开的目的，表述“A/B”意指A或者B。针对本公开的目的，表述“A和/或B”意指“(A)、(B)或者(A和B)”。针对本公开的目的，表述“A、B和C中的至少一个”意指“(A)、(B)、(C)、(A和B)、(A和C)、(B和C)或者(A、B和C)”。针对本公开的目的，表述“(A)B”意指“(B)或者(AB)”，亦即A为可选元素。
以对理解所提出的主题内容最有帮助的方式，将各种操作依次描述为多个分立的操作。然而，描述的顺序不应解释为暗示这些操作一定依赖于顺序。具体而言，这些操作可以不以所展现的顺序来执行。所描述的操作可以以与所描述的实施方式不同的顺序来执行。在附加实施方式中，可以执行各种附加操作和/或省略掉所描述的操作。
描述使用了短语“在一个实施方式中”、“在实施方式中”或者类似的语言，它们可以各自指一个或多个相同或不同的实施方式。此外，关于本公开的实施方式所用的术语“包括”、“包含”、“具有”等是同义的。
图1示意性地示出使用中介层108来保护嵌入在衬底160中的裸片102的示例封装体组件100。衬底160包括第一叠层116、第二叠层120和放置于第一叠层116与第二叠层120之间的芯材料118。第一叠层116和/或第二叠层120可以包含叠合材料，举例而言，比如基于环氧树脂/树脂的材料。在一些实施方式中，叠合材料包含4号阻燃剂(Flame Retardant 4，FR4)或者双马来酰亚胺三嗪(BT)。芯材料118例如可以包含树脂。在一些实施方式中，芯材料118包含B/C阶段热固性树脂。材料并不限于这些例子，并且在其他实施方式中可以使用其他针对第一叠层116、第二叠层120和/或芯材料118的合适的材料。
如图所示，衬底160还包括耦合至第一叠层116的第一阻焊(solder mask)层124和耦合至第二叠层120的第二阻焊层122。第一阻焊层124和第二阻焊层122一般包括阻焊(solder resist)材料，举例而言，比如环氧树脂。在其他实施方式中可以使用其他合适的材料来制造第一阻焊层124和第二阻焊层122。
衬底160还包括路由结构126、128、130、132和134，该路由结构分别设置于第一叠层116、芯材料118、第二叠层120、第二阻焊层122和第一阻焊层124中。路由结构126、128、130、132和134一般包括导电材料(例如，铜)，以路由裸片102的电信号。裸片102的电信号例如可以包括输入/输出(I/O)信号和/或用于形成于裸片102上的集成电路(IC)器件(未示出)的供电/接地。
如图所示，路由结构126、128、130、132和134可以包括：用以在衬底160的一层内路由电信号的线型结构、和/或用以将电信号路由通过衬底160的层的通孔型结构。在其他实施方式中，路由结构126、128、130、132和134可以包括除所描绘的配置之外的其他配置。虽然已描述并示出了用于衬底160的特定配置，但其他使用三维(3D)封装方法来将一个或多个裸片进行嵌入的衬底亦可从本文所述原理中受益。
如图所示，裸片102和中介层108可以被嵌入在衬底160中。根据各个实施方式，裸片102和中介层108嵌入在第一叠层116与第二叠层120之间的芯材料118中。
裸片102包括半导体材料，比如硅，并且一般包含IC器件(未示出)，比如形成于裸片102的有源侧S1上的用于逻辑和/或存储器或其他电路系统的晶体管。裸片102的非有源侧S2与裸片102的有源侧S1相对布置。有源侧S1和非有源侧S2一般指裸片102的相对表面，以便于对本文所述各种配置的描述而并非旨在限于裸片102的特定结构。
在一些实施方式中，使用胶黏剂(举例而言，比如树脂)将裸片102的非有源侧S2上的表面附接至第一叠层116。在其他实施方式中，可以使用其他技术(比如使用载体组)将裸片102耦合至第一叠层116。
裸片102的有源侧S1具有一个包括电介质材料104的表面。在一些实施方式中，电介质材料104包含低k电介质材料，该低k电介质材料具有比二氧化硅的介电常数更小的介电常数。低k电介质材料，诸如那些用于制造包括具有大约40纳米或更小尺寸的特征的裸片的材料，一般可能具有比非低k电介质材料更易遭受来自工艺相关应力的结构缺陷的材料性质。根据各个实施方式，电介质材料104包含掺杂有诸如碳或氟之类材料的二氧化硅。在其他实施方式中，电介质材料104可以包括其他低k电介质材料。
裸片102的有源侧S1上的表面还包括一个或多个键合焊盘106或者类似的结构，用于路由裸片102的电信号。该一个或多个键合焊盘106一般包括导电材料，举例而言，比如铝或者铜。在其他实施方式中可以使用其他合适的材料。
在一些实施方式中裸片102可以包括一个或多个裸片。例如，裸片102可以是片上系统(SOC)或者多芯片模块(MCM)配置的组成部分。
如图所示，中介层108耦合至裸片102(例如，在有源侧S1上的)的具有电介质材料104和一个或多个键合焊盘106的表面。中介层108一般包含形成于诸如硅之类的半导体材料中的一个或多个通孔110。在一些实施方式中，如图所示，该一个或多个通孔110包括硅贯通孔(through-silicon via，TSV)，其完全穿透中介层108。一个或多个通孔110电耦合至一个或多个键合焊盘106并且一般填充有导电材料(例如铜)以进一步路由裸片102的电信号。
可以例如使用热压缩工艺或者焊接回流工艺将中介层108键合至裸片102。在一些实施方式中，将与一个或多个通孔110耦合的金属或焊接材料键合至布置于裸片102的有源侧S1上的金属或焊接材料。例如，可以使用热压缩来形成中介层108与裸片102之间的金属-金属键合，举例而言，诸如铜与铜、金与铜或者金与金。可以使用焊接回流来形成焊料键合，举例而言，诸如焊料与焊料或者焊料与金属。可以使用各种结构来形成键合，举例而言，诸如包括再分布层(RDL)焊盘配置的凸块、导柱(pillar)和焊盘(例如一个或多个键合焊盘106)。在其他实施方式中可以使用其他合适的材料、结构和/或键合技术。
在一些实施方式中，裸片102和中介层108二者包括具有相同或相似热膨胀系数(CTE)的材料(例如，硅)。针对裸片102和中介层108使用具有相同或相似CTE的材料减小了与材料的加热和/或冷却失配相关联的应力。
根据各个实施方式，中介层108被配置用以保护裸片102的电介质材料104免受与在衬底160中嵌入裸片102相关联的裂缝或其他缺陷的损害。例如，用以在衬底160中嵌入裸片102的一个或多个层的形成(例如，芯材料118的沉积)可以产生应力，而该应力造成裸片的电介质材料104中的结构缺陷。中间层108向裸片102(例如电介质材料104)提供物理缓冲、支撑以及加固剂，特别是在形成所述一个或多个层用以在衬底160中嵌入裸片102的过程中尤为如此。亦即，本文所述的耦合至中介层108的裸片102提供受保护的集成电路结构150，其在结构上比仅裸片102自身更能抵抗与衬底160的制造相关的应力，从而使得裸片102产量和可靠性提高。虽然已针对图1中所示衬底160总体上描述了实施方式，但从这些原理中受益的其他衬底配置也包括在本公开的范围中。
路由结构126、128、130、132和134电耦合至一个或多个通孔110，以进一步在整个衬底160中路由裸片102的电信号。例如，一个或多个通孔110可以电耦合至路由结构128，该路由结构128使用扇出、扇入或直式连接来布置在芯材料118的区域中。在一些实施方式中，包括导电材料(例如铜)的再分布层112形成于中介层108上，以在一个或多个通孔110与路由结构128之间路由电信号。如图所示，路由结构126、128、130、132和134可以用于在衬底160的相对表面上为裸片102的电信号提供电连接。
可以形成附加结构来进一步路由裸片102的电信号。例如，可以在衬底160的表面上形成一个或多个键合焊盘136。在所描绘的实施方式中，一个或多个键合焊盘136布置在第一阻焊层124中并且电耦合至一个或多个通孔110。虽未绘出，但在其他实施方式中可以在第二阻焊层122中形成一个或多个键合焊盘。一个或多个键合焊盘136一般包括导电材料，比如铜或者铝。在其他实施方式中可以使用其他导电材料来形成一个或多个键合焊盘136。
在一些实施方式中，在一个或多个键合焊盘136上形成一个或多个焊球138或者类似的封装体互连结构，以促进封装体组件100与其他电子部件(例如，诸如母板之类的印刷电路板)的电耦合。根据各个实施方式，封装体组件100为球栅阵列(BGA)封装体。在其他实施方式中，封装体组件100可以包括其他类型的封装体。
可将无源或有源器件耦合至衬底160。例如，在图1中，无源器件175(例如电容器)电耦合至布置在第二阻焊层122中的路由结构132。在其他实施方式中，可以将其他类型的无源和/或有源器件电耦合至衬底160。
图2示意性地示出在被耦合在一起之前的裸片102和中介层108。裸片102和中介层108可以与已针对图1描述的实施方式相一致。
可以使用公知的半导体制造技术来制作裸片102。例如，裸片102可以与多个其他裸片形成在一个晶片上，其中在裸片102的有源侧S1上形成有诸如晶体管之类的一个或多个IC器件(未示出)。电介质材料104和一个或多个键合焊盘106一般形成在裸片102的有源侧S1上的表面上。可将晶片单体化，以提供单体形式的裸片102。
中介层108可以同样使用公知的半导体制造技术来制作。与裸片102类似，中介层108可以与多个其他中介层形成于一个晶片上。穿过中介层108可以形成一个或多个通孔110和/或在中介层108的表面上可以形成再分布层112。可将晶片单体化，以提供单体形式的中介层108。
根据各种技术，裸片102和中介层108可以以单体形式或晶片形式或者单体与晶片组合的形式来键合在一起。例如，可将中介层108进行单体化并且将其键合至晶片形式的裸片102，或者反之亦然。
根据各个实施方式，使用如本文所述的热压缩工艺或者焊接回流工艺将中介层108键合至裸片102。亦即，在中介层108和裸片102上形成一个或多个导电结构(例如，导柱、凸块、焊盘、再分布层)，以在中介层108与裸片102之间形成键合。可以使用任何合适的热压缩工艺或焊接回流工艺将裸片102的一个或多个键合焊盘106电耦合至中介层108的一个或多个通孔110，以在一个或多个导电结构之间形成键合。中介层108键合至裸片102(例如，有源侧S1上的)的在其上布置有电介质材料104和一个或多个键合焊盘106的表面，如箭头所示。
图3示意性地示出在将裸片102和中介层108附接至衬底(例如图1的衬底160)的一层后的封装体组件300。在一些实施方式中，衬底的该层为第一叠层116。第一叠层116可以与已针对图1描述的实施方式一致。
可以使用胶黏剂114将裸片102附接至第一叠层116，以将裸片102的非有源侧S2耦合至第一叠层116。胶黏剂114可以与已针对图1描述的实施方式一致。在其他实施方式中可以使用其他技术(例如，载体组)将裸片102附接至衬底的该层。
图4至图8示意性地示出在形成衬底的用以将裸片嵌入衬底的一个或多个附加层后的封装体组件。图4的封装体组件400代表在形成衬底(例如图1的衬底160)的芯材料118之后图3的封装体组件300。芯材料118可以与已联系图1描述的实施方式一致。
如图所示，可以沉积芯材料118，以封装裸片102和中介层108。例如，芯材料118可以通过将热固性树脂沉积在模具中来形成。
根据一些实施方式，中介层108被布置用以保护裸片102的电介质材料104免受与芯材料118的沉积相关联的应力的损害。裸片102上的中介层108形成如针对图1所述的受保护的IC结构150。
在一些实施方式中，在沉积芯材料118之前在第一叠层116上形成路由结构128。可以在将裸片102附接至第一叠层116之前将路由结构128形成在第一叠层116上。路由结构128可以与已针对图1描述的实施方式一致。
如图所示，图5的封装体组件500代表在对芯材料118构图并形成附加路由结构128和路由结构130之后图4的封装体组件400。路由结构130可以与已针对图1描述的实施方式一致。
可以使用任何合适的工艺(例如光刻/蚀刻或激光打孔)对芯材料118进行构图，以去除芯材料118的一些部分。去除芯材料118的一些部分以允许导电材料的沉积，从而形成路由结构128、130。例如，可以对芯材料118进行构图以促进通过芯材料118与中介层108的一个或多个通孔110的电连接的形成。如图所示，例如可以通过沉积导电材料以形成通过再分布层112与一个或多个通孔110电耦合的路由结构128、130，来形成电连接。
封装体组件600代表在芯材料118上形成第二叠层120之后的封装体组件500。第二叠层120可以与已针对图1描述的实施方式一致。
可以通过在芯材料118上沉积叠合材料并对叠合材料进行构图以促进通过叠合材料与中介层108的一个或多个通孔110的电连接的形成，来形成第二叠层120。例如，可以将导电材料沉积在第二叠层120的已进行构图的区域中，如图所示，在该区域中已去除叠合材料来形成附加的路由结构130。路由结构130提供通过第二叠层120与一个或多个通孔110的电连接。
封装体组件700代表在第二叠层120上形成阻焊层(例如图1的第二阻焊层122)之后的封装体组件600。第二阻焊层122可以与针对图1所述的实施方式一致。
可以通过在第二叠层120上沉积和/或构图导电材料来形成路由结构132。路由结构132可以与针对图1所述的实施方式一致。可以沉积和/或构图阻焊材料来形成第二阻焊层122。阻焊材料可以如此形成，使得路由结构132的一些路由结构被暴露用于进一步的电连接。
封装体组件800代表在第一叠层116中形成路由结构126之后并且在第一叠层116上形成阻焊层(例如图1的第一阻焊层124)之后的封装体组件700。第一阻焊层124、一个或多个键合焊盘136、一个或多个焊球138以及路由结构126、134可以与针对图1所述的实施方式一致。
在一些实施方式中，第一叠层116被构图用以促进通过第一叠层116与中介层108的一个或多个通孔110的电连接的形成。可以将导电材料沉积到第一叠层的已进行构图的部分中，以形成提供与一个或多个通孔110的电连接的路由结构126。
路由结构134形成在第一叠层116上并且电耦合至路由结构126，以路由裸片102的电信号。一个或多个键合焊盘136形成在路由结构126上。沉积和/或构图阻焊材料以形成阻焊层124。在阻焊材料中可以形成开口，以允许焊球138在一个或多个键合焊盘134上的形成/放置。
图9是用于制造本文所述封装体组件(例如图1的封装体组件100)的方法900的工艺流程图。方法900可以与针对图1至图8描述的实施方式一致。
在902处，方法900包括制造裸片(例如图1的裸片102)。该裸片可以使用公知的半导体制造技术来制造。将裸片的有源侧(例如，图1的有源侧S1)上的表面制造成包含电介质材料(例如，图1的电介质材料104)和键合焊盘(例如，图1的一个或多个键合焊盘106)或者类似结构，以路由裸片的电信号。
在904处，方法900还包括制造中介层(例如，图1的中介层108)。该中介层可以使用公知的半导体制造技术来制造。将中介层制造成包含形成于其中的通孔(例如，图1的一个或多个通孔110)。
在906处，方法900还包括将中介层键合至裸片。可以例如使用热压缩工艺或者焊接回流工艺来将中介层键合至裸片。在一些实施方式中，键合工艺形成将中介层的通孔和裸片的键合焊盘进行电耦合的键合。可以例如使用凸块、导柱、焊盘等将中介层耦合至裸片，以在中介层与裸片之间形成导电键合。
在908处，方法900还包括提供这样的裸片，其具有键合至该裸片的有源侧的表面的中介层。在一些实施方式中，裸片的表面包含电介质材料和键合焊盘，以路由裸片的电信号。中介层具有与键合焊盘电耦合的通孔，以进一步路由裸片的电信号。
在910处，方法900还包括将裸片附接至衬底(例如，图1的衬底160)的一层(例如，图1的第一叠层116)。例如，可以使用胶黏剂或载体组将裸片附接至衬底的该层。
在912处，方法900还包括形成衬底的一个或多个附加层以在衬底中嵌入半导体裸片。中介层被布置用以保护裸片的电介质材料免受与形成一个或多个附加层相关联的应力的损害。
形成衬底的一个或多个附加层包括形成衬底的芯(例如，图1的芯材料118)。可以通过沉积芯材料(比如树脂)以封装裸片和中介层，从而形成所述芯。(例如通过构图)芯材料的某些部分被去除，或者除此之外在芯材料中提供开口以促进通过芯材料与中介层的通孔的电连接的形成。例如，可以在芯材料的构图部分中沉积导电材料以提供电连接(例如，图1的路由结构128)。
形成衬底的一个或多个附加层还可以包括在芯材料上形成一层。在一些实施方式中，通过在芯材料上沉积叠合材料来形成叠层(例如，图1的第二叠层120)。可以(例如通过构图)去除叠合材料的某些部分，或者除此之外可以在叠层中提供开口以促进通过叠合材料与中介层的通孔的电连接的形成。例如，可以在叠合材料的构图部分沉积导电材料以提供电连接(例如，图1的路由结构130)。
形成一个或多个附加层还可以包括在沉积于芯材料上的叠合材料上形成阻焊层(例如图1的第二阻焊层122)。可以通过沉积和/或构图导电材料以形成路由结构(例如，图1的路由结构132)、并且通过沉积和/或构图阻焊材料以允许与该路由结构的进一步电连接，来形成阻焊层。例如，可将无源器件(例如，图1的无源器件175)电耦合至路由结构。
形成一个或多个附加层还可以包括：(例如通过构图)去除衬底的层(例如，图1的第一叠层116)的叠合材料的某些部分，或者除此之外在叠合材料中提供开口以促进通过衬底的所述层与中介层的通孔的电连接的形成。可向去除的部分或开口中沉积导电材料，以形成电连接(例如，图1的路由结构126)。
形成一个或多个附加层还可以包括在衬底的层上形成阻焊层(例如，图1的第一阻焊层124)。可以通过沉积和/或构图导电材料以形成路由结构(例如，图1的路由结构134)、并且通过沉积和/或构图阻焊材料以允许进一步的电连接，来形成阻焊层。在该路由结构上可以形成一个或多个键合焊盘(例如，一个或多个键合焊盘136)。
在914处，方法900还包括在衬底上形成一个或多个封装体互连结构。该一个或多个封装体互连结构例如可以包括焊球(例如，焊球118)或者任何其他进一步路由用于封装体组件(例如，图1的封装体组件100)的裸片的电信号的其他类似结构。在一个实施方式中，焊球附接至阻焊层的一个或多个键合焊盘，以进一步路由裸片的电信号。
虽然在本文中示例说明了某些实施方式，但在不偏离本公开的范围的前提下，为了实现相同用途而计算出的多种替代和/或等效实施方式或实现方式可以替代所示和所述的实施方式。本公开旨在涵盖本文所讨论的实施方式的任何修改和改动。因此，本文所述实施方式显然仅应由权利要求及其等同体所限定。

Claims (20)

1.一种方法，其包括：
提供一个裸片，所述裸片具有键合至所述裸片的有源侧的表面的中介层，所述表面包括(i)电介质材料和(ii)用以路由所述裸片的电信号的键合焊盘，所述中介层具有形成于其中的通孔，所述通孔电耦合至所述键合焊盘以进一步路由所述裸片的所述电信号；
将所述裸片附接至衬底的一层；以及
形成所述衬底的一个或多个附加层，以将所述裸片嵌入在所述衬底中。
2.根据权利要求1所述的方法，其中提供一个裸片，所述裸片具有键合至裸片的有源侧的表面的中介层包括：
制造所述裸片；
制造所述中介层；以及
将所述中介层键合至所述裸片的所述有源侧的所述表面。
3.根据权利要求2所述的方法，其中：
使用热压缩工艺或者焊接回流工艺将所述中介层键合至所述裸片；
所述裸片包括硅并且所述中介层包括硅；
所述中介层的通孔包括硅贯通孔(TSV)；以及
所述裸片的所述电介质材料为低k电介质材料。
4.根据权利要求1所述的方法，其中：
通过使用胶黏剂将所述裸片附接至所述衬底的所述层，来将所述裸片的非有源侧耦合至所述衬底的所述层；
所述衬底的所述层包括叠合材料；以及
所述裸片的所述非有源侧与所述裸片的所述有源侧相对布置。
5.根据权利要求1所述的方法，其中形成所述一个或多个附加层包括：
沉积包括树脂的芯材料，以封装所述裸片和所述中介层；以及
对所述芯材料进行构图，以促进通过所述芯材料与所述中介层的所述通孔的电连接的形成。
6.根据权利要求5所述的方法，其中形成所述一个或多个附加层还包括：
在所述芯材料上沉积叠合材料；以及
对所述叠合材料进行构图，以促进通过所述叠合材料与所述中介层的所述通孔的电连接的形成。
7.根据权利要求6所述的方法，其中形成所述一个或多个附加层还包括：
在沉积于所述芯材料上的所述叠合材料上形成阻焊层。
8.根据权利要求7所述的方法，其中形成所述一个或多个附加层还包括：
构图所述衬底的所述层，以促进通过所述衬底的所述层与所述中介层的所述通孔的电连接的形成。
9.根据权利要求8所述的方法，其中形成所述一个或多个附加层还包括：
在所述衬底的所述层上形成阻焊层。
10.根据权利要求9所述的方法，其还包括：
向所述阻焊层附接焊球。
11.一种装置，其包括：
衬底，其具有(i)第一叠层、(ii)第二叠层以及(iii)布置于所述第一叠层与所述第二叠层之间的芯材料；以及
附接至所述第一叠层的裸片，所述裸片具有键合至所述裸片的有源侧的表面的中介层，所述表面包括(i)电介质材料和(ii)用以路由所述裸片的电信号的键合焊盘，所述中介层具有形成于其中的通孔，所述通孔电耦合至所述键合焊盘以进一步路由所述裸片的所述电信号，其中所述裸片和所述中介层嵌入在所述衬底的芯材料中。
12.根据权利要求11所述的装置，其中：
所述裸片包括硅并且所述中介层包括硅；
所述中介层的所述通孔包括硅贯通孔(TSV)；
所述裸片的所述电介质材料为低k电介质材料；
所述裸片的所述键合焊盘包括铝或者铜；
所述衬底的所述芯材料包括树脂；以及
使用金属-金属键合或者焊料键合将所述中介层键合至所述裸片。
13.根据权利要求11所述的装置，其中：
使用胶黏剂将所述裸片附接至所述第一叠层，以将所述裸片的非有源侧耦合至所述第一叠层；
所述裸片的所述非有源侧与所述裸片的所述有源侧相对布置。
14.根据权利要求11所述的装置，还包括：
一个或多个路由结构，其电耦合至所述中介层的所述通孔，用以进一步通过所述芯材料、所述第一叠层和所述第二叠层路由所述裸片的电信号。
15.根据权利要求14所述的装置，其中使用形成于所述中介层上的再分布层将所述一个或多个路由结构电耦合至所述中介层的所述通孔。
16.根据权利要求14所述的装置，其中所述一个或多个路由结构包括铜。
17.根据权利要求11所述的装置，其中所述衬底还包括：
第一阻焊层，耦合至所述第一叠层；以及
第二阻焊层，耦合至所述第二叠层。
18.根据权利要求17所述的装置，其中所述衬底还包括：
键合焊盘，i)布置于所述第一阻焊层中并且ii)电耦合至所述一个或多个通孔，以进一步路由所述裸片的所述电信号。
19.根据权利要求18所述的装置，还包括：
焊球，其耦合至布置于所述第一阻焊层中的所述键合焊盘，所述焊球进一步路由所述裸片的所述电信号。
20.根据权利要求19所述的装置，其中所述衬底包括球栅阵列(BGA)衬底。
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