TWI616990B - 一種高密度立體封裝的積體電路系統 - Google Patents

一種高密度立體封裝的積體電路系統 Download PDF

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TWI616990B
TWI616990B TW102113948A TW102113948A TWI616990B TW I616990 B TWI616990 B TW I616990B TW 102113948 A TW102113948 A TW 102113948A TW 102113948 A TW102113948 A TW 102113948A TW I616990 B TWI616990 B TW I616990B
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power
low
insert
power chips
chip
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TW201351579A (zh
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姜澤圭
翟軍
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輝達公司
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    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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Abstract

本發明之具體實施例提供一種積體電路系統，該系統包括一插入件，其具有貫穿該插入件的複數個導電貫孔；一個或多個高功率晶片，其固定於該插入件之第一表面上，其中該等一個或多個高功率晶片在正常操作期間產生至少10W熱量；一個或多個低功率晶片，其固定於該插入件之第二表面上，其中該等一個或多個低功率晶片在正常操作期間產生低於5W熱量，且該等第一和第二表面係彼此相對並大體上平行；以及一包覆材料，其形成於上方並配置成包覆該等一個或多個高功率晶片和該等一個或多個低功率晶片。由於低功率晶片和高功率晶片係各別固定於該插入件之前側面和後側面上，因此減少該插入件之覆蓋區和與其相關聯的製造成本。

Description

一種高密度立體封裝的積體電路系統
本發明之具體實施例一般係關於積體電路晶片封裝，更具體而言係關於封裝著高功率晶片和低功率晶片的立體系統。
最先進電子設備的尺寸不斷降低。為了縮小電子設備的尺寸，該等微處理器、記憶體裝置和其他半導體元件藉以與電路板一起封裝和組合的該等結構必須變得更加緊密。
在積體電路晶片之封裝中，已開發眾多組合技術以縮小該等積體電路和電路板之組合件之整體尺寸。覆晶接合(flip-chip bonding)技術，舉例來說，係用於提供經改良之積體密度給該積體電路封裝系統的該等組合方法之一。第一圖例示慣用的覆晶封裝結構100之示意剖面圖。該覆晶結構100通常包括半導體元件102，諸如以其後表面固定於插入件104之頂端表面上的高功率晶片102a和低功率晶片102b。該插入件104係以焊料凸塊108直接結合於封裝基板106之頂端表面。該封裝基板106隨後係以焊料球112固定於印刷電路板(printed circuit board，PCB)110上，讓該等半導體元件102與該PCB 110之間能夠電連接。覆晶封裝結構提供以與使用傳統線接合技術的積體電路封裝系統相較經縮小之封裝尺寸和較短的互連線距離將半導體元件互連線至外部電路之優勢，其中半導體元件(諸如高/低功率晶片)係以承載於該封裝基板上相對較厚的金屬線和對應的接合墊線接合至封裝基板。
在第一圖中所顯示的該封裝結構之該設置之一個缺點，係為了達成積體電路之較高的封裝密度，高功率晶片102a和低功率晶片102b係固定於該插入件之相同側上。因此，需求該插入件之大得多的覆蓋區(footprint)。又，製造插入件(尤其通矽貫孔(through-silicon via，TSV)型插入 件)之製程係複雜且非常昂貴，因為其藉由貫穿該插入件的導電貫孔(例如導電貫孔116b)在半導體元件與下面的PCB之間提供垂直電互連線，以及藉由導電連接(例如導電連接116a)在並排水平設置的半導體元件之間提供面內電互連線。現行多晶片封裝不僅增加該插入件之覆蓋區並因此施加較重的佈線負荷於該封裝基板上，而且增加與插入件製造相關聯的成本，其起因於該插入件之高複雜度和諸如凸塊間距限制的製造挑戰，尤其當試圖將不同的積體電路垂直結合於單一封裝中時。
因此，本領域亟需符合成本效益的封裝系統，其具有較大密度之在封裝尺寸和互連線距離上對應縮小的積體電路。
本發明之一個具體實施例提供積體電路系統，該系統一般包括一插入件，其具有貫穿該插入件的複數個導電貫孔；一個或多個高功率晶片，其固定於該插入件之第一表面上，其中該等一個或多個高功率晶片在正常操作期間產生至少10W熱量；一個或多個低功率晶片，其固定於該插入件之第二表面上，其中該等一個或多個低功率晶片在正常操作期間產生低於5W熱量，且該第一表面和該第二表面係彼此相對並大體上平行；以及一包覆材料，其形成於上方並配置成包覆該等一個或多個高功率晶片和該等一個或多個低功率晶片。
本發明之一個優勢係低功率晶片和高功率晶片係各別固定於該插入件之前側面和後側面上，相對於高功率和低功率晶片係放置於該插入件之相同側上的現行多晶片封裝。因此，減少該插入件之覆蓋區和與其相關聯的製造成本。此外，由於該插入件將低功率晶片熱絕緣於高功率晶片，故低功率晶片可以緊鄰高功率晶片放置而不會受到高功率晶片所產生熱量的不利影響。這樣的靠近緊鄰和直接貫穿該插入件之本體的導電貫孔具優勢地縮短在該等高功率與低功率晶片之間的互連線之路徑長度，其在該積體電路(IC)系統中改良元件性能並縮小互連線寄生現象(parasitics)。
100‧‧‧覆晶封裝結構；覆晶結構
102‧‧‧半導體元件
102a‧‧‧高功率晶片
102b‧‧‧低功率晶片
104‧‧‧插入件
106‧‧‧封裝基板
108‧‧‧焊料凸塊
110‧‧‧印刷電路板(PCB)
112‧‧‧焊料球
116a‧‧‧導電連接
116b‧‧‧導電貫孔
200‧‧‧積體電路(IC)系統
201‧‧‧高功率晶片
202‧‧‧低功率晶片
203a‧‧‧側面
203b‧‧‧相對側面
204‧‧‧插入件
205‧‧‧通矽貫孔(TSVs)
206a‧‧‧插入件204之第一表面
206b‧‧‧插入件204之第二表面
207‧‧‧電連接
208、226‧‧‧焊料凸塊
210、220、224‧‧‧包覆材料
212‧‧‧散熱座
214‧‧‧封裝基板
215‧‧‧晶片黏著材料
216a‧‧‧低功率晶片202之前表面
216b‧‧‧低功率晶片202之後表 面
218‧‧‧微凸塊
221、242‧‧‧導電線
222‧‧‧封裝引線
290‧‧‧印刷電路板(PCB)
300‧‧‧積體電路(IC)系統
301‧‧‧高功率晶片
302‧‧‧低功率晶片
303‧‧‧輸入/輸出(I/O)端點
304‧‧‧插入件
305‧‧‧通矽貫孔(TSVs)
306、308‧‧‧焊料凸塊
310‧‧‧插入件304之第一表面
312‧‧‧插入件304之第二表面
314‧‧‧邊緣
400‧‧‧積體電路(IC)系統
401a、401b‧‧‧高功率晶片
402、402a-402h(402a-h)‧‧‧低功率晶片
404‧‧‧插入件
405‧‧‧通矽貫孔(TSVs)
406、408‧‧‧焊料凸塊
410‧‧‧插入件404之第一表面
412‧‧‧插入件404之第二表面
414‧‧‧邊緣
500‧‧‧製程序列
502-518‧‧‧步驟
600‧‧‧積體電路(IC)系統
601‧‧‧高功率晶片
602‧‧‧低功率晶片
603‧‧‧通矽貫孔(TSV)尖端
604‧‧‧插入件；插入件基板
605‧‧‧通矽貫孔(TSVs)
606a‧‧‧插入件604之表面
607‧‧‧C4凸塊682之較高部分
614‧‧‧封裝基板
618‧‧‧凸塊接點；焊料凸塊
620、686、696‧‧‧包覆材料
622‧‧‧封裝引線
624‧‧‧第一載體基板
625‧‧‧黏著劑
626‧‧‧插入件604之後側面
680‧‧‧微凸塊
682‧‧‧C4凸塊
684‧‧‧導電墊
688‧‧‧凸塊接點
690‧‧‧印刷電路板(PCB)
691‧‧‧半成品元件693之後側面
692‧‧‧第二載體基板
693‧‧‧半成品元件
694‧‧‧半成品元件693之前側面
700‧‧‧積體電路(IC)系統
701‧‧‧高功率晶片
702‧‧‧低功率晶片
704‧‧‧插入件
705‧‧‧通矽貫孔(TSVs)
708‧‧‧電連接
713‧‧‧封裝基板714之頂端表 面
714‧‧‧封裝基板
718‧‧‧電連接
719‧‧‧低功率晶片702之主動表面
720‧‧‧包覆材料
730‧‧‧凹穴；凹陷開孔
732‧‧‧成型材料
734‧‧‧間隙
L‧‧‧連續長度
M、N‧‧‧觀看軸
A-A、B-B‧‧‧線
P1‧‧‧間距
T、D1、D3‧‧‧厚度
D2‧‧‧長度
藉由參照其中某些係例示於所附圖式中的具體實施例，可具有可以詳細理解本發明之該等上述所陳述特徵的該方式，以及上述簡要總 結的本發明之更特定的說明。然而，應注意所附圖式僅例示本發明之一般具體實施例並係因此不被視為其範疇之限制，因為本發明可承認其他同樣有效的具體實施例。此外，在所附圖式中的該例示圖並非成比例繪製並係為了例示用途而提供。
第一圖係慣用的覆晶封裝結構之示意剖面圖。
根據本發明之一個具體實施例，第二A圖係積體電路(IC)系統之示意剖面圖。
第二B圖係顯示在插入件與低功率晶片之間的電連接的經放大之局部剖面圖。
根據本發明之一個具體實施例，第三A圖係顯示涉及高功率和低功率晶片的插入件之示例性位置關係的積體電路(IC)系統之示意俯視圖。
第三B圖係順著第三A圖之線A-A所採取的剖面圖。
根據本發明之另一具體實施例，第四A圖係顯示涉及高功率和低功率晶片的插入件之示例性位置關係的積體電路(IC)系統之示意俯視圖。
第四B圖係順著第四A圖之線B-B所採取的剖面圖。
根據本發明之一個具體實施例，第五圖例示用於形成積體電路(IC)系統的示例性製程序列。
第六A-六F圖例示在第五圖中所顯示的該製程序列之不同階段的插入件之示意剖面圖。
根據本發明之又另一具體實施例，第七圖係積體電路(IC)系統之示意剖面圖。
為了促進理解，在可能的情況下已使用相同參考數字來代表對於該等圖示係共用的相同元件。列入考慮在一個具體實施例中所揭示的元件可有益利用於其他具體實施例上而沒有具體陳述。
本發明提供一種系統，其中一個或多個低功率晶片係固定於插入件之一側上，而一個或多個高功率晶片係固定於該插入件之該另一側 上。該插入件具有貫穿其間以電連接該等低和高功率晶片的複數個導電貫孔。在各種具體實施例中，低功率晶片和高功率晶片係包覆以防止在該等晶片與該插入件之間起因於組件之間不同的熱膨脹係數的相對移動。低功率晶片可以並排配置放置使得低功率晶片之每個皆偏離每個高功率晶片之中心，允許從電源更快的直接饋送功率至高功率晶片而未經歷與該等低功率晶片相關聯的電阻損耗。在一個具體實施例中，該系統可配置成具有放置於在封裝基板之表面中所形成的凹穴內的一個或多個低功率晶片，以進一步縮小整體封裝輪廓。本發明之細節係在下方更詳細地討論。
根據本發明之一個具體實施例，第二A圖係積體電路(integrated circuit，IC)系統200之示意剖面圖。IC系統200包括多個半導體元件，諸如IC晶片和/或其他分離的微電子組件，且係配置成將前述晶片和組件電連接和機械連接至印刷電路板(PCB)290。如在下方更詳細地討論，在本發明之各種具體實施例中，IC系統200可包括一個或多個高功率晶片201、一插入件204和一個或多個低功率晶片202之一堆疊配置，其中該等一個或多個低功率晶片202可覆晶凸出於該插入件204之第一表面206a上，而該等一個或多個高功率晶片201可凸出於該插入件204之第二表面206b上。該插入件204之該第一表面206a和該第二表面206b係彼此相對並大體上平行。該等一個或多個低功率晶片202係由該插入件204熱絕緣於該等一個或多個高功率晶片201並因此不會被高功率晶片201大幅影響。尤其是，由於該等高功率晶片201和該等低功率晶片202係各別黏著於該插入件204之前側面和後側面，因此縮小該插入件204之覆蓋區，相對於高功率和低功率晶片係放置於該插入件之相同側上的現行多晶片封裝。
該插入件204包括複數個通矽貫孔(TSVs)205，其用於堆疊晶片。TSVs 205適於用作貫穿該插入件204的電源、接地和信號互連線以促進垂直堆疊的晶片之間的電連接，舉例來說，高功率晶片201和低功率晶片202。具體而言，TSVs 205係貫穿該插入件204以在高功率晶片201與低功率晶片202之間有效提供垂直電連接的「微貫孔(micro vias)」，而非如同在傳統的立體(3D)封裝中一般所使用在該等晶片之邊緣穿越該等側 壁。因此，TSVs 205在高功率晶片201與低功率晶片202之間提供非常短的路徑長度互連線。
高功率晶片201可能係在高電壓操作的任何半導體元件，諸如中央處理單元(central processing unit，CPU)、圖形處理單元(graphics processing unit，GPU)、應用處理器或其他邏輯元件，或者可能係在操作期間產生足夠熱量以不利影響位於IC系統200中的低功率晶片202或被動元件之性能的任何IC晶片。如於文中所定義的「高功率晶片(high-power chip)」係在正常操作期間產生至少10W熱量的任何IC晶片。高功率晶片201係固定於該插入件204之表面上，諸如該第二表面206b，且係經由電連接207電連接至該插入件204之該第二表面206b。在高功率晶片201與該插入件204之間的該等電連接207可使用本領域已習知的任何在技術上可實行的方法做到，包括但不限於將設置於該高功率晶片201之側面203a上的焊料凸塊208黏著於在該插入件204之該第二表面206b上所形成的接合墊(未顯示)。該等焊料凸塊208可由銅或另一導電材料諸如鋁、金、銀或兩種或多種元素之合金組成。另外，這樣的電連接可藉由在該高功率晶片201上將針柵陣列(pin-grid array，PGA)機械按壓至形成於該插入件204中的通孔中而做到。若有需要，焊料凸塊208之可靠度可藉由以包覆材料210保護該等焊料凸塊208而改良。該包覆材料210可能係樹脂，諸如環氧化合物樹脂、丙烯酸樹脂、聚矽氧樹脂、聚氨酯樹脂、聚醯胺樹脂、聚亞醯胺樹脂等。
該高功率晶片201之該側面203a係固定於該插入件204，而背離該插入件204的該高功率晶片201之相對側面203b可使用為黏著於其上的散熱座或其他冷卻機制。在第二A圖中所例示的該具體實施例中，該高功率晶片201之該側面203a係熱耦合於散熱座212以增強IC系統200之熱傳送。
低功率晶片202可能係在與該高功率晶片201之電壓相較相對較低的電壓操作的任何半導體元件。低功率晶片202可能係位於IC系統200中的被動元件、諸如隨機存取記憶體(RAM)、快閃記憶體等的記憶體裝置、輸入/輸出(I/O)晶片，或者在操作期間不會產生足夠熱量以不利影響緊 鄰的IC晶片或元件之性能的任何其他晶片。如於文中所定義的「低功率晶片(low-power chip)」係在正常操作期間產生等級為大約1W熱量的任何IC晶片，亦即不超過大約5W。低功率晶片202係以其後表面216b固定於該插入件204之表面，諸如該第一表面206a，且係使用能夠在該插入件204與該等低功率晶片202之間建立電接點、本領域已習知的任何在技術上可實行的方法電連接至在該插入件204之該第一表面206a上的電連接。第二B圖係顯示在該插入件204與使用微凸塊218的該等低功率晶片202之間的該等電連接之一個具體實施例的經放大之局部剖面圖。該等微凸塊218可以包覆材料220包覆以增強該等微凸塊218之可靠度。另外或此外，該等微凸塊218之可靠度可藉由包覆材料224增強，其保護並防止該等整個低功率晶片202與該插入件204和封裝基板214起因於在該高功率晶片201、該插入件204與低功率晶片202之間不同的熱膨脹係數的任何相對移動。在使用該包覆材料224的某些情況下，可省略該包覆材料220。
低功率晶片202之另一側面，亦即前表面216a，可以本領域已習知的任何在技術上可實行的方法固定於該封裝基板214，諸如焊料凸塊或導電黏著材料。在第二A圖中所顯示的一個具體實施例中，使用晶片黏著材料215。然而，只要低功率晶片202維持電連接至該封裝基板214，則可省略該晶片黏著材料215。舉例來說，低功率晶片202可經由放置於該插入件204與該封裝基板214之間對應於該高功率晶片201之位置的區域的焊料凸塊226電連接至該封裝基板214。在這樣的情況下，該等焊料凸塊226可放置於該插入件204與該封裝基板214之間在該高功率晶片201之中心底下的中間區域中。該等焊料凸塊226係提供以將該插入件204(以及因此該等低功率晶片202)固定於該封裝基板214。該等焊料凸塊226係配置成經由導電線242從電源(未顯示)提供功率和/或接地信號之直接傳送至該高功率晶片201而未經歷與該等低功率晶片202相關聯的電阻損耗。該等焊料凸塊226可使用微凸塊或諸如C4凸塊的較大凸塊以在該高功率晶片201與該封裝基板214之間提供有效的電連接。因此，該高功率晶片201、該插入件204、該低功率晶片202和該封裝基板214係以堆疊配置彼此電連接。在第二A圖中所顯示的一個態樣中，該封裝基板214可具有足以支撐並包 覆所有低功率晶片202於該包覆材料224內的連續長度「L」，以防止該封裝基板214在該包覆製程或後續的熱循環期間彎曲。
該封裝基板214係經由導電線221和封裝引線222電連接至該PCB 290。封裝引線222在IC系統200與該PCB 290之間提供電連接，且可能係本領域已習知的任何在技術上可實行的晶片封裝電連接，包括一球柵陣列(ball-grid array，BGA)、一針柵陣列(PGA)以及此類。雖然於文中未顯示，但列入考慮該封裝基板214可能係由一疊絕緣層組成的層疊基板。此外，嵌入該封裝基板214內的導電線221可包括複數個水平面向的導線或垂直面向的貫孔，其穿過該封裝基板214內以在高和低功率晶片201、202與該PCB 290之間提供電源、接地和/或輸入/輸出(I/O)信號互連線。如於文中所使用的該用語「水平面(horizontal)」係定義為平行於該積體電路之平面或表面的平面，而不論其面向為何。此外，該用語「垂直面(vertical)」指稱垂直於如於文中所定義的該水平的方向。封裝基板214因此提供IC系統200結構剛性，以及用於在高功率晶片201、低功率晶片202與印刷電路板290之間佈線輸入和輸出信號和電源的電子介面。
用於製造在本發明之具體實施例中所使用的層疊封裝基板有許多本領域已廣泛習知的適合的材料，其具備必需的機械強度、電性和所需的低熱傳導係數。這樣的材料可包括但不限於FR-2和FR-4，其係傳統的環氧化合物型層疊，以及來自三菱瓦斯化學株式會社(Mitsubishi Gas and Chemical)的樹脂型雙馬來亞醯胺-三氮雜苯(Bismaleimide-Triazine，BT)。FR-2係具有大約0.2W(瓦)/(K-m)(絕對溫度-公尺)範圍之熱傳導係數的合成樹脂接合紙(synthetic resin bonded paper)。FR-4係有具有大約0.35W/(K-m)範圍之熱傳導係數的環氧化合物樹脂接合物的編織玻璃纖維布(woven fiberglass cloth)。BT/環氧化合物層疊封裝基板亦具有大約0.35W/(K-m)範圍之熱傳導係數。具有低於大約0.5W/(K-m)之熱傳導係數的其他適合的剛性、電絕緣和熱絕緣材料亦可使用並仍然落於本發明之範疇內。
根據本發明之一個具體實施例，第三A圖係顯示涉及高功率和低功率晶片的插入件之示例性位置關係的積體電路(IC)系統300之示意俯視圖。第三B圖係順著第三A圖之線A-A所採取的剖面圖。在這些具 體實施例中，高功率晶片301係固定於插入件304之第一表面310上，而低功率晶片302(在第三A圖中由虛線指示)係固定於該插入件304之第二表面312上。該第一表面310和該第二表面312係彼此相對並大體上平行。如上述涉及第二A圖所討論該高功率晶片301、該等低功率晶片302和該插入件304可能係那些高功率和低功率晶片201、202和該插入件204。同樣地，如上述所討論該高功率晶片301和低功率晶片302係使用本領域已習知的任何在技術上可實行的方法各別固定於該插入件304之該等第一和第二表面310、312上，諸如焊料凸塊306、308。該高功率晶片301和低功率晶片302係放置使得低功率晶片302部分重疊該高功率晶片301。具體而言，低功率晶片302係以並排配置放置，且當從俯視圖或在垂直於該插入件304之該第一表面310的觀看軸「M」上觀看時，低功率晶片302之每個皆偏離該高功率晶片301之中心(「偏離中心(off-center)」設置)並重疊該高功率晶片301之邊緣314。在一個具體實施例中，低功率晶片302之每個之輸入/輸出(I/O)端點303皆可成一列對準，或者可與高功率晶片301之該邊緣314成複數個列對準。雖然僅顯示四個I/O端點303，但列入考慮I/O端點303之數量可變化以改良資料傳送該處理速度。
由於低功率晶片302之每個皆設置緊鄰該高功率晶片301並僅藉由該插入件304分開，因此在低功率晶片302與該高功率晶片301之間的互連線(亦即TSVs 305)之路徑長度非常短。此經縮短之互連線距離伴隨著低功率晶片302之該「偏離中心(off-center)」設置允許從電源(未顯示)更快的直接饋送功率和/或接地信號至該高功率晶片301而未經歷與該等低功率晶片320相關聯的電阻損耗，從而滿足高電流元件之功率需求。為了提供這樣的直接功率傳送，可以任何適合的形式的一個或多個電互連線(未顯示)可用於經由該插入件305直接從PCB提供功率和/或接地信號至該高功率晶片301。舉例來說，電互連線，諸如在第二A圖中所顯示的導電線242，可經由封裝基板至與貫穿該插入件的一個或多個TSVs電通訊的焊料凸塊226從PCB 290提供功率之直接饋送至該高功率晶片201。
根據本發明之另一具體實施例，第四A圖係顯示涉及高功率和低功率晶片的插入件之示例性位置關係的積體電路(IC)系統400之示 意俯視圖。第四B圖係順著第四A圖之線B-B所採取的剖面圖。在此具體實施例中，該IC系統400一般包括一插入件404；兩個高功率晶片401a、401b，其固定於該插入件404之第一表面410上；以及複數個低功率晶片(諸如八個低功率晶片402a-402h)，其固定於該插入件404之第二表面412上。該第一表面410和該第二表面412係彼此相對並大體上平行。同樣地，如上述涉及第二A圖所討論該等高功率晶片401a、401b、該等低功率晶片402a-h和該插入件404可能係那些高功率和低功率晶片201、202和該插入件204，且可以使用諸如TSVs 405和焊料凸塊406、408的適合方式彼此電連接和/或機械連接。該等高功率晶片401a、401b和低功率晶片402a-h係放置使得低功率晶片402a-h之每個皆部分重疊該高功率晶片401a或401b。
類似於上述所討論的該設置和優勢，低功率晶片402a-h係以並排配置放置，且當從俯視圖或在垂直於該插入件404之該第一表面410的觀看軸「N」上觀看時，低功率晶片402a-h之每個(舉例來說低功率晶片402a、402b、402c和402d)皆偏離每個高功率晶片(舉例來說高功率晶片401a)之中心並重疊該高功率晶片401a之邊緣414。在某些具體實施例中，低功率晶片402a-d和低功率晶片402e-h可配置以各別與高功率晶片401a和高功率晶片401b一起使用。若有需要，IC系統400可包括額外的低功率和高功率晶片。列入考慮在第三A-三B和四A-四B圖中所例示的該等設置可依該應用/晶片設計而定變化，且係適用於如上述涉及第二A圖所討論的該IC系統200，或者將在下方討論的IC系統600和700。
根據本發明之一個具體實施例，第五圖例示用於形成積體電路系統(諸如第二A圖之IC系統200)的示例性製程序列500。第六A-六F圖例示在第五圖中所顯示的該製程序列之不同階段的插入件604之示意剖面圖。應注意由於可添加、刪除和/或重新排序一個或多個步驟而不偏離本發明之基本範疇，因此在第五圖中所例示的步驟之數量和序列係不欲限制於文中所說明的本發明之範疇。
該製程序列500開始於提供如在第六A圖中所顯示的插入件基板604的步驟502。該插入件604可能係具有貫穿該含矽基板的通矽貫孔(TSVs)605的塊體含矽基板。在各種具體實施例中，TSVs 605可形成為 大約10μm(微米)至大約20μm之直徑並以諸如銅的導電材料充分填充。TSVs 605通常用作貫穿該插入件厚度的電源、接地和信號互連線，且可使用本領域任何現行矽製程技術製造。該插入件604可具有低於大約1200μm之厚度，舉例來說厚度大約800μm。該插入件604具有形成於該插入件604之表面606a上的凸塊接點618之陣列，諸如微凸塊或C4凸塊，且該等焊料凸塊618之每個皆連接至TSVs 605。TSVs 605之間距「P1」可大於大約50μm，然而在實際設計中，間距「P1」可依應用而定較大或較小。
在步驟504中，一個或多個低功率晶片602，諸如上述涉及第二A圖所討論的低功率晶片202，係以覆晶方式正側面朝下固定於該插入件604之該表面606a上，如在第六A圖中所顯示。該用語「正側面(face side)」代表該等低功率晶片602之該側面，其以半導體製程處理使得電路係製造於該等低功率晶片602之該正側面上。低功率晶片202係放置於該插入件604之該表面606a上，且該等凸塊接點618係加熱並迴焊以形成焊料接頭。這些焊料接頭係與TSVs 605對準並係配置成在低功率晶片602與該插入件604之間提供電連接和機械連接。在低功率晶片602係固定於凸塊接點618上之後，低功率晶片602、凸塊接點618和該插入件604之表面606a係使用底部填充製程以包覆材料620包覆。該包覆材料620在結構上將低功率晶片602耦合於該封裝基板(例如封裝基板214)並在熱循環期間防止或限制低功率晶片602和該封裝基板之差動移動。該包覆材料之高剛性亦讓該包覆材料能夠容納否則將作用於該等焊料接頭的該等熱應力。因此，該包覆材料620減少在該等凸塊接點618中的裂紋，且延長在低功率晶片602與該封裝基板之間的該等焊料接頭之生命期。該包覆材料620可能係可以固化至硬化的諸如液態環氧化合物、可變形膠體、矽橡膠或此類的任何適合的材料。此外或另外，低功率晶片602和該插入件604之表面606a之一部分可藉由包覆材料以如在第二B圖中所顯示的類似方式包覆，而非包覆該整個表面606a。
在第六B圖中所顯示的又另一具體實施例中，該插入件604之該表面606a可具備凸塊接點，包括一微凸塊680之陣列和一C4凸塊682之陣列。C4凸塊682可以在該插入件604之該表面606a上圖案化的匹配的 導電墊684定位(registered)，且隨後C4凸塊682係迴焊以形成焊料接頭。C4凸塊682可緊鄰或環繞低功率晶片602放置。同樣地，在低功率晶片602係固定於微凸塊680上之後，微凸塊680、C4凸塊682、在該等C4凸塊之間的低功率晶片602和該插入件604之表面606a係使用底部填充製程以諸如環氧化合物或聚合物材料的包覆材料686包覆。C4凸塊682之較高部分607可穿越該包覆材料686暴露，以促進將該插入件604焊接於在隨後的薄化製程中所使用的載體基板上。該包覆材料686在結構上將低功率晶片602耦合於該封裝基板(例如封裝基板214)並在熱循環期間防止或限制低功率晶片602和該隨後黏著的封裝基板之差動移動。該包覆材料686亦減少在該等C4凸塊682和/或微凸塊680上的疲勞損害，且延長在低功率晶片602與該封裝基板之間的該等焊料接頭之生命期。
在步驟506中，該插入件604，諸如在第六A圖中所顯示的該插入件604或在第六B圖中所顯示的該插入件604，係藉由黏著劑625以「正側面朝下(face-side down)」方式翻轉並黏著於第一載體基板624，或者若使用在第六B圖中所顯示的該插入件604則藉由伴隨著C4凸塊682的黏著劑。在隨後的薄化製程和在薄化之後的後製程步驟期間，該第一載體基板624提供暫時性的機械性和結構性支撐。該第一載體基板624可包括，舉例來說，玻璃、矽、剛性聚合物以及此類。該黏著劑625可能係能夠以適合啟動隨後的製程的方式固定該第一載體基板624的本領域已習知的任何暫時性的黏著劑。該黏著劑625應提供適當的機械性強度、熱安定性、耐化學性、容易脫黏(debonding)和清潔。在將該插入件604黏著於該第一載體基板624之後，在該插入件604之後側面626上執行薄化製程，亦即背離低功率晶片602的該側面，以達成該插入件604之所需厚度(暴露TSV尖端603)。可使用諸如蝕刻製程和/或平坦化製程的本領域任何適合的技術執行該薄化製程。在一個具體實施例中，該插入件604在薄化之後可具有大約50μm至大約100μm之厚度「T」。第六C圖例示在嵌入該插入件604(來自第六B圖)之該後側面之後黏著於該第一載體基板624的該插入件604之所產生的狀態。
在步驟508中，在薄化該插入件604之後，一個或多個高功 率晶片601係固定於該插入件604之該後側面626上，如在第六D圖中所顯示。高功率晶片601可包括用於特定應用的任何適合的電路。舉例來說，高功率晶片601可能係上述涉及第二A圖所討論的那些高功率晶片201任一者。在第六D圖中所顯示的該具體實施例中，顯示一個高功率晶片601。高功率晶片601係以覆晶配置電耦合至該插入件604，使得在該等高功率晶片601上的接點墊(未顯示)面向該插入件604之該後側面626。該等高功率晶片601之該等接點墊係透過在該等高功率晶片601上所形成並與TSVs605對準的凸塊接點688電連接至該插入件604。凸塊接點688可能係諸如C4凸塊的任何適合的導電構件。
在步驟510中，高功率晶片601、凸塊接點688和經薄化之插入件604之後側面626之部分係使用底部填充製程以包覆材料690包覆，如在第六D圖中所顯示。該包覆材料690之高剛性讓該包覆材料能夠容納否則將作用於該等凸塊接點688的該等熱應力，且因此減少在該等凸塊接點688中的裂紋並延長在高功率晶片601與該插入件604之間的該等焊料接頭之生命期。該包覆材料690可能係可以固化至硬化的諸如液體環氧化合物、可變形膠體、矽橡膠或此類的任何適合的材料。此外或另外，高功率晶片601、凸塊接點688和該經薄化之插入件604之後側面626之一部分可藉由包覆材料以如在第二B圖中所顯示的類似方式包覆，而非包覆該整個後側面626。
在步驟512中，在高功率晶片601已固定於該插入件604上並被包覆之後，承載高功率晶片601和低功率晶片602(亦即該半成品元件693)的該插入件604係使用如上述所討論本領域已習知的任何暫時性的黏著劑以其前側面694黏著於第二載體基板692，如在第六E圖中所顯示。該半成品元件693之該前側面係包覆該高功率晶片601的該側面。該第二載體基板692可使用如同該第一載體基板624的相同材料以提供適當的機械性強度和熱安定性，促成該半成品元件693之隨後的製程，諸如該半成品元件693之抬起、轉移和黏著於封裝基板。
在步驟514中，在該第二載體基板692已黏著於該插入件604之後，該第一載體基板624係藉由脫黏在該第一載體基板624與該半成 品元件693之間的該暫時性的黏著劑，而從該半成品元件693之後側面691拆離(detached)。脫黏可包括本領域已習知的任何化學性或熱性脫黏技術。第六E圖顯示已移除該第一載體基板的狀態。
在步驟516中，在脫黏該第一載體基板624之後，該半成品元件693係藉由該第二載體基板692之支撐而抬起並轉移，以經由C4凸塊682以其後側面691黏著於封裝基板614。C4凸塊682係重新加熱或迴焊以在金屬蛤殼法(metallurgically)和電性上將該半成品元件693接合於該封裝基板614。該封裝基板214係因此經由該等電連接與高功率晶片601和低功率晶片602電通訊，諸如凸塊接點688、TSVs 605、微凸塊680和C4凸塊682。該封裝基板614可能係上述涉及第二A圖所討論的該封裝基板214。其後，該第二載體基板692係從該半成品元件693之該前側面694拆離，如在第六F圖中所顯示。
在步驟518中，該封裝基板614係經由封裝引線622黏著於PCB 690，如在第六F圖中所顯示。封裝引線622可能係本領域已習知的任何在技術上可實行的晶片封裝電連接，諸如焊料凸塊或球柵陣列(BGA)，以讓高功率和低功率晶片601、602與該PCB 690之間能夠電通訊。因此，提供經封裝之IC系統600。散熱座(未顯示)，諸如在第二A圖中所顯示的該散熱座212，可放置在上方並由該經封裝之IC系統支撐以增強IC系統之熱傳送。列入考慮該散熱座可能係任何所需形狀，且係由能夠傳導和散逸從該IC系統產生的熱量的任何材料製成。
根據本發明之另一具體實施例，第七圖例示積體電路(IC)系統700之示意剖面圖。IC系統700在配置和操作上大體上類似於IC系統200或IC系統600，除了該IC系統700之該封裝基板714具備用於容納低功率晶片702的凹穴或凹陷開孔730。該凹陷開孔730可以藉由本領域已習知的任何適合的製程形成於該封裝基板714之頂端表面中，諸如濕式或乾式蝕刻製程。低功率晶片702之該主動表面719，亦即，具有複數個電極墊(未顯示)的該表面，可與該封裝基板714之該頂端表面713齊平或略高。有低功率晶片702嵌入其中的該封裝基板714降低該封裝基板714之整體高度，提供較薄的封裝輪廓。低功率晶片702之該主動表面719電連接至電 連接718，諸如焊料凸塊，其輪流電連接至有貫穿插入件704和諸如焊料凸塊的電連接708的TSVs 705的高功率晶片701。該封裝基板714之該凹陷開孔730可以成型材料732填充以包覆低功率晶片702。類似於在第二A圖或第六F圖中所顯示的該具體實施例，高功率晶片701可使用底部填充製程以包覆材料720包覆。此外，在電連接718之間的該等間隙734可以包覆材料724填充或包覆，以防止低功率晶片702與該插入件704起因於在該高功率晶片701、該插入件704與低功率晶片702之間不同的熱膨脹係數的任何相對移動。在各種具體實施例中，該凹陷開孔730可具有大約20mm(毫米)至大約550mm之厚度「D1」和大約20mm至大約850mm之長度「D2」，且該封裝基板714可具有大約20mm至大約850mm之厚度「D3」。列入考慮該尺寸可依該等晶片之尺寸而變化。
總結來說，本發明之具體實施例超越先前技術設備提供各種優勢，諸如起因於嵌入該封裝基板內的低功率晶片的較薄的封裝輪廓。由於高功率和低功率晶片之堆疊配置，本發明讓該插入件之整體覆蓋區能夠減少，如在圖示中所顯示，相對於高功率晶片和低功率晶片係並排放置於該插入件之相同側面上的現行IC封裝。低功率晶片可以「偏離中心(off-center)」配置設置以允許從電源更快的直接饋送功率和/或接地信號至高功率晶片，而未經歷與該等低功率晶片相關聯的電阻損耗。在高功率和低功率晶片之間的互連線之較短的佈線在該IC系統中導致較快的信號傳遞並減少雜訊、串音和其他寄生現象。由於熱量係藉由黏著於高功率晶片的散熱座轉移和散逸，因此本發明亦最小化從高功率晶片至低功率晶片的熱轉移。再者，設置於高功率晶片與低功率晶片之間的該插入件用作熱絕緣層以允許低功率晶片緊鄰高功率晶片放置而不會受到高功率晶片所產生熱量的不利影響。
雖然前述係關於本發明之具體實施例，但可設計本發明之其他和進一步的具體實施例而不悖離其基本範疇。該等不同的具體實施例之範疇係由以下諸申請專利範圍判定。
200‧‧‧積體電路系統
201‧‧‧高功率晶片
202‧‧‧低功率晶片
204‧‧‧插入件
205‧‧‧通矽貫孔
207‧‧‧電連接
208、226‧‧‧焊料凸塊
210、220、224‧‧‧包覆材料
212‧‧‧散熱座
214‧‧‧封裝基板
215‧‧‧晶片黏著材料
218‧‧‧微凸塊
221、242‧‧‧導電線
222‧‧‧封裝引線
290‧‧‧印刷電路板

Claims (9)

  1. 一種積體電路系統包含：一插入件，其包含貫穿該插入件的複數個導電貫孔；一個或多個高功率晶片，其固定於該插入件之一第一表面上，其中該等一個或多個高功率晶片在正常操作期間產生至少10W熱量；一個或多個低功率晶片，其固定於該插入件之一第二表面上，其中該等一個或多個低功率晶片在正常操作期間產生低於5W熱量，該等一個或多個低功率晶片之每個皆包括輸入/輸出端點，其與該等一個或多個高功率晶片之一邊緣成一列對準，且該第一表面和該第二表面係彼此相對並大體上平行；以及一包覆材料，其形成於上方並配置成包覆該等一個或多個高功率晶片和該等一個或多個低功率晶片。
  2. 如申請專利範圍第1項之系統，其中該等一個或多個低功率晶片係由該等複數個導電貫孔電連接至該等一個或多個高功率晶片。
  3. 如申請專利範圍第1項之系統，其中該等一個或多個低功率晶片係以一並排配置放置。
  4. 如申請專利範圍第3項之系統，其中該等一個或多個低功率晶片之每個皆偏離該等一個或多個高功率晶片之每個之一中心。
  5. 如申請專利範圍第4項之系統，其中該等一個或多個低功率晶片之每個皆重疊該等一個或多個高功率晶片之一邊緣。
  6. 如申請專利範圍第1項之系統，更包含一封裝基板，其電連接和機械連接至該等一個或多個低功率晶片，該封裝基板具有足以支撐所有低功率晶片的一連續長度。
  7. 如申請專利範圍第6項之系統，其中該包覆材料包覆位於該封裝基板與該插入件之間的所有低功率晶片。
  8. 如申請專利範圍第1項之系統，更包含一封裝基板，其電連接和機械連接至該等一個或多個低功率晶片，其中該封裝基板具有形成於該封裝基板之一頂端表面上用於容納該等一個或多個低功率晶片之該厚度的一凹陷開孔。
  9. 如申請專利範圍第8項之系統，其中該等一個或多個低功率晶片係以一包覆材料包覆於該凹陷開孔內。
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TW201351579A (zh) 2013-12-16
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