CN103168358A - 嵌入式结构及其制造方法 - Google Patents

嵌入式结构及其制造方法 Download PDF

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Publication number
CN103168358A
CN103168358A CN201180044155XA CN201180044155A CN103168358A CN 103168358 A CN103168358 A CN 103168358A CN 201180044155X A CN201180044155X A CN 201180044155XA CN 201180044155 A CN201180044155 A CN 201180044155A CN 103168358 A CN103168358 A CN 103168358A
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China
Prior art keywords
nude film
coupled
lamination
nude
substrate
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CN201180044155XA
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CN103168358B (zh
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S·苏塔德雅
A·吴
S·吴
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Kaiwei International Co
Marvell International Ltd
Marvell Asia Pte Ltd
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Mawier International Trade Co Ltd
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Abstract

本公开的实施例提供一种方法，该方法包括：提供第一裸片，该第一裸片具有包括键合焊盘的表面，以路由第一裸片的电信号；以及将第一裸片附接到衬底的层。该方法还包括：形成衬底的一个或多个附加层，以将第一裸片嵌入在衬底中；以及将第二裸片耦合到该一个或多个附加层，第二裸片具有包括键合焊盘的表面，以路由第二裸片的电信号。将第二裸片耦合到该一个或多个附加层，使得在第一裸片和第二裸片之间路由电信号。

Description

嵌入式结构及其制造方法
相关申请的交叉引用
本公开要求于2010年7月20日递交的第61/366,136号美国临时专利申请和于2010年7月28日递交的第61/368,555号美国临时专利申请的优先权，其整个说明书通过引用的方式全部并入于此用于所有目的，如果存在与本说明书不一致的那些部分则除了那些部分之外全部并入。本申请有关于2011年3月16日递交的第13/049,550号美国专利申请，其整个说明书通过引用的方式全部并入于此用于所有目的，如果存在与本说明书不一致的那些部分则除了那些部分之外全部并入。
技术领域
本公开的实施例涉及集成电路领域，并且更具体地涉及嵌入在衬底内的结构的技术、结构和配置，以及并入这种嵌入在衬底内的结构的封装布置。
背景技术
在此提供的背景描述用于一般性地呈现本公开上下文的目的。就在此背景技术部分中所描述的程度上的当前提名的发明人的工作以及在提交时不作为现有技术的描述方面，既不被明确地也不被暗含地承认为本公开的现有技术。
通常，在许多多芯片封装布置中，封装布置按照层叠封装(POP)布置或多芯片模块(MCM)布置中的任意一个来布置。这两种封装布置一般相当厚，具有达2.6毫米的高度。此外，在MCM布置中，布置内的芯片之一通常为配置有一个或多个系统级芯片(SoC)的集成电路，而另一个芯片通常为某种类型的存储器器件。来自SoC内的处理器的热量一般不利地影响存储器器件的性能。
发明内容
在各种实施例中，本公开提供一种方法，包括：提供第一裸片，该第一裸片具有包括键合焊盘的表面，以路由第一裸片的电信号；以及将第一裸片附接到衬底的层。该方法还包括：形成衬底的一个或多个附加层，以将第一裸片嵌入在衬底中；以及将第二裸片耦合到该一个或多个附加层，第二裸片具有包括键合焊盘的表面，以路由第二裸片的电信号。将第二裸片耦合到该一个或多个附加层，使得在第一裸片和第二裸片之间路由电信号。
本公开还提供一种装置，该装置包括：衬底，该衬底具有(i)第一叠层、(ii)第二叠层和(iii)置于第一叠层与第二叠层之间的芯材料。该装置还包括：第一裸片，该第一裸片耦合到第一叠层，第一裸片包括含键合焊盘的表面，以路由第一裸片的电信号，其中第一裸片嵌入在衬底的芯材料中。该装置还包括：第二裸片，该第二裸片耦合到第二叠层，第二裸片具有包括键合焊盘的表面，以路由第二裸片的电信号。第二裸片耦合到第二叠层，使得在第一裸片和第二裸片之间路由电信号。
附图说明
通过以下结合附图的详细描述将容易理解本公开的实施例。为了便于该描述，相同的参考表号标示相同的结构元件。在附图的各图中通过示例的方式而不是通过限制的方式示出在此的实施例。
图1A-图1D示意性地示出了示例性封装布置，该封装布置包括示例性裸片布置，该裸片布置包括嵌入在衬底中的裸片。
图2A-图2D示意性地示出了另一示例性封装布置，该封装布置包括另一示例性裸片布置，该裸片布置包括嵌入在衬底中的两个裸片。
图3A示意性地示出了另一示例性封装布置，该封装布置包括另一示例性裸片布置，该裸片布置包括嵌入在衬底中的两个裸片。
图3B示意性地示出了另一示例性封装布置，该封装布置包括另一示例性裸片布置，该裸片布置包括嵌入在衬底中的四个裸片。
图4示意性地示出了示例性裸片布置，该裸片布置包括嵌入在衬底中的裸片。
图5示意性地示出了在耦合在一起之前的裸片和中介层(interposer)。
图6示意性地示出了在将裸片和中介层附接到衬底的层之后的裸片布置。
图7-图11示意性地示出了在形成衬底的一个或多个附加层以将裸片嵌入在衬底中之后的裸片布置。
图12是用于制造在此描述的封装布置的方法的工艺流程图。
具体实施方式
图1A示出了封装布置100，该封装布置包括裸片布置102，该裸片布置具有嵌入在衬底106内的第一裸片104。根据各种实施例，第一裸片104为存储器器件，并且根据实施例，第一裸片104为动态随机存取存储器(DRAM)。然而，可以利用其它类型的存储器器件。为了清楚起见，对裸片布置102内的组件中的许多组件不进行描述。在此将结合图4-图11更详细地描述裸片布置102。
第二裸片108耦合到裸片布置102。第二裸片108包括键合焊盘110。第二裸片108经由焊料球112耦合到裸片布置102，使得第二裸片108的键合焊盘110经由路由结构128、130和132与第一裸片104的键合焊盘114通信地耦合。因而，可以在第一裸片104和第二裸片108之间路由电信号。第二裸片108也经由焊料球112耦合到裸片布置102，使得键合焊盘110经由路由结构128、130和132与路由结构126和134通信地耦合，以将电信号路由到封装布置100外部的设备。根据各种实施例，第二裸片108被配置为包括一个或多个系统级芯片(SoC)。
根据各种实施例，在第二裸片108与裸片布置102之间提供底部填充材料116。底部填充材料116提供对由焊料球112形成的接合处的保护。参照图1B，根据各种实施例，不包括底部填充材料116。一般而言，焊料球112的尺寸越大，对底部填充材料116存在的需求越小。
参照图1A和图1B，根据各种实施例，包括热沉(heat sink)118。热沉118可以经由合适的诸如环氧树脂之类的粘附剂耦合到裸片布置102。此外，利用传热化合物120来将热沉118耦合到第二裸片108。传热化合物120通常为金属填充树脂胶，而热沉118通常包括例如铝或铜。根据各种实施例，热沉118仅仅经由传热化合物120耦合到第二裸片108，而不耦合到裸片布置102。
图1C示出了封装布置100的实施例，其中封装布置100不包括热沉118，因此不包括传热化合物120。在图1C所示的实施例中，在第二裸片108与裸片布置102之间包括底部填充材料116。图1D示出了不包括热沉118的封装布置100的实施例，因此不包括传热化合物120，并且也不包括第二裸片108和裸片布置102之间的底部填充材料116。
图2A示出了与封装布置100类似的封装布置200。封装布置200包括嵌入在裸片布置202内的两个第一裸片204a、204b，该裸片布置202类似于裸片布置102。如在图2A中可见的那样，两个第一裸片204a、204b按照并排关系嵌入在裸片布置202内。根据各种实施例，第一裸片204a、204b为存储器器件，并且根据实施例，第一裸片204a、204b为动态随机存取存储器(DRAM)。然而，可以利用其它类型的存储器器件。
第二裸片208耦合到裸片布置202。第二裸片208包括键合焊盘210。第二裸片208经由焊料球212耦合到裸片布置202，使得第二裸片208的键合焊盘210经由路由结构228、230和232而与第一裸片204a的键合焊盘214a和第一裸片204b的键合焊盘214b通信地耦合。因而，可以在第一裸片204a、204b和第二裸片208之间路由电信号。第二裸片208也经由焊料球212耦合到裸片布置202，使得键合焊盘210经由路由结构228、230和232而与路由结构226和234通信地耦合，以将电信号路由到封装布置200外部的设备。根据各种实施例，第二裸片208被配置为包括一个或多个系统级芯片(SoC)。
根据各种实施例，在第二裸片208与裸片布置202之间提供底部填充材料216。底部填充材料216提供对由焊料球212形成的接合处的保护。参照图2B，根据各种实施例，不包括底部填充材料216。
参照图2A和图2B，根据各种实施例，包括热沉218。热沉218可以经由合适的诸如环氧树脂之类的粘附剂耦合到裸片布置202。此外，利用传热化合物220来将热沉218耦合到第二裸片208。传热化合物220通常为金属填充树脂胶，而热沉218通常包括例如铝或铜。根据各种实施例，热沉218仅仅经由传热化合物220耦合到第二裸片208，而不耦合到裸片布置202。
图2C示出了封装布置200的实施例，其中封装布置200不包括热沉218，因此不包括传热化合物220。在图2C所示的实施例中，在第二裸片208与裸片布置202之间包括底部填充材料216。图2D示出了不包括热沉218的封装布置200的实施例，因此不包括传热化合物220，并且也不包括在第二裸片208和裸片布置202之间的底部填充材料216。
图3A示出了与封装布置100和200类似的封装布置300。封装布置300包括嵌入在裸片布置302内的两个第一裸片304a、304b，该裸片布置302类似于裸片布置102和202。如在图3A中可见的那样，与并排布置相反，两个第一裸片304a、304b按照叠置布置嵌入在裸片布置302内。根据各种实施例，第一裸片304a、304b为存储器器件，并且根据实施例，第一裸片304a、304b为动态随机存取存储器(DRAM)。然而，可以利用其它类型的存储器器件。
两个第一裸片304a、304b通常利用衬底通孔(TSV，throughsubstrate via)布置组合成单个器件并且然后嵌入在衬底306内。两个第一裸片304a、304b均分别包括键合焊盘314a、314b。通孔322是为第一裸片304a提供的。
第二裸片308耦合到裸片布置302。第二裸片308包括键合焊盘310。第二裸片308经由焊料球312耦合到裸片布置302，使得第二裸片308的键合焊盘310经由路由结构328、330和332而与第一裸片304b的键合焊盘314b通信地耦合。第二裸片308也经由焊料球312耦合到裸片布置302，使得键合焊盘310经由路由结构328、330和332与通孔322耦合，因而与第一裸片304a的键合焊盘314a通信地耦合。因而，可以在第一裸片304a、304b与第二裸片308之间路由电信号。第二裸片308也经由焊料球312耦合到裸片布置302，使得键合焊盘310经由路由结构328、330和332而与路由结构326和334通信地耦合，以将电信号路由到封装布置300外部的设备。根据各种实施例，第二裸片308被配置为包括一个或多个系统级芯片(SoC)。
图3A示出了在第二裸片308和裸片布置302之间包括底部填充材料316的布置。然而，至于在此描述的其它实施例，可以根据需要消除底部填充材料316。类似地，尽管图3A示出了包括热沉318和传热化合物320的封装布置300，但是可以根据需要消除热沉318和传热化合物320，如在此之前关于其它实施例描述的那样。
图3B示出了包括裸片布置302的封装布置300，该裸片布置302包括四个第一裸片304a-304d。两个第一裸片304a、304b布置成叠置关系，而其它两个第一裸片304c、304d也布置成叠置关系。根据各种实施例，第一裸片304a-304d为存储器器件，并且根据实施例，第一裸片304a-304d为动态随机存储存储器(DRAM)。然而，可以利用其它类型的存储器器件。
两个第一裸片304a、304b通常利用TSV布置组合成单个器件并且然后嵌入在衬底306内。两个第一裸片304a、304b均分别包括键合焊盘314a、314b。通孔322a是为第一裸片304a提供的。另两个第一裸片304c、304d通常利用TSV布置组合成单个器件并且然后嵌入在衬底306内。这两个第一裸片304c、304d均分别包括键合焊盘314c、314d。通孔322c是为第一裸片304c提供的。
第二裸片308耦合到裸片布置302。第二裸片308包括键合焊盘310。第二裸片308经由焊料球312耦合到裸片布置302，使得第二裸片308的键合焊盘310经由路由结构328、330和332而与第一裸片304b的键合焊盘314b和第一裸片314d的键合焊盘314d通信地耦合。第二裸片308还经由焊料球312耦合到裸片布置302，使得键合焊盘310经由路由结构328、330和332而与通孔320a耦合，并且因而与第一裸片304a的键合焊盘314a通信地耦合。第二裸片308还经由焊料球312耦合到裸片布置302，使得键合焊盘310经由路由结构328、330和332而与通孔320b耦合，并且因而与第一裸片304c的键合焊盘314c通信地耦合。因而，可以在第一裸片304a-304d与第二裸片308之间路由电信号。第二裸片308也经由焊料球312耦合到裸片布置302，使得键合焊盘310经由路由结构328、330和332而与路由结构326和334通信地耦合，以将电信号路由到封装布置300外部的设备。根据各种实施例，第二裸片308被配置为包括一个或多个系统级芯片(SoC)。
图3B示出了在第二裸片308与裸片布置302之间包括底部填充材料316的布置。然而，至于在此描述的其它实施例，根据需要可以消除底部填充材料316。类似地，尽管图3B示出了包括热沉318和传热化合物320的封装布置300，但是根据需要可以消除热沉318和传热化合物320，如在此之前关于结合其它实施例描述的那样。
图4示意性地示出了包括嵌入在衬底460中的裸片402的示例性裸片布置400。在此，可以利用裸片布置400来实现之前结合图1A-图1D、图2A-图2D和图3A-图3B描述的裸片布置102、202和302。
衬底460包括第一叠层416、第二叠层420以及置于第一叠层416与第二叠层420之间的芯材料418。第一叠层416和/或第二叠层420可以包括诸如基于环氧树脂/树脂的材料的叠层材料。在一些实施例中，叠层材料包括4号阻燃剂(Flame Retardant 4，FR4)或双马来酰亚胺三嗪(BT)。芯材料418可以包括例如树脂。在一些实施例中，芯材料418包括阶段B/C热固性树脂。材料并不限于这些示例，在其它实施例中可以使用用于第一叠层416、第二叠层420和/或芯材料418的其它合适材料。
如所示，衬底460还包括耦合到第一叠层416的第一焊料掩膜层424和耦合到第二叠层420的第二焊料掩膜层422。第一焊料掩膜层424和第二焊料掩膜层422通常包括诸如环氧树脂之类的焊料抗蚀剂。在其它实施例中可以使用其它合适材料来制造第一焊料掩膜层424和第二焊料掩膜层422。
衬底460还包括分别布置在第一叠层416、芯材料418、第二叠层420、第二焊料掩膜层422和第一焊料掩膜层424中的路由结构426、428、430、432和434。路由结构426、428、430、432和434通常包括例如铜的导电材料以路由裸片402的电信号。裸片102的电信号可以包括例如用于裸片402上形成的集成电路(IC)器件(未示出)的电源/接地和/或输入/输出(I/O)信号。
如所示，路由结构426、428、430、432和434可以包括用于路由衬底460的层内的电信号的线型结构和/或用于路由穿过衬底460的层的电信号的过孔型结构。在其它实施例中，路由结构426、428、430、432和434可以包括与所描述的配置不同的其它配置。尽管针对衬底460描述和示出了特定配置，但是使用三维(3D)封装方法来嵌入一个或多个裸片的其它衬底可以受益于在此描述的原理。
尽管在图1A-图1D、图2A-图2D和图3A-图3B的实施例中未示出，但是裸片布置400(并且因而裸片布置102、202和302)可以包括一个或多个中介层408。裸片402和中介层408嵌入在衬底406中，如图4所示。根据各种实施例，裸片402和中介层408嵌入在第一叠层416与第二叠层420之间的芯材料418中。根据各种实施例，与嵌入在衬底460内相反，中介层408可以通过重新分布线(RDL)构图来形成。也可以通过RDL构图创建衬底460内的其它层和/或结构。
裸片402包括诸如硅之类的半导体材料，并且通常包括形成在裸片402的有源侧S1上的IC器件(未示出)，诸如用于逻辑和/或存储器或其它电路的晶体管。裸片402的非有源侧S2布置成与裸片402的有源侧S1相对。有源侧S1和非有源侧S2通常是指裸片402的相对表面，以便于描述在此描述的各种配置，并且并不旨在限制于裸片402的特定结构。
在一些实施例中，使用诸如树脂之类的粘附剂414将裸片402的非有源侧S2上的表面附接于第一叠层416。在其它实施例中，可以使用其它技术(诸如使用载体组)将裸片402耦合到第一叠层416。
裸片402的有源侧S1具有包括介电材料404的表面。在一些实施例中，介电材料404包括低k介电材料，该低k介电材料具有比二氧化硅的介电常数小的介电常数。诸如用于制造包括具有大约40纳米或更小尺寸的特征的裸片的那些低k介电材料通常可以具有如下材料属性：与非低k介电材料相比，更容易受到来自工艺相关应力的结构性缺陷影响。根据各种实施例，介电材料404包括掺杂有诸如碳或氟之类的材料的二氧化硅。在其他实施例中，介电材料404可以包括其他低k介电材料。
裸片402的有源侧S1上的表面还包括一个或多个键合焊盘406或类似结构以路由裸片402的电信号。一个或多个键合焊盘406通常包括诸如铝或铜之类的导电材料。在其它实施例中可以使用其它合适材料。
如所示，中介层408耦合到裸片402的具有介电材料404和一个或多个键合焊盘406的表面(例如在有源侧S1上)。中介层408通常包括形成在诸如硅的半导体材料中的一个或多个过孔410。在一些实施例中，一个或多个过孔410包括硅通孔(TSV)，该硅通孔完全穿过中介层408，如所示那样。一个或多个过孔410电耦合到一个或多个键合焊盘406并且通常填充有例如铜的导电材料以进一步路由裸片402的电信号。
可以使用例如热压工艺或焊料回流工艺将中介层408键合到裸片402。在一些实施例中，耦合到一个或多个过孔408的金属或焊料材料键合到布置在裸片402的有源侧S1上的金属或焊料材料。例如，可以使用热压来形成中介层408与裸片402之间的金属-金属键合，例如铜-铜、金-铜或金-金。可以使用焊料回流来形成诸如焊料-焊料或焊料-金属之类的焊料键合。可以使用各种各样的结构来形成该键合，诸如包括重新分布层(RDL)焊盘配置的凸块、小片和焊盘(例如一个或多个键合焊盘406)。在其它实施例中可以使用其它合适材料、结构和/或键合技术。
在一些实施例中，裸片402和中介层408都包括具有相同或类似的热膨胀系数(CTE)的材料(例如硅)。对于裸片402和中介层408使用具有相同或类似CTE的材料减少了与该材料的热和/或冷失配相关联的应力。
根据各种实施例，中介层408被配置为保护裸片402的介电材料404免于破裂或与裸片402嵌入在衬底460中相关联的其它缺陷。例如，用于将裸片402嵌入在衬底460中的一个或多个层的形成(例如芯材料418的沉积)可以产生在裸片的介电材料404中引起结构缺陷的应力。中介层408提供对裸片402(例如介电材料404)的物理缓冲、支撑和补强剂，特别是在形成一个或多个层以将裸片402嵌入在衬底460中期间。也就是，如在此描述的耦合到中介层408的裸片402提供受保护集成电路结构450，该结构450相比单独裸片402而言在结构上更适应于与制造衬底460相关联的应力，带来裸片402的提高的产率和可靠性。尽管结合图4所示的衬底460一般性地描述了实施例，但是在本公开的范围中包括受益于这些原理的其它衬底配置。
路由结构426、428、430、432和434电耦合到一个或多个过孔410以进一步在整个衬底460中路由裸片402的电信号。例如，可以使用扇出、扇入或直接连接，将一个或多个过孔410电耦合到置于芯材料418区域中的路由结构428。在一些实施例中，包括例如铜的导电材料的重新分布层412形成在中介层408上，以在一个或多个过孔410与路由结构428之间路由电信号。如所示，在衬底460的相对表面上，可以使用路由结构426、428、430、432和434来为裸片402的电信号提供电连接。
可以形成附加结构来进一步路由裸片402的电信号。例如，可以在衬底460的表面上形成一个或多个键合焊盘436。在所描绘的实施例中，该一个或多个键合焊盘436置于第一焊料掩膜层424中并且电耦合到一个或多个过孔410。尽管未描绘，但在其它实施例中，一个或多个键合焊盘可以形成在第二焊料掩膜层422中。该一个或多个键合焊盘436通常包括诸如铜或铝之类的导电材料。在其它实施例中，可以使用其它导电材料来形成该一个或多个键合焊盘436。
在一些实施例中，在该一个或多个键合焊盘436上形成一个或多个焊料球438或类似封装互连结构，以便于裸片布置400与其它电子组件的电耦合，该其它电子组件例如为诸如母板之类的印刷电路板。根据各种实施例，裸片布置400为球栅阵列(BGA)封装。在其它实施例中，裸片布置400可以包括其它类型的封装。
图5示意性地示出了在耦合在一起之前的裸片402和中介层408。该裸片402和中介层408可以适合于已经结合图4描述的实施例。
裸片402可以使用熟知的半导体制造技术来制造。例如，裸片402可以形成在具有多个其它裸片的晶片上，其中在裸片402的有源侧S1上形成有诸如晶体管的一个或多个IC器件(未示出)。介电材料404和一个或多个键合焊盘406通常形成在裸片402的有源侧S1上的表面上。可以对该晶片进行单片化以按照单片形式提供裸片402。
中介层408可以类似地使用熟知的半导体制造技术来制造。类似于裸片402，中介层408可以形成在具有多个其它中介层的晶片上。诸如TSV之类的一个或多个过孔410可以穿过中介层408而形成，并且/或者重新分布层412可以形成在中介层408的表面上。可以对该晶片进行单片化以按照单片形式提供中介层408。
根据各种各样的技术，裸片402和中介层408可以按照单片或晶片形式或其组合来键合在一起。例如，可以对中介层408进行单片化并键合到晶片形式的裸片402，或反之亦然。
根据各种实施例，使用在此描述的热压工艺或焊料回流工艺将中介层408键合到裸片402。也就是，在中介层408和裸片402上形成一个或多个导电结构(例如小片、凸块、焊盘、重新分布层)，以在中介层408与裸片402之间形成键合。裸片402的一个或多个键合焊盘406可以使用任何合适的热压工艺或焊料回流工艺来电耦合到中介层408的一个或多个过孔410，以在一个或多个导电结构之间形成键合。中介层408键合到裸片402的在其上布置有介电材料404和一个或多个键合焊盘406的表面(例如在有源侧S1上)，如箭头所示。
图6示意性地示出了在将裸片402和中介层408附接到衬底的层(例如图4的衬底460)之后的裸片布置600。在一些实施例中，衬底该层为第一叠层416。第一叠层416可以适合于已经结合图4描述的实施例。
裸片402可以使用粘附剂414附接到第一叠层416，以将裸片402的非有源侧S2耦合到第一叠层416。粘附剂414可以适合于已经结合图4描述的实施例。在其它实施例中，可以使用其它技术(例如载体组)将裸片402附接到衬底的该层。
图7-图11示意性地示出了在形成衬底的一个或多个附加层以将裸片嵌入在衬底中之后的裸片布置。图7的裸片布置700表示在形成衬底(例如图4的衬底460)的芯材料418之后的图6的裸片布置600。芯材料418可以适合于已经结合图4描述的实施例。
如所示，可以沉积芯材料418以封装裸片402和中介层408。例如，芯材料418可以通过将热固性树脂沉积到模具中而形成。
根据一些实施例，中介层408被布置成保护裸片402的介电材料404免受与芯材料418的沉积相关联的应力。裸片402上的中介层408形成结合图4所述的受保护IC结构450。
在一些实施例中，在沉积芯材料418之前在第一叠层416上形成路由结构428。可以在将裸片402附接到第一叠层416之前将路由结构428形成在第一叠层416上。路由结构428可以适合于已经结合图4描述的实施例。
图8的裸片布置800表示在构图芯材料418和形成所示的附加路由结构428和路由结构430之后的图7的裸片布置700。路由结构430可以适合于已经结合图4描述的实施例。
芯材料418可以使用任何适当工艺例如光刻/刻蚀或激光打孔来构图以去除部分芯材料418。去除部分芯材料418以允许沉积导电材料来形成路由结构428、430。例如，可以构图芯材料418以便于通过芯材料418形成与中介层408的一个或多个过孔410的电连接。该电连接可以例如通过沉积导电材料以形成路由结构428、430来形成，如所示那样，该路由结构428、430通过重新分布层412电耦合到一个或多个过孔410。
图9的裸片布置900表示在芯材料418上形成第二叠层420之后的裸片布置800。第二叠层420可以适合于已经结合图4描述的实施例。
第二叠层420可以通过在芯材料418上沉积叠层材料并构图叠层材料而形成，以便于通过叠层材料形成与中介层408的一个或多个过孔410的电连接。例如，导电材料可以沉积到第二叠层420的构图区域中，在该构图区域中已经去除叠层材料而形成附加路由结构430，如所示那样。路由结构430通过第二叠层420提供到一个或多个过孔410的电连接。
图10的裸片布置1000表示在第二叠层420上形成焊料掩膜层(例如图4的第二焊料掩膜层422)之后的裸片布置900。第二焊料掩膜层422可以适合于结合图4描述的实施例。
路由结构432可以通过在第二叠层420上对导电材料的沉积和/或构图而形成。路由结构432可以适合于结合图4描述的实施例。可以沉积和/或构图焊料抗蚀剂材料以形成第二焊料掩膜层422。可以形成焊料抗蚀剂材料使得露出路由结构432中的一些而用于进一步的电连接。
图11的裸片布置1100表示在第一叠层416中形成路由结构426之后并且在第一叠层416上形成焊料掩膜层(例如图4的第一焊料掩膜层424)之后的裸片布置1000。第一焊料掩膜层424、一个或多个键合焊盘436、一个或多个焊料球438和路由结构426、434可以适合于结合图4描述的实施例。
在一些实施例中，构图第一叠层416以便于通过第一叠层416形成与中介层408的一个或多个过孔410的电连接。可以将导电材料沉积到第一叠层的构图部分中以形成路由结构426，该路由结构426提供与一个或多个过孔410的电连接。
路由结构434形成在第一叠层416上并且电耦合到路由结构426以路由裸片402的电信号。一个或多个键合焊盘436形成于路由结构426上。沉积和/或构图焊料抗蚀剂材料以形成焊料掩膜层424。可以在焊料抗蚀剂材料中形成开口以允许焊料球438形成/布置在一个或多个键合焊盘434上。
在此描述的封装布置100、200和300通常可以具有大致1.2毫米的厚度。此外，第二裸片108、208和308(被配置有一个或多个SoC)与第一裸片104、204a、204b和304a-304d(当为存储器形式时)的分离导致来自第二裸片的少量热量影响第一裸片的性能。热沉118、218和318以及传热化合物120、220和320也有助于来自第二裸片的热量免于影响第一裸片的性能。
图12示出了根据本公开实施例的示例性方法1200。在1204处，提供第一裸片，使得第一裸片具有包括键合焊盘的表面，以路由第一裸片的电信号。在1208处，将第一裸片附接到衬底的层。在1212处，形成衬底的一个或多个附加层，以将第一裸片嵌入在衬底中。在1216处，将第二裸片耦合到一个或多个附加层，其中第二裸片具有包括键合焊盘的表面以路由第二裸片的电信号。在实施例中，第二裸片耦合到一个或多个附加层，使得在第一裸片与第二裸片之间路由电信号。
该描述可以使用基于透视图的描述，诸如上/下、上方/下方和/或顶部/底部。这样的描述仅用于便于讨论，而不旨在于将在此描述的实施例的应用限制到任何特定取向。
为了本公开的目的，用语“A/B”是指A或B。为了本公开的目的，用语“A和/或B”是指“(A)、(B)或(A和B)”。为了本公开的目的，用语“A、B和C中的至少一个”是指“(A)、(B)、(C)、(A和B)、(A和C)(B和C)或(A，B和C)”。为了本公开的目的，用语“(A)B”是指“(B)或(AB)”。也就是，A是可任选元件。
按照最有助于理解所请求保护的主题的方式，将各种操作作为多个分立的操作依次描述。然而，描述顺序不应被认为是暗示这些操作必定是依赖顺序的。具体而言，这些操作可以不按照表示的顺序执行。描述的操作可以按照与所述实施例不同的顺序执行。在附加实施例中，可以执行各种附加操作和/或可以省略描述的操作。
该描述使用用语“在一个实施例中”、“在一些实施例中”或类似用语，这可以各自指代相同或不同实施例中的一个或多个。此外，关于本公开实施例使用的术语“包括”、“包含”、“具有”等是同义词。
术语芯片、集成电路、单片器件、半导体器件、裸片和微电子器件在微电子领域中通常可互换使用。本发明可适用于上述所有内容，因为它们在该领域中是公知的。
尽管在此已经示出和描述了特定实施例，但是可以在不脱离本公开范围的情况下，用于实现相同目的而计算的各种各样的变更和/或等同实施例或实现方案可以替代所图示和描述的实施例。本公开旨在覆盖在此讨论的实施例的任意修改或变型。因此，明显旨在仅通过权利要求和其等同方案来限制在此描述的实施例。

Claims (20)

1.一种方法，包括：
提供第一裸片，所述第一裸片具有包括键合焊盘的表面，以路由所述第一裸片的电信号；
将所述第一裸片附接到衬底的层；
形成所述衬底的一个或多个附加层，以将所述第一裸片嵌入在所述衬底中；以及
将第二裸片耦合到所述一个或多个附加层，所述第二裸片具有包括键合焊盘的表面，以路由所述第二裸片的电信号，
其中将所述第二裸片耦合到所述一个或多个附加层，使得在所述第一裸片和所述第二裸片之间路由电信号。
2.根据权利要求1所述的方法，其中将第二裸片耦合到所述一个或多个附加层包括：
使用焊料球将所述第二裸片耦合到所述一个或多个附加层。
3.根据权利要求2所述的方法，还包括：
在所述第二裸片和所述一个或多个附加层之间提供底部填充材料。
4.根据权利要求1所述的方法，还包括：
将热沉耦合到所述第二裸片，
其中在所述第二裸片的第一表面处，将所述第二裸片耦合到所述一个或多个附加层，以及
其中在与所述第二裸片的第一表面相对的所述第二裸片的第二表面处，将所述热沉耦合到所述第二裸片。
5.根据权利要求4所述的方法，其中将第二裸片耦合到所述一个或多个附加层包括：
使用焊料球将第二裸片耦合到所述一个或多个附加层。
6.根据权利要求5所述的方法，还包括：
在所述第二裸片和所述一个或多个附加层之间提供底部填充材料。
7.根据权利要求1所述的方法，还包括：
提供第三裸片，所述第三裸片具有包括键合焊盘的表面，以路由该裸片的电信号；以及
将所述第三裸片附接到所述衬底的层，
其中形成所述衬底的一个或多个附加层以将所述第一裸片嵌入在所述衬底中包括形成所述衬底的一个或多个附加层以将所述第三裸片嵌入在所述衬底中，以及
其中将所述第二裸片耦合到所述一个或多个附加层，使得在所述第三裸片和所述第二裸片之间路由电信号。
8.根据权利要求7所述的方法，其中提供第三裸片包括：
在所述第一裸片旁边按照基本并排的布置提供所述第三裸片。
9.根据权利要求7所述的方法，其中提供第三裸片包括：
在所述第一裸片之上提供所述第三裸片，使得所述第三裸片和所述第一裸片处于基本叠置的布置。
10.根据权利要求9所述的方法，还包括：
提供第四裸片，所述第四裸片具有包括键合焊盘的表面，以路由所述第四裸片的电信号；以及
提供第五裸片，所述第五裸片具有包括键合焊盘的表面，以路由所述第五裸片的电信号，
其中在所述第一裸片之上提供所述第三裸片，使得所述第三裸片和所述第一裸片处于基本叠置的布置，
其中在所述第四裸片之上提供所述第五裸片，使得所述第五裸片和所述第四裸片处于基本叠置的布置，
其中按照基本并排的布置来布置所述第一和第三裸片与所述第四和第五裸片，
其中形成所述衬底的一个或多个附加层以将所述第一裸片嵌入在所述衬底中包括形成所述衬底的一个或多个附加层以将所述第四和第五裸片嵌入在所述衬底中，
其中将所述第二裸片耦合到所述一个或多个附加层，使得在所述第四裸片和所述第二裸片之间路由电信号，以及
其中将所述第二裸片耦合到所述一个或多个附加层，使得在所述第五裸片和所述第二裸片之间路由电信号。
11.一种装置，包括：
衬底，所述衬底具有(i)第一叠层、(ii)第二叠层和(iii)置于所述第一叠层与所述第二叠层之间的芯材料；
第一裸片，所述第一裸片耦合到所述第一叠层，所述第一裸片包括含键合焊盘的表面，以路由所述第一裸片的电信号，其中所述第一裸片嵌入在所述衬底的芯材料中；以及
第二裸片，所述第二裸片耦合到所述第二叠层，所述第二裸片具有包括键合焊盘的表面，以路由所述第二裸片的电信号，
其中所述第二裸片耦合到所述第二叠层，使得在所述第一裸片和所述第二裸片之间路由电信号。
12.根据权利要求10所述的装置，其中所述第二裸片经由焊料球耦合到所述第二叠层。
13.根据权利要求12所述的装置，还包括：
底部填充材料，所述底部填充材料在所述第二裸片与所述第二叠层之间。
14.根据权利要求10所述的装置，还包括：
热沉，所述热沉耦合到所述第二裸片，
其中在所述第二裸片的第一表面处，所述第二裸片耦合到所述第二叠层，以及
其中在与所述第二裸片的第一表面相对的所述第二裸片的第二表面处，所述热沉耦合到所述第二裸片。
15.根据权利要求14所述的装置，其中所述第二裸片经由焊料球耦合到所述第二叠层。
16.根据权利要求15所述的装置，还包括：
底部填充材料，所述底部填充材料在所述第二裸片与所述第二叠层之间。
17.根据权利要求10所述的装置，还包括：
第三裸片，所述第三裸片耦合到所述第一叠层，所述第三裸片包括含键合焊盘的表面，以路由所述第三裸片的电信号，
其中所述第三裸片嵌入在所述衬底的芯材料中，以及
其中所述第二裸片耦合到所述第二叠层，使得在所述第三裸片与所述第二裸片之间路由电信号。
18.根据权利要求17所述的装置，其中所述第三裸片定位成(i)相对于所述第一裸片基本并排的布置或者(ii)相对于所述第一裸片基本叠置的布置中的一种。
19.根据权利要求17所述的装置，还包括：
第四裸片，所述第四裸片耦合到所述第一叠层，所述第四裸片包括含键合焊盘的表面，以路由所述第四裸片的电信号，其中所述第四裸片嵌入在所述衬底的芯材料中；以及
第五裸片，所述第五裸片耦合到所述第一叠层，所述第五裸片包括含键合焊盘的表面，以路由所述第五裸片的电信号，其中所述第五裸片嵌入在所述衬底的芯材料中，
其中所述第三裸片定位在所述第一裸片之上，使得所述第三裸片和所述第一裸片处于基本叠置的布置，
其中所述第五裸片定位在所述第四裸片之上，使得所述第五裸片和所述第四裸片处于基本叠置的布置，
其中所述第一和第三裸片与所述第四和第五裸片按照基本并排的布置来布置，
其中所述第二裸片耦合到所述第二叠层，使得在所述第四裸片和所述第二裸片之间路由电信号，以及
其中所述第二裸片耦合到所述第二叠层，使得在所述第五裸片和所述第二裸片之间路由电信号。
20.根据权利要求10所述的装置，其中所述第一裸片为存储器器件，并且所述第二裸片为被配置为包括一个或多个系统级芯片(SoC)的集成电路。
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US20140106508A1 (en) 2014-04-17
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