CN103168358A - 嵌入式结构及其制造方法 - Google Patents
嵌入式结构及其制造方法 Download PDFInfo
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- CN103168358A CN103168358A CN201180044155XA CN201180044155A CN103168358A CN 103168358 A CN103168358 A CN 103168358A CN 201180044155X A CN201180044155X A CN 201180044155XA CN 201180044155 A CN201180044155 A CN 201180044155A CN 103168358 A CN103168358 A CN 103168358A
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Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Wire Bonding (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims (20)
Applications Claiming Priority (7)
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US61/366,136 | 2010-07-20 | ||
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US61/368,555 | 2010-07-28 | ||
US13/184,304 US8618654B2 (en) | 2010-07-20 | 2011-07-15 | Structures embedded within core material and methods of manufacturing thereof |
US13/184,304 | 2011-07-15 | ||
PCT/US2011/044381 WO2012012338A1 (en) | 2010-07-20 | 2011-07-18 | Embedded structures and methods of manufacture thereof |
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CN103168358B CN103168358B (zh) | 2016-05-25 |
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US9543373B2 (en) * | 2013-10-23 | 2017-01-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure and manufacturing method thereof |
US9679839B2 (en) | 2013-10-30 | 2017-06-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chip on package structure and method |
US9443758B2 (en) | 2013-12-11 | 2016-09-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Connecting techniques for stacked CMOS devices |
US9287248B2 (en) | 2013-12-12 | 2016-03-15 | Intel Corporation | Embedded memory and power management subpackage |
JP2015216263A (ja) * | 2014-05-12 | 2015-12-03 | マイクロン テクノロジー, インク. | 半導体装置 |
US11239138B2 (en) * | 2014-06-27 | 2022-02-01 | Taiwan Semiconductor Manufacturing Company | Methods of packaging semiconductor devices and packaged semiconductor devices |
KR101640076B1 (ko) * | 2014-11-05 | 2016-07-15 | 앰코 테크놀로지 코리아 주식회사 | 웨이퍼 레벨의 칩 적층형 패키지 및 이의 제조 방법 |
TWI581325B (zh) * | 2014-11-12 | 2017-05-01 | 精材科技股份有限公司 | 晶片封裝體及其製造方法 |
KR20160103394A (ko) * | 2015-02-24 | 2016-09-01 | 에스케이하이닉스 주식회사 | 반도체 패키지 |
US9711488B2 (en) * | 2015-03-13 | 2017-07-18 | Mediatek Inc. | Semiconductor package assembly |
KR101952676B1 (ko) * | 2015-03-26 | 2019-02-27 | 정문기 | 센서 패키지 구조 |
EP3255668A4 (en) * | 2015-04-14 | 2018-07-11 | Huawei Technologies Co., Ltd. | Chip |
US9613942B2 (en) * | 2015-06-08 | 2017-04-04 | Qualcomm Incorporated | Interposer for a package-on-package structure |
US10269767B2 (en) | 2015-07-31 | 2019-04-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-chip packages with multi-fan-out scheme and methods of manufacturing the same |
US9735131B2 (en) | 2015-11-10 | 2017-08-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-stack package-on-package structures |
US9627365B1 (en) | 2015-11-30 | 2017-04-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Tri-layer CoWoS structure |
US9831148B2 (en) | 2016-03-11 | 2017-11-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated fan-out package including voltage regulators and methods forming same |
US10236245B2 (en) * | 2016-03-23 | 2019-03-19 | Dyi-chung Hu | Package substrate with embedded circuit |
US10186499B2 (en) * | 2016-06-30 | 2019-01-22 | Intel IP Corporation | Integrated circuit package assemblies including a chip recess |
US10308480B2 (en) * | 2016-07-08 | 2019-06-04 | Otis Elevator Company | Embedded power module |
US10157828B2 (en) * | 2016-09-09 | 2018-12-18 | Powertech Technology Inc. | Chip package structure with conductive pillar and a manufacturing method thereof |
US10068879B2 (en) * | 2016-09-19 | 2018-09-04 | General Electric Company | Three-dimensional stacked integrated circuit devices and methods of assembling the same |
US20190181093A1 (en) * | 2016-09-30 | 2019-06-13 | Intel Corporation | Active package substrate having embedded interposer |
US10861763B2 (en) | 2016-11-26 | 2020-12-08 | Texas Instruments Incorporated | Thermal routing trench by additive processing |
US10256188B2 (en) | 2016-11-26 | 2019-04-09 | Texas Instruments Incorporated | Interconnect via with grown graphitic material |
US10811334B2 (en) | 2016-11-26 | 2020-10-20 | Texas Instruments Incorporated | Integrated circuit nanoparticle thermal routing structure in interconnect region |
US10529641B2 (en) * | 2016-11-26 | 2020-01-07 | Texas Instruments Incorporated | Integrated circuit nanoparticle thermal routing structure over interconnect region |
US11004680B2 (en) | 2016-11-26 | 2021-05-11 | Texas Instruments Incorporated | Semiconductor device package thermal conduit |
US11676880B2 (en) | 2016-11-26 | 2023-06-13 | Texas Instruments Incorporated | High thermal conductivity vias by additive processing |
US10410969B2 (en) * | 2017-02-15 | 2019-09-10 | Mediatek Inc. | Semiconductor package assembly |
US10090199B2 (en) * | 2017-03-01 | 2018-10-02 | Semiconductor Components Industries, Llc | Semiconductor device and method for supporting ultra-thin semiconductor die |
CN107093588B (zh) * | 2017-04-21 | 2019-09-03 | 华润微电子(重庆)有限公司 | 一种芯片双面垂直封装结构及封装方法 |
US11328969B2 (en) | 2017-11-16 | 2022-05-10 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor device and manufacturing method thereof |
US10418316B1 (en) * | 2018-04-04 | 2019-09-17 | Advanced Semiconductor Engineering, Inc. | Semiconductor substrate, semiconductor package structure and method of manufacturing a semiconductor device |
US10720416B2 (en) * | 2018-08-15 | 2020-07-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package including thermal relaxation block and manufacturing method thereof |
US11476232B2 (en) * | 2019-03-25 | 2022-10-18 | Analog Devices International Unlimited Company | Three-dimensional packaging techniques for power FET density improvement |
US11721657B2 (en) | 2019-06-14 | 2023-08-08 | Stmicroelectronics Pte Ltd | Wafer level chip scale package having varying thicknesses |
US11296062B2 (en) * | 2019-06-25 | 2022-04-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three-dimension large system integration |
US11462495B2 (en) * | 2020-05-21 | 2022-10-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Chiplets 3D SoIC system integration and fabrication methods |
DE102020128855A1 (de) * | 2020-05-21 | 2021-11-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Chiplets-3d-soic-systemintegrations- und herstellungsverfahren |
TWI733619B (zh) * | 2020-11-20 | 2021-07-11 | 力成科技股份有限公司 | 封裝結構及其製造方法 |
US20220262766A1 (en) | 2021-02-12 | 2022-08-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Through-Dielectric Vias for Direct Connection and Method Forming Same |
US20220352082A1 (en) * | 2021-04-28 | 2022-11-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor Package and Method |
US12015003B2 (en) * | 2021-09-29 | 2024-06-18 | International Business Machines Corporation | High density interconnection and wiring layers, package structures, and integration methods |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6344682B1 (en) * | 1999-02-01 | 2002-02-05 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device comprising a semiconductor element mounted on a substrate and covered by a wiring board |
US20020167079A1 (en) * | 2001-05-11 | 2002-11-14 | Han-Ping Pu | Chip-on-chip based multi-chip module with molded underfill and method of fabricating the same |
US6506633B1 (en) * | 2002-02-15 | 2003-01-14 | Unimicron Technology Corp. | Method of fabricating a multi-chip module package |
US20080224306A1 (en) * | 2007-01-03 | 2008-09-18 | Wen-Kun Yang | Multi-chips package and method of forming the same |
WO2010057808A1 (en) * | 2008-11-24 | 2010-05-27 | Stmicroelectronics (Grenoble) Sas | Semiconductor device having stacked components |
US20100148316A1 (en) * | 2008-12-11 | 2010-06-17 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Topside and Bottom-side Interconnect Structures Around Core Die with TSV |
Family Cites Families (58)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4955011A (en) | 1986-04-10 | 1990-09-04 | Canon Kabushiki Kaisha | Information recording/reproducing apparatus with control device for maintaining head velocity below a critical velocity |
JP3034180B2 (ja) * | 1994-04-28 | 2000-04-17 | 富士通株式会社 | 半導体装置及びその製造方法及び基板 |
US5994166A (en) * | 1997-03-10 | 1999-11-30 | Micron Technology, Inc. | Method of constructing stacked packages |
CN1332888A (zh) * | 1998-12-30 | 2002-01-23 | 因芬尼昂技术股份公司 | 垂直集成半导体装置 |
JP3119649B2 (ja) * | 1999-03-30 | 2000-12-25 | 大衆電腦股▲ふん▼有限公司 | 両面に放熱構造を具えた半導体装置及びその製造方法 |
JP3631638B2 (ja) * | 1999-09-29 | 2005-03-23 | 京セラ株式会社 | 半導体素子用パッケージの実装構造 |
US6801422B2 (en) * | 1999-12-28 | 2004-10-05 | Intel Corporation | High performance capacitor |
US6437990B1 (en) * | 2000-03-20 | 2002-08-20 | Agere Systems Guardian Corp. | Multi-chip ball grid array IC packages |
JP4329235B2 (ja) * | 2000-06-27 | 2009-09-09 | セイコーエプソン株式会社 | 半導体装置及びその製造方法 |
US6356453B1 (en) * | 2000-06-29 | 2002-03-12 | Amkor Technology, Inc. | Electronic package having flip chip integrated circuit and passive chip component |
JP3722209B2 (ja) * | 2000-09-05 | 2005-11-30 | セイコーエプソン株式会社 | 半導体装置 |
JP4248157B2 (ja) * | 2000-12-15 | 2009-04-02 | イビデン株式会社 | 多層プリント配線板 |
US7161239B2 (en) | 2000-12-22 | 2007-01-09 | Broadcom Corporation | Ball grid array package enhanced with a thermal and electrical connector |
KR20030029743A (ko) * | 2001-10-10 | 2003-04-16 | 삼성전자주식회사 | 플랙서블한 이중 배선기판을 이용한 적층 패키지 |
US7202556B2 (en) | 2001-12-20 | 2007-04-10 | Micron Technology, Inc. | Semiconductor package having substrate with multi-layer metal bumps |
SG104293A1 (en) | 2002-01-09 | 2004-06-21 | Micron Technology Inc | Elimination of rdl using tape base flip chip on flex for die stacking |
JP2003318361A (ja) * | 2002-04-19 | 2003-11-07 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2004186422A (ja) * | 2002-12-03 | 2004-07-02 | Shinko Electric Ind Co Ltd | 電子部品実装構造及びその製造方法 |
US6833628B2 (en) * | 2002-12-17 | 2004-12-21 | Delphi Technologies, Inc. | Mutli-chip module |
WO2004105134A1 (en) * | 2003-05-20 | 2004-12-02 | Infineon Technologies Ag | An integrated circuit package |
JP4771808B2 (ja) * | 2003-09-24 | 2011-09-14 | イビデン株式会社 | 半導体装置 |
JP4865197B2 (ja) * | 2004-06-30 | 2012-02-01 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP4199724B2 (ja) * | 2004-12-03 | 2008-12-17 | エルピーダメモリ株式会社 | 積層型半導体パッケージ |
JP4518992B2 (ja) * | 2005-03-31 | 2010-08-04 | Okiセミコンダクタ株式会社 | 半導体チップパッケージ及びその製造方法 |
JP4551321B2 (ja) * | 2005-07-21 | 2010-09-29 | 新光電気工業株式会社 | 電子部品実装構造及びその製造方法 |
US7279795B2 (en) * | 2005-12-29 | 2007-10-09 | Intel Corporation | Stacked die semiconductor package |
SG135074A1 (en) | 2006-02-28 | 2007-09-28 | Micron Technology Inc | Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices |
US7569918B2 (en) * | 2006-05-01 | 2009-08-04 | Texas Instruments Incorporated | Semiconductor package-on-package system including integrated passive components |
US20080116589A1 (en) * | 2006-11-17 | 2008-05-22 | Zong-Fu Li | Ball grid array package assembly with integrated voltage regulator |
US7608921B2 (en) * | 2006-12-07 | 2009-10-27 | Stats Chippac, Inc. | Multi-layer semiconductor package |
US20080174008A1 (en) * | 2007-01-18 | 2008-07-24 | Wen-Kun Yang | Structure of Memory Card and the Method of the Same |
US7982297B1 (en) * | 2007-03-06 | 2011-07-19 | Amkor Technology, Inc. | Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same |
US7553752B2 (en) * | 2007-06-20 | 2009-06-30 | Stats Chippac, Ltd. | Method of making a wafer level integration package |
US20090008766A1 (en) * | 2007-07-02 | 2009-01-08 | Chien-Wei Chang | High-Density Fine Line Structure And Method Of Manufacturing The Same |
US7687899B1 (en) | 2007-08-07 | 2010-03-30 | Amkor Technology, Inc. | Dual laminate package structure with embedded elements |
US7709944B2 (en) * | 2007-12-18 | 2010-05-04 | Stats Chippac Ltd. | Integrated circuit package system with package integration |
US8230589B2 (en) | 2008-03-25 | 2012-07-31 | Intel Corporation | Method of mounting an optical device |
JP5510323B2 (ja) * | 2008-07-23 | 2014-06-04 | 日本電気株式会社 | コアレス配線基板、半導体装置及びそれらの製造方法 |
US8270176B2 (en) * | 2008-08-08 | 2012-09-18 | Stats Chippac Ltd. | Exposed interconnect for a package on package system |
KR20100046760A (ko) * | 2008-10-28 | 2010-05-07 | 삼성전자주식회사 | 반도체 패키지 |
KR101198411B1 (ko) * | 2008-11-17 | 2012-11-07 | 삼성전기주식회사 | 패키지 온 패키지 기판 |
TW201023308A (en) * | 2008-12-01 | 2010-06-16 | Advanced Semiconductor Eng | Package-on-package device, semiconductor package and method for manufacturing the same |
US8008125B2 (en) * | 2009-03-06 | 2011-08-30 | General Electric Company | System and method for stacked die embedded chip build-up |
US7989270B2 (en) * | 2009-03-13 | 2011-08-02 | Stats Chippac, Ltd. | Semiconductor device and method of forming three-dimensional vertically oriented integrated capacitors |
US7847382B2 (en) * | 2009-03-26 | 2010-12-07 | Stats Chippac Ltd. | Integrated circuit packaging system with package stacking and method of manufacture thereof |
KR101058621B1 (ko) * | 2009-07-23 | 2011-08-22 | 삼성전기주식회사 | 반도체 패키지 및 이의 제조 방법 |
US8263434B2 (en) * | 2009-07-31 | 2012-09-11 | Stats Chippac, Ltd. | Semiconductor device and method of mounting die with TSV in cavity of substrate for electrical interconnect of Fi-PoP |
US20110031607A1 (en) * | 2009-08-06 | 2011-02-10 | Advanced Chip Engineering Technology Inc. | Conductor package structure and method of the same |
US8383457B2 (en) * | 2010-09-03 | 2013-02-26 | Stats Chippac, Ltd. | Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect |
US8749040B2 (en) * | 2009-09-21 | 2014-06-10 | Stats Chippac Ltd. | Integrated circuit packaging system with package-on-package and method of manufacture thereof |
US9875911B2 (en) * | 2009-09-23 | 2018-01-23 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming interposer with opening to contain semiconductor die |
US8304888B2 (en) * | 2009-12-22 | 2012-11-06 | Fairchild Semiconductor Corporation | Integrated circuit package with embedded components |
US8519537B2 (en) * | 2010-02-26 | 2013-08-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D semiconductor package interposer with die cavity |
US9385095B2 (en) * | 2010-02-26 | 2016-07-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D semiconductor package interposer with die cavity |
US8455995B2 (en) * | 2010-04-16 | 2013-06-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | TSVs with different sizes in interposers for bonding dies |
US8674513B2 (en) * | 2010-05-13 | 2014-03-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structures for substrate |
US8866301B2 (en) * | 2010-05-18 | 2014-10-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package systems having interposers with interconnection structures |
US8217502B2 (en) * | 2010-06-08 | 2012-07-10 | Stats Chippac Ltd. | Integrated circuit packaging system with multipart conductive pillars and method of manufacture thereof |
-
2011
- 2011-07-15 US US13/184,304 patent/US8618654B2/en active Active
- 2011-07-18 CN CN201180044155.XA patent/CN103168358B/zh active Active
- 2011-07-18 JP JP2013520779A patent/JP6198322B2/ja active Active
- 2011-07-18 KR KR1020137004195A patent/KR20130133166A/ko not_active Application Discontinuation
- 2011-07-18 EP EP11749029.2A patent/EP2596531B1/en active Active
- 2011-07-18 WO PCT/US2011/044381 patent/WO2012012338A1/en active Application Filing
- 2011-07-20 TW TW100125576A patent/TWI527187B/zh not_active IP Right Cessation
-
2013
- 2013-12-24 US US14/140,149 patent/US9087835B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6344682B1 (en) * | 1999-02-01 | 2002-02-05 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device comprising a semiconductor element mounted on a substrate and covered by a wiring board |
US20020167079A1 (en) * | 2001-05-11 | 2002-11-14 | Han-Ping Pu | Chip-on-chip based multi-chip module with molded underfill and method of fabricating the same |
US6506633B1 (en) * | 2002-02-15 | 2003-01-14 | Unimicron Technology Corp. | Method of fabricating a multi-chip module package |
US20080224306A1 (en) * | 2007-01-03 | 2008-09-18 | Wen-Kun Yang | Multi-chips package and method of forming the same |
WO2010057808A1 (en) * | 2008-11-24 | 2010-05-27 | Stmicroelectronics (Grenoble) Sas | Semiconductor device having stacked components |
US20100148316A1 (en) * | 2008-12-11 | 2010-06-17 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Topside and Bottom-side Interconnect Structures Around Core Die with TSV |
Cited By (45)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104425433A (zh) * | 2013-08-30 | 2015-03-18 | 三星电机株式会社 | 插入件、半导体封装件及制造插入件的方法 |
CN104600064A (zh) * | 2013-10-30 | 2015-05-06 | 台湾积体电路制造股份有限公司 | 封装件上芯片结构和方法 |
CN104600064B (zh) * | 2013-10-30 | 2018-08-28 | 台湾积体电路制造股份有限公司 | 封装件上芯片结构和方法 |
CN104882416B (zh) * | 2013-11-13 | 2017-10-20 | 钰桥半导体股份有限公司 | 具有堆叠式封装能力的半导体封装件及其制作方法 |
CN104882416A (zh) * | 2013-11-13 | 2015-09-02 | 钰桥半导体股份有限公司 | 具有堆叠式封装能力的半导体封装件及其制作方法 |
CN104064551B (zh) * | 2014-06-05 | 2018-01-16 | 华为技术有限公司 | 一种芯片堆叠封装结构和电子设备 |
CN106449609A (zh) * | 2015-07-30 | 2017-02-22 | 联发科技股份有限公司 | 半导体封装结构及其形成方法 |
US10256210B2 (en) | 2015-07-30 | 2019-04-09 | Mediatek Inc. | Semiconductor package structure and method for forming the same |
CN107919345B (zh) * | 2015-10-15 | 2023-04-25 | 矽力杰半导体技术(杭州)有限公司 | 芯片的叠层封装结构及叠层封装方法 |
CN107919345A (zh) * | 2015-10-15 | 2018-04-17 | 矽力杰半导体技术(杭州)有限公司 | 芯片的叠层封装结构及叠层封装方法 |
TWI632649B (zh) * | 2016-06-20 | 2018-08-11 | Samsung Electronics Co., Ltd. | 扇出型半導體封裝 |
CN107527884A (zh) * | 2016-06-21 | 2017-12-29 | 三星电机株式会社 | 扇出型半导体封装件 |
US10229865B2 (en) | 2016-06-23 | 2019-03-12 | Samsung Electro-Mechanics Co., Ltd. | Fan-out semiconductor package |
TWI655734B (zh) * | 2016-07-26 | 2019-04-01 | 南韓商三星電機股份有限公司 | 扇出型半導體封裝 |
US10026703B2 (en) | 2016-08-11 | 2018-07-17 | Samsung Electro-Mechanics Co., Ltd. | Fan-out semiconductor package |
TWI667748B (zh) * | 2016-08-11 | 2019-08-01 | 南韓商三星電子股份有限公司 | 扇出型半導體封裝 |
US10474868B2 (en) | 2016-08-22 | 2019-11-12 | Samsung Electro-Mechanics Co., Ltd. | Fan-out semiconductor package |
TWI646648B (zh) * | 2016-08-22 | 2019-01-01 | 南韓商三星電機股份有限公司 | 扇出型半導體封裝 |
US10061967B2 (en) | 2016-08-22 | 2018-08-28 | Samsung Electro-Mechanics Co., Ltd. | Fan-out semiconductor package |
CN107785358B (zh) * | 2016-08-25 | 2023-05-26 | Imec 非营利协会 | 半导体管芯封装及生产这种封装的方法 |
CN107785358A (zh) * | 2016-08-25 | 2018-03-09 | Imec 非营利协会 | 半导体管芯封装及生产这种封装的方法 |
TWI669803B (zh) * | 2016-09-12 | 2019-08-21 | 南韓商三星電子股份有限公司 | 扇出型半導體封裝 |
US10096559B2 (en) | 2016-09-12 | 2018-10-09 | Samsung Electro-Mechanics Co., Ltd. | Fan-out semiconductor package |
US10096560B2 (en) | 2016-09-12 | 2018-10-09 | Samsung Electro-Mechanics Co., Ltd. | Fan-out semiconductor package |
US10714440B2 (en) | 2016-09-29 | 2020-07-14 | Samsung Electronics Co., Ltd. | Fan-out semiconductor package |
US10403588B2 (en) | 2016-09-29 | 2019-09-03 | Samsung Electronics Co., Ltd. | Fan-out semiconductor package |
TWI662666B (zh) * | 2016-09-29 | 2019-06-11 | Samsung Electronics Co., Ltd. | 扇出型半導體封裝 |
TWI651821B (zh) * | 2016-10-04 | 2019-02-21 | Samsung Electronics Co., Ltd. | 扇出型半導體封裝 |
US10050016B2 (en) | 2016-10-04 | 2018-08-14 | Samsung Electro-Mechanics Co., Ltd. | Fan-out semiconductor package |
TWI655725B (zh) * | 2016-10-10 | 2019-04-01 | 三星電機股份有限公司 | 扇出型半導體封裝 |
US10217709B2 (en) | 2016-10-10 | 2019-02-26 | Samsung Electro-Mechanics Co., Ltd. | Fan-out semiconductor package |
US10446322B2 (en) | 2016-11-16 | 2019-10-15 | Samsung Electro-Mechanics Co., Ltd. | Composite electronic component and board having the same mounted thereon |
TWI651818B (zh) * | 2016-11-23 | 2019-02-21 | 三星電機股份有限公司 | 扇出型半導體封裝 |
US10177100B2 (en) | 2016-11-23 | 2019-01-08 | Samsung Electro-Mechanics Co., Ltd. | Fan-out semiconductor package |
CN110192053A (zh) * | 2016-12-09 | 2019-08-30 | 龙沙有限公司 | 生物反应器的破裂盘及其使用方法 |
CN110192053B (zh) * | 2016-12-09 | 2021-10-15 | 龙沙有限公司 | 生物反应器的破裂盘及其使用方法 |
WO2018165819A1 (zh) * | 2017-03-13 | 2018-09-20 | 深圳修远电子科技有限公司 | 电路连线方法 |
US10312195B2 (en) | 2017-07-14 | 2019-06-04 | Samsung Electro-Mechanics Co., Ltd. | Fan-out semiconductor package |
JP7282794B2 (ja) | 2018-06-14 | 2023-05-29 | インテル コーポレイション | 小型電子アセンブリ |
JP2021526309A (ja) * | 2018-06-14 | 2021-09-30 | インテル コーポレイション | 小型電子アセンブリ |
CN112151460A (zh) * | 2019-06-28 | 2020-12-29 | 三星电机株式会社 | 半导体封装件 |
CN111009520B (zh) * | 2019-11-22 | 2022-06-24 | 中国电子科技集团公司第十三研究所 | 一种3d集成芯片及其制备方法 |
CN111009520A (zh) * | 2019-11-22 | 2020-04-14 | 中国电子科技集团公司第十三研究所 | 一种3d集成芯片及其制备方法 |
CN113611692B (zh) * | 2021-07-29 | 2023-05-26 | 矽磐微电子(重庆)有限公司 | Mcm封装结构及其制作方法 |
CN113611692A (zh) * | 2021-07-29 | 2021-11-05 | 矽磐微电子(重庆)有限公司 | Mcm封装结构及其制作方法 |
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US8618654B2 (en) | 2013-12-31 |
KR20130133166A (ko) | 2013-12-06 |
CN103168358B (zh) | 2016-05-25 |
JP2013538445A (ja) | 2013-10-10 |
US9087835B2 (en) | 2015-07-21 |
EP2596531B1 (en) | 2018-10-03 |
US20140106508A1 (en) | 2014-04-17 |
TWI527187B (zh) | 2016-03-21 |
WO2012012338A1 (en) | 2012-01-26 |
EP2596531A1 (en) | 2013-05-29 |
WO2012012338A8 (en) | 2013-02-14 |
JP6198322B2 (ja) | 2017-09-20 |
US20120049364A1 (en) | 2012-03-01 |
TW201214658A (en) | 2012-04-01 |
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