CN1332888A - 垂直集成半导体装置 - Google Patents

垂直集成半导体装置 Download PDF

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CN1332888A
CN1332888A CN99815360A CN99815360A CN1332888A CN 1332888 A CN1332888 A CN 1332888A CN 99815360 A CN99815360 A CN 99815360A CN 99815360 A CN99815360 A CN 99815360A CN 1332888 A CN1332888 A CN 1332888A
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M·斯莫拉
A·库克斯
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Infineon Technologies AG
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Abstract

本发明提出具有包含第1和第2主面的至少一只半导体芯片的半导体装置,该芯片在第1和第2主面上具有有源结构,它们借助通过半导体芯片的连接彼此连接,其中该至少一只半导体芯片以主面之一安排在载体的第1主面上。

Description

垂直集成半导体装置
为了例如可以将多个半导体芯片彼此叠置组装，在新的工艺框架内半导体芯片的磨薄是令人感兴趣的。为此目的，半导体芯片研磨得这样薄，以至于可实现用于两层或多层连接的通孔电路连接(Durchkontaktierung)。除了运用较低结构高度的半导体芯片叠层组装件的可能性之外，也可以使用这种研磨得很薄的半导体芯片的通孔电路连接，以便把半导体芯片的背面充分利用于电路结构。这首先在安全卡IC和芯片卡IC的领域内是令人感兴趣的，因为按照这种方式可以实现防止物理上的侵害有效保护的结构(例如背面的保护板)。
为此目的，今天的半导体芯片一直研磨到15～20μm的厚度。其后果是：对于由此产生的半导体芯片进一步加工是相当困难的。其一，半导体芯片可能“卷绕”，其二，在传统的载体上装配是相当困难的。此外可能在叠层组装件的层间出现应力，这种应力在最坏情况下导致装置的减小热负荷能力。
在高性能计算机已经使用了上述叠层组装件，但是这也与中间加工和芯片装配的昂贵费用相联系。这时为了避免中间加工，即在制造中的上述问题，而使用暂时的载体，它只在装配期间与半导体芯片连接，并在半导体叠层组装件组合后去除。除了高费用之外，复杂的、并且具有多个工艺步骤运行的制法对于低价应用是不希望的。
因此本发明的任务在于：提出一种具有磨薄的半导体芯片的、可以低价制造的半导体装置。
本任务用权利要求1的特征解决。提出一种具有包含第1和第2主面的至少一只半导体芯片的半导体装置，其中半导体芯片在第1和第2主面上包含有源结构，它借助通过半导体芯片的连接而彼此连接，其中，该至少一只半导体芯片以主面之一安排在载体的第1主面上。
也提出将磨薄的半导体芯片牢固地装配在低价的载体上。由此有源结构的通孔电路连接的优点和为此必要的半导体芯片的微小的材料厚度与良好的机械稳定性联系在一起。与现有技术相反，在半导体装置内，保留载体，因此在制造时保证良好的可操作性。在此存在可能性，在载体的第1主面上安排多个芯片。在本发明的一种扩展中，在载体的第2、与第1主面对置的主面上，至少提供在其第1和第2主面上具有有源结构的另一只半导体芯片，它以其主面之一面向载体，并且与在载体的第1主面上的半导体芯片对置。在这种情况下，以“三明治”结构形式提供在载体两侧的半导体装置。因此只需很小空间的半导体装置是可能的。
在本发明的另一扩展中，第1和/或第2主面的载体具有接触连接点，它们与有源结构的半导体芯片接触点连接。因此，载体可以用于采纳简单的无源连接结构，因此一方面可以降低有源层的复杂性，而另一方面可保证防止有源结构和载体分离的可靠性。因此，经载体内的无源连接结构连接一只半导体芯片的接触点或经载体内的无源连接结构连接不同半导体芯片的接触点是可能的。在载体的一个平面或多个平面内可以提供连接结构。
此外，或者在载体的第1主面上的接触连接点彼此连接和/或在载体的第2主面上的接触连接点彼此连接和/或在载体的第1和第2主面上的接触连接点经通孔电路连接彼此连接。处在载体对置的主面上的两半导体芯片之间的电连接可以经载体内的通孔电路连接实现。当半导体装置的操作性能只在至少两只半导体芯片彼此电连接才得以保证时，在与安全有关的应用中是有利的。这时半导体芯片的彼此连接的接触以有利方式各自处在面对载体的半导体芯片一侧。假如半导体芯片之一与载体之间的接触分开，则在半导体芯片上实现的电路不再有操作能力。因此能阻碍在导线上形成的充电电位的检测。
在一个有益的扩展中，载体以有规则的间隔具有从第1到第2主面伸展的通孔电路连接和非导电区。其优点在于：当遵守半导体芯片接触的、相应的最小间距时，可以利用通用的载体，该载体可以与半导体芯片的有源面的接触位置无关地应用。
在本发明的扩展中，载体以有利方式作为半导体晶片实现。用作载体的半导体晶片是可以低价制造的，并且此外具有优点：可以根据机械要求选择层厚，而这时不影响有源层的工艺上的边界条件。显然这也适合于任意的其它载体，例如由塑料或陶瓷制的载体。而且作为载体的半导体晶片具有优点：它可以特别简单地与半导体芯片连接。而且热膨胀系数彼此匹配。
本发明及其优点依靠附图详细说明如下，即：
图1是在载体的一个主面上具有半导体芯片的本发明半导体装置的第1实施例，
图2是在载体的两个主面上具有半导体芯片的本发明半导体装置的第2实施例，以及
图3是具有载体的通孔电路连接的特殊结构的、本发明半导体装置的第3实施例。
图1示出本发明半导体装置的最简单的结构。在载体7的第1主面8上叠置半导体芯片1。半导体芯片1在第1主面2上具有有源结构4。在第2主面3上也叠置有源结构5。这时，半导体芯片1的第2主面3与载体7的第1主面8连接。半导体芯片1的有源结构4、5经多个从第1到第2主面2、3伸展的连接彼此连接。
半导体芯片1是一只磨薄的半导体芯片，例如具有厚度从15到20μm。载体例如具有100μm的厚度。这时的载体层厚可以根据机械要求选择。因为载体7是非导电的，所以这时不必考虑有源层5的工艺上的边界条件。
此外，在图1内的载体7具有连接结构18，它在本例中将半导体芯片1的接触(未示出)彼此连接。载体7在此可以具有一个或甚至多个附加的布线位置。因此可以减少在半导体芯片1的有源结构内布线的复杂性。在载体7和半导体芯片1之间的连接例如可以借助粘合或胶合实现。显然连接也可以各种其它方式实现。
在本发明中重要事实是，磨薄的半导体芯片和载体7牢固地彼此连接。因此，简单的处理半导体芯片是可能的。在现有技术中出现的缺点被绕开了，因此在两主面上配备有源层的半导体芯片或芯片叠层组装件也为低价应用而开发。
图2示出本发明半导体装置的第2实施例。在载体7上现在既在第1主面8上也在第2主面9上各叠置半导体芯片1及半导体芯片10。载体7此刻在第1也在第2主面8、9上具有接触连接点15、16。接触连接点15、16经通孔电路连接彼此连接，并且在半导体芯片1的有源结构5和半导体芯片10的有源结构14之间产生电连接。在半导体芯片1、10和载体7之间基于接触连接点15、16形成的间距可以例如用填料(未示出)填充。
半导体芯片1和半导体芯片10是这样安排在载体7上，使得其边缘彼此对置，即各个半导体芯片的边缘大致确凿地彼此隔绝。因此可以产生具有较小外形尺寸的半导体装置。
在图1和2所示的实施例内，在载体7的主面上，分别只展示了一只半导体芯片。当然，可以设想，不仅在载体7的第1而且也在第2主面8、9上可以并排安排多只半导体芯片。这可以例如经载体7内的连接结构彼此连接。这时这种连接结构可以有这样的特性，使得这种连接在载体的一个主面上多个半导体芯片的接触彼此连接。然而连接结构也可以有如此的特性，使得它们可以仅是一只半导体芯片的接触彼此连接，如图1所示。
也可以设想，把图1和图2所示的多个半导体装置彼此叠置。在这里似乎两只半导体芯片的有源结构彼此连接。随后，这种半导体装置的层序列例如由半导体芯片-载体-半导体芯片-半导体芯片-载体-半导体芯片组成。因为(由一个载体和一个或两侧叠置的半导体芯片组成的)每个“基本模块”本身单独考察具有高稳定性，所以两只半导体芯片的有源结构直接彼此连接此刻是可能的。
此刻也可以设想：在一“基本模块”上，根据所示的实施例之一，只有另一磨薄的、和一侧或两侧配备有源结构的半导体芯片叠置在“基本模块”的一只半导体芯片的有源结构上。
图3示出本发明的半导体装置的第3实施例。它与图2示出的半导体装置的区别只在于：载体由垂直的、即从载体7的第1到第2主面8、9走向的结构，交替地导电(通孔电路连接17)和非导电区构成的正规的结构组成。在这种情况下，半导体芯片的接触和在载体上的接触连接点不必彼此对准。可以利用通用载体，它可以与在半导体芯片上接触的位置无关地应用。在这里只应注意：遵守在半导体芯片上接触的相应最小间距，因此，通过通孔电路连接17不会在半导体芯片的两接触点之间产生短路。
本发明可以实现叠置安排两侧结构化的半导体芯片的半导体装置，其中，在制造该半导体装置时可实现简单和低价的操作。本发明的半导体装置具有良好机械特性。同时基于磨薄的半导体芯片可实现极小层厚。
参考符号表1半导体芯片，2第1主面，3第2主面，4，5有源结构，6连接，7载体，8第1主面，9第2主面，10半导体芯片，11第1主面，12第2主面，13，14有源结构，15，16接触连接点，17通孔电路连接，18连接结构。

Claims (7)

1.具有包含第1主面和第2主面(2，3)的至少一只半导体芯片(1)的半导体装置，该芯片在第1和第2主面(2，3)上具有有源结构(4，5)，它们借助通过半导体芯片(1)的焊接(6)彼此连接，其中该至少一只半导体芯片(1)以主面之一(3)安排在载体(7)的第一主面(8)上。
2.根据权利要求1所述的半导体装置，其特征为，
在载体(7)的第2、与第1主面对置的主面(9)上，至少提供在第1和第2主面(11，12)上具有有源结构(13，14)的另一半导体芯片(10)，该芯片以其主面之一(14)面向载体(7)，并且与在载体(7)的第一主面(8)上的半导体芯片(1)对置。
3.根据权利要求1或2所述的半导体装置，其特征为，
载体(7)在第1和/或第2主面(8，9)上具有接触连接点(15，16)，它们与有源结构(4，5)的半导体芯片(1，10)的接触连接。
4.根据权利要求1到3之一的半导体装置，其特征为，
载体(7)具有无源连接结构(18)。
5.根据权利要求3或4所述的半导体装置，其特征为，
在载体(7)的第1主面(8)上的接触连接点(15)彼此连接，和/或在载体(7)的第2主面(9)上的接触连接点(16)彼此连接，和/或在载体(7)的第1和第2主面上接触连接点(15，16)经通孔电路连接(17)彼此连接。
6.根据权利要求2到5之一所述的半导体装置，其特征为，
载体(7)具有交替地以规则间距从第1到第2主面(8，9)走向的通孔电路连接(17)和非导电区。
7.根据前述权利要求之一所述的半导体装置，其特征为，
载体(7)是半导体晶片。
CN99815360A 1998-12-30 1999-12-21 垂直集成半导体装置 Pending CN1332888A (zh)

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