JP5510323B2 - コアレス配線基板、半導体装置及びそれらの製造方法 - Google Patents
コアレス配線基板、半導体装置及びそれらの製造方法 Download PDFInfo
- Publication number
- JP5510323B2 JP5510323B2 JP2010521727A JP2010521727A JP5510323B2 JP 5510323 B2 JP5510323 B2 JP 5510323B2 JP 2010521727 A JP2010521727 A JP 2010521727A JP 2010521727 A JP2010521727 A JP 2010521727A JP 5510323 B2 JP5510323 B2 JP 5510323B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- layer
- electrode terminal
- insulating layer
- sectional shape
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/113—Via provided in pad; Pad over filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/2405—Shape
- H01L2224/24051—Conformal with the semiconductor or solid-state device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0103—Zinc [Zn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01056—Barium [Ba]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01058—Cerium [Ce]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01073—Tantalum [Ta]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0352—Differences between the conductors of different layers of a multilayer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
- H05K2203/1469—Circuit made after mounting or encapsulation of the components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
本願は、先の日本特許出願2008−190101号(2008年7月23日出願)の優先権を主張するものであり、前記先の出願の全記載内容は、本書に引用をもって繰込み記載されているものとみなされる。
本発明は、コアレス基板とコアレス基板を用いた半導体装置およびそれらの製造方法に関する。特に、多層のコアレス基板と多層のコアレス基板を用いた半導体装置及びそれらの製造方法に関する。
コア層を持ったビルドアップ基板では、コア基板の貫通スルーホール(TH)・配線幅がビルドアップ層のビア径・配線幅に比べて数倍大きいため、そのスケール差がパッケージ基板の高速化・高密度微細配線化の障害となる。一方、配線層にコア層を用いないコアレス基板は、ビルドアップ基板に対して、高速化・高密度微細配線化が可能であるが、支持体上に逐次的に配線体を積層する構造のため、層数が増えると歩留まりが層数の階乗で劣化することが知られている。狭ピッチ、多ピンの半導体素子と接続するコアレス基板は、多層化が必須であるため、高歩留まりで多層化を実現するコアレス基板が必要不可欠である。
12 半導体装置
13 半導体素子
14 電極端子
15 絶縁層A
16 ビアA
17 配線A(配線層)
18、18A 絶縁層B
19、19A ビアB
20、20A 配線B(配線層)
21、21A 絶縁層C
22、22A ビアC
23、23A 配線C(配線層、外部接続端子、第二の電極端子)
24 ソルダーレジスト
25 支持体
26 接着層
30 金属ポスト(ビア)
31 回路基板
32 ビアD
33 配線D
41 半田ボール
42 アンダーフィル樹脂
115 電気素子接続用パッド
117 端子パッド
図1は、実施形態1のコアレス配線基板の断面図である。図1に示すように、このコアレス配線基板は、コア層がない全層ビルドアップ層からなるコアレス基板で、半導体素子と接続する電極端子14と外部接続端子である配線C(23)とを電気的に接続する絶縁層A(15)、ビアA(16)、配線A(17)、絶縁層B(18)、ビアB(19)、配線B(20)、絶縁層C(21)、ビアC(22)が設けられている。図1では、層数が3層であるが、それに限るものではなく、複数層であれば何層でも構わない。本実施形態では、配線層3層、絶縁層3層とした。
図13は、実施形態1の変形例1によるコアレス配線基板の断面図である。図13は、図1と比べると、絶縁層B(18A)、絶縁層C(21A)の膜厚を絶縁層A(15)の膜厚とほぼ同一にして薄くしている。従って、コアレス配線基板全体の薄型化が可能である。ただし、配線B(20)、配線C(23)の配線断面形状は、図1と同様に配線A(17)より拡大させている。狭ピッチの第一の電極端子14に対する最近接層である配線層17をファンアウト層として配線を外側へ引き出し、配線層17より第二の電極端子23側の配線層は、ピッチを広げて配線できるようにしている。従って、第一の電極端子14が狭ピッチであるにも係らず、第一の電極端子14に対する最近接層である配線層17以外の配線層の配線断面形状を拡大することができる。ちなみに、配線層17の最小配線幅、最小配線間隔が10μm、厚さが10μmであるのに対して、配線層20、配線層23の最小配線幅、最小配線間隔を50μm以上、厚さを15μm以上とすることができる。また、絶縁層の膜厚を薄くしているので、ビアB(19)、ビアC(22)のビア断面形状は、アスペクト比が崩れないようにビアA(16)とほぼ同一形状にしている。この変形例によれば、コアレス配線基板の薄型化が可能であり、さらに、第一の電極端子13の最近接層である配線層17以外の配線層の配線断面形状を拡大できるので、低コストで製造できる。
図14は、実施形態1の変形例2によるコアレス配線基板の断面図である。図14は、図1と比べると、配線B(20A)、配線C(23A)の配線断面形状を配線A(17)とほぼ同一にしている。一般に、狭ピッチで微細な配線を形成するためには、高精度の配線形成工程が必要になるため、高コストになりやすい。しかし、配線層によって配線形成工程を変えない方が、安定して低コストで製造できる場合は、図14のように全ての配線層の配線に微細な配線が可能な配線層を用いることもできる。なお、図14では、配線B(20A)、配線C(23A)の配線抵抗が図1に比べて高くなるのを防ぐため、配線B(20A)、配線C(23A)の配線は、図1より配線幅を太くしている。ただし、設計ルール上の最小配線幅は、配線A(17)と同一である。また、配線B(20A)、配線C(23A)の最小配線間隔、配線の厚さは、配線A(17)と同一である。
図15は、実施形態1の変形例3によるコアレス配線基板の断面図である。図15では、図1に対して、外部電極である配線C(23)の面には、配線C(23)の一部を露出させ残部を覆うように、ソルダーレジスト24が形成されている。この変形例では、ソルダーレジスト24の材料は、感光性レジストインクを用いた。ソルダーレジスト24から開口した配線C(23)の表面には、金、銀、銅、錫及び半田材料からなる群から選ばれる少なくとも1種の金属又は合金で形成されていてもよい。この変形例では、厚み3μmのニッケルおよび0.5μmの金を順に積層した。なお、ソルダーレジスト24は、片面だけでなく、両面に設けられても構わない。
図2は、実施形態2の半導体装置の断面図である。図2に示すように、この実施形態の半導体装置は、図15に示すコアレス基板11の電極端子14上に半導体素子13を搭載し、コアレス配線基板11と半導体素子13との電気的な接続を半田ボール41で行っている。コアレス配線基板11は、電極端子14と外部接続端子である配線C(23)とを電気的に接続する絶縁層A(15)、ビアA(16)、配線A(17)、絶縁層B(18)、ビアB(19)、配線B(20)、絶縁層C(21)、ビアC(22)、から構成されている。また、配線C(23)の一部を開口するようにソルダーレジスト24が設けられている。また、ソルダーレジスト24は、片方だけでなく、両面に設けられていても構わない。図2では、層数が3層であるが、それに限るものではなく、複数層であれば何層でも構わない。本実施形態では、配線層3層、絶縁層3層とした。
図3は、実施形態3の半導体装置の断面図である。図3の半導体装置12は、半導体素子13の側面と電極端子14を有する面の少なくとも一部が絶縁層A(15)に接しており、電極端子14の表裏に、電極端子14と半導体装置12の外部接続端子である配線C(23)とを電気的に接続するビアA(16)、配線A(17)、絶縁層B(18)、ビアB(19)、配線B(20)、絶縁層C(21)、ビアC(22)、ビアD(32)、配線D(33)が設けられている。また、配線C(23)の一部を開口するようにソルダーレジスト24が設けられている。
図4は、実施形態4の半導体装置の断面図である。図4の半導体装置12は、半導体素子13の側面と電極端子14を有する面の少なくとも一部が絶縁層A(15)に接しており、電極端子14上に金属ポスト30が設けられ、電極端子14の表裏に、電極端子14と半導体装置12の外部接続端子である配線C(23)とを電気的に接続する配線A(17)、絶縁層B(18)、ビアB(19)、配線B(20)、絶縁層C(21)、ビアC(22)、ビアD(32)、配線D(33)が設けられている。また、配線C(23)の一部を開口するようにソルダーレジスト24が設けられている。図4では、層数が半導体素子13を挟んで表裏に3層であるが、それに限るものではなく、複数層であれば何層でも構わない。本実施形態では、表裏に配線層3層、絶縁層は3層とした。この実施形態4では、実施形態3のビアA(16)が金属ポスト30に置き換わっているが、この金属ポスト30は、電極端子14と配線A(17)とを接続するビアとして機能する。
図5は、実施形態5のコアレス配線基板の製造方法を示す工程図である。本実施形態の製造方法により、実施形態1の変形例3(図15)のコアレス配線基板を製造することができる。
図6は、実施形態6の半導体装置の製造方法を示す工程図である。本実施形態の図6(a)から(e)に示す製造方法により、実施形態2(図2)の半導体装置を製造することができる。
図7および図8は、本発明の実施形態7の半導体装置の製造方法を示す工程図である。図7(a)〜(e)および図8(f)、(g)に示す製造方法により、実施形態3(図3)の半導体装置を製造することができる。
図9および図10は、本発明の実施形態8の半導体装置の製造方法を示す工程図である。図9(a)〜(f)および図10(g)〜(i)に示す製造方法により、実施形態4(図4)の半導体装置を製造することができる。
本発明の全開示(請求の範囲を含む)の枠内において、さらにその基本的技術思想に基づいて、実施形態ないし実施例の変更・調整が可能である。また、本発明の請求の範囲の枠内において種々の開示要素の多様な組み合わせないし選択が可能である。すなわち、本発明は、請求の範囲を含む全開示、技術的思想にしたがって当業者であればなし得るであろう各種変形、修正を含むことは勿論である。
Claims (12)
- 積層された複数の配線層及び絶縁層と、
前記配線層に設けられた配線と、
前記絶縁層に設けられ前記絶縁層上下の前記配線を電気的に接続するビアと、
を有し、第一の表面に第一の電極端子が、前記第一の表面の反対面に第二の電極端子が設けられ、前記第一の電極端子のパッドピッチが前記第二の電極端子のパッドピッチより狭ピッチであるコアレス配線基板において、
前記第一の電極端子と前記第二の電極端子とが、前記配線または前記ビアの少なくとも一つを介して電気的に導通し、
前記ビアまたは前記配線の少なくとも一つが、他の絶縁層または配線層に設けられたビアまたは配線と異なる断面形状を有し、
前記複数の絶縁層のうち、絶縁材料が他の絶縁層と異なる絶縁層を有し、
前記絶縁層の弾性率が、前記第一の電極端子の最近接層から前記第二の電極端子側の層へ向けて段階的に高くなり、
前記第一の電極端子は、半導体素子と接続されることを特徴とするコアレス配線基板。 - 前記ビアの断面形状が、前記第一の電極端子の最近接層で最も小さいことを特徴とする請求項1に記載のコアレス配線基板。
- 前記ビアの断面形状が、前記第一の電極端子の最近接層から前記第二の電極端子側の層へ向けて段階的に拡大していることを特徴とする請求項1又は2に記載のコアレス配線基板。
- 前記ビアの径及び高さが、前記第一の電極端子の最近接層から前記第二の電極端子側の層へ向けて段階的に拡大していることを特徴とする請求項3に記載のコアレス配線基板。
- 前記第一の表面に接する絶縁層から前記第二の表面に接する絶縁層へ向けて前記ビアの断面形状が略相似形状を保ちつつ1層毎に拡大していることを特徴とする請求項4に記載のコアレス配線基板。
- 前記配線の断面形状が、前記第一の電極端子の最近接層で最も小さいことを特徴とする請求項1乃至5いずれか1項記載のコアレス配線基板。
- 前記配線の断面形状が、前記第一の電極端子の最近接層から前記第二の電極端子側の層へ向けて段階的に拡大していることを特徴とする請求項1乃至6いずれか1項記載のコアレス配線基板。
- 前記ビアは前記第一の電極端子側の径より前記第二の電極端子側の径が大きいビアであることを特徴とする請求項1乃至7いずれか1項記載のコアレス配線基板。
- 前記第一の電極端子のパッドピッチが5μm以上200μm以下であることを特徴とする請求項1乃至8いずれか1項記載のコアレス配線基板。
- 請求項1乃至9いずれか1項記載のコアレス配線基板と、前記コアレス配線基板の前記第一の電極端子に接続された少なくとも一つの半導体素子を有することを特徴とする半導体装置。
- 前記半導体素子が、低融点金属又は導電性樹脂のいずれかの材料により前記配線基板にフリップチップ接続されていることを特徴とする請求項10に記載の半導体装置。
- 前記半導体素子が、主に金を材料とするワイヤーにより前記配線基板にワイヤーボンディング接続されていることを特徴とする請求項10に記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010521727A JP5510323B2 (ja) | 2008-07-23 | 2009-07-23 | コアレス配線基板、半導体装置及びそれらの製造方法 |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008190101 | 2008-07-23 | ||
JP2008190101 | 2008-07-23 | ||
PCT/JP2009/063155 WO2010010910A1 (ja) | 2008-07-23 | 2009-07-23 | コアレス配線基板、半導体装置及びそれらの製造方法 |
JP2010521727A JP5510323B2 (ja) | 2008-07-23 | 2009-07-23 | コアレス配線基板、半導体装置及びそれらの製造方法 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013167339A Division JP2013236105A (ja) | 2008-07-23 | 2013-08-12 | コアレス配線基板、半導体装置及びそれらの製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2010010910A1 JPWO2010010910A1 (ja) | 2012-01-05 |
JP5510323B2 true JP5510323B2 (ja) | 2014-06-04 |
Family
ID=41570370
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010521727A Expired - Fee Related JP5510323B2 (ja) | 2008-07-23 | 2009-07-23 | コアレス配線基板、半導体装置及びそれらの製造方法 |
JP2013167339A Pending JP2013236105A (ja) | 2008-07-23 | 2013-08-12 | コアレス配線基板、半導体装置及びそれらの製造方法 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013167339A Pending JP2013236105A (ja) | 2008-07-23 | 2013-08-12 | コアレス配線基板、半導体装置及びそれらの製造方法 |
Country Status (3)
Country | Link |
---|---|
JP (2) | JP5510323B2 (ja) |
TW (1) | TWI401000B (ja) |
WO (1) | WO2010010910A1 (ja) |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8766440B2 (en) | 2010-03-04 | 2014-07-01 | Nec Corporation | Wiring board with built-in semiconductor element |
US8618654B2 (en) * | 2010-07-20 | 2013-12-31 | Marvell World Trade Ltd. | Structures embedded within core material and methods of manufacturing thereof |
JP5566200B2 (ja) * | 2010-06-18 | 2014-08-06 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
JP5715835B2 (ja) * | 2011-01-25 | 2015-05-13 | 新光電気工業株式会社 | 半導体パッケージ及びその製造方法 |
US9153507B2 (en) | 2012-01-31 | 2015-10-06 | Broadcom Corporation | Semiconductor package with improved testability |
JP2013206937A (ja) * | 2012-03-27 | 2013-10-07 | Kyocer Slc Technologies Corp | 配線基板およびその製造方法 |
JP5261756B1 (ja) * | 2012-03-30 | 2013-08-14 | 株式会社フジクラ | 多層配線基板 |
JP6478309B2 (ja) * | 2012-12-31 | 2019-03-06 | サムソン エレクトロ−メカニックス カンパニーリミテッド. | 多層基板及び多層基板の製造方法 |
JP2014154800A (ja) * | 2013-02-13 | 2014-08-25 | Shinko Electric Ind Co Ltd | 配線基板及びその製造方法 |
JP6320681B2 (ja) * | 2013-03-29 | 2018-05-09 | ローム株式会社 | 半導体装置 |
WO2015076121A1 (ja) | 2013-11-20 | 2015-05-28 | 株式会社村田製作所 | 多層配線基板およびこれを備えるプローブカード |
JP6378616B2 (ja) * | 2014-11-12 | 2018-08-22 | イビデン株式会社 | 電子部品内蔵プリント配線板 |
JP6694153B2 (ja) * | 2015-09-24 | 2020-05-13 | 東芝ライテック株式会社 | 発光装置、および照明装置 |
KR102450576B1 (ko) * | 2016-01-22 | 2022-10-07 | 삼성전자주식회사 | 전자 부품 패키지 및 그 제조방법 |
US10600748B2 (en) | 2016-06-20 | 2020-03-24 | Samsung Electronics Co., Ltd. | Fan-out semiconductor package |
KR101982044B1 (ko) * | 2016-08-31 | 2019-05-24 | 삼성전기주식회사 | 팬-아웃 반도체 패키지 |
JP2018049938A (ja) * | 2016-09-21 | 2018-03-29 | 株式会社東芝 | 半導体装置 |
JP6989632B2 (ja) * | 2016-09-21 | 2022-01-05 | 株式会社東芝 | 半導体装置 |
KR20180061913A (ko) | 2016-11-30 | 2018-06-08 | 삼성전기주식회사 | 전자부품 내장 인쇄회로기판 및 전자부품 내장 인쇄회로기판의 제조방법 |
JP6904055B2 (ja) * | 2017-05-19 | 2021-07-14 | Tdk株式会社 | 半導体ic内蔵基板及びその製造方法 |
KR20200038279A (ko) | 2017-09-11 | 2020-04-10 | 라이징 테크놀로지즈 가부시키가이샤 | 전자회로장치 및 전자회로장치의 제조방법 |
KR101942744B1 (ko) * | 2017-11-03 | 2019-01-28 | 삼성전기 주식회사 | 팬-아웃 반도체 패키지 |
JP7371882B2 (ja) | 2019-04-12 | 2023-10-31 | 株式会社ライジングテクノロジーズ | 電子回路装置および電子回路装置の製造方法 |
WO2020230442A1 (ja) | 2019-05-16 | 2020-11-19 | 株式会社ライジングテクノロジーズ | 電子回路装置および電子回路装置の製造方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001217514A (ja) * | 2000-02-03 | 2001-08-10 | Denso Corp | 多層配線基板 |
JP2001291802A (ja) * | 2000-04-06 | 2001-10-19 | Shinko Electric Ind Co Ltd | 配線基板及びその製造方法ならびに半導体装置 |
JP2005072328A (ja) * | 2003-08-26 | 2005-03-17 | Kyocera Corp | 多層配線基板 |
JP2006186321A (ja) * | 2004-12-01 | 2006-07-13 | Shinko Electric Ind Co Ltd | 回路基板の製造方法及び電子部品実装構造体の製造方法 |
JP2007109802A (ja) * | 2005-10-12 | 2007-04-26 | Nec Corp | 配線基板及び配線基板を用いた半導体装置並びにその製造方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001156457A (ja) * | 1999-11-30 | 2001-06-08 | Taiyo Yuden Co Ltd | 電子回路装置の製造方法 |
CN1791311B (zh) * | 2004-12-01 | 2012-02-22 | 新光电气工业株式会社 | 制造电路基板的方法和制造电子部件封装结构的方法 |
JP4016039B2 (ja) * | 2005-06-02 | 2007-12-05 | 新光電気工業株式会社 | 配線基板および配線基板の製造方法 |
JP2007059821A (ja) * | 2005-08-26 | 2007-03-08 | Shinko Electric Ind Co Ltd | 配線基板の製造方法 |
JP2008159973A (ja) * | 2006-12-26 | 2008-07-10 | Nec Corp | 電子部品モジュールおよびこれを内蔵した部品内蔵回路基板 |
-
2009
- 2009-07-23 JP JP2010521727A patent/JP5510323B2/ja not_active Expired - Fee Related
- 2009-07-23 WO PCT/JP2009/063155 patent/WO2010010910A1/ja active Application Filing
- 2009-07-23 TW TW098124847A patent/TWI401000B/zh not_active IP Right Cessation
-
2013
- 2013-08-12 JP JP2013167339A patent/JP2013236105A/ja active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001217514A (ja) * | 2000-02-03 | 2001-08-10 | Denso Corp | 多層配線基板 |
JP2001291802A (ja) * | 2000-04-06 | 2001-10-19 | Shinko Electric Ind Co Ltd | 配線基板及びその製造方法ならびに半導体装置 |
JP2005072328A (ja) * | 2003-08-26 | 2005-03-17 | Kyocera Corp | 多層配線基板 |
JP2006186321A (ja) * | 2004-12-01 | 2006-07-13 | Shinko Electric Ind Co Ltd | 回路基板の製造方法及び電子部品実装構造体の製造方法 |
JP2007109802A (ja) * | 2005-10-12 | 2007-04-26 | Nec Corp | 配線基板及び配線基板を用いた半導体装置並びにその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
JPWO2010010910A1 (ja) | 2012-01-05 |
TWI401000B (zh) | 2013-07-01 |
TW201021640A (en) | 2010-06-01 |
WO2010010910A1 (ja) | 2010-01-28 |
JP2013236105A (ja) | 2013-11-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5510323B2 (ja) | コアレス配線基板、半導体装置及びそれらの製造方法 | |
JP5378380B2 (ja) | 半導体装置及びその製造方法 | |
JP5258045B2 (ja) | 配線基板、配線基板を用いた半導体装置、及びそれらの製造方法 | |
US8710669B2 (en) | Semiconductor device manufacture in which minimum wiring pitch of connecting portion wiring layer is less than minimum wiring pitch of any other wiring layer | |
JP5267987B2 (ja) | 半導体装置およびその製造方法 | |
JP3591524B2 (ja) | 半導体装置搭載基板とその製造方法およびその基板検査法、並びに半導体パッケージ | |
WO2010041630A1 (ja) | 半導体装置及びその製造方法 | |
JP4452222B2 (ja) | 多層配線基板及びその製造方法 | |
JP5331958B2 (ja) | 配線基板及び半導体パッケージ | |
WO2011089936A1 (ja) | 機能素子内蔵基板及び配線基板 | |
JP4921354B2 (ja) | 半導体パッケージ及びその製造方法 | |
WO2009088000A1 (ja) | 配線基板、半導体装置及びそれらの製造方法 | |
JP5548855B2 (ja) | 配線基板及びその製造方法 | |
JP5310103B2 (ja) | 半導体装置及びその製造方法 | |
WO2010101167A1 (ja) | 半導体装置及びその製造方法 | |
KR20190046511A (ko) | 다층 인쇄회로기판 | |
KR102449368B1 (ko) | 다층 인쇄회로기판 | |
JP4063240B2 (ja) | 半導体装置搭載基板とその製造方法、並びに半導体パッケージ | |
JP4812287B2 (ja) | 多層配線基板及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20120607 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130611 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130812 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20130924 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20131224 |
|
A911 | Transfer of reconsideration by examiner before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20140108 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20140225 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20140310 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5510323 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
LAPS | Cancellation because of no payment of annual fees |