JP5378380B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
- Publication number
- JP5378380B2 JP5378380B2 JP2010521728A JP2010521728A JP5378380B2 JP 5378380 B2 JP5378380 B2 JP 5378380B2 JP 2010521728 A JP2010521728 A JP 2010521728A JP 2010521728 A JP2010521728 A JP 2010521728A JP 5378380 B2 JP5378380 B2 JP 5378380B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- layer
- insulating layer
- semiconductor device
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 375
- 238000004519 manufacturing process Methods 0.000 title description 28
- 229910052751 metal Inorganic materials 0.000 claims description 67
- 239000002184 metal Substances 0.000 claims description 67
- 229920005989 resin Polymers 0.000 claims description 55
- 239000011347 resin Substances 0.000 claims description 55
- 239000000758 substrate Substances 0.000 claims description 46
- 239000011810 insulating material Substances 0.000 claims description 44
- 238000007789 sealing Methods 0.000 claims description 14
- 238000009413 insulation Methods 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 496
- 238000000034 method Methods 0.000 description 154
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 59
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 56
- 229910052802 copper Inorganic materials 0.000 description 51
- 239000010949 copper Substances 0.000 description 51
- 239000000463 material Substances 0.000 description 48
- 229910000679 solder Inorganic materials 0.000 description 43
- 239000011368 organic material Substances 0.000 description 35
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 33
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 32
- 229910052737 gold Inorganic materials 0.000 description 32
- 239000010931 gold Substances 0.000 description 32
- -1 etc. Substances 0.000 description 31
- 230000008569 process Effects 0.000 description 31
- 229920002577 polybenzoxazole Polymers 0.000 description 30
- 239000004925 Acrylic resin Substances 0.000 description 29
- 230000015572 biosynthetic process Effects 0.000 description 29
- 239000011521 glass Substances 0.000 description 28
- 229910052759 nickel Inorganic materials 0.000 description 28
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 27
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 24
- 239000000654 additive Substances 0.000 description 24
- 239000000956 alloy Substances 0.000 description 24
- 229910045601 alloy Inorganic materials 0.000 description 24
- 239000003822 epoxy resin Substances 0.000 description 24
- 229920000647 polyepoxide Polymers 0.000 description 24
- 229910052709 silver Inorganic materials 0.000 description 24
- 239000004332 silver Substances 0.000 description 24
- 230000004048 modification Effects 0.000 description 21
- 238000012986 modification Methods 0.000 description 21
- 229920001721 polyimide Polymers 0.000 description 17
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 16
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 16
- 229910052782 aluminium Inorganic materials 0.000 description 16
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 16
- 239000003990 capacitor Substances 0.000 description 16
- 239000000919 ceramic Substances 0.000 description 16
- UHESRSKEBRADOO-UHFFFAOYSA-N ethyl carbamate;prop-2-enoic acid Chemical compound OC(=O)C=C.CCOC(N)=O UHESRSKEBRADOO-UHFFFAOYSA-N 0.000 description 16
- 229910052763 palladium Inorganic materials 0.000 description 16
- 239000005011 phenolic resin Substances 0.000 description 16
- 229920000636 poly(norbornene) polymer Polymers 0.000 description 16
- 239000004744 fabric Substances 0.000 description 15
- 229920001225 polyester resin Polymers 0.000 description 15
- 239000004645 polyester resin Substances 0.000 description 15
- 238000009713 electroplating Methods 0.000 description 13
- 239000009719 polyimide resin Substances 0.000 description 13
- KCTAWXVAICEBSD-UHFFFAOYSA-N prop-2-enoyloxy prop-2-eneperoxoate Chemical compound C=CC(=O)OOOC(=O)C=C KCTAWXVAICEBSD-UHFFFAOYSA-N 0.000 description 13
- 239000000945 filler Substances 0.000 description 12
- 229910052451 lead zirconate titanate Inorganic materials 0.000 description 12
- 239000012790 adhesive layer Substances 0.000 description 11
- 238000007772 electroless plating Methods 0.000 description 11
- 238000003475 lamination Methods 0.000 description 11
- 229910052582 BN Inorganic materials 0.000 description 8
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 8
- BVKZGUZCCUSVTD-UHFFFAOYSA-L Carbonate Chemical compound [O-]C([O-])=O BVKZGUZCCUSVTD-UHFFFAOYSA-L 0.000 description 8
- 229910019142 PO4 Inorganic materials 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 8
- 230000000996 additive effect Effects 0.000 description 8
- 229920006231 aramid fiber Polymers 0.000 description 8
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 8
- 229910002113 barium titanate Inorganic materials 0.000 description 8
- 229910052799 carbon Inorganic materials 0.000 description 8
- 239000002041 carbon nanotube Substances 0.000 description 8
- 229910021393 carbon nanotube Inorganic materials 0.000 description 8
- 239000003054 catalyst Substances 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 239000002131 composite material Substances 0.000 description 8
- 239000011889 copper foil Substances 0.000 description 8
- 239000003989 dielectric material Substances 0.000 description 8
- 150000004820 halides Chemical class 0.000 description 8
- 150000004679 hydroxides Chemical class 0.000 description 8
- 229910010272 inorganic material Inorganic materials 0.000 description 8
- 239000011147 inorganic material Substances 0.000 description 8
- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 description 8
- 150000004767 nitrides Chemical class 0.000 description 8
- 239000004745 nonwoven fabric Substances 0.000 description 8
- NBIIXXVUZAFLBC-UHFFFAOYSA-K phosphate Chemical compound [O-]P([O-])([O-])=O NBIIXXVUZAFLBC-UHFFFAOYSA-K 0.000 description 8
- 239000010452 phosphate Substances 0.000 description 8
- 229920000052 poly(p-xylylene) Polymers 0.000 description 8
- 229910010271 silicon carbide Inorganic materials 0.000 description 8
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 229910052718 tin Inorganic materials 0.000 description 8
- 239000011135 tin Substances 0.000 description 8
- 239000010936 titanium Substances 0.000 description 8
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 8
- 238000001039 wet etching Methods 0.000 description 8
- 239000002759 woven fabric Substances 0.000 description 8
- 239000011787 zinc oxide Substances 0.000 description 8
- 239000004593 Epoxy Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 238000001312 dry etching Methods 0.000 description 7
- 238000003754 machining Methods 0.000 description 7
- 238000007639 printing Methods 0.000 description 7
- 238000003672 processing method Methods 0.000 description 6
- 230000017525 heat dissipation Effects 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- 239000012779 reinforcing material Substances 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 4
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 4
- JOYRKODLDBILNP-UHFFFAOYSA-N Ethyl urethane Chemical compound CCOC(N)=O JOYRKODLDBILNP-UHFFFAOYSA-N 0.000 description 4
- 229910020684 PbZr Inorganic materials 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 4
- GEIAQOFPUVMAGM-UHFFFAOYSA-N ZrO Inorganic materials [Zr]=O GEIAQOFPUVMAGM-UHFFFAOYSA-N 0.000 description 4
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 238000000748 compression moulding Methods 0.000 description 4
- 239000012792 core layer Substances 0.000 description 4
- 238000007766 curtain coating Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 238000007607 die coating method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000000696 magnetic material Substances 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 4
- 229920001568 phenolic resin Polymers 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 238000004528 spin coating Methods 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 229910001936 tantalum oxide Inorganic materials 0.000 description 4
- 238000001721 transfer moulding Methods 0.000 description 4
- 238000011109 contamination Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000011049 filling Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 230000007704 transition Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000012744 reinforcing agent Substances 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 230000004044 response Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0102—Calcium [Ca]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0103—Zinc [Zn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01038—Strontium [Sr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0104—Zirconium [Zr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01041—Niobium [Nb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01056—Barium [Ba]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01057—Lanthanum [La]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01058—Cerium [Ce]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01073—Tantalum [Ta]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01084—Polonium [Po]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0352—Differences between the conductors of different layers of a multilayer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0147—Carriers and holders
- H05K2203/0152—Temporary metallic carrier, e.g. for transferring material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0147—Carriers and holders
- H05K2203/0156—Temporary polymeric carrier or foil, e.g. for processing or transferring
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/06—Lamination
- H05K2203/063—Lamination of preperforated insulating layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
- H05K2203/1469—Circuit made after mounting or encapsulation of the components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
本発明は、日本国特許出願:特願2008−190100号(2008年7月23日出願)の優先権主張に基づくものであり、同出願の全記載内容は引用をもって本書に組み込み記載されているものとする。
本発明は、半導体装置及びその製造方法に関する。特に、半導体素子をコアレス配線基板に内蔵させ、樹脂等の絶縁層で覆い、その上に多層の配線層と絶縁層を積層した半導体装置及びその製造方法に関する。
半導体パッケージのインターポーザ基板にコア層を持ったビルドアップ基板を用いた場合には、コア基板の貫通スルーホール(TH)・配線幅がビルドアップ層のビア径・配線幅に比べて数倍大きいため、そのスケール差がパッケージ基板の高速化・高密度微細配線化の障害となる。一方、配線層にコア層を用いないコアレス基板は、ビルドアップ基板に対して、高速化・高密度微細配線化が可能であるが、支持体上に逐次的に配線体を積層する構造のため、層数が増えると歩留まりが層数の階乗で劣化することが知られている。狭ピッチ、多ピンの半導体素子と接続するコアレス基板は、多層化が必須であるため、高歩留まりで多層化を実現するコアレス基板が必要不可欠であった。
13、13A 半導体素子
14 電極端子
15 絶縁層A
16 ビアA
17 配線A
18、18A 絶縁層B
19、19A ビアB
20、20A 配線B
21、21A 絶縁層C
22、22A ビアC
23、23A、23B 配線C(外部接続端子)
24 ソルダーレジスト
25 支持体
26 接着層
27 補強材
28 ヒートシンク
29 絶縁層D
30 金属ポスト(ビア)
31 コアレス配線基板(回路基板)
111 絶縁層
112 配線回路層
113 ビア導体
117 端子パッド
119 配線基板
121 電子部品内蔵型多層基板
124 キャビティ
125 電子部品
127 パッド
128 パッシベーション膜
129 トランジション層
131 バイアホール
132 導体回路(配線層)
1回以上繰り返す第二の配線体形成工程(図12(e)、図18(e))のうち、少なくとも1回の第二の配線体形成工程が、当該工程より前の工程で形成したビア(16、30)の断面形状より拡大された断面形状を有するビア(19、22)を新たに形成する工程を含む。
図1は、本発明の実施形態1による半導体装置を示す断面図である。図1の半導体装置12は、半導体素子13の側面と電極端子14を有する面の少なくとも一部が絶縁層A(15)に接しており、電極端子14の上面側に、電極端子14と半導体装置12の外部接続端子である配線C(23)とを電気的に接続するビアA(16)、配線A(17)、絶縁層B(18)、ビアB(19)、配線B(20)、絶縁層C(21)、ビアC(22)が設けられている。また、半導体素子13の電極端子14が設けられた面の反対面が、絶縁層A(15)から露出している構造である。
図21は、実施形態1の変形例1による半導体装置の断面図である。図21は、図1と比べると、絶縁層B(18A)、絶縁層C(21A)の膜厚を絶縁層A(15)の膜厚とほぼ同一にして薄くしている。また、半導体素子13Aの厚さも図1より薄くしている。従って、半導体装置12全体の薄型化が可能である。配線B(20)の配線断面形状は、配線A(17)より拡大させているが、配線C(23A)の配線断面形状は、配線B(20)とほぼ同一にしている。半導体素子13Aの電極端子14のピッチに合わせて半導体素子13Aに対する最近接層である配線層17の配線を狭いピッチで配線すると共に、最近接層17の配線をファンアウト層として、最近接層より外部接続端子23側の配線層、ビアの配線ピッチを拡大して配線できるように、半導体素子13Aから引き出した配線の一部を半導体素子13Aより外側でビアB(19A)へ接続している。従って、配線A(17)より外部接続端子23A側の配線層(20、23A)では配線ピッチを広げて、配線断面形状を拡大して配線できる。従って、電極端子14が狭ピッチであるにも係らず、第一の電極端子14に対する最近接層である配線層17以外の配線層の配線断面形状を拡大して配線できる。ちなみに、配線層17の最小配線幅、最小配線間隔が10μm、厚さは10μmであるのに対して、配線層20、配線層23の最小配線幅、最小配線間隔を50μm、厚さ15μmとすることができる。また、絶縁層の膜厚を薄くしているので、ビアB(19A)、ビアC(22A)のビア断面形状は、アスペクト比が崩れないようにビアA(16)とほぼ同一形状にしている。すなわち、この変形例では、半導体素子13Aに対する最近接層の配線層17の配線断面形状を他の配線層より小さくすることにより、薄型でかつ、歩留まりよく製造が可能な半導体素子内蔵コアレス基板が実現できる。
図22は、実施形態1の変形例2による半導体装置の断面図である。図22は、図1と比べると、配線B(20A)、配線C(23B)の配線断面形状を配線A(17)とほぼ同一にしている。一般に、狭ピッチで微細な配線を形成するためには、高精度の配線形成工程が必要になるため、高コストになりやすい。しかし、配線層によって配線形成工程を変えない方が、安定して低コストで製造できる場合は、図22のように全ての配線層の配線に微細な配線が可能な配線層を用いることもできる。なお、電極端子14のピッチに合わせて微細な配線を形成しなければならない配線A(17)に対して、配線B(20A)、配線C(23B)の配線に余裕がある場合は、開いたスペースをグランド配線で覆うこともできる。ただし、配線B(20A)、配線C(23B)の設計ルール上の最小配線幅、最小配線間隔は、配線A(17)と同一である。また、配線B(20A)、配線C(23B)の配線の厚さは、配線A(17)と同一である。
図23は、実施形態1の変形例2による半導体装置を示す断面図である。図23では、図1に対して、半導体装置12の最上面に、配線C(23)の一部を開口するようにソルダーレジスト24が設けられている。ソルダーレジスト24は、配線C(23)の一部を露出させ残部を覆うよう設けられている。この変形例では、ソルダーレジスト23の材料として、感光性レジストインクを用いた。ソルダーレジスト24から開口した表面には、金、銀、銅、錫及び半田材料からなる群から選ばれる少なくとも1種の金属又は合金で形成されていてもよい。本実施形態では、厚み3μmのニッケルおよび0.5μmの金を順に積層した。
また、図2に示すように、半導体素子13の電極端子14の反対面に接着層26が設けられていても構わない。その場合、接着層26が半導体素子13への汚染防止として機能する。また、図3に示すように、接着層26は、半導体素子13の電極端子14の反対面のみに限らず、絶縁層A(15)と接するように設けられていても構わない。
図4は、本発明の実施形態2による半導体装置を示す断面図である。図4の半導体装置12は、半導体素子13の電極端子14を有する面の少なくとも一部が絶縁層A(15)に接しており、半導体素子13の側面が絶縁層D(29)に接しており、電極端子14の上面側に、電極端子14と半導体装置12の外部接続端子である配線C(23)とを電気的に接続するビアA(16)、配線A(17)、絶縁層B(18)、ビアB(19)、配線B(20)、絶縁層C(21)、ビアC(22)が設けられている。また、配線C(23)の一部を開口するようにソルダーレジスト24が設けられている。また、半導体素子13の電極端子14が設けられた面の反対面が、絶縁層D(29)から露出している構造である。
図6は、本発明の実施形態3による半導体装置を示す断面図である。図6の半導体装置12は、半導体素子13の側面と電極端子14を有する面の少なくとも一部が絶縁層A(15)に接しており、電極端子14の上面側に、電極端子14と半導体装置12の外部接続端子である配線C(23)とを電気的に接続する金属ポスト30、配線A(17)、絶縁層B(18)、ビアB(19)、配線B(20)、絶縁層C(21)、ビアC(22)が設けられている。また、配線C(23)の一部を開口するようにソルダーレジスト24が設けられている。また、半導体素子13の電極端子14が設けられた面の反対面が、絶縁層A(15)から露出している構造である。
図7は、本発明の実施形態4による半導体装置を示す断面図である。図7の半導体装置12は、半導体素子13の側面と電極端子14を有する面の少なくとも一部が絶縁層A(15)に接しており、電極端子14の上面側に、電極端子14と半導体装置12の外部接続端子である配線C(23)とを電気的に接続するビアA(16)、配線A(17)、絶縁層B(18)、ビアB(19)、配線B(20)、絶縁層C(21)、ビアC(22)が設けられている。また、配線C(23)の一部を開口するようにソルダーレジスト24が設けられている。また、半導体素子13の電極端子14が設けられた面の反対面に支持体25が設けられている構造である。図7では、層数が3層であるが、それに限るものではなく、複数層であれば何層でも構わない。本実施形態では、配線層3層、絶縁層3層とした。
図11及び図12は、本発明の実施形態5による半導体装置の製造方法を示す工程図である。図11の(a)から(d)の工程に続く工程を図12の(e)と(f)に示す。本実施形態の製造方法により、実施形態1(図2)の半導体装置を製造することができる。
図13及び図14は、本発明の実施形態6による半導体装置の製造方法を示す工程図である。図13の(a)、(b)の工程に続く工程を図14の(c)と(d)に示す。本実施形態の製造方法により、実施形態2(図5)の半導体装置を製造することができる。
図15及び図16は、本発明の実施形態7による半導体装置の製造方法を示す工程図である。図15の(a)、(b)の工程に続く工程を図16の(c)と(d)に示す。本実施形態の製造方法により、実施形態3(図6)の半導体装置を製造することができる。
図17及び図18は、本発明の実施形態8による半導体装置の製造方法を示す工程図である。図17の(a)〜(c)の工程に続く工程を図18の(d)と(e)に示す。本実施形態の製造方法により、実施形態4(図7)の半導体装置を製造することができる。
Claims (16)
- 表面と、前記表面とは反対側の裏面とを有し、前記表面上に複数の電極端子が配置された半導体素子と、
第1主面と、前記第1主面とは反対側の第2主面と、前記第2主面に設置された複数の外部接続端子と、前記第1主面と前記第2主面との間に積層された複数の絶縁層と、前記複数の絶縁層の間に配置された複数の配線層と、前記絶縁層に設けられるとともに前記絶縁層の上下の前記配線層を電気的に接続する複数のビアとを含む基板と、
前記基板の前記第1主面と前記半導体素子とを封止する封止樹脂と、
前記封止樹脂に設けられるとともに、前記封止樹脂の上下の前記複数の電極端子と前記複数の配線層とを電気的に接続する複数の第1ビアと、
を含み、
前記複数の絶縁層は、前記第1主面を形成する第1絶縁層と、前記第1絶縁層と前記第2主面との間に位置する第2絶縁層と、を含み、
前記複数の配線層は、前記第1主面上に配置された第1配線層と、前記第1絶縁層と前記第2絶縁層との間に配置された第2配線層と、を含み、
前記複数のビアは、前記第1配線層と前記第2配線層とを電気的に接続するとともに前記第1絶縁層に形成された第2ビアと、前記第2配線層と前記外部接続端子とを電気的に接続するとともに前記第2絶縁層に形成された第3ビアと、を含み、
断面視において、前記第2ビアの断面積は前記第1ビアの断面積より大きく、前記第3ビアの断面積は前記第2ビアの断面積より大きく、
断面視において、前記第1絶縁層の膜厚は前記電極端子と前記第1配線層との間の前記封止樹脂の膜厚より厚く、前記第2絶縁層の膜厚は前記第1絶縁層の膜厚より厚い半導体装置。 - 前記ビアの断面形状が、前記電極端子の最近接層で最も小さいことを特徴とする請求項1に記載の半導体装置。
- 前記ビアの断面形状が、前記電極端子の最近接層から前記外部接続端子側の層へ向けて段階的に拡大していることを特徴とする請求項1又は2に記載の半導体装置。
- 前記電極端子の最近接層から前記外部接続端子側の層へ向けて前記ビアの断面形状が略相似形状を保ちつつ1層毎に拡大していることを特徴とする請求項3に記載の半導体装置。
- 前記配線の断面形状が、前記電極端子の最近接層で最も小さいことを特徴とする請求項1乃至4いずれか1項記載の半導体装置。
- 前記配線の断面形状が、前記電極端子の最近接層から表裏の前記外部接続端子側の層へ向けて段階的に拡大していることを特徴とする請求項1乃至5いずれか1項記載の半導体装置。
- 前記電極端子のピッチが前記外部接続端子のピッチより狭ピッチであることを特徴とする請求項1乃至6いずれか1項記載の半導体装置。
- 前記ビアは前記電極端子側の径より前記外部接続端子側の径が大きいことを特徴とする請求項1乃至7いずれか1項記載の半導体装置。
- 前記複数の絶縁層のうち、絶縁材料が他の絶縁層と異なる絶縁層を有することを特徴とする請求項1乃至8いずれか1項記載の半導体装置。
- 前記半導体素子の前記電極端子の表面を封止する絶縁層と前記半導体素子の側面を封止する絶縁層が異なることを特徴とする請求項1乃至9いずれか1項記載の半導体装置。
- 前記絶縁層の弾性率が、前記電極端子の最近接層から前記外部接続端子側の層へ向けて段階的に高くなることを特徴とする請求項1乃至10いずれか1項記載の半導体装置。
- 前記電極端子のピッチが、5μm以上200μm以下であることを特徴とする請求項1乃至11いずれか1項記載の半導体装置。
- 前記半導体素子の前記電極端子の表面に金属ポストが設けられ、前記金属ポストが前記第1ビアとして機能するように構成されていることを特徴とする請求項1乃至12いずれか1項記載の半導体装置。
- 前記半導体素子の前記裏面に支持体が設けられていることを特徴とする請求項1乃至13いずれか1項記載の半導体装置。
- 前記支持体に凹部が形成され、その凹部の中に前記半導体素子が設けられていることを特徴とする請求項14記載の半導体装置。
- 前記半導体素子の前記裏面に、ヒートシンクが設けられていることを特徴とする請求項1乃至15いずれか1項記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010521728A JP5378380B2 (ja) | 2008-07-23 | 2009-07-23 | 半導体装置及びその製造方法 |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008190100 | 2008-07-23 | ||
JP2008190100 | 2008-07-23 | ||
PCT/JP2009/063156 WO2010010911A1 (ja) | 2008-07-23 | 2009-07-23 | 半導体装置及びその製造方法 |
JP2010521728A JP5378380B2 (ja) | 2008-07-23 | 2009-07-23 | 半導体装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2010010911A1 JPWO2010010911A1 (ja) | 2012-01-05 |
JP5378380B2 true JP5378380B2 (ja) | 2013-12-25 |
Family
ID=41570371
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010521728A Active JP5378380B2 (ja) | 2008-07-23 | 2009-07-23 | 半導体装置及びその製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US8304915B2 (ja) |
JP (1) | JP5378380B2 (ja) |
CN (1) | CN102106198B (ja) |
TW (1) | TWI402017B (ja) |
WO (1) | WO2010010911A1 (ja) |
Families Citing this family (53)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102017133B (zh) | 2008-05-09 | 2012-10-10 | 国立大学法人九州工业大学 | 芯片尺寸两面连接封装件及其制造方法 |
US8618652B2 (en) * | 2010-04-16 | 2013-12-31 | Intel Corporation | Forming functionalized carrier structures with coreless packages |
JP5685012B2 (ja) * | 2010-06-29 | 2015-03-18 | 新光電気工業株式会社 | 半導体パッケージの製造方法 |
JP5550526B2 (ja) | 2010-10-29 | 2014-07-16 | Tdk株式会社 | 積層型電子部品およびその製造方法 |
CN102479271B (zh) * | 2010-11-25 | 2014-07-23 | 英业达股份有限公司 | 辅助布线的方法 |
JP5715835B2 (ja) * | 2011-01-25 | 2015-05-13 | 新光電気工業株式会社 | 半導体パッケージ及びその製造方法 |
US8957520B2 (en) * | 2011-06-08 | 2015-02-17 | Tessera, Inc. | Microelectronic assembly comprising dielectric structures with different young modulus and having reduced mechanical stresses between the device terminals and external contacts |
US9312214B2 (en) * | 2011-09-22 | 2016-04-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor packages having polymer-containing substrates and methods of forming same |
US10991669B2 (en) * | 2012-07-31 | 2021-04-27 | Mediatek Inc. | Semiconductor package using flip-chip technology |
WO2014054353A1 (ja) * | 2012-10-05 | 2014-04-10 | 株式会社村田製作所 | 電子部品内蔵モジュール及び通信端末装置 |
KR101835566B1 (ko) | 2012-10-08 | 2018-03-07 | 삼성전기주식회사 | 패키지 구조물 및 그 제조 방법 |
KR101472633B1 (ko) * | 2012-10-16 | 2014-12-15 | 삼성전기주식회사 | 하이브리드 적층기판, 그 제조방법 및 패키지 기판 |
KR101420543B1 (ko) * | 2012-12-31 | 2014-08-13 | 삼성전기주식회사 | 다층기판 |
JP6478309B2 (ja) * | 2012-12-31 | 2019-03-06 | サムソン エレクトロ−メカニックス カンパニーリミテッド. | 多層基板及び多層基板の製造方法 |
CN104938040B (zh) * | 2013-01-18 | 2017-10-24 | 名幸电子有限公司 | 内置有零件的基板及其制造方法 |
US8884427B2 (en) | 2013-03-14 | 2014-11-11 | Invensas Corporation | Low CTE interposer without TSV structure |
TW201446083A (zh) | 2013-05-17 | 2014-12-01 | Microcosm Technology Co Ltd | 垂直導電單元及其製造方法 |
US9685414B2 (en) * | 2013-06-26 | 2017-06-20 | Intel Corporation | Package assembly for embedded die and associated techniques and configurations |
CN104299919B (zh) * | 2013-07-15 | 2017-05-24 | 碁鼎科技秦皇岛有限公司 | 无芯层封装结构及其制造方法 |
JP5583828B1 (ja) | 2013-08-05 | 2014-09-03 | 株式会社フジクラ | 電子部品内蔵多層配線基板及びその製造方法 |
CN105379437B (zh) * | 2013-08-29 | 2018-04-27 | 株式会社村田制作所 | 部件一体型片的制造方法、内置有电子部件的树脂多层基板的制造方法、以及树脂多层基板 |
US9379041B2 (en) * | 2013-12-11 | 2016-06-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan out package structure |
JP6341714B2 (ja) | 2014-03-25 | 2018-06-13 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
CN105981484B (zh) * | 2014-04-10 | 2018-11-09 | 株式会社村田制作所 | 元器件内置多层基板 |
JP6298722B2 (ja) * | 2014-06-10 | 2018-03-20 | 新光電気工業株式会社 | 配線基板、半導体装置及び配線基板の製造方法 |
TWI474417B (zh) * | 2014-06-16 | 2015-02-21 | Phoenix Pioneer Technology Co Ltd | 封裝方法 |
JP6466252B2 (ja) * | 2014-06-19 | 2019-02-06 | 株式会社ジェイデバイス | 半導体パッケージ及びその製造方法 |
KR102212559B1 (ko) | 2014-08-20 | 2021-02-08 | 삼성전자주식회사 | 반도체 발광소자 및 이를 이용한 반도체 발광소자 패키지 |
JP2016058472A (ja) * | 2014-09-08 | 2016-04-21 | イビデン株式会社 | 電子部品内蔵配線板及びその製造方法 |
JP2016127248A (ja) * | 2015-01-08 | 2016-07-11 | 日本特殊陶業株式会社 | 多層配線基板 |
KR102450576B1 (ko) * | 2016-01-22 | 2022-10-07 | 삼성전자주식회사 | 전자 부품 패키지 및 그 제조방법 |
US20170287838A1 (en) | 2016-04-02 | 2017-10-05 | Intel Corporation | Electrical interconnect bridge |
CN105977233A (zh) * | 2016-04-28 | 2016-09-28 | 合肥祖安投资合伙企业(有限合伙) | 芯片封装结构及其制造方法 |
WO2018056426A1 (ja) * | 2016-09-26 | 2018-03-29 | 株式会社パウデック | 半導体パッケージ、モジュールおよび電気機器 |
JP6304700B2 (ja) * | 2016-09-26 | 2018-04-04 | 株式会社パウデック | 半導体パッケージ、モジュールおよび電気機器 |
US10181447B2 (en) | 2017-04-21 | 2019-01-15 | Invensas Corporation | 3D-interconnect |
JP6826947B2 (ja) * | 2017-05-18 | 2021-02-10 | 新光電気工業株式会社 | 配線基板、配線基板の製造方法 |
US10643936B2 (en) * | 2017-05-31 | 2020-05-05 | Dyi-chung Hu | Package substrate and package structure |
KR20190012485A (ko) * | 2017-07-27 | 2019-02-11 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조 방법 |
US10396053B2 (en) * | 2017-11-17 | 2019-08-27 | General Electric Company | Semiconductor logic device and system and method of embedded packaging of same |
US10566301B2 (en) * | 2017-11-17 | 2020-02-18 | General Electric Company | Semiconductor logic device and system and method of embedded packaging of same |
US10276523B1 (en) * | 2017-11-17 | 2019-04-30 | General Electric Company | Semiconductor logic device and system and method of embedded packaging of same |
JP2019114677A (ja) * | 2017-12-25 | 2019-07-11 | イビデン株式会社 | プリント配線板 |
EP3629682A1 (en) | 2018-09-25 | 2020-04-01 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Component carrier with embedded component having pads connected in different wiring layers |
EP3916772A4 (en) | 2019-03-12 | 2023-04-05 | Absolics Inc. | PACKAGING SUBSTRATE AND SEMICONDUCTOR DEVICE WITH IT |
CN113366628B (zh) * | 2019-03-12 | 2022-09-30 | 爱玻索立克公司 | 封装基板及包括其的半导体装置 |
CN113424304B (zh) | 2019-03-12 | 2024-04-12 | 爱玻索立克公司 | 装载盒及对象基板的装载方法 |
CN114678344A (zh) | 2019-03-29 | 2022-06-28 | 爱玻索立克公司 | 半导体用封装玻璃基板、半导体封装基板及半导体装置 |
JP7104245B2 (ja) | 2019-08-23 | 2022-07-20 | アブソリックス インコーポレイテッド | パッケージング基板及びこれを含む半導体装置 |
US11031325B2 (en) * | 2019-10-18 | 2021-06-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Low-stress passivation layer |
CN113380681B (zh) * | 2020-03-10 | 2022-03-25 | 重庆康佳光电技术研究院有限公司 | 一种巨量转移方法 |
CN112349738A (zh) * | 2020-10-27 | 2021-02-09 | 武汉新芯集成电路制造有限公司 | 半导体器件及其形成方法、图像传感器 |
US12040284B2 (en) | 2021-11-12 | 2024-07-16 | Invensas Llc | 3D-interconnect with electromagnetic interference (“EMI”) shield and/or antenna |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001217514A (ja) * | 2000-02-03 | 2001-08-10 | Denso Corp | 多層配線基板 |
JP2002246722A (ja) * | 2000-12-15 | 2002-08-30 | Ibiden Co Ltd | プリント配線板 |
JP2004288711A (ja) * | 2003-03-19 | 2004-10-14 | Taiyo Yuden Co Ltd | 電子部品内蔵型多層基板 |
JP2005072328A (ja) * | 2003-08-26 | 2005-03-17 | Kyocera Corp | 多層配線基板 |
JP2007207872A (ja) * | 2006-01-31 | 2007-08-16 | Nec Electronics Corp | 配線基板および半導体装置ならびにそれらの製造方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4854845B2 (ja) | 2000-02-25 | 2012-01-18 | イビデン株式会社 | 多層プリント配線板 |
TW554456B (en) * | 2002-07-04 | 2003-09-21 | Silicon Integrated Sys Corp | Process via mismatch detecting device |
US7372151B1 (en) * | 2003-09-12 | 2008-05-13 | Asat Ltd. | Ball grid array package and process for manufacturing same |
JP5114041B2 (ja) | 2006-01-13 | 2013-01-09 | 日本シイエムケイ株式会社 | 半導体素子内蔵プリント配線板及びその製造方法 |
IL175011A (en) * | 2006-04-20 | 2011-09-27 | Amitech Ltd | Coreless cavity substrates for chip packaging and their fabrication |
US7462784B2 (en) * | 2006-05-02 | 2008-12-09 | Ibiden Co., Ltd. | Heat resistant substrate incorporated circuit wiring board |
US8916452B2 (en) * | 2008-11-23 | 2014-12-23 | Stats Chippac, Ltd. | Semiconductor device and method of forming WLCSP using wafer sections containing multiple die |
US7985671B2 (en) * | 2008-12-29 | 2011-07-26 | International Business Machines Corporation | Structures and methods for improving solder bump connections in semiconductor devices |
US8581418B2 (en) * | 2010-07-21 | 2013-11-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-die stacking using bumps with different sizes |
-
2009
- 2009-07-23 CN CN2009801289567A patent/CN102106198B/zh active Active
- 2009-07-23 JP JP2010521728A patent/JP5378380B2/ja active Active
- 2009-07-23 TW TW098124848A patent/TWI402017B/zh active
- 2009-07-23 US US13/055,372 patent/US8304915B2/en active Active
- 2009-07-23 WO PCT/JP2009/063156 patent/WO2010010911A1/ja active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001217514A (ja) * | 2000-02-03 | 2001-08-10 | Denso Corp | 多層配線基板 |
JP2002246722A (ja) * | 2000-12-15 | 2002-08-30 | Ibiden Co Ltd | プリント配線板 |
JP2004288711A (ja) * | 2003-03-19 | 2004-10-14 | Taiyo Yuden Co Ltd | 電子部品内蔵型多層基板 |
JP2005072328A (ja) * | 2003-08-26 | 2005-03-17 | Kyocera Corp | 多層配線基板 |
JP2007207872A (ja) * | 2006-01-31 | 2007-08-16 | Nec Electronics Corp | 配線基板および半導体装置ならびにそれらの製造方法 |
Also Published As
Publication number | Publication date |
---|---|
WO2010010911A1 (ja) | 2010-01-28 |
TW201028065A (en) | 2010-07-16 |
CN102106198A (zh) | 2011-06-22 |
US20110121445A1 (en) | 2011-05-26 |
US8304915B2 (en) | 2012-11-06 |
JPWO2010010911A1 (ja) | 2012-01-05 |
TWI402017B (zh) | 2013-07-11 |
CN102106198B (zh) | 2013-05-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5378380B2 (ja) | 半導体装置及びその製造方法 | |
JP5510323B2 (ja) | コアレス配線基板、半導体装置及びそれらの製造方法 | |
JP5258045B2 (ja) | 配線基板、配線基板を用いた半導体装置、及びそれらの製造方法 | |
WO2010041630A1 (ja) | 半導体装置及びその製造方法 | |
US8710669B2 (en) | Semiconductor device manufacture in which minimum wiring pitch of connecting portion wiring layer is less than minimum wiring pitch of any other wiring layer | |
JP5267987B2 (ja) | 半導体装置およびその製造方法 | |
US8039756B2 (en) | Multilayered wiring board, semiconductor device in which multilayered wiring board is used, and method for manufacturing the same | |
JP3591524B2 (ja) | 半導体装置搭載基板とその製造方法およびその基板検査法、並びに半導体パッケージ | |
US8929090B2 (en) | Functional element built-in substrate and wiring substrate | |
WO2011114774A1 (ja) | 半導体素子内蔵基板およびその製造方法 | |
JP4921354B2 (ja) | 半導体パッケージ及びその製造方法 | |
JP5310103B2 (ja) | 半導体装置及びその製造方法 | |
WO2010101167A1 (ja) | 半導体装置及びその製造方法 | |
KR20190046511A (ko) | 다층 인쇄회로기판 | |
JP4584700B2 (ja) | 配線基板の製造方法 | |
JP4063240B2 (ja) | 半導体装置搭載基板とその製造方法、並びに半導体パッケージ |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20120607 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130611 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20130702 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130805 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130924 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130925 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5378380 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |