JP5583828B1 - 電子部品内蔵多層配線基板及びその製造方法 - Google Patents
電子部品内蔵多層配線基板及びその製造方法 Download PDFInfo
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- 229910052802 copper Inorganic materials 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
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- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
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- 229910052742 iron Inorganic materials 0.000 description 1
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
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- 229910052718 tin Inorganic materials 0.000 description 1
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
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- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/142—Arrangements of planar printed circuit boards in the same plane, e.g. auxiliary printed circuit insert mounted in a main printed circuit
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- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
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- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
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- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
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- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
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- H05K3/46—Manufacturing multilayer circuits
- H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
- H05K3/4694—Partitioned multilayer circuits having adjacent regions with different properties, e.g. by adding or inserting locally circuit layers having a higher circuit density
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
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- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09727—Varying width along a single conductor; Conductors or pads having different widths
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- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
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- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
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Abstract
【解決手段】複数の第1のプリント配線基板を積層して構成され、電子部品パッケージを内蔵する電子部品内蔵多層配線基板であって、電子部品パッケージは、第1の電子部品を内蔵し、この第1の電子部品の電極ピッチよりも広いピッチで第1のプリント配線基板の配線ピッチと同等のピッチの電極をパッケージの最表層に有するように複数の第2のプリント配線基板を積層して構成され、電子部品パッケージの高さと、第1のプリント配線基板又は複数の第1のプリント配線基板の積層体の厚さとが同等である。
【選択図】図1
Description
まず、図3に示すように、多層配線基板1に内蔵される電子部品パッケージ100を作製する(ステップS100)。ここで、電子部品パッケージ100は、例えば次のように製造される。すなわち、図4に示すように、電子部品パッケージ100を構成する各部材、この電子部品パッケージ100に内蔵される第1の電子部品60を作製する(ステップS200)。
7 貫通穴
8a,8b 開口部
10 第1プリント配線基板
20 第2プリント配線基板
30 第3プリント配線基板
40 第4プリント配線基板
50 第5プリント配線基板
60 第1の電子部品
100 電子部品パッケージ
110 第1層の配線基板
120 第2層の配線基板
130 第3層の配線基板
140 第4層の配線基板
200 第2の電子部品
300 第3の電子部品
Claims (7)
- 複数の第1のプリント配線基板を熱圧着により一括積層して構成され、電子部品パッケージを内蔵する電子部品内蔵多層配線基板であって、
前記電子部品パッケージは、第1の電子部品を内蔵し、この第1の電子部品の電極ピッチよりも広いピッチで前記第1のプリント配線基板の配線ピッチに合わせたピッチの電極をパッケージの最表層に有するように複数の第2のプリント配線基板を積層して構成され、
前記電子部品内蔵多層配線基板は、前記第1の電子部品よりも厚さが厚い第2の電子部品を含み、
前記電子部品パッケージの高さは、前記第2の電子部品の厚さの80%〜125%である
ことを特徴とする電子部品内蔵多層配線基板。 - 前記電子部品パッケージは、
前記複数の第2のプリント配線基板のうち、
前記第1の電子部品の電極形成面側とは反対側の裏面側に配置される第1層の配線基板、前記第1の電子部品が収容される開口部が形成された第2層の配線基板、前記第1の電子部品の電極ピッチに合わせたピッチの導電性ペーストビアが形成され一方の面に前記第1の電子部品の電極ピッチから前記第1のプリント配線基板の配線ピッチへとピッチを拡大させる電極が形成された第3層の配線基板、及び一方の面に前記第1のプリント配線基板の配線ピッチに合わせたピッチの電極が形成され導電性ペーストビアが形成された第4層の配線基板を、
前記第2層の配線基板の開口部に前記第1の電子部品を前記第3層の配線基板の導電性ペーストビアと前記第1の電子部品の電極とが対向するように収容した上で、前記第4層の配線基板の導電性ペーストビアと前記第3層の配線基板の電極とが対向するように配置して一括積層してなる
ことを特徴とする請求項1記載の電子部品内蔵多層配線基板。 - 前記第2のプリント配線基板は、前記第1のプリント配線基板と同一の材料で形成されている
ことを特徴とする請求項1又は2記載の電子部品内蔵多層配線基板。 - 前記複数の第1のプリント配線基板のうちの前記電子部品内蔵多層配線基板の中間層に配置される所定の第1のプリント配線基板は、前記第2の電子部品と前記電子部品パッケージとをそれぞれ搭載可能な開口部を備え、
前記第2の電子部品と前記電子部品パッケージとを各開口部に搭載した上で、前記積層体及び前記第1のプリント配線基板を一括積層してなる
ことを特徴とする請求項1〜3のいずれか1項記載の電子部品内蔵多層配線基板。 - 前記第1及び第2の電子部品とは異なる第3の電子部品を、前記電子部品パッケージの内蔵箇所の直上又は直下に、前記第1のプリント配線基板の配線ピッチに合わせたピッチで形成された前記第3の電子部品の電極と前記電子部品パッケージの電極とが電気的に最短経路で接続されるように表面実装してなる
ことを特徴とする請求項1〜4のいずれか1項記載の電子部品内蔵多層配線基板。 - 複数の第1のプリント配線基板を熱圧着により一括積層して構成され、電子部品パッケージを内蔵する電子部品内蔵多層配線基板の製造方法であって、
第1の電子部品を内蔵し、この第1の電子部品の電極ピッチよりも広いピッチで前記第1のプリント配線基板の配線ピッチに合わせたピッチの電極をパッケージの最表層に有するように複数の第2のプリント配線基板を積層して前記電子部品パッケージを形成する工程と、
前記複数の第1のプリント配線基板のうちの所定の第1のプリント配線基板に前記第1の電子部品よりも厚さが厚い第2の電子部品と前記電子部品パッケージとをそれぞれ搭載可能な開口部を形成し、前記各開口部に前記第2の電子部品と前記電子部品パッケージとを搭載した上で、前記複数の第1のプリント配線基板を前記開口部を塞ぐように積層する工程とを備え、
前記電子部品パッケージを形成する工程は、前記電子部品パッケージをその高さが前記第2の電子部品の厚さの80%〜125%となるように形成する
ことを特徴とする電子部品内蔵多層配線基板の製造方法。 - 前記電子部品パッケージを形成する工程では、
前記複数の第2のプリント配線基板のうち、
前記第1の電子部品の電極形成面側とは反対側の裏面側に配置される第1層の配線基板、前記第1の電子部品が収容される開口部が形成された第2層の配線基板、前記第1の電子部品の電極ピッチに合わせたピッチの導電性ペーストビアが形成され一方の面に前記第1の電子部品の電極ピッチから前記第1のプリント配線基板の配線ピッチへとピッチを拡大させる電極が形成された第3層の配線基板、及び一方の面に前記第1のプリント配線基板の配線ピッチに合わせたピッチの電極が形成され導電性ペーストビアが形成された第4層の配線基板を、
前記第2層の配線基板の開口部に前記第1の電子部品を前記第3層の配線基板の導電性ペーストビアと前記第1の電子部品の電極とが対向するように収容した上で、前記第4層の配線基板の導電性ペーストビアと前記第3層の配線基板の電極とが対向するように配置して一括積層する
ことを特徴とする請求項6記載の電子部品内蔵多層配線基板の製造方法。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPWO2016060073A1 (ja) * | 2014-10-16 | 2017-04-27 | 株式会社村田製作所 | 複合デバイス |
CN112738994A (zh) * | 2020-11-24 | 2021-04-30 | 鹤山市世拓电子科技有限公司 | 一种内嵌功率器件的印刷电路板 |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103857210A (zh) * | 2012-11-28 | 2014-06-11 | 宏启胜精密电子(秦皇岛)有限公司 | 承载电路板、承载电路板的制作方法及封装结构 |
US9900983B2 (en) | 2014-06-18 | 2018-02-20 | Intel Corporation | Modular printed circuit board electrical integrity and uses |
US9829915B2 (en) | 2014-06-18 | 2017-11-28 | Intel Corporation | Modular printed circuit board |
TWI578416B (zh) * | 2015-09-18 | 2017-04-11 | Subtron Technology Co Ltd | 封裝載板及其製作方法 |
JP6626697B2 (ja) * | 2015-11-24 | 2019-12-25 | 京セラ株式会社 | 配線基板およびその製造方法 |
JP2017123459A (ja) | 2016-01-08 | 2017-07-13 | サムソン エレクトロ−メカニックス カンパニーリミテッド. | プリント回路基板 |
WO2017142662A1 (en) * | 2016-02-16 | 2017-08-24 | Intel Corporation | Modular printed circuit board electrical integrity and uses |
KR102041661B1 (ko) * | 2016-12-06 | 2019-11-07 | 삼성전기주식회사 | 팬-아웃 반도체 패키지 |
EP3373714B1 (en) * | 2017-03-08 | 2023-08-23 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Hybrid component carrier and method for manufacturing the same |
FR3069127B1 (fr) * | 2017-07-13 | 2019-07-26 | Safran Electronics & Defense | Carte electronique comprenant des cms brases sur des plages de brasage enterrees |
KR102117463B1 (ko) * | 2017-08-18 | 2020-06-02 | 삼성전기주식회사 | 팬-아웃 반도체 패키지 |
EP3468312B1 (en) * | 2017-10-06 | 2023-11-29 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Method of manufacturing a component carrier having a three dimensionally printed wiring structure |
KR102025906B1 (ko) * | 2017-12-06 | 2019-11-04 | 삼성전자주식회사 | 안테나 모듈 |
JP7046639B2 (ja) * | 2018-02-21 | 2022-04-04 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
JP2019176118A (ja) * | 2018-03-28 | 2019-10-10 | 京セラ株式会社 | 配線基板 |
JP7103030B2 (ja) * | 2018-07-31 | 2022-07-20 | Tdk株式会社 | 電子部品内蔵パッケージ及びその製造方法 |
GB201917680D0 (en) * | 2019-12-04 | 2020-01-15 | Sinclair Grant | Wafr v1 |
KR20220001568A (ko) * | 2020-06-30 | 2022-01-06 | 삼성전기주식회사 | 인쇄회로기판 |
KR20230075176A (ko) * | 2021-11-22 | 2023-05-31 | 삼성전기주식회사 | 인쇄회로기판 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPWO2007126090A1 (ja) * | 2006-04-27 | 2009-09-17 | 日本電気株式会社 | 回路基板、電子デバイス装置及び回路基板の製造方法 |
WO2009141927A1 (ja) * | 2008-05-23 | 2009-11-26 | イビデン株式会社 | プリント配線板及びその製造方法 |
JP2009289802A (ja) * | 2008-05-27 | 2009-12-10 | Tdk Corp | 電子部品内蔵モジュール及びその製造方法 |
JPWO2008136251A1 (ja) * | 2007-05-02 | 2010-07-29 | 株式会社村田製作所 | 部品内蔵モジュール及びその製造方法 |
WO2011102561A1 (ja) * | 2010-02-22 | 2011-08-25 | 三洋電機株式会社 | 多層プリント配線基板およびその製造方法 |
JPWO2010010911A1 (ja) * | 2008-07-23 | 2012-01-05 | 日本電気株式会社 | 半導体装置及びその製造方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11317582A (ja) | 1998-02-16 | 1999-11-16 | Matsushita Electric Ind Co Ltd | 多層配線基板およびその製造方法 |
JP2003243797A (ja) * | 2002-02-19 | 2003-08-29 | Matsushita Electric Ind Co Ltd | モジュール部品 |
US6972964B2 (en) * | 2002-06-27 | 2005-12-06 | Via Technologies Inc. | Module board having embedded chips and components and method of forming the same |
JP4633129B2 (ja) * | 2003-11-11 | 2011-02-16 | オリンパス株式会社 | マルチスペクトル画像撮影装置 |
KR100890371B1 (ko) * | 2004-10-29 | 2009-03-25 | 가부시키가이샤 무라타 세이사쿠쇼 | 세라믹 다층기판 및 그 제조방법 |
JP4866061B2 (ja) * | 2005-11-07 | 2012-02-01 | パイオニア株式会社 | 情報記録装置、情報記録方法、情報記録プログラムおよびコンピュータに読み取り可能な記録媒体 |
JP5107807B2 (ja) * | 2008-06-25 | 2012-12-26 | アンリツ株式会社 | 携帯電話端末用試験装置及び方法 |
-
2013
- 2013-08-05 JP JP2013162214A patent/JP5583828B1/ja active Active
-
2014
- 2014-08-04 US US14/451,215 patent/US9253882B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPWO2007126090A1 (ja) * | 2006-04-27 | 2009-09-17 | 日本電気株式会社 | 回路基板、電子デバイス装置及び回路基板の製造方法 |
JPWO2008136251A1 (ja) * | 2007-05-02 | 2010-07-29 | 株式会社村田製作所 | 部品内蔵モジュール及びその製造方法 |
WO2009141927A1 (ja) * | 2008-05-23 | 2009-11-26 | イビデン株式会社 | プリント配線板及びその製造方法 |
JP2009289802A (ja) * | 2008-05-27 | 2009-12-10 | Tdk Corp | 電子部品内蔵モジュール及びその製造方法 |
JPWO2010010911A1 (ja) * | 2008-07-23 | 2012-01-05 | 日本電気株式会社 | 半導体装置及びその製造方法 |
WO2011102561A1 (ja) * | 2010-02-22 | 2011-08-25 | 三洋電機株式会社 | 多層プリント配線基板およびその製造方法 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPWO2016060073A1 (ja) * | 2014-10-16 | 2017-04-27 | 株式会社村田製作所 | 複合デバイス |
US9960122B2 (en) | 2014-10-16 | 2018-05-01 | Murata Manufacturing Co., Ltd. | Composite device with substrate and mounted component |
CN112738994A (zh) * | 2020-11-24 | 2021-04-30 | 鹤山市世拓电子科技有限公司 | 一种内嵌功率器件的印刷电路板 |
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