WO2011114774A1 - 半導体素子内蔵基板およびその製造方法 - Google Patents
半導体素子内蔵基板およびその製造方法 Download PDFInfo
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- WO2011114774A1 WO2011114774A1 PCT/JP2011/051295 JP2011051295W WO2011114774A1 WO 2011114774 A1 WO2011114774 A1 WO 2011114774A1 JP 2011051295 W JP2011051295 W JP 2011051295W WO 2011114774 A1 WO2011114774 A1 WO 2011114774A1
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Definitions
- the present invention relates to a semiconductor element built-in substrate and a method for manufacturing the same.
- the technology that is expected to have the highest functionality and performance is the chip stacking technology using TSV.
- this technology requires the TSV to be formed in an area where there is no LSI circuit, and there are many restrictions on the layout due to the keepout zone, and further logic LSIs tend to be smaller in chip size. There is a problem that it is difficult to increase the density.
- TSV formation has a problem that the yield rate of TSV formation affects the yield rate of the entire chip including the LSI circuit formation step, whether it is performed before or after the LSI circuit formation step.
- chip stacking technology that connects chips by wire bonding or solder bumps within a single package can achieve three-dimensionalization with a relatively high yield.
- connection terminals on the chip are limited to the periphery of the chip, and in the case of connection by solder bumps, it is difficult to stack three or more chips. There is a problem that.
- package stacking technology such as package-on-package is widely used mainly for mobile phone applications because of its ease of function combination and cost reduction.
- the pin arrangement of the package mounted on the upper stage is limited to the peripheral, and thus the number of pins of the LSI chip in the lower package is limited.
- the package stacking technique has a problem that the mounting height is higher than the chip stacking technique.
- an LSI-embedded substrate in which an LSI chip is built in a package substrate has attracted attention as a technique for realizing a reduction in thickness, size, and number of pins. ing.
- Patent Document 1 discloses a semiconductor device having a package structure in which a chip is mounted inside a wiring board.
- the semiconductor device includes a core substrate having a conductor layer that is conductive on the front and back via a through hole, a chip mounted on the core substrate with a circuit surface facing upward, an insulating layer covering the chip, and the chip A wiring on the chip connected to the electrode, wiring on the upper surface side of the package connected to the wiring through a via, and a via connected to the conductor layer on the core substrate on the insulating layer on the side of the chip.
- an insulating layer is provided on the lower surface side of the core substrate, a via that is electrically connected to the via on the side of the chip is provided on the insulating layer, and wiring that connects to the via is provided on the lower surface side of the package.
- the semiconductor device described in the above-mentioned patent document has wirings on both surfaces, and vias are provided in the insulating layer on the side of the built-in chip in order to make these conductive. Since the height of the via is determined according to the height of the built-in chip, when the chip is thick, it is necessary to provide a via having a large diameter, and it is difficult to increase the density of the via. This high-density via can be achieved if a high-aspect-ratio via can be formed. However, when forming a via, the higher the aspect-ratio, the more difficult it is to form holes or the filling of conductive material into the holes. It becomes difficult.
- the via formation process involves many steps such as laser processing, desmear treatment, seed layer formation, resist film formation, resist patterning, plating treatment, resist stripping, and seed layer removal.
- steps such as laser processing, desmear treatment, seed layer formation, resist film formation, resist patterning, plating treatment, resist stripping, and seed layer removal.
- the via is formed after the chip is built in, there is a problem that the yield of the via is directly connected to the yield of the chip built-in substrate.
- An object of the present invention is to provide a small and thin semiconductor element-embedded substrate that can be manufactured at a high yield and a method for manufacturing the same.
- a wiring board containing a semiconductor element is The semiconductor element; Chip parts, A peripheral insulating layer covering at least an outer peripheral side surface of the semiconductor element and the chip component; Upper surface side wiring provided on the upper surface side of the wiring board; Including lower surface side wiring provided on the lower surface side of the wiring board,
- the semiconductor element has a terminal on the upper surface side, and the terminal is electrically connected to the upper surface side wiring,
- the chip component is An upper surface side terminal electrically connected to the upper surface side wiring; A lower surface side terminal electrically connected to the lower surface side wiring;
- a semiconductor element-embedded substrate is provided that has a through-chip via that penetrates the chip component and connects the upper surface side terminal and the lower surface side terminal.
- a method of manufacturing a wiring board incorporating a semiconductor element A step of mounting a semiconductor element having a terminal on the upper surface side with its lower surface facing the support surface on the support; Mounting a chip component having terminals on the upper surface side and the lower surface side on the support; Forming a peripheral insulating layer covering the semiconductor element and the chip component; Removing the support; Forming a first wiring electrically connected to a lower surface side terminal of the chip component; Forming a second wiring electrically connected to the terminal of the semiconductor element and the upper surface side terminal of the chip component; A manufacturing method is provided in which the chip component has a through-chip via that penetrates the chip component and connects the upper surface side terminal and the lower surface side terminal.
- This manufacturing method further includes a step of forming a base insulating layer on the support, and the semiconductor element and the chip component can be mounted on the base insulating layer.
- the semiconductor element and the chip component can be mounted via an adhesive layer.
- a method of manufacturing a wiring board incorporating a semiconductor element Forming at least a first wiring on the support; On the support, mounting a semiconductor element having a terminal on the upper surface side with the lower surface facing the support, Mounting a chip component having terminals on the upper surface side and the lower surface side on the support so that the terminals on the lower surface side are electrically connected to the first wiring; Forming a peripheral insulating layer covering the semiconductor element and the chip component; Removing the support; Forming a second wiring electrically connected to the terminal of the semiconductor element and the upper surface side terminal of the chip component;
- a manufacturing method is provided in which the chip component has a through-chip via that penetrates the chip component and connects the upper surface side terminal and the lower surface side terminal.
- a multilayer wiring structure including the first wiring as a wiring on the uppermost layer side and including wiring and insulating layers alternately provided on the support is formed.
- the semiconductor element and the chip component can be mounted on the multilayer wiring structure, and the terminal on the lower surface side of the chip component can be electrically connected to the first wiring.
- the lower surface side terminal of the chip component can be connected to the first wiring via a solder member.
- the peripheral insulating layer may include a first insulating layer that surrounds outer peripheral side surfaces of the semiconductor element and the chip component, and a second insulating layer that covers upper surfaces of the semiconductor element and the chip component.
- the first insulating layer can include a reinforcing material.
- FIG. 1 is a cross-sectional view showing a semiconductor element built-in substrate according to a first embodiment of the present invention.
- FIG. 3 is a plan view showing an arrangement example of embedded chips in the semiconductor element embedded substrate according to the first embodiment of the present invention.
- FIG. 10 is a plan view showing another arrangement example of the built-in chip in the semiconductor element built-in substrate according to the first embodiment of the present invention.
- FIG. 10 is a plan view showing another arrangement example of the built-in chip in the semiconductor element built-in substrate according to the first embodiment of the present invention.
- FIG. 10 is a plan view showing another arrangement example of the built-in chip in the semiconductor element built-in substrate according to the first embodiment of the present invention.
- FIG. 10 is a plan view showing an arrangement example of embedded chips and chip side vias in a semiconductor element embedded substrate according to a second embodiment of the present invention. It is sectional drawing for demonstrating the manufacturing method of the board
- a substrate with a built-in semiconductor element includes a semiconductor element, a chip component, a peripheral insulating layer covering at least an outer peripheral side surface of the semiconductor element and the chip component, and an upper surface side provided on the upper surface side of the substrate. Wiring and lower surface side wiring provided on the lower surface side of the substrate.
- the built-in semiconductor element has a terminal on its upper surface side, and this terminal is electrically connected to the upper surface side wiring.
- the terminal of this semiconductor element can be connected to the upper surface side wiring through a via.
- a semiconductor chip having a semiconductor circuit can be used as this semiconductor element.
- the built-in chip component can be disposed on the side of the semiconductor element, and includes an upper surface side terminal electrically connected to the upper surface side wiring, a lower surface side terminal electrically connected to the lower surface side wiring,
- the chip component has a through-chip via that penetrates the chip component and connects the upper surface side terminal and the lower surface side terminal.
- the upper surface side terminal of this chip component can be connected to the upper surface side wiring through a via.
- the lower surface side terminal of this chip component can be connected to the lower surface side wiring via a via or a solder member.
- this chip component a semiconductor chip having no semiconductor circuit can be used.
- the peripheral insulating layer includes a lower surface side insulating layer covering the lower surface of the built-in semiconductor element and the lower surface of the built-in chip component, a reinforcing insulating layer surrounding the outer peripheral side surface of the semiconductor element and the outer peripheral side surface of the chip component, An upper surface side insulating layer covering the upper surface of the semiconductor element and the upper surface of the chip component can be included.
- the reinforcing insulating layer can contain a reinforcing material such as glass cloth.
- a chip side via penetrating the peripheral insulating layer can be provided. This chip side via can be connected to the wiring on the upper surface side and the wiring on the lower surface side of the semiconductor element built-in substrate.
- the outer diameter of the chip side via can be made larger than the outer diameter of the through-chip via.
- power or ground can be transmitted to the thick chip side via, and a signal can be transmitted to the thin through-chip via.
- via diameter In comparison of the outer diameter of the vias (hereinafter referred to as “via diameter”), when the via diameter is different in the direction perpendicular to the substrate plane (the direction from the upper end of the via to the lower end), the via diameter of one via A is the other via B.
- the larger via diameter means that the smallest via diameter of via A is larger than the largest via diameter of via B.
- via cross section When the cross section along the substrate plane direction of the via (hereinafter referred to as “via cross section”) is a polygon (in the case of a prism) or an ellipse, the maximum outer diameter in the via cross section is the via diameter of the via (for example, For rectangles and squares, the length of the diagonal line; for ellipses, the length of the major axis).
- the plane area of the built-in chip component can be made larger than the plane area of the built-in semiconductor element.
- the planar area means a projected area on the substrate plane.
- a plurality of chip components may be incorporated, and in that case, the plurality of chip components can be arranged so as to surround the outer peripheral side surface of the semiconductor element to be incorporated.
- the planar shape of the semiconductor element is a square or a rectangle
- four chip components can be arranged on each side of the semiconductor element.
- four chip components having the same shape and the same size can be arranged on the diagonal lines of the semiconductor element.
- four chip components having the same shape and size can be arranged so as to face each side of the semiconductor element.
- the distance between the built-in chip component and the semiconductor element adjacent to the chip component can be set to, for example, 500 ⁇ m or less, preferably 100 ⁇ m or less, and more preferably 10 ⁇ m or less from the viewpoint of miniaturization.
- the distance between the chip component and the semiconductor element is preferably set to 1 ⁇ m or more.
- interval of a chip component and a semiconductor element means the shortest distance which connects both in the board
- the substrate with a built-in semiconductor element according to the present embodiment can have a protective insulating film that covers the upper surface side wiring, the protective insulating film has an opening, and an external terminal that is an exposed portion of the upper surface side wiring in the opening, Alternatively, an external terminal made of a conductive portion provided in this opening can be provided.
- the semiconductor element-embedded substrate according to the present embodiment can have a protective insulating film that covers the lower surface side wiring, and has an opening in the protective insulating film, and an external terminal consisting of an exposed portion of the lower surface side wiring in the opening, Alternatively, an external terminal made of a conductive portion provided in this opening can be provided.
- the semiconductor element built-in substrate according to the present embodiment can have a multilayer wiring structure including wirings and insulating layers alternately provided on the upper surface side of the substrate.
- the lowermost layer wiring of this multilayer wiring structure corresponds to the upper surface side wiring.
- an insulating layer having an opening is provided on the uppermost layer side of the multilayer wiring structure, and an external terminal composed of an exposed portion of the wiring in the opening or an external terminal composed of a conductive portion provided in the opening is provided. it can.
- the semiconductor element built-in substrate according to the present embodiment can have a multilayer wiring structure including wiring and insulating layers alternately provided on the lower surface side of the substrate.
- the wiring on the uppermost layer side of this multilayer wiring structure corresponds to the lower surface side wiring.
- an insulating layer having an opening is provided on the lowermost layer side of the multilayer wiring structure, and an external terminal composed of an exposed portion of the wiring in the opening or an external terminal composed of a conductive portion provided in the opening is provided. it can.
- the pitch of the terminals of the built-in semiconductor element and chip component can be made narrower than the pitch of the external terminals on both sides of the semiconductor element built-in substrate.
- a substrate with a built-in semiconductor element includes a semiconductor element (hereinafter, “IC chip”, for example, an LSI chip) that includes a semiconductor circuit (for example, an LSI circuit) and has terminals on one side, and a through-chip via ( Chip components (hereinafter “TSV chips”) having terminals connected to the TSVs on both sides.
- IC chip for example, an LSI chip
- TSV chips through-chip via
- This TSV chip can be handled as a “chip component having a via function”, and can be embedded in an insulating layer in the same manner as an IC chip.
- TSV chip can electrically connect the upper surface side wiring and the lower surface side wiring of the semiconductor element built-in substrate via the TSV in the chip, vias (hereinafter referred to as “hereinafter referred to as“ vias ”provided in the insulating layer on the side of the IC chip”). Chip side vias ”). As a result, the semiconductor element built-in substrate can be manufactured with a high yield.
- the TSV in this TSV chip can be reduced in pitch, increased in aspect ratio, and reduced in diameter as compared with a chip side via, a multi-pin, narrow pitch IC chip (for example, a CPU class LSI chip) ) Can be easily incorporated, and as a result, the electronic device can be reduced in size and thickness.
- a multi-pin, narrow pitch IC chip for example, a CPU class LSI chip
- the TSV chip can be arranged in a desired area around the IC chip, various sizes of TSVs can be arranged at a desired place. As a result, the degree of freedom in wiring design is increased, and a high-functional and high-performance semiconductor element-embedded substrate can be provided.
- the TSV chip By arranging the TSV chip around the IC chip, the stress from the side surface of the IC chip is reduced, and the warpage of the IC chip when the IC chip is thinned can be reduced.
- the TSV of the TSV chip can be easily increased in aspect ratio, it is not necessary to reduce the thickness of the built-in IC chip from the viewpoint of TSV formation, and the yield deterioration and warping due to the reduced handling property due to the thinner IC chip are eliminated. Reduced.
- an electrical characteristic such as a power supply characteristic is obtained by using a wiring structure in which a signal is transmitted through a small-diameter TSV and a power supply and a ground are transmitted through a large-diameter chip side via. Can be improved.
- the wiring distance from the IC chip terminal to the via area can be shortened, so that the signal characteristics can be improved.
- Semiconductor substrates (base materials) used for IC chips are, for example, silicon, germanium, gallium arsenide (GaAs), gallium arsenide phosphorus, gallium nitride (GaN), silicon carbide (SiC), zinc oxide (ZnO), and other compounds.
- a substrate made of a semiconductor (II-VI group compound, III-V group compound, VI group compound), diamond, or the like can be used, but is not limited thereto.
- a chip using a silicon substrate can be suitably used as the IC chip.
- the base material of the TSV chip it is preferable to use a semiconductor substrate of the same type as the semiconductor substrate used for the IC chip, from the viewpoint of reducing the difference in thermal expansion coefficient and reducing warpage. Moreover, it is preferable to use a material with high thermal conductivity from the viewpoint of heat dissipation, and a silicon material is particularly preferable.
- the TSV chip can be manufactured by applying a normal method for forming a via penetrating the semiconductor chip.
- a TSV chip can be formed as follows. First, a hole is formed on the upper surface side of the wafer (chip base material). Next, the hole is filled with a conductive material to form a plug. Thereafter, the lower surface of the wafer is ground and thinned so that the lower end of each plug is exposed. As a result, a plug penetrating the wafer, that is, a TSV is obtained. Then, by dicing this wafer, a chip (TSV chip) including TSV can be obtained.
- FIG. 1 is a cross-sectional view showing a substrate with a built-in semiconductor element according to a first embodiment of the present invention.
- a semiconductor element built-in substrate 23 includes an LSI chip 11 having a terminal 13 on the upper surface and a TSV chip 12 having a terminal 14 on the upper surface and a terminal 15 on the lower surface. 16 is covered.
- a wiring 18a is provided on the upper surface side of the semiconductor element built-in substrate, and a wiring 18b is provided on the lower surface side.
- the terminal 13 of the LSI chip is electrically connected to the wiring 18a on the upper surface side through the via 17a.
- the terminal 14 on the upper surface side of the TSV chip 12 is electrically connected to the wiring 18a on the upper surface side via the via 17b, and the terminal 15 on the lower surface side is electrically connected to the wiring 18b on the lower surface side via the via 17c.
- An LSI circuit (not shown) is provided on the upper surface side of the LSI chip 11.
- TSV through via
- FIG. 2 to 5 are plan views showing examples of the arrangement and planar shape of the built-in LSI chip 11 and TSV chip 12.
- LSI chips 11 and TSV chips 12 having the same shape and size are arranged side by side. Each chip can be arranged in a desired region, can be arranged with a high degree of design freedom and improved electrical characteristics. Further, as shown in FIG. 2, by making the size and shape of the LSI chip 11 and the TSV chip 12 the same, the mounting accuracy of each chip is improved and the cost can be reduced. When the planar shape of the chip is square, the mounting accuracy can be improved as compared with other shapes.
- the size of the LSI chip 11 is smaller than the size of the TSV chip 12.
- a semiconductor device-embedded substrate that can be constructed with an LSI chip suitable for the trend toward smaller chips due to miniaturization and a TSV chip suitable for the trend toward higher pins and higher density, and can be mounted at low cost and at high density.
- the size of the LSI chip 11 may be larger than the size of the TSV chip 12. In that case, a plurality of small-sized TSV chips can be arranged, and the degree of freedom in design can be increased.
- a plurality of TSV chips 12 are arranged around the LSI chip 11.
- the stress exerted on the LSI chip 11 from the insulating layer 16 around the LSI chip 11 can be reduced, and the warpage can be reduced.
- a material having higher thermal conductivity than the insulating layer 16 is disposed around the LSI chip 11, the heat dissipation characteristics of the semiconductor element built-in substrate 23 are improved.
- the planar shape of the TSV chip 12 and the LSI chip 11 can be a rectangle and a square, respectively.
- the terminal pitch of the TSV chip 12 can be loosened according to the length in the longitudinal direction, and the number of terminals arranged can be reduced. For example, it becomes easy to form a single row. As a result, a loose wiring rule can be applied to the wiring between the LSI chip 11 and the TSV chip 12, and the wiring yield can be improved.
- the upper surface side wiring and the lower surface side wiring are each one layer, but as shown in FIG. 6, the upper surface side wiring and the lower surface side wiring are each provided with two or more layers through the insulating layer 16d. It is good also as a structure.
- the upper and lower upper side wirings can be connected via vias 17d, and the upper and lower lower side wirings can be connected via vias 17e. In that case, the power supply characteristics and the ground characteristics can be improved as the number of wiring layers increases.
- the lower surface side wiring 18b of the semiconductor element-embedded substrate and the lower surface side terminal 15 of the TSV chip are connected via vias 17c, but as shown in FIG. It may be connected. In that case, the electrical connection with the wiring 18b is facilitated in the process of mounting the TSV chip, which is advantageous for cost reduction. On the other hand, as shown in FIG. 1, connection reliability is further improved when connecting vias without using solder balls or the like.
- the insulating layer covering the LSI chip 11 and the TSV chip 12 may have a laminated structure as shown in FIG.
- this insulating layer includes an insulating layer 16c that covers the lower surface side of the chip, a chip side insulating layer 16b that is provided on the chip and covers the periphery of the chip, and covers the upper surface side of the chip that is provided thereon.
- the insulating layer 16a is used. Warping can be reduced by forming the chip side insulating layer 16b with a highly rigid insulating resin including a reinforcing material such as glass cloth.
- Finer wiring can be formed by lowering the wiring formation surfaces of the upper and lower insulating layers 16a and 16c, and the built-in LSI chip 11 and TSV chip 12 can be made narrower and have more pins.
- This roughening can be performed by performing wet etching with a chemical solution or dry etching with plasma on the surface of the insulating layer. Or it can implement by pressing the member with a low roughening surface on the surface of an insulating layer, and transferring a low roughening surface.
- the chip is more firmly fixed on the adhesive layer, Reliability in cycle tests can be improved.
- the adhesive layer may be provided on either the LSI chip 11 or the TSV chip 12, but is preferably provided on both.
- the thickness (length in the direction perpendicular to the substrate plane) of the LSI chip 11 and the TSV chip 12 can be set according to a predetermined thickness of the semiconductor element built-in substrate.
- the thickness of each chip can be set to 50 to 100 ⁇ m.
- the size of one side is determined in terms of processing accuracy and the like.
- 0.2 mm or more preferably 1 mm or more, and preferably 15 mm or less, more preferably 12 mm or less from the viewpoint of miniaturization and the like.
- the circumference is preferably 0.8 mm or more, more preferably 4 mm or more, preferably 60 mm or less, and more preferably 50 mm or less.
- the number of LSI chips 11 and the number of TSV chips 12 are one each, but a plurality of them may be used.
- one LSI chip 11 and one TSV chip 12 are provided.
- the LSI chip 11 is provided with an LSI circuit.
- the TSV chip is not provided with an LSI circuit, and a TSV 24 is provided inside the silicon base material.
- TSV can be formed with a narrow pitch, a high aspect ratio, and a small diameter.
- the TSV 24 penetrates the silicon base material and conducts the terminal 14 on the upper surface side of the chip and the terminal 15 on the lower surface side.
- the outer diameter of TSV can be appropriately set in the range of 0.1 ⁇ m to 100 ⁇ m, for example. From the viewpoint of yield, it is preferably 1 ⁇ m or more, and more preferably 10 ⁇ m or more. From the viewpoint of the TSV accommodation rate, it is also possible to set it to 10 ⁇ m or less. Typically, for example, the outer diameter of TSV can be set to 10 to 50 ⁇ m, and the pitch can be set to 80 to 200 ⁇ m.
- the plane area of the TSV chip is preferably larger than the plane area of the LSI chip from the viewpoint of miniaturization of the LSI chip and the TSV accommodation rate.
- the planar area of the TSV chip can be appropriately set within a range of 2 to 100 times the planar area of the LSI chip. 10 times or more is preferable from the viewpoint of miniaturization of the LSI chip and the TSV accommodation rate, etc., and 50 times or less is preferable and 20 times or less is more preferable from the viewpoint of miniaturization and yield of the wiring board.
- a photosensitive or non-photosensitive organic material can be used as the material of the insulating layer.
- the organic material include an epoxy resin, an epoxy acrylate resin, a urethane acrylate resin, a polyester resin, a phenol resin, a polyimide resin, BCB (benzocycle), PBO (polybenzoxole), and polynorbornene resin.
- a material obtained by impregnating these organic materials into a reinforcing material such as a woven fabric or a non-woven fabric formed of glass cloth or aramid fiber can be used.
- an epoxy resin that is a non-photosensitive resin can be suitably used as the material of the insulating layer 16.
- Examples of materials for wiring, chip terminals, vias, and TSV include copper, silver, gold, nickel, aluminum, titanium, molybdenum, tungsten, and palladium, and one kind of metal selected from these, or selected from these.
- An alloy containing at least one kind as a main component can be used.
- copper is desirable from the viewpoint of electrical resistance and cost.
- copper can be suitably used as the material for the wiring, terminals, vias, and TSV.
- the semiconductor element-embedded substrate described above may be provided with a capacitor serving as a circuit noise filter at a desired position in each layer.
- the dielectric material constituting the capacitor include metal oxides such as titanium oxide, tantalum oxide, Al 2 O 3 , SiO 2 , ZrO 2 , HfO 2 , and Nb 2 O 5 ; BST (Ba x Sr 1-x TiO 3 ), PZT (PbZr x Ti 1 -x O 3) or PLZT (Pb 1-y La y Zr x Ti 1-x O 3) perovskite such material (0 ⁇ x ⁇ 1,0 ⁇ y ⁇ 1); A Bi-based layered compound such as SrBi 2 Ta 2 O 9 is preferred.
- a dielectric material constituting the capacitor an organic material mixed with an inorganic material or a magnetic material may be used. In addition to the LSI chip and the capacitor, discrete components may be provided.
- FIG. 10 is a cross-sectional view showing a substrate with a built-in semiconductor element according to a second embodiment of the present invention.
- chip side vias 21 for connecting the wirings 18a and 18b on the front and back of the semiconductor element built-in substrate 23 are provided in the insulating layer 16 on the side of the LSI chip 11 and the TSV chip 12. Except for this, it is the same as the first embodiment.
- FIG. 11 is a plan view showing an arrangement example of the built-in chips 11 and 12 and the chip side vias 21 in the semiconductor element built-in substrate according to the present embodiment.
- the chip side via 21 can be disposed in a desired area around the LSI chip 11 and the TSV chip 12.
- the chip side via 21 may be disposed between the LSI chip 11 and the TSV chip 12.
- the wirings 18 a and 18 b on the front and back sides of the semiconductor element built-in substrate 23 can be electrically connected.
- the heat dissipation characteristics are improved and the stress in the chip side surface direction (substrate plane direction) is reduced. It can be expected to reduce the warpage of the chip.
- the chip side via 21 and the TSV 24 can be electrically connected to the terminals of the LSI chip via the wiring on the upper surface side, respectively.
- Examples of the material of the chip side via 21 include copper, silver, gold, nickel, aluminum, titanium, molybdenum, tungsten, and palladium. One type of metal selected from these and at least one type selected from these are used. An alloy having a main component can be used. In particular, copper is desirable from the viewpoint of electrical resistance and cost. In the present embodiment, for example, copper can be suitably used as the material of the chip side via 21.
- the height of the chip side via 21 (the length in the direction perpendicular to the substrate plane) is higher than the height of the built-in LSI chip 11 and TSV chip 12, and can be set to 60 to 110 ⁇ m, for example.
- the outer diameter of the chip side via can be appropriately set within a range of 10 ⁇ m to 300 ⁇ m, for example. 50 ⁇ m or more is preferable from the viewpoint of yield, transmission of power and ground, etc., and 100 ⁇ m or more is more preferable, but 100 ⁇ m or less is preferable from the viewpoint of accommodation ratio of chip side vias.
- the outer diameter of the chip side via can be set to 50 to 100 ⁇ m, and the pitch can be set to 150 to 500 ⁇ m.
- the outer diameter of the chip side via can be set to about 2 to 100 times the outer diameter of the TSV, for example.
- the pitch and via diameter of the chip side vias 21 can be made larger than the pitch and via diameter of the TSV 24.
- a large-capacity power supply and ground can be transmitted through the large-diameter, slow-pitch chip side vias 21, and a multi-pin, fine-wiring signal can be transmitted through the small-diameter, narrow-pitch TSV24. it can.
- the electrical characteristics of the substrate with a built-in semiconductor element can be improved by properly using the chip side via and the TSV according to the application.
- FIGS. 12A to 12F are cross-sectional views showing an example of a manufacturing method of a semiconductor element built-in substrate in the order of steps. With this manufacturing method, the semiconductor element-embedded substrate shown in FIG. 8 can be manufactured.
- an insulating layer 16c is formed on the support 22.
- the support 22 is preferably a highly rigid material. It is preferable that a position mark for mounting the LSI chip 11 and the TSV chip 12 is provided on the support 22. As long as the position mark can be recognized with high accuracy through the insulating layer 16c and functions as a position mark, even a metal portion provided on the support 22 is a recess provided by wet etching or machining. There may be.
- a copper plate having a thickness of 0.5 mm can be used as the support 22 and an epoxy resin layer having a thickness of 20 to 50 ⁇ m can be provided as the insulating layer 16c.
- a nickel film can be formed on the support 22 by electrolytic plating. Can be formed.
- the LSI chip 11 is mounted on the insulating layer 16c on the support 22 with the surface having the terminals 13 facing up with reference to the position mark. Then, the TSV chip 12 is mounted in the same manner. At this time, it is desirable that there is an adhesive layer between the LSI chip 11 and the insulating layer 16c, and between the TSV chip 12 and the insulating layer 16c, but the insulating layer 16c is made of uncured resin without providing an adhesive layer.
- the upper surface can be used as an adhesive surface.
- an insulating layer 16b that covers the periphery of the side surfaces of the LSI chip 11 and the TSV chip 12 is formed, and then, as shown in FIG. 12D, insulation that covers the upper surfaces of these chips is formed.
- Layer 16a is formed.
- the insulating layer 16b can include a reinforcing material such as a glass cloth, and can be prepared on the support 22 by providing an opening that can accommodate a chip.
- a film-like insulating material may be provided so as to collectively cover the upper surface and the side of the LSI chip 11 and the TSV chip 12.
- the insulating layer 16 covering the upper surface, side surfaces and lower surface of these chips can be formed as shown in FIG.
- the semiconductor element-embedded substrate shown in FIG. 9 can be formed. At that time, the vias 17c and the wirings 18b on the lower surface side can be provided after the support substrate is removed.
- the insulating layer can be formed using a transfer molding method, compression molding method, printing method, vacuum press, vacuum lamination, spin coating method, die coating method, curtain coating method, or the like.
- a transfer molding method compression molding method, printing method, vacuum press, vacuum lamination, spin coating method, die coating method, curtain coating method, or the like.
- a vacuum pressing method, a vacuum laminating method, or the like can be used.
- a liquid resin is used, a molding method, a coating method, or the like can be used.
- the insulating layers 16a and 16b can be laminated by vacuum lamination using an epoxy resin film as the insulating resin.
- the support 22 is removed.
- the support 22 can be removed using a technique such as wet etching, dry etching, physical peeling, and polishing.
- a support made of a copper plate can be easily removed by wet etching.
- vias 17a connected to the terminals 13 of the LSI chip 11 and vias 17b and 17c connected to the terminals 14 and 15 of the TSV chip 12 are provided, and the upper surface side is provided.
- the wiring 18a and the lower surface side wiring 18b are formed.
- the via hole can be formed by photolithography when the insulating layer forming the via hole is made of a photosensitive material.
- the via hole can be formed by a laser processing method, a dry etching method, or a blast method. In this production example, via holes are formed by laser processing, for example.
- the via hole is filled with the metal material, and a via connected to the terminal of the chip is formed.
- electrolytic plating, electroless plating, a printing method, a molten metal suction method, or the like can be used as a method for filling the via hole with the metal material.
- a metal post for energization is provided in advance on the terminals of these chips, and after forming an insulating layer covering these metal posts, the surface of the insulating layer is scraped off by polishing or the like. Vias may be formed by exposing the surface of the post.
- the wiring 18a can be connected to the terminals of these chips without vias.
- Wirings 18a and 18b can be formed by a subtractive method, a semi-additive method, a full additive method, or the like.
- the subtractive method is a method in which a resist having a desired pattern is formed on a copper foil provided on a substrate, an unnecessary copper foil is etched, and then the resist is removed to obtain a desired pattern.
- a power supply layer is formed by an electroless plating method, a sputtering method, a CVD (chemical vapor deposition) method, etc., a resist having an opening in a desired pattern is formed, and a metal by electrolytic plating is formed in the resist opening.
- the power feeding layer is etched to obtain a desired wiring pattern.
- a pattern is formed with a resist, and the catalyst is activated while leaving the resist as an insulating film.
- a desired wiring pattern is obtained by precipitating a metal.
- the wiring material the above metal materials can be used, and copper is particularly preferable from the viewpoint of electric resistance and cost.
- a protective insulating film (not shown) made of a solder resist or the like having an opening through which a part of the wiring is exposed is provided on the upper surface side of the obtained semiconductor element-embedded substrate. It can be used as an external terminal.
- a bump may be formed by providing a conductive material in the opening.
- a protective insulating film (not shown) made of a solder resist or the like having an opening through which a part of the wiring is exposed is provided on the lower surface side of the obtained substrate with a built-in semiconductor element. Can be used as A bump may be formed by providing a conductive material in the opening.
- a multilayer wiring structure may be provided by alternately providing insulating layers and wirings on the upper surface side of the obtained semiconductor element-embedded substrate.
- a multilayer wiring structure may be provided by alternately providing insulating layers and wirings on the lower surface side of the obtained semiconductor element-embedded substrate. In this way, for example, the structure shown in FIG. 6 can be obtained.
- FIG. 6 in each multilayer wiring structure, there are two wiring layers and one insulating layer, but three or more wiring layers and two or more insulating layers can be provided.
- a protective insulating film such as a solder resist having an opening exposing a part of the wiring on the uppermost layer side of the multilayer wiring structure is provided on the upper surface side, and the exposed portion of the wiring in this opening is used as an external terminal.
- a bump may be formed by providing a conductive material in the opening.
- a protective insulating film such as a solder resist having an opening through which a part of the wiring on the lowermost layer side of the multilayer wiring structure is exposed is provided on the lower surface side, and the exposed portion of the wiring in this opening may be used as an external terminal. Good.
- a bump may be formed by providing a conductive material in the opening.
- FIGS. 13A to 13E are cross-sectional views showing another example of a method of manufacturing a semiconductor element embedded substrate in the order of steps.
- a multilayer wiring structure including wiring 18b, via 17e, and insulating layer 16d is formed on the support 22.
- the LSI chip 11 is mounted on the multilayer wiring structure on the support 22 via the adhesive layer 20.
- the TSV chip 12 is mounted such that the terminal 15 on the lower surface side of the chip is connected to a predetermined conductive portion on the upper surface of the multilayer wiring structure via the solder ball 19. Since the lower surface side electrical connection is performed in the chip mounting process, the lower surface side via forming step is not required, and the manufacturing can be performed at low cost.
- an insulating layer 16 that covers the upper and side surfaces of these chips is formed.
- a via 17a connected to the terminal 13 of the LSI chip 11 and a via 17b connected to the terminal 14 of the TSV chip 12 are provided.
- a multilayer wiring structure including the upper surface side wiring 18a, the insulating layer 16d, and the via 17d electrically connected to these vias is formed.
- the support 22 is removed.
- a barrier conductive film made of a material having a different etching rate from that of the support is formed between the wiring and the support.
- the support can be selectively removed by wet etching. If the removal accuracy of the support is within a desired range, the support may be removed by dry etching or polishing without forming the barrier conductive film.
- a solder resist 16e having an opening through which a part of the wiring on the uppermost layer side of the multilayer wiring structure on the upper surface side is exposed is provided.
- the exposed portion of the wiring in this opening can be used as an external terminal.
- a bump may be formed by providing a conductive material in the opening.
- a solder resist 16e having an opening through which a part of the wiring on the lowermost layer side of the multilayer wiring structure on the lower surface side is exposed is provided.
- the exposed portion of the wiring in this opening can be used as an external terminal.
- a bump may be formed by providing a conductive material in the opening.
- the semiconductor element built-in substrate can be efficiently manufactured.
- FIGS. 14A to 14E are cross-sectional views showing another example of a method of manufacturing a semiconductor element embedded substrate in the order of steps.
- a semiconductor element-embedded substrate provided with chip side vias 21 penetrating the insulating layers 16a, 16b and 16c can be manufactured.
- This manufacturing example can be carried out in the same manner as in Manufacturing Example 1 except that the chip side via 21 is formed in the side of the LSI chip 11 and the TSV chip 12 so as to penetrate the insulating layers 16a, 16b and 16c.
- chip side vias 21 penetrating the insulating layers 16a, 16b and 16c around the LSI chip 11 and the TSV chip 12 are formed.
- the chip side via 21 can be formed by photolithography when these insulating layers are made of a photosensitive material.
- the via hole can be formed by a laser processing method, a dry etching method, or a blast method. In this production example, via holes are formed by laser processing, for example.
- the metal material is filled in the via hole to form a chip side via.
- electrolytic plating As a method for filling the via hole with the metal material, electrolytic plating, electroless plating, a printing method, a molten metal suction method, or the like can be used. In this manufacturing example, for example, it is formed using electrolytic plating.
- the vias 17b connected to the terminals 14 of the TSV chip 12 are formed, then the vias 17c connected to the terminals 15 on the lower surface side of the TSV chip 12 are formed, and the upper surface side wiring 18a and the lower surface side wiring 18b are formed.
- the chip side via 21 may be formed simultaneously with the formation of the vias 17a and 17b on the upper surface side of the chip.
- the step of scraping the insulating layer surface covering these metal posts to expose the metal post surface is performed after the chip side vias 21 are formed. You may go or you may go before.
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Abstract
Description
半導体素子を内蔵する配線基板であって、
前記配線基板は、
前記半導体素子と、
チップ部品と、
該半導体素子および該チップ部品の少なくとも外周側面を覆う周辺絶縁層と、
当該配線基板の上面側に設けられた上面側配線と、
当該配線基板の下面側に設けられた下面側配線とを含み、
前記半導体素子は、その上面側に端子を有し、該端子は前記上面側配線と電気的に接続され、
前記チップ部品は、
前記上面側配線と電気的に接続する上面側端子と、
前記下面側配線と電気的に接続する下面側端子と、
当該チップ部品を貫通し、該上面側端子と該下面側端子とを接続するチップ貫通ビアとを有する、半導体素子内蔵基板が提供される。
半導体素子を内蔵する配線基板の製造方法であって、
支持体上に、上面側に端子を有する半導体素子をその下面を支持体側に向けて搭載する工程と、
前記支持体上に、上面側および下面側に端子を有するチップ部品を搭載する工程と、
前記半導体素子および前記チップ部品を覆う周辺絶縁層を形成する工程と、
前記支持体を除去する工程と、
前記チップ部品の下面側端子に電気的に接続する第1配線を形成する工程と、
前記半導体素子の端子および前記チップ部品の上面側端子に電気的に接続する第2配線を形成する工程を含み、
前記チップ部品は、当該チップ部品を貫通し、前記上面側端子と前記下面側端子とを接続するチップ貫通ビアを有している、製造方法が提供される。
半導体素子を内蔵する配線基板の製造方法であって、
支持体上に、少なくとも第1配線を形成する工程と、
前記支持体上に、上面側に端子を有する半導体素子をその下面を支持体側に向けて搭載する工程と、
前記支持体上に、上面側および下面側に端子を有するチップ部品を、該下面側の端子が前記第1配線に電気的に接続するように搭載する工程と、
前記半導体素子および前記チップ部品を覆う周辺絶縁層を形成する工程と、
前記支持体を除去する工程と、
前記半導体素子の端子および前記チップ部品の上面側端子に電気的に接続する第2配線を形成する工程を含み、
前記チップ部品は、当該チップ部品を貫通し、前記上面側端子と前記下面側端子とを接続するチップ貫通ビアを有している、製造方法が提供される。
図1は、本発明の第1の実施形態の半導体素子内蔵基板を示す断面図である。
図10は、本発明の第2の実施形態の半導体素子内蔵基板を示す断面図である。本実施形態の半導体素子内蔵基板は、LSIチップ11とTSVチップ12の側方の絶縁層16に、半導体素子内蔵基板23の表裏の配線18a、18bを接続するチップ側方ビア21が設けられている以外は第1の実施形態と同様である。
図12(a)から(f)は、半導体素子内蔵基板の製造方法の一例を工程順に示す断面図である。この製造方法により、図8に示す半導体素子内蔵基板を製造することができる。
図13(a)から(e)は、半導体素子内蔵基板の製造方法の他の例を工程順に示す断面図である。
図14(a)から(e)は、半導体素子内蔵基板の製造方法の他の例を工程順に示す断面図である。この製造方法により、図8に示す構造において、絶縁層16a、16b及び16cを貫通するチップ側方ビア21が設けられた半導体素子内蔵基板を製造することができる。
12 TSVチップ
13 端子
14 端子
15 端子
16、16a、16b、16c、16d 絶縁層
16e ソルダーレジスト
17a、17b、17c、17d、17e ビア
18a、18b 配線
19 半田ボール
20 接着層
21 チップ側方ビア
22 支持体
23 半導体素子内蔵基板
24 TSV
Claims (24)
- 半導体素子を内蔵する配線基板であって、
前記配線基板は、
前記半導体素子と、
チップ部品と、
該半導体素子および該チップ部品の少なくとも外周側面を覆う周辺絶縁層と、
当該配線基板の上面側に設けられた上面側配線と、
当該配線基板の下面側に設けられた下面側配線とを含み、
前記半導体素子は、その上面側に端子を有し、該端子は前記上面側配線と電気的に接続され、
前記チップ部品は、
前記上面側配線と電気的に接続する上面側端子と、
前記下面側配線と電気的に接続する下面側端子と、
当該チップ部品を貫通し、該上面側端子と該下面側端子とを接続するチップ貫通ビアとを有する、半導体素子内蔵基板。 - 前記半導体素子は、半導体回路を有する半導体チップであり、
前記チップ部品は、半導体回路を有しない半導体チップである、請求項1に記載の半導体素子内蔵基板。 - 前記チップ部品の平面面積が、前記半導体素子の平面面積より大きい、請求項1又は2に記載の半導体素子内蔵基板。
- 複数の前記チップ部品が、前記半導体素子の外周側面を囲むように配置されている、請求項1から3のいずれか一項に記載の半導体素子内蔵基板。
- 前記半導体素子の端子は、ビアを介して前記上面側配線に接続され、
前記チップ部品の上面側端子は、ビアを介して前記上面側配線と接続され、
前記チップ部品の下面側端子は、ビアを介して前記下面側配線と接続されている、請求項1から4のいずれか一項に記載の半導体素子内蔵基板。 - 前記半導体素子の端子は、ビアを介して前記上面側配線に接続され、
前記チップ部品の上面側端子は、ビアを介して前記上面側配線と接続され、
前記チップ部品の下面側端子は、半田部材を介して前記下面側配線と接続されている、請求項1から4のいずれか一項に記載の半導体素子内蔵基板。 - 前記周辺絶縁層は、前記半導体素子の下面および前記チップ部品の下面を覆う下面側絶縁層と、該半導体素子の外周側面および該チップ部品の外周側面を取り囲む補強絶縁層と、該半導体素子の上面および該チップ部品の上面を覆う上面側絶縁層を含む、請求項1から6のいずれか一項に記載の半導体素子内蔵基板。
- 前記半導体素子および前記チップ部品の周囲の領域に、前記周辺絶縁層を貫通するチップ側方ビアが設けられている、請求項1から7のいずれか一項に記載の半導体素子内蔵基板。
- 前記チップ側方ビアの外径は、前記チップ貫通ビアの外径より大きい、請求項8に記載の半導体素子内蔵基板。
- 前記チップ側方ビアには電源またはグランドが伝送され、前記チップ貫通ビアには信号が伝送される、請求項9に記載の半導体素子内蔵基板。
- 前記上面側配線を覆う保護絶縁膜を有し、
該保護絶縁膜は開口を有し、該開口内の該上面側配線の露出部からなる外部端子、または該開口に設けられた導電部からなる外部端子を備えた、請求項1から10のいずれか一項に記載の半導体素子内蔵基板。 - 前記配線基板の上面側に交互に設けられた配線と絶縁層を含む多層配線構造を有する、請求項1から10のいずれか一項に記載の半導体素子内蔵基板。
- 前記上面側の多層配線構造の最上層側に開口をもつ絶縁層を有し、該開口内の配線の露出部からなる外部端子、または該開口に設けられた導電部からなる外部端子を備えた、請求項12に記載の半導体素子内蔵基板。
- 前記配線基板の下面側に交互に設けられた配線と絶縁層を含む多層配線構造を有する、請求項1から13のいずれか一項に記載の半導体素子内蔵基板。
- 前記下面側の多層配線構造の最下層側に開口をもつ絶縁層を有し、該開口内の配線の露出部からなる外部端子、または該開口に設けられた導電部からなる外部端子を備えた、請求項14に記載の半導体素子内蔵基板。
- 前記下面側配線を覆う保護絶縁膜を有し、
前記保護絶縁膜は開口を有し、該開口内の前記下面側配線の露出部からなる外部端子、または該開口に設けられた導電部からなる外部端子を備えた、請求項1から13のいずれか一項に記載の半導体素子内蔵基板。 - 半導体素子を内蔵する配線基板の製造方法であって、
支持体上に、上面側に端子を有する半導体素子をその下面を支持体側に向けて搭載する工程と、
前記支持体上に、上面側および下面側に端子を有するチップ部品を搭載する工程と、
前記半導体素子および前記チップ部品を覆う周辺絶縁層を形成する工程と、
前記支持体を除去する工程と、
前記チップ部品の下面側端子に電気的に接続する第1配線を形成する工程と、
前記半導体素子の端子および前記チップ部品の上面側端子に電気的に接続する第2配線を形成する工程を含み、
前記チップ部品は、当該チップ部品を貫通し、前記上面側端子と前記下面側端子とを接続するチップ貫通ビアを有している、製造方法。 - 前記支持体上に下地絶縁層を形成する工程をさらに含み、該下地絶縁層上に、前記半導体素子および前記チップ部品を搭載する請求項17に記載の製造方法。
- 前記半導体素子および前記チップ部品は、それぞれ接着層を介して搭載される、請求項17又は18に記載の製造方法。
- 半導体素子を内蔵する配線基板の製造方法であって、
支持体上に、少なくとも第1配線を形成する工程と、
前記支持体上に、上面側に端子を有する半導体素子をその下面を支持体側に向けて搭載する工程と、
前記支持体上に、上面側および下面側に端子を有するチップ部品を、該下面側の端子が前記第1配線に電気的に接続するように搭載する工程と、
前記半導体素子および前記チップ部品を覆う周辺絶縁層を形成する工程と、
前記支持体を除去する工程と、
前記半導体素子の端子および前記チップ部品の上面側端子に電気的に接続する第2配線を形成する工程を含み、
前記チップ部品は、当該チップ部品を貫通し、前記上面側端子と前記下面側端子とを接続するチップ貫通ビアを有している、製造方法。 - 前記第1配線を形成する工程において、該第1配線を最上層側の配線として含み、前記支持体上に交互に設けられた配線および絶縁層を含む多層配線構造を形成し、
該多層配線構造上に前記半導体素子および前記チップ部品が搭載され、
該チップ部品の下面側の端子が該第1配線に電気的に接続される、請求項20に記載の製造方法。 - 前記チップ部品の下面側端子は、半田部材を介して前記第1配線に接続される、請求項20又は21に記載の製造方法。
- 前記周辺絶縁層は、前記半導体素子および前記チップ部品の外周側面を取り囲む第1絶縁層と、前記半導体素子および前記チップ部品の上面を覆う第2絶縁層を含む、請求項17から22のいずれか一項に記載の製造方法。
- 前記第1絶縁層は補強材を含む、請求項23に記載の製造方法。
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US8810008B2 (en) | 2014-08-19 |
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