CN107785358A - 半导体管芯封装及生产这种封装的方法 - Google Patents

半导体管芯封装及生产这种封装的方法 Download PDF

Info

Publication number
CN107785358A
CN107785358A CN201710735129.0A CN201710735129A CN107785358A CN 107785358 A CN107785358 A CN 107785358A CN 201710735129 A CN201710735129 A CN 201710735129A CN 107785358 A CN107785358 A CN 107785358A
Authority
CN
China
Prior art keywords
contact
tsv
lateral connection
die
rdl
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201710735129.0A
Other languages
English (en)
Other versions
CN107785358B (zh
Inventor
E·贝内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Interuniversitair Microelektronica Centrum vzw IMEC
Original Assignee
Interuniversitair Microelektronica Centrum vzw IMEC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Interuniversitair Microelektronica Centrum vzw IMEC filed Critical Interuniversitair Microelektronica Centrum vzw IMEC
Publication of CN107785358A publication Critical patent/CN107785358A/zh
Application granted granted Critical
Publication of CN107785358B publication Critical patent/CN107785358B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/36—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of semiconductors, not otherwise provided for
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/08235—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bonding area connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73209—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80003—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/80006—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92124—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1436—Dynamic random-access memory [DRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明涉及包括嵌入在用已知的FO‑WLP或eWLB技术可获得的重构晶片中的第一管芯的一种封装。除了第一管芯以外，穿基板通孔插入件被嵌入在晶片中，TSV插入件是分开的元件，可能是具有将插入件的前侧和背侧上的各触点互连的金属填充通孔的硅管芯。第二管芯被安装在基板的背侧，其中第二管芯上的触点与基板的背侧上的TSV插入件的触点电连接。在基板的前侧上安装了横向连接设备，其将基板的前侧上的TSV插入件的各触点与第一管芯的前侧上的各触点互连。因此，横向连接设备和TSV插入件有效地将第一和第二管芯上的各触点互连。优选地，如从FO‑WLP技术中已知的，横向连接设备被安装在基板的前侧上的再分布层上。

Description

半导体管芯封装及生产这种封装的方法
技术领域
本发明涉及半导体处理，尤其涉及多个集成电路管芯在3D互连的封装中的集成。
背景技术
集成电路设备(也称为半导体芯片或管芯)的3D集成近年来已经经历了许多发展。具体而言，具有大量管芯到管芯互连的两个或更多个管芯的集成在封装尺寸和散热问题方面已成为挑战。传统的PoP(Package-on-Package(封装层叠))方法涉及将两个管芯(例如移动应用中的应用处理器和存储器芯片)封装在分开的球栅阵列型封装中，并将一个封装组装在另一个之上。所产生的封装高度可能是有问题的，并且封装级焊球不允许以例如根据宽I/O标准实现集成所要求的小间距来实现大量互连。
已被提出的一种改进是针对底部管芯使用嵌入式管芯封装或晶片级重构管芯封装。嵌入式管芯封装将硅管芯嵌入在层压PCB中。重构的封装使用晶片级成型技术来重构晶片或面板形基板，这允许薄膜封装级互连在再分布层(RDL)中的创建。该技术被称为扇出晶片级封装(FO-WLP)或者eWLB(即嵌入式晶片级球栅阵列)，例如在文档“Next generationeWLB packaging(下一代eWLB封装)”(Yonggang Jin等，电子封装技术会议(EPTC)纪要，2010)中所解说的。
为了实现封装层叠解决方案，FO-WLP方法要求将封装的前侧连接到背侧的垂直穿封装(through-package)互连。这可以通过激光钻孔以及用Cu或焊料填充孔来完成以产生穿封装通孔(TPV)。另一种技术在管芯嵌入之前使用铜柱的电镀。然而，可获得的TPV间距相当有限(例如，TPV到TPV间距不小于几百μm)。
为了实现(诸如宽I/O DRAM存储器所需的)高带宽技术(其由间距为40μm的4组6x73接触焊盘组成)，要求高得多的穿封装互连密度。
这可以通过使用逻辑管芯中的穿Si通孔将宽I/O DRAM直接堆叠在逻辑管芯上来实现。然而，这要求在逻辑管芯中的TSV(穿硅通孔，或更一般而言，穿基板通孔)。此外，逻辑管芯和DRAM管芯之间的热耦合相当高。不同的解决方案是使用硅中介层以实现使用高密度硅技术的高密度互连。这允许管芯的横向放置(即并排在中介层上)。然而，封装构造变得相当昂贵。一种替代解决方案是移除封装基板并将封装实现为晶片级管芯规模封装(CSP)。然而，这些解决方案不允许逻辑管芯的独立封装和简单测试。
发明概述
本发明涉及如所附权利要求公开的一种半导体管芯封装及用于生产该封装的方法。根据本发明的封装包括嵌入在用上面提到的已知的FO-WLP或eWLB技术可获得的重构晶片中的第一管芯。除了第一管芯以外，毗邻该第一管芯放置的穿基板通孔插入件被嵌入在晶片中，TSV插入件是分开的元件，可能是具有将插入件的前侧和背侧上的触点互连的金属填充通孔的硅管芯。第二管芯被安装在基板的背侧，其中第二管芯上的触点与基板的背侧上的TSV插入件的触点电连接。在第一管芯和TSV插入件的前侧上安装了横向连接设备，其将基板的前侧上的TSV插入件的触点与第一管芯的前侧上的触点互连。因此，横向连接设备和TSV插入件有效地将第一和第二管芯上的触点互连。根据一实施例，如从FO-WLP技术中已知的，横向连接设备被安装在基板的前侧上的再分布层(RDL)上。封装级焊球被提供在如已知的封装中的RDL上，并且可能在横向连接设备的位置处被中断。根据另一实施例，横向连接设备同样被嵌入在重构晶片中。
根据本发明的封装的优点之一在于，第一管芯的测试可在安装第二管芯之前被执行。此外，取决于第二管芯上的触点的位置，第二管芯在许多情况下可被放置成与第一管芯重叠。当重叠可能时，这与传统的中介层解决方案相比减少了总体封装尺寸以及互连长度。TSV插入件和横向连接设备可通过应用如将在详细描述中解释的已知的中介层技术来产生。这允许昂贵的中介层技术被限于较小的管芯，从而导致与现有技术相比的成本降低。
具体而言，本发明涉及半导体管芯封装，包括：
·由模具材料形成的基板，其中在所述模具材料中并排嵌入的是第一半导体管芯和穿基板通孔(TSV)插入件，基板、TSV插入件和第一管芯具有前侧和背侧，并且其中
·TSV插入件包括插入件的前侧上的N个触点、插入件的背侧上的N个触点以及分别将插入件的前侧和背侧上的所述触点互连的N个金属填充的通孔，N是大于或等于1的整数，
·第一管芯包括在第一管芯的前侧上的N个触点，
·第一管芯还包括在第一管芯的前侧上的一个或多个接触端子，
·被安装在基板的背侧上的第二半导体管芯，该第二半导体管芯包括N个触点，该N个触点被分别连接到TSV插入件在插入件的背侧上的N个触点，
·被安装在第一管芯和TSV插入件的前侧上的横向连接设备，该横向连接设备设置有第一和第二组的N个触点，这些组各自被并排放置在横向连接设备的同一表面上，其中第一和第二组的N个触点在横向连接设备内部分别被互连，并且其中横向连接设备上的第一和第二组的N个触点分别被相应地连接到第一管芯上的N个触点以及TSV插入件的在插入件的前侧上的N个触点，使得第一管芯上的N个触点通过横向连接设备和TSV插入件分别被连接到第二管芯上的N个触点，
·被连接到第一管芯上的至少一些接触端子的多个封装级接触凸块。
根据一实施例，横向连接设备在基板的外部且被安装在基板的前侧。在后一种情况下，封装还可包括在基板的前侧上的再分布层(RDL)，其中封装级接触凸块被安装在所述RDL的外表面上，并通过RDL内的导体被连接到第一管芯的接触端子，并且其中横向连接设备同样被安装在RDL的外表面上。
RDL可包括将第一管芯上的N个触点连接到RDL的外表面上的第一组的N个对应触点的导体，RDL还包括将TSV插入件的前侧上的N个触点连接到RDL的外表面上的第二组的N个对应触点的导体，并且其中横向连接设备上的第一和第二组的N个触点分别被相应地接合到RDL上的第一和第二组的触点。
根据本发明的一实施例，横向连接设备被直接接合到第一半导体管芯和TSV插入件的前侧。在后一种情况下，横向连接设备可同样被嵌入在基板的模具材料中。仍然在后一种情况下，无论横向连接设备是否被嵌入在模具材料中，第一管芯的接触端子都可以是接触柱，其高度足够用于从前侧接触第一管芯，而不管横向连接设备的存在。
在后一实施例中，封装可包括在基板的前侧上的再分布层(RDL)，其中封装级接触凸块被安装在所述RDL的外表面上，并通过RDL内的导体被连接到第一管芯的接触柱。所述RDL可以与横向连接设备的背侧直接物理接触，或者在RDL与横向连接设备的背侧之间可存在一层模具材料。
根据本发明的包括RDL的封装还可包括被安装在基板的背侧上的一个或多个附加的半导体管芯，每个附加的管芯通过附加的TSV插入件被连接到基板的前侧，并且其中附加的TSV插入件通过RDL内的导体被连接到第一半导体管芯。
根据一实施例，横向连接设备包括半导体基板和线路部分的后端，并且横向连接设备的第一和第二组的触点之间的互连通过所述线路部分的后端中的电路来被建立。
根据一实施例，第一半导体管芯是逻辑管芯，而第二半导体管芯是存储器管芯，其中第一和第二管芯上的N个触点被形成为致密的I/O触点阵列。
根据一实施例，第二半导体管芯上的N个触点被直接接合到TSV插入件的背侧上的N个触点。
附图说明
各附图是解说本发明的示意图，且未按比例绘制。
图1示出了根据本发明的一个实施例的半导体管芯封装。
图2a至2h例示了用于生产图1的封装的优选方法步骤。
图3例示了根据本发明的包括附加的管芯的封装的一个实施例。
图4例示了根据另一实施例的半导体封装。
图5a至5j示出了适用于生产图4所示封装的方法步骤。
图6示出了带有附加的管芯和附加的图4的TSV插入件的封装。
图7示出了根据本发明的封装的替代实施例。
具体实施方式
图1所示的封装包括具有互连的I/O触点阵列7/8的逻辑管芯1和存储器管芯15。例如，存储器管芯15可以是根据宽I/O标准配置的DRAM管芯。两个触点阵列7和8在这种情况下均根据该标准来被配置，即每个阵列包括间距为40μm的4组6x73接触焊盘。然而，本发明不限于这样的设备，并且图1的实施例应被理解成仅仅例示了本发明的典型应用领域。逻辑管芯1被嵌入在由模具材料形成的基板2中，并且在该基板的前侧上包括再分布层(RDL)3。封装级焊球4被安装在设置在RDL 3的表面上的接触焊盘5上，以用于通过被包含在RDL 3中的电路(未示出)来建立到在逻辑管芯1的前侧上设置的接触端子6的连接。逻辑管芯1的前侧还设置有I/O触点阵列7，这些I/O触点被分别连接到安装在基板2的背侧上的存储器管芯15上的对应的I/O触点阵列8，“分别”意指一个阵列的每个触点均被连接到另一阵列的对应的触点(贯穿本说明书，该“分别”的定义是有效的)。除了逻辑管芯1以外，毗邻所述管芯的穿基板通孔(TSV)插入件16被嵌入在基板2的模具材料中。TSV插入件16可以是包括多个金属填充的通孔17的硅管芯，这些金属填充的通孔将插入件16的背侧上的触点阵列11连接到插入件16的前侧上的对应的触点阵列12。当插入件16被嵌入在基板材料中时，插入件16的前侧和背侧与基板2的前侧和背侧重合。通孔17的数量对应于逻辑管芯1上的I/O触点7的数量，并且对应于存储器管芯15上的I/O触点8的数量。
存储器管芯15上的I/O触点8被直接接合到TSV插入件16的背侧上的触点11。在RDL3的前侧上安装有横向连接设备18。横向连接设备18包括在该横向连接设备18的相同表面上的两个触点阵列19/20，每个阵列具有与逻辑管芯1和存储器管芯15上的阵列7和8相同数量的触点。第一阵列的触点19通过设置在横向连接设备18中的电路来被分别连接到第二阵列的对应的触点20。此外，第一阵列的触点19还通过设置在RDL 3中的电路，优选地通过垂直导体9来被分别连接到逻辑管芯1上的I/O触点7。同样地，第二阵列的触点20通过设置在RDL 3中的电路，优选地通过垂直连接9'来被分别连接到TSV插入件16的前侧上的触点12。这些垂直连接9/9'被示意性地绘制成线，但是它们可以根据已知技术来被实践。优选地，垂直连接9/9'由在RDL互连堆叠中设计的一系列通孔和焊盘连接组成。典型的实现是堆叠的通孔连接(所有通孔和焊盘都与互连焊盘印痕对齐)或者阶梯通孔连接(通孔不在彼此之上对齐，而是相对于彼此稍微偏移)。横向连接设备18和TSV插入件16由此在逻辑管芯1以及存储管芯15的I/O触点7和8之间建立单独的连接。存储器管芯15由第二层的模具材料21保护。
横向连接设备18可以是包括多个线层(例如电源/接地参考层和单个高密度互连层)的后端的硅管芯，以用于在横向连接设备上实现第一和第二触点阵列19和20之间的连接。
图2例示了用于生产图1的封装的优选方法步骤。该过程在晶片级(即，在包括多个逻辑管芯1的晶片上)被执行。逻辑管芯1首先通过粘合剂层26来被附接到临时载体晶片25(图2a)。在这之后，TSV插入件16被放置成与逻辑管芯1相邻(图2b)。逻辑管芯1的高度与TSV插入件16的高度基本相同。逻辑管芯1和插入件16接着优选地通过上述扇出晶片级封装技术领域中本身已知的压缩模制技术来被嵌入在模具材料2'中(图2c)。载体晶片25和粘合剂层26的类型也可以根据FO-WLP中已知的技术。模具材料还优选地是通常被应用于FO-WLP的材料。这样的模具材料通常由与大体积分数的无机材料(通常为小的二氧化硅颗粒)混合的热固性聚合物材料组成，以控制模具材料的机械属性(热膨胀系数和弹性模量)。在模具材料的设置之后，该材料通过合适的减薄技术(优选通过研磨)在逻辑管芯1和插入件16的水平面上被移除，在这之后，载体25和粘合剂层26通过剥离来被移除，从而产生由具有嵌入其中的逻辑管芯1和TSV插入件16的模具材料组成的重构基板2，如图2d所示。
在翻转基板之后，再分布层3同样根据被应用于FO-WLP中的已知技术来被应用(图2e)，优选地应用薄膜技术以用于产生将逻辑管芯1上的接触端子6连接到RDL 3的上表面上的接触焊盘5的线型互连级别的一个或多个后端，其中封装级焊球4被产生在该上表面上，例如这可以是球栅阵列(BGA)或芯片规模封装(CSP)型接触结构。RDL 3通常包括在厚度、宽度和间距方面相对较大的线几何形状。典型的线宽和间距约为5μm的数量级，通过应用最先进的技术下降到约2μm。RDL 3还包括在逻辑管芯1上的I/O触点阵列7和RDL 3的表面上的第一触点阵列27之间的单独连接9，以及在TSV插入件16的前侧的触点阵列12和RDL 3的表面上的第二触点阵列28之间的单独连接9'。没有封装级焊球被施加在包括接触点27/28的区域上此时，触点可用于对嵌入式管芯1的全面测试，并且在故障管芯的情况下，可以作出不在重构晶片的该特定位置上组装附加的管芯的决定。
如图2f所示，横向连接设备18接着优选地通过本领域中已知的倒装芯片技术来被安装到RDL 3上，使得每个横向连接设备18上的第一和第二触点阵列19/20被分别接合到RDL 3的表面上的第一和第二触点阵列27/28。此时，高密度TSV插入件16以及经由横向连接设备18到嵌入式管芯1的连接可被测试。假使这些连接是有缺陷的，则可以作出不在该位置处组装附加的设备的决定。
如图2g所示，存储器管芯15接着优选地通过倒装芯片技术来被安装在封装的背侧上，使得存储器管芯的I/O触点8被接合到TSV插入件16的背侧上的触点11。存储器管芯15可通过第二包覆成型过程来被保护，其中另外的模具材料21被施加在存储器管芯上，如图2h所示。基板2接着可被分割以形成图1所示的类型的分开的封装。
上述过程步骤的替代方案在本领域技术人员的知识之内，并且可取决于通过TSV插入件16和横向连接设备18来被互连的半导体管芯1和15的类型。例如，再分布层3并不总被要求。当不存在RDL时，横向连接设备18可分别被直接接合到逻辑管芯1和TSV插入件16的前侧上的触点阵列7和12。
在全部附图中，且除非另有阐明，触点已被呈现为位于通过倒装芯片技术来被接合的设备的外层中的接触焊盘。这是对现实中可能更复杂的情况的简化表示，这对于技术人员而言是清楚的。术语“触点”可以是接触焊盘或接触凸块，这取决于触点将如何与随后的设备或层互连。例如，一个设备可设置有焊盘或中空接触区域，而另一设备设置有凸块，或者两侧可设置有凸块。凸起或焊盘可由多个层构建。触点可以在上层的顶部而不是被嵌入在其中，如附图中所呈现的。关于附图的另一注意点在于，设备在接合之前和之后已被同样地绘制。实际中的情况并非如此，因为倒装芯片在许多情况下涉及底层填料(underfill)步骤，其中经接合的触点在实际接合已被建立之后被嵌入在底层填料材料中。此外，接触焊盘或凸块将通常经历回流及并合成单个接触结构。附图已作出这些细节的抽象，以使附图不变得过于拥挤。然而，应当注意，如在附图中呈现且在本说明书中描述的触点的接合可以根据当今现有技术中可应用的任何方法来发生。
此外，无论什么情况下在本说明书或权利要求书中阐明了在经组装的设备中，第一设备的“触点”被“直接接合”到第二设备的“触点”，这意味着该组装件是通过使第一设备的触点与第二设备的触点直接物理接触来被获得的，从而形成触点之间的电连接。在接合之后被获得的组装件中，由于已存在形成经建立的接合的材料的合并，因此两个经接合的设备的原始触点可能不再是可区分的。当在这种情况下，经组装的设备的“触点”因此应被理解成合并的接触结构的一部分，一个部分被附接到第一设备，第二部分被附接到第二设备。“直接接合”的特征接着应被理解成这样的特征，根据该特征，这些部分通过随“触点”均匀的接触结构来被连接。
TSV插入件16和横向连接设备18可通过例如从Si-中介层技术已知的技术来被产生。下文描述用于产生TSV插入件16的优选过程流程。
1.提供Si晶片
2.通过化学气相沉积(CVD)将绝缘层沉积在晶片(例如硅)上
3.形成TSV阵列17：
a.光致抗蚀剂的沉积和TSV图案的光图案化。
b.蚀刻绝缘层和Si，以在Si基板的前侧形成深盲孔；例如，10μm直径和100μm深，或5μm直径和50μm深。
c.沉积电介质层，从而共形地覆盖曝露的Si孔的侧壁和底部以及晶片的上表面，其目的是为了在TSV和Si基板之间形成绝缘衬垫。被用作衬垫的典型材料是臭氧－正硅酸乙酯CVD氧化物(Ozone-Teos CVD oxide)以及等离子体增强的ALD共形氧化物。
d.在形成盲孔和衬垫之后，Cu阻挡层(例如Ti或Ta)被沉积在盲孔的壁和底部以及晶片的上表面上，随后是通过物理气相沉积(PVD)以在所述壁和底部以及上表面上形成Cu晶种层的Cu沉积过程。
e.随后，这些孔使用Cu电镀来被填充，Cu也在晶片的上表面上形成。
f.在Cu退火之后，电镀的Cu、晶种Cu以及阻挡和衬垫层通过CMP处理从晶片的上表面被移除，从而得到在Si晶片的顶层中的电隔离的Cu插入件。
4.在TSV处理之后，前侧Cu柱被制造在晶片前侧。这些Cu柱将形成TSV插入件的前侧上的触点12。这些柱是例如使用如下所示的半添加Cu电镀过程来被实现的：
a.Cu电镀晶种层通过物理气相沉积(PVD)来被沉积：例如，Ti/Cu或TiW/Cu，
b.光致抗蚀剂被沉积和图案化，从而在旨在用于Cu柱的位置上留下孔，这些孔覆盖晶片的顶层中的隔离的Cu插入件，
c.在图案化的光致抗蚀剂的开放区域中电解沉积Cu，
d.剥离光致抗蚀剂，
e.对PVD Cu晶种和(Ti或TiW)粘合剂层进行背面蚀刻，从而最小化厚得多的Cu柱的Cu的损耗。
5.在形成Cu柱之后，这些柱被嵌入在聚合物层中。这可例如通过旋涂或干膜层压来完成。
6.在沉积聚合物层之后，晶片的表面被平坦化，从而仅曝露Cu柱的顶部。这可通过晶片级研磨、表面平坦化或CMP(化学机械抛光)技术来完成，
7.使用临时接合的粘合剂层将晶片接合到载体Si晶片，
8.晶片的背侧使用机械研磨来被减薄；晶片在研磨之后被清洗，
9.嵌入在晶片中的TSV从背侧曝露。优选地使用如下所示的“软”通孔揭露过程：
a.使用湿法或干法蚀刻技术来进一步减薄Si。使用端点检测系统，当嵌入的CuTSV结构的尖端从晶片背侧曝露时，减薄被停止。Cu TSV仍然覆盖有TSV衬垫氧化物层。
b.背侧钝化和绝缘层被沉积(例如，SiN和SiO2层的堆叠)。光致抗蚀剂层被施加，从而平坦化曝露的TSV尖端。
c.干法背面蚀刻步骤被用来揭露TSV尖端，并且使用氧蚀刻化学，背侧钝化和TSV衬垫的尖端被移除，从而曝露TSV的金属(实际上是TSV阻挡层，例如Ti或Ta)。
替代地，CMP打开过程可被使用，其中较厚的背侧氧化物层首先被沉积，从而嵌入曝露的背侧TSV尖端。接下来，CMP步骤被用来打开曝露的TSV的Cu。
10.最后，用于产生前侧Cu柱12的过程在经减薄的晶片的背侧上被重复以形成背侧柱11，从而得到图1至图5所示的对称TSV插入件结构。
11.剩余的过程包括将薄晶片从载体基板剥离并转移到切割带，随后将晶片切割成最终单独的TSV插入件16。
根据一个实施例，Cu柱不被嵌入在聚合物中，或者这些柱仅被嵌入在插入件16的两侧中的一者上的聚合物中。当柱不被嵌入时，它们可例如被接合到半导体管芯的触点或者横向连接设备18上的中空接合焊盘。
横向连接设备18可通过在所述晶片上产生多个线路后端型层(诸如电源/接地参考层和单个高密度互连层)并在其上产生两个触点阵列19和20来被产生自硅晶片。之后，晶片可被附接到临时载体并被减薄。晶片可接着被切割以形成分开的横向连接设备18。应用于在横向连接设备18上产生线路后端型层和触点阵列的技术可以是用于(例如使用成本有效的65nm节点处理设施)在中介层基板上产生类似的层和触点的已知技术。
横向连接设备18允许在非常致密的触点阵列之间建立连接，如在宽I/O型技术中所遇到的。对于这样的高密度互连，如被用于产生再分布层3的针对封装的常规扇出互连技术是不够的，或者要求大量的层来实现逻辑管芯1和TSV插入件16之间的互连。横向连接设备18的应用提供了该问题的解决方案。当互连的数量较不致密时，可以在再分布层3本身内实现连接。图3例示了其中附加的管芯被包括在封装中的一个实施例。在其中第一管芯1是逻辑管芯而第二管芯15是宽I/O DRAM的示例性情况下，第三管芯30可以是闪存管芯，其同样与逻辑管芯1重叠并经由附加的TSV插入件31与其连接。该第二插入件31包括较少的金属填充的通孔32，这与闪存存储器管芯30和逻辑管芯1之间的减少的连接数一致。该减少的连接数不要求分开的横向连接设备：在第二插入件31的前侧上的触点与逻辑管芯1上的接触端子6之间的连接可被合并在再分布层3的电路中。
根据另一实施例，横向连接设备18同样被嵌入在FO-WLP基板的模具材料中。根据该实施例的封装在图4中示出。在该实施例中，逻辑管芯1设置有可以以与以上关于TSV插入件1所述类似的方式获得的高接触柱35，然而不带有将这些柱嵌入在聚合物层中的步骤。TSV插入件16本身和横向连接设备18与前述实施例中的相同。横向连接设备18现在被安装成使得其触点阵列19/20被直接接合到逻辑管芯1以及TSV插入件16的前侧上的触点阵列7。由于横向连接设备18的位置，因此需要高接触柱35，并且这些柱必须足够高以允许从前侧接触这些柱35并由此允许从前侧接触逻辑管芯1，而不管所述前侧上的横向连接设备的存在。在所示的实施例中，柱35通过再分布层3中的再分布电路36来被连接到RDL 3以及所述RDL 3上的封装级焊球4。该实施例具有的优点在于，焊球4不需要被中断以用于横向连接设备18的放置。再分布电路36也存在于图1至图3所示的RDL 3中，但是其未明确示出在这些附图中，以不至于使附图的细节过多。
图5a至5j例示了用于生产根据图4的封装的可能的过程步骤。示出了用于一个单个封装的生产的步骤，但是它们优选地在晶片级上被执行(即，用于在单个晶片上的若干封装的生产)，类似于图2a-2h所示的步骤。如图5a-5b所示，逻辑管芯1和TSV插入件16经由粘合剂层26来被附接到临时载体25。然后，横向连接设备18通过倒装芯片接合来被直接接合到逻辑管芯1和插入件16，参见图5c，即，逻辑管芯1上的触点阵列7被直接接合到横向连接设备18上的第一触点阵列19，并且TSV插入件16的前侧上的触点阵列12被直接接合到横向连接设备18上的第二触点阵列20。横向连接设备18的高度高于前述实施例。然后，三个设备1、16和18的该组装件优选地通过压缩模制来被嵌入在模具材料2'中，参见图5d，随后是通过背面研磨的平坦化，参见图5e，直到逻辑管芯1的金属接触柱35变成曝露的。横向连接设备18本身同样通过背面研磨步骤来被减薄。这导致了模制材料的重构晶片2的产生，逻辑管芯1、TSV插入件16以及(经减薄的)横向连接设备18的组装件被嵌入其中。图5d和5e所示的步骤的替代方案是使用模具材料的膜通过转移模塑来嵌入组装件，在这种情况下，横向连接设备18当被接合到TSV插入件16和逻辑管芯1时需要处于正确的厚度。
然后，再分布层3被产生在重建晶片上(图5f)，包括从逻辑管芯1的金属柱35到RDL3的外表面上的接触焊盘5的导体36。RDL可以以FO-WLP技术中已知的任何方式来被产生。此时，触点可用于对嵌入式管芯1的全面测试，并且在故障管芯的情况下，可以作出不在重构晶片的该特定位置上组装附加的管芯的决定。组装件接着被转移到第二临时载体晶片40(图5g)并经由第二粘合剂层41来被附接到其上，在这之后，第一载体25和粘合剂层26被移除，从而曝露TSV插入件16和逻辑管芯1的背侧。此时，高密度TSV插入件16以及经由横向连接设备18到嵌入式管芯1的连接可被测试。假使这些连接是有缺陷的，则可以作出不在该位置处组装附加的设备的决定。仍然如图5g所示，存储器管芯15接着通过倒装芯片接合来被安装在所述背侧上，从而建立存储器管芯上的触点阵列8与TSV插入件16的背侧上的触点阵列11之间的接触。存储器管芯15接着还被嵌入在模具材料21中(图5h)，在这之后，第二载体40和粘合剂层41被移除(图5i)，并且封装级凸块4被施加(图5j)。
其他过程序列可由本领域技术人员设计以用于图4的封装的生产。例如，还可以首先将横向连接设备18放置在第一临时载体上，随后是TSV插入件16和逻辑管芯1到横向连接设备18的倒装芯片接合。在这之后跟随的是通过压缩成型或传递模塑来将横向连接设备18、TSV插入件16和逻辑管芯1的组装件嵌入在模具材料中，以及生产RDL 3和封装级凸块4。过程序列的选择可能影响完成制造过程所需的临时载体的数量。
如图6所示，图4的实施例也可以与具有较少TSV 32的附加的插入件31组合，以用于将闪存存储器管芯30连接到逻辑管芯1。
图7示出了具有与这些实施例相同优点的图4至图6所示实施例的替代方案。在图7的组装件中，柱35显著地高于横向连接设备18的厚度，并且RDL 3不与横向连接设备18的背侧物理接触。在用于产生这样的封装的过程序列中，横向连接设备18在模制步骤之前被安装在逻辑管芯1和TSV插入件16上，如图5c所示，但是横向连接设备18此时已具有最终厚度，而在图5c中，其具有之后在图5d所示的步骤中被减薄的更高的厚度。在替代过程中，聚合物2'的减薄进行直到(较高)柱35曝露为止。此时，聚合物层2'仍然存在于横向连接设备18的背侧上。RDL 3接着以与图5f所示相同的方式被产生在平坦化的表面上，并且封装的完成也以图5g至5j所示的方式进行。
尽管已经在附图和前面的描述中具体地解说和描述了本发明，但是此类解说和描述被认为是解说性的或者示例性的而非限制性的。通过研究附图、公开和所附权利要求，本领域技术人员可在实践要求保护的发明时理解和实施所公开实施例的其他变体。在权利要求中，单词“包括”不排除其他元素或步骤，并且不定冠词“一”或“一个”不排除复数。在相互不同的从属权利要求中陈述某些措施的纯粹事实并不表示不能有利地使用这些措施的组合。权利要求中的任何引用符号不应被解释为限制范围。
除非特别指明，否则对在另一层或基板“上”存在、沉积或产生的层的描述包括以下选项：
·所述层位于、产生或直接沉积在所述另一层或基板上，即，与所述另一层或基板直接接触，以及
·所述层位于、产生或沉积在处于所述层和所述另一层或基板之间的一个或一堆中间层上。
除非特别指明，否则对在表面“上”存在、沉积或产生的设备的描述包括以下选项：
·所述设备位于、安装或直接产生在所述表面上，即，与所述表面物理接触，以及
·所述设备位于、安装或直接产生在所述表面或所述设备之间的中间层之一或中间层的堆叠上。

Claims (14)

1.一种半导体管芯封装，包括：
·由模具材料形成的基板(2)，其中在所述模具材料中并排嵌入的是第一半导体管芯(1)和穿基板通孔(TSV)插入件(16)，所述基板(2)、所述TSV插入件(16)和所述第一管芯(1)具有前侧和背侧，并且其中
·所述TSV插入件(16)包括所述插入件的前侧上的N个触点(12)、所述插入件的背侧上的N个触点(11)以及分别将所述插入件的前侧和背侧上的所述触点(12、11)互连的N个金属填充的通孔(17)，N是大于或等于1的整数，
·所述第一管芯(1)包括在所述第一管芯的前侧上的N个触点(7)，
·所述第一管芯还包括在所述第一管芯的所述前侧上的一个或多个接触端子(6、35)，
·被安装在所述基板(2)的背侧上的第二半导体管芯(15)，所述第二半导体管芯包括N个触点(8)，所述N个触点被分别连接到所述TSV插入件(16)在所述插入件(16)的背侧上的N个触点(11)，
·被安装在所述第一管芯(1)和所述TSV插入件(16)的所述前侧上的横向连接设备(18)，所述横向连接设备设置有第一和第二组(19、20)的N个触点，所述组各自被并排放置在所述横向连接设备的同一表面上，其中所述第一和第二组(19、20)的N个触点在所述横向连接设备内部分别被互连，并且其中所述横向连接设备上的所述第一和第二组(19、20)的N个触点分别被相应地连接到所述第一管芯上的所述N个触点(7)以及所述TSV插入件(16)的在所述插入件的前侧上的N个触点(12)，使得所述第一管芯(1)上的所述N个触点(7)通过所述横向连接设备(18)和所述TSV插入件(16)分别被连接到所述第二管芯上(15)的所述N个触点(8)，
·被连接到所述第一管芯上的所述接触端子(6)的至少一些的多个封装级接触凸块(4)。
2.根据权利要求1所述的封装，其特征在于，所述横向连接设备(18)在所述基板(2)的外部且被安装在所述基板(2)的前侧。
3.根据权利要求2所述的封装，其特征在于，包括在所述基板(2)的前侧上的再分布层(RDL)(3)，并且其中所述封装级接触凸块(4)被安装在所述RDL(3)的外表面上，并通过所述RDL(3)内的导体(36)被连接到所述第一管芯(1)的接触端子，并且其中所述横向连接设备(18)同样被安装在所述RDL(3)的外表面上。
4.根据权利要求3所述的封装，其特征在于，所述RDL(3)包括将所述第一管芯(1)上的所述N个触点(7)连接到所述RDL(3)的外表面上的第一组的N个对应触点(27)的导体(9)，所述RDL(3)还包括将所述TSV插入件(16)的前侧上的所述N个触点(12)连接到所述RDL的外表面上的第二组的N个对应触点(28)的导体(9')，并且其中所述横向连接设备(18)上的所述第一和第二组的N个触点(19、20)分别被相应地接合到所述RDL(3)上的所述第一和第二组的触点(27、28)。
5.根据权利要求1所述的封装，其特征在于，所述横向连接设备(18)被直接接合到所述第一半导体管芯(1)和所述TSV插入件(16)的前侧。
6.根据权利要求5所述的封装，其特征在于，所述横向连接设备(18)同样被嵌入在所述基板(2)的所述模具材料中。
7.根据权利要求5或6所述的封装，其特征在于，所述第一管芯的接触端子是接触柱(35)，所述接触柱的高度足够用于从所述前侧接触所述第一管芯(1)，而不管所述横向连接设备(18)的存在。
8.根据权利要求7所述的封装，其特征在于，包括在所述基板(2)的前侧上的再分布层(RDL)(3)，并且其中所述封装级接触凸块(4)被安装在所述RDL(3)的外表面上，并通过所述RDL(3)内的导体(36)被连接到所述第一管芯(1)的所述接触柱(35)。
9.根据权利要求8所述的封装，其特征在于，所述RDL(3)与所述横向连接设备(18)的背侧直接物理接触。
10.根据权利要求8所述的封装，其特征在于，在所述RDL(3)与所述横向连接设备(18)的背侧之间存在一层模具材料。
11.根据权利要求3、4或8到10中任一项所述的封装，其特征在于，包括被安装在所述基板(2)的背侧上的一个或多个附加的半导体管芯(31)，每个附加的管芯通过附加的TSV插入件(32)被连接到所述基板的前侧，并且其中所述附加的TSV插入件通过所述RDL(3)内的导体被连接到所述第一半导体管芯(1)。
12.根据前述权利要求中任一项所述的封装，其特征在于，其中所述横向连接设备(18)包括半导体基板和线路部分的后端，并且其中所述横向连接设备(18)的第一和第二组的触点(19、20)之间的所述互连通过线路部分所述后端中的电路来被建立。
13.根据前述权利要求中任一项所述的封装，其特征在于，所述第一半导体管芯是逻辑管芯(1)，并且其中所述第二半导体管芯是存储器管芯(15)，并且其中所述第一和第二管芯上的所述N个触点(7、8)被形成为致密的I/O触点阵列。
14.根据前述权利要求中任一项所述的封装，其特征在于，所述第二半导体管芯(15)上的所述N个触点(8)被直接接合到所述TSV插入件(16)的背侧上的所述N个触点(11)。
CN201710735129.0A 2016-08-25 2017-08-24 半导体管芯封装及生产这种封装的方法 Active CN107785358B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP16185640.6A EP3288076B1 (en) 2016-08-25 2016-08-25 A semiconductor die package and method of producing the package
EP16185640.6 2016-08-25

Publications (2)

Publication Number Publication Date
CN107785358A true CN107785358A (zh) 2018-03-09
CN107785358B CN107785358B (zh) 2023-05-26

Family

ID=56801426

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710735129.0A Active CN107785358B (zh) 2016-08-25 2017-08-24 半导体管芯封装及生产这种封装的方法

Country Status (3)

Country Link
US (1) US9966325B2 (zh)
EP (1) EP3288076B1 (zh)
CN (1) CN107785358B (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020103162A1 (zh) * 2018-11-23 2020-05-28 华为技术有限公司 一种芯片以及芯片封装方法
CN112652605A (zh) * 2019-10-09 2021-04-13 财团法人工业技术研究院 多芯片封装件及其制造方法
US20210134690A1 (en) * 2019-11-01 2021-05-06 Advanced Semiconductor Engineering, Inc. Semiconductor device packages and methods of manufacturing the same
CN113035858A (zh) * 2021-05-31 2021-06-25 杭州光智元科技有限公司 半导体装置及其制造方法

Families Citing this family (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9136236B2 (en) 2012-09-28 2015-09-15 Intel Corporation Localized high density substrate routing
US9190380B2 (en) * 2012-12-06 2015-11-17 Intel Corporation High density substrate routing in BBUL package
US10553515B2 (en) * 2016-04-28 2020-02-04 Intel Corporation Integrated circuit structures with extended conductive pathways
US10366968B2 (en) * 2016-09-30 2019-07-30 Intel IP Corporation Interconnect structure for a microelectronic device
TW202404049A (zh) 2016-12-14 2024-01-16 成真股份有限公司 標準大宗商品化現場可編程邏輯閘陣列(fpga)積體電路晶片組成之邏輯驅動器
US11625523B2 (en) 2016-12-14 2023-04-11 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips
US10447274B2 (en) 2017-07-11 2019-10-15 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells
US10957679B2 (en) 2017-08-08 2021-03-23 iCometrue Company Ltd. Logic drive based on standardized commodity programmable logic semiconductor IC chips
US10630296B2 (en) 2017-09-12 2020-04-21 iCometrue Company Ltd. Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells
US10529693B2 (en) * 2017-11-29 2020-01-07 Advanced Micro Devices, Inc. 3D stacked dies with disparate interconnect footprints
US10608642B2 (en) 2018-02-01 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile radom access memory cells
US10623000B2 (en) 2018-02-14 2020-04-14 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
US11043478B2 (en) 2018-04-24 2021-06-22 Cisco Technology, Inc. Integrated circuit bridge for photonics and electrical chip integration
US11276676B2 (en) * 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
US10608638B2 (en) 2018-05-24 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
US10727204B2 (en) 2018-05-29 2020-07-28 Advances Micro Devices, Inc. Die stacking for multi-tier 3D integration
US10937755B2 (en) 2018-06-29 2021-03-02 Advanced Micro Devices, Inc. Bond pads for low temperature hybrid bonding
US10892011B2 (en) 2018-09-11 2021-01-12 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
US11309334B2 (en) 2018-09-11 2022-04-19 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
US10937762B2 (en) 2018-10-04 2021-03-02 iCometrue Company Ltd. Logic drive based on multichip package using interconnection bridge
EP3640979A1 (en) * 2018-10-15 2020-04-22 IMEC vzw A method for packaging semiconductor dies
EP3644359A1 (en) 2018-10-23 2020-04-29 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Z-axis interconnection with protruding component
US11616046B2 (en) 2018-11-02 2023-03-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
US11211334B2 (en) 2018-11-18 2021-12-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
EP3671833A1 (en) 2018-12-20 2020-06-24 IMEC vzw A method for packaging semiconductor dies
US10833051B2 (en) * 2019-01-24 2020-11-10 International Business Machines Corporation Precision alignment of multi-chip high density interconnects
US10770433B1 (en) * 2019-02-27 2020-09-08 Apple Inc. High bandwidth die to die interconnect with package area reduction
US10803548B2 (en) * 2019-03-15 2020-10-13 Intel Corporation Disaggregation of SOC architecture
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US11227838B2 (en) 2019-07-02 2022-01-18 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cooperating or supporting circuits
US10985154B2 (en) 2019-07-02 2021-04-20 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cryptography circuits
US11887930B2 (en) 2019-08-05 2024-01-30 iCometrue Company Ltd. Vertical interconnect elevator based on through silicon vias
TW202109800A (zh) * 2019-08-15 2021-03-01 力成科技股份有限公司 具有微細間距矽穿孔封裝的扇出型封裝晶片結構以及扇出型封裝單元
DE102020106799A1 (de) * 2019-09-20 2021-03-25 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleiterbauelemente und verfahren zur herstellung
US11637056B2 (en) 2019-09-20 2023-04-25 iCometrue Company Ltd. 3D chip package based on through-silicon-via interconnection elevator
US11856800B2 (en) 2019-09-20 2023-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices with system on chip devices
US11587905B2 (en) 2019-10-09 2023-02-21 Industrial Technology Research Institute Multi-chip package and manufacturing method thereof
TWI759844B (zh) * 2019-10-09 2022-04-01 財團法人工業技術研究院 多晶片封裝件及其製造方法
TWI701777B (zh) * 2019-10-22 2020-08-11 財團法人工業技術研究院 影像感測器封裝件及其製造方法
US11735564B2 (en) * 2019-12-04 2023-08-22 Sj Semiconductor (Jiangyin) Corporation Three-dimensional chip packaging structure and method thereof
CN113013125A (zh) * 2019-12-20 2021-06-22 奥特斯奥地利科技与系统技术有限公司 嵌入有在侧向上位于堆叠体的导电结构之间的内插件的部件承载件
TWI768294B (zh) * 2019-12-31 2022-06-21 力成科技股份有限公司 封裝結構及其製造方法
US11309283B2 (en) 2019-12-31 2022-04-19 Powertech Technology Inc. Packaging structure and manufacturing method thereof
US11600526B2 (en) 2020-01-22 2023-03-07 iCometrue Company Ltd. Chip package based on through-silicon-via connector and silicon interconnection bridge
KR20210095442A (ko) 2020-01-23 2021-08-02 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US11616003B2 (en) * 2021-07-01 2023-03-28 Deca Technologies Usa, Inc. Stackable fully molded semiconductor structure with through silicon via (TSV) vertical interconnects
US11728248B2 (en) 2021-07-01 2023-08-15 Deca Technologies Usa, Inc. Fully molded semiconductor structure with through silicon via (TSV) vertical interconnects
KR20230032587A (ko) * 2021-08-31 2023-03-07 삼성전자주식회사 반도체 패키지

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103168358A (zh) * 2010-07-20 2013-06-19 马维尔国际贸易有限公司 嵌入式结构及其制造方法
US20140103527A1 (en) * 2012-03-23 2014-04-17 Stats Chippac, Ltd. Semiconductor Device and Method of Forming a POP Device with Embedded Vertical Interconnect Units
US20140264836A1 (en) * 2013-03-15 2014-09-18 Qualcomm Incorporated System-in-package with interposer pitch adapter

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7098542B1 (en) 2003-11-07 2006-08-29 Xilinx, Inc. Multi-chip configuration to connect flip-chips to flip-chips
US20080157316A1 (en) 2007-01-03 2008-07-03 Advanced Chip Engineering Technology Inc. Multi-chips package and method of forming the same
US8064224B2 (en) 2008-03-31 2011-11-22 Intel Corporation Microelectronic package containing silicon patches for high density interconnects, and method of manufacturing same
US8227904B2 (en) 2009-06-24 2012-07-24 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
US9230898B2 (en) 2009-08-17 2016-01-05 Stats Chippac Ltd. Integrated circuit packaging system with package-on-package and method of manufacture thereof
KR101918608B1 (ko) * 2012-02-28 2018-11-14 삼성전자 주식회사 반도체 패키지
US8872349B2 (en) 2012-09-11 2014-10-28 Intel Corporation Bridge interconnect with air gap in package assembly
US9236366B2 (en) * 2012-12-20 2016-01-12 Intel Corporation High density organic bridge device and method
US8901748B2 (en) 2013-03-14 2014-12-02 Intel Corporation Direct external interconnect for embedded interconnect bridge package
US9041205B2 (en) * 2013-06-28 2015-05-26 Intel Corporation Reliable microstrip routing for electronics components
KR20170027391A (ko) * 2015-09-02 2017-03-10 에스케이하이닉스 주식회사 복수의 칩들이 내장된 반도체 패키지 및 그의 제조방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103168358A (zh) * 2010-07-20 2013-06-19 马维尔国际贸易有限公司 嵌入式结构及其制造方法
US20140103527A1 (en) * 2012-03-23 2014-04-17 Stats Chippac, Ltd. Semiconductor Device and Method of Forming a POP Device with Embedded Vertical Interconnect Units
US20140264836A1 (en) * 2013-03-15 2014-09-18 Qualcomm Incorporated System-in-package with interposer pitch adapter

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020103162A1 (zh) * 2018-11-23 2020-05-28 华为技术有限公司 一种芯片以及芯片封装方法
CN112219276A (zh) * 2018-11-23 2021-01-12 华为技术有限公司 一种芯片以及芯片封装方法
CN112652605A (zh) * 2019-10-09 2021-04-13 财团法人工业技术研究院 多芯片封装件及其制造方法
US20210134690A1 (en) * 2019-11-01 2021-05-06 Advanced Semiconductor Engineering, Inc. Semiconductor device packages and methods of manufacturing the same
CN113035858A (zh) * 2021-05-31 2021-06-25 杭州光智元科技有限公司 半导体装置及其制造方法

Also Published As

Publication number Publication date
EP3288076A1 (en) 2018-02-28
US20180061741A1 (en) 2018-03-01
CN107785358B (zh) 2023-05-26
EP3288076B1 (en) 2021-06-23
US9966325B2 (en) 2018-05-08

Similar Documents

Publication Publication Date Title
CN107785358A (zh) 半导体管芯封装及生产这种封装的方法
KR100826979B1 (ko) 스택 패키지 및 그 제조방법
TWI694570B (zh) 半導體封裝及製作半導體封裝的方法
US8421193B2 (en) Integrated circuit device having through via and method for preparing the same
US8970047B2 (en) Method for creating a 3D stacked multichip module
US6838774B2 (en) Interlocking conductor method for bonding wafers to produce stacked integrated circuits
US8779601B2 (en) Embedded wafer level package for 3D and package-on-package applications, and method of manufacture
TWI393240B (zh) 組裝堆疊晶粒之半導體封裝的方法
US20050156330A1 (en) Through-wafer contact to bonding pad
US7700410B2 (en) Chip-in-slot interconnect for 3D chip stacks
TW202101728A (zh) 半導體結構及其製造方法
TW201336040A (zh) 半導體封裝及其製造方法
US11367705B2 (en) Method for packaging semiconductor dies
US20140273354A1 (en) Fabrication of 3d chip stacks without carrier plates
KR20150137970A (ko) 반도체 디바이스 및 반도체 디바이스 제조 방법
WO2020029096A1 (zh) 芯片封装结构及其制造方法
US9093456B2 (en) Stack of semiconductor structures and corresponding manufacturing method
KR101095055B1 (ko) 반도체 소자의 제조 방법
US20120193809A1 (en) Integrated circuit device and method for preparing the same
CN112582389A (zh) 半导体封装件、封装件及其形成方法
KR101013545B1 (ko) 스택 패키지 및 그의 제조방법
TW201742189A (zh) 用於製作包含中介層之半導體結構之方法
WO2022012475A1 (zh) 晶圆级封装方法以及封装结构
TW202347662A (zh) 積體電路封裝及其形成方法
CN116344509A (zh) 形成封装件的方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant