TW201336040A - 半導體封裝及其製造方法 - Google Patents

半導體封裝及其製造方法 Download PDF

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Publication number
TW201336040A
TW201336040A TW101151239A TW101151239A TW201336040A TW 201336040 A TW201336040 A TW 201336040A TW 101151239 A TW101151239 A TW 101151239A TW 101151239 A TW101151239 A TW 101151239A TW 201336040 A TW201336040 A TW 201336040A
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Taiwan
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semiconductor wafer
redistribution pattern
package
pattern layer
embedded
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TW101151239A
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English (en)
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TWI531044B (zh
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Yun-Mook Park
Byoung-Yool Jeon
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Nepes Corp
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    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

此處所揭示的是一半導體封裝，其具有一扇出結構，其中一半導體晶片係藉由一封裝構件埋入，且一外部連接構件係配置在該埋入半導體晶片的下方。該半導體封裝包括一嵌入式重接線圖案層；一上部半導體晶片，其係配置在該嵌入式重接線圖案層的上方；一上部封裝構件，其封裝該上部半導體晶片；一下部半導體晶片，其係配置在該嵌入式重接線圖案層的下方；及一下部封裝構件，其封裝該下部半導體晶片，以防止其暴露。

Description

半導體封裝及其製造方法
本發明之實施例係關於一半導體封裝，其具有一扇出結構，其中一半導體晶片係藉由一封裝構件埋入，且一外部連接構件係配置在該埋入半導體晶片的下方；及其製造方法。
近來，隨著半導體裝置的小型化以及半導體裝置功能的多樣化，半導體晶片的尺寸縮減，且半導體晶片之輸入及輸出端子的數目增加，因此，電極墊的間距遂進一步地小型化。此外，依據各種功能的加速整合，出現了一系統層級的封裝技術，其中多種裝置係整合在一單一封裝中。此外，該系統層級封裝技術已改變為三維堆疊技術，在其中可維持短訊號距離，以最小化操作間的雜訊，並改善訊號速率。為了控制產品成本的增加、增加生產率及降低原物料成本，除了這類針對製造技術進展的需求之外，已引入包括複數個彼此相堆疊之半導體晶片的半導體封裝。
在一習知的堆疊型半導體封裝(例如，一系統級封裝(SIP))中，輸入及輸出端子係形成在堆疊於一第一半導體晶片上之一第二半導體晶片的外部區域，且因此必須作出第一及第二半導體晶片的尺寸差。此外，隨著這類尺寸差減少，輸入及輸出端子的數目遂受到限制。
因此，本發明之一實施態樣係提供一半導體封裝，其具有一扇出結構，其中一半導體晶片係藉由一封裝構件埋入，且一外部連接構件係配置在該埋入半導體晶片的下方。
本發明之另一實施態樣係提供一製造半導體封裝的方法。
本發明之額外的實施態樣將在下文敘述中部分提出，而部分則由敘述當可明白或可藉由實行本發明而習得。
根據本發明之一實施態樣，一半導體封裝包括一嵌入式重接線圖案層；一上部半導體晶片，其係配置在該嵌入式重接線圖案層的上方；一上部封裝構件，其封裝該上部半導體晶片；一下部半導體晶片，其係配置在該嵌入式重接線圖案層的下方；及一下部封裝構件，其封裝該下部半導體晶片，以防止其暴露。
該半導體封裝可進一步包括一導電柱，其電連接至該嵌入式重接線圖案層；及外部連接構件，其電連接至該導電柱。
該半導體封裝可進一步包括一外部重接線圖案層，其係形成在該下部封裝構件之一下部表面上，並將該導電柱電連接至該外部連接構件。
一些該外部連接構件可配置在該下部半導體晶片的下方。
該上部封裝構件及該下部封裝構件可彼此連接，以封裝該嵌入式重接線圖案層來防止其暴露。
該下部封裝構件可穿透一部分的該嵌入式重接線圖案層，以連接至該上部封裝構件。
該上部半導體晶片及該下部半導體晶片可經由該嵌入式重接線圖案層彼此電連接。
該下部半導體晶片可包括複數個下部半導體晶片。
該半導體封裝可進一步包括複數個導電柱，其電連接至該嵌入式重接線圖案層，並藉由該下部封裝構件嵌入，該導電柱包括一些配置在該下部半導體晶片間的導電柱。
該上部半導體晶片可包括複數個上部半導體晶片。
該上部及下部半導體晶片可具有相同尺寸。
根據本發明之另一實施態樣，一製造半導體封裝的方法包含以下步驟：將一上部半導體晶片附接至一第一載體基材；形成一上部封裝構件，其封裝該上部半導體晶片；將一第二載體基材附接至該上部封裝構件；移除該第一載體基材，以暴露出該上部半導體晶片；在該已暴露的上部半導體晶片及該上部封裝構件上形成一嵌入式重接線圖案層；形成一導電柱，其電連接至該嵌入式重接線圖案層；在該嵌入式重接線圖案層的下方將一下部半導體晶片附接在一相對該上部半導體晶片的位置之中；形成一下部封裝構件，其封裝該下部半導體晶片及該導電柱；平坦化該下部封裝構件，以暴露出該導電柱；形成一外部重接線圖案層，其在該下部封裝構件上電連接至該導電柱；及附接一外部連接構件，以電連接至該外部重接線圖案層。
本發明之這些及/或其他實施態樣由下文之實施例敘述連同伴隨圖式當可更加明白及更容易了解，其中：
第1圖為根據本發明之一實施例之一半導體封裝的剖面圖；
第2至8圖為根據本發明之實施例之半導體封裝的剖面圖；及
第9至18圖為剖面圖，循序地繪示根據本發明之一實施例之一製造第1圖之半導體封裝的方法。
現將詳細參照本發明之實施例，其範例係在伴隨圖式中繪示。不過，本實施例可具有不同形式，且不應理解為受限於此處所提出的敘述。倒不如說，提供這些實施例，以便此揭示內容將是詳盡且完整的，並將向那些熟悉此項技術者完全傳達本發明的範圍。如此處所用，「及/或」一詞包括一或多個相關聯之列出項目的任一或所有組合。就這一點而言，在上下文各處，相似的參考數字指的是相似的元件。另外，圖中的多種元件及區域係為概略繪示。因此，本發明並未受限於伴隨圖式中所示的相對尺寸或區間。
第1圖為根據本發明之一實施例之半導體封裝1的剖面圖。
參照第1圖，半導體封裝1包括嵌入式重接線圖案層30及配置在嵌入式重接線圖案層30之相對側的上部與下部半導體晶片10和40。舉例來說，上部半導體晶片10可配置在嵌入式重接線圖案層30的上方，且下部半導體晶片40可配置在嵌入式重接線圖案層30的下方。半導體封裝1亦可包括上部封裝構件20，其封裝上部半導體晶片10；及下部封裝構件60，其封裝下部半導體晶片40。半導體封裝1可進一步包括導電柱50，其電連接至嵌入式重接線圖案層30；外部重接線圖案層70，其電連接至導電柱50；及外部連接構件80。
構成上部及下部半導體晶片10及40的材料可相同或相異。舉例來說，上部及下部半導體晶片10及40可為記憶體晶片或邏輯晶片。記憶體晶片的範例包括DRAM、SRAM、快閃、PRAM、ReRAM、FeRAM及MRAM。邏輯晶片可為控制器，其控制記憶體晶片。舉例來說，上部半導體晶片10可為包括邏輯電路的邏輯晶片，且下部半導體晶片40可為記憶體晶片，或反之亦然。半導體封裝1可為系統單晶片(SOC)或系統級封裝(SIP)。
上部與下部半導體晶片10及40可具有相同尺寸或相異尺寸。
上部半導體晶片10可包括上部半導體晶片墊12，且下部半導體晶片40可包括下部半導體晶片墊42。此外，連接至每一下部半導體晶片墊42的絕緣層44及焊墊46可配置在下部半導體晶片40之上。
嵌入式重接線圖案層30可包括第一絕緣層32、重接線圖案34及第二絕緣層36。重接線圖案34可包括導電材料，例如，如銅、銅合金、鋁或鋁合金的金屬。上部半導體晶片10及/或下部半導體晶片40可藉由重接線圖案34重接線，並電連接至外部連接構件80。因此，上部半導體晶片10及/或下部半導體晶片40的輸入與輸出端子可縮小尺寸，且輸入及輸出端子的數目可增加。此外，上部半導體晶片10及/或下部半導體晶片40可連接至嵌入式重接線圖案層30。就此而言，半導體封裝1可具有扇出結構。上部及下部半導體晶片10及40可共享重接線圖案34。在此情況下，上部及下部半導體晶片10及40可經由重接線圖案34彼此電連接。或者，上部及下部半導體晶片10及40可連接至彼此電絕緣的個別重接線圖案34。在此情況下，上部及下部半導體晶片10及40彼此可不經由重接線圖案34電連接。
第一絕緣層32可形成為覆蓋重接線圖案34的上部部分，且第二絕緣層36可形成為覆蓋重接線圖案34的下部部分。重接線圖案34的上部表面可透過第一絕緣層32部分地暴露，且部分暴露的重接線圖案34可電連接至上部半導體晶片10。也就是說，重接線圖案34及上部半導體晶片10的上部半導體晶片墊12可彼此電連接。此外，重接線圖案34的下部表面可經由第二絕緣層36部分地暴露，且重接線圖案34之暴露的下部表面部分可電連接至下部半導體晶片40。重接線圖案34可形成為單一層或可形成多層的重接線圖案34。
可將一先前製造的基材用作嵌入式重接線圖案層30。在一些實施例中，嵌入式重接線圖案層30可藉由沖壓、黏著或迴焊製程來黏著至上部半導體晶片10及上部封裝構件20。
連接構件48可配置在個別的焊墊46及嵌入式重接線圖案層30之重接線圖案34的個別暴露表面部分之上，並可電連接至嵌入式重接線圖案層30的重接線圖案34及下部半導體晶片40的下部半導體晶片墊42。此外，上部及下部半導體晶片10及40可經由嵌入式重接線圖案層30及連接構件48彼此電連接。連接構件48可包括例如金屬的導電材料。連接構件48可為例如焊錫球，並可透過迴焊製程附接至焊墊46及嵌入式重接線圖案層30。
上部封裝構件20可封裝上部半導體晶片10。上部封裝構件20可完全覆蓋上部半導體晶片10。或者，上部半導體晶片10之一上部表面可經由上部封裝構件20暴露。上部封裝構件20可包括一例如環氧模造物(EMC)的絕緣材料。
導電柱50可電連接至嵌入式重接線圖案層30。每一導電柱50可配置在嵌入式重接線圖案層30之一暴露部分之上，且導電柱50可電連接至嵌入式重接線圖案層30。導電柱50可配置在下部半導體晶片40的該側。同樣地，上部半導體晶片10可朝導電柱50上方的區域延伸。導電柱50始於嵌入式重接線圖案層30的高度可大於下部半導體晶片40的高度。導電柱50可包括一導電材料，例如，如銅、銅合金、鋁或鋁合金的金屬。同樣地，導電柱50可包括導電焊錫或含有導電材料的焊錫膏。或者，導電柱50可為貫通電極，例如，貫通矽貫孔(TSV)。
下部封裝構件60可封裝下部半導體晶片40及導電柱50。下部封裝構件60可封裝下部半導體晶片40，以防止其暴露。此外，下部封裝構件60可封裝嵌入式重接線圖案層30。下部封裝構件60可填充下部半導體晶片40的連接構件48之間的空隙。下部封裝構件60可包括一例如EMC的絕緣材料。
上部及下部封裝構件20及60可彼此連接，並可封裝嵌入式重接線圖案層30，以防止其暴露。或者，嵌入式重接線圖案層30可經由上部封裝構件20及/或下部封裝構件60暴露。上部及下部封裝構件20及60可包括相同材料或相異材料。上部及下部封裝構件20及60可形成一單體結構。
導電柱50始於嵌入式重接線圖案層30的高度可大於下部半導體晶片40的高度，且因此下部半導體晶片40可藉由下部封裝構件60嵌入，以防止其暴露。
外部重接線圖案層70可配置在下部封裝構件60的下部側上，並電連接至導電柱50。外部重接線圖案層70可將導電柱50電連接至外部連接構件80。此外，上部半導體晶片10及/或下部半導體晶片40可連接至外部重接線圖案層70，且就此而言，半導體封裝1可具有扇出結構。
外部重接線圖案層70可包括第三絕緣層72、外部重接線圖案74、第四絕緣層76及外部焊墊78。外部重接線圖案74可包括導電材料，例如，如銅、銅合金、鋁或鋁合金的金屬。外部重接線圖案74的上部部分可由第三絕緣層72覆蓋，且外部重接線圖案74的下部部分可由第四絕緣層76覆蓋。外部重接線圖案74的上部部分可經由第三絕緣層72部分地暴露，且外部重接線圖案74之部分暴露的上部部分可電連接至導電柱50。也就是說，外部重接線圖案74及嵌入式重接線圖案層30可彼此電連接。同樣地，外部重接線圖案74的下部部分可經由第四絕緣層76部分地暴露，且外部重接線圖案74之部分暴露的下部部分可電連接至外部連接構件80。外部焊墊78可進一步形成在外部重接線圖案74的暴露部分之上。外部重接線圖案層70可為一先前製造的基材，並可藉由沖壓、黏著或迴焊製程黏著至導電柱50及下部封裝構件60。
外部連接構件80可配置為與外部重接線圖案層70電連接。外部連接構件80可附接至外部重接線圖案74的暴露部分或外部焊墊78。外部連接構件80可包括例如金屬的導電材料。外部連接構件80可為焊錫球。
外部重接線圖案層70可提供重接線，且因此一些外部連接構件80可配置在下部半導體晶片40的下方。因此，外部連接構件80可安排在相對廣域的區域上方。結果，可小型化上部半導體晶片10及/或下部半導體晶片40的輸入及輸出端子，並可增加輸入及輸出端子的數目。
第2至8圖繪示根據本發明之實施例的半導體封裝2、3、4、5、6、7及8。根據本實施例的半導體封裝2、3、4、5、6、7及8具有一結構，其中一些元件係修改自第1圖所繪示之半導體封裝1的那些，且因此其詳細敘述並未於此處提供。
參照第2圖，上部封裝構件20及下部封裝構件60係彼此連接，以封裝嵌入式重接線圖案層30a來防止其暴露。此外，下部封裝構件60可穿透一部分的嵌入式重接線圖案層30a，且因此更緊密地連接至上部封裝構件20。因此，可進一步增加上部及下部封裝構件20及60間的黏著強度。
參照第3圖，半導體封裝3可包括複數個下部半導體晶片40a。下部半導體晶片40a可電連接至嵌入式重接線圖案層30，類似於第1圖的下部半導體晶片40。導電柱50a可配置在下部半導體晶片40a之間，且導電柱50a可電連接至嵌入式重接線圖案層30。
參照第4圖，半導體封裝4可包括複數個下部半導體晶片40a。下部半導體晶片40a可電連接至嵌入式重接線圖案層30a，類似於第1圖的下部半導體晶片40。導電柱50a可配置在下部半導體晶片40a之間，且導電柱50a可電連接至嵌入式重接線圖案層30a。此外，上部封裝構件20及下部封裝構件60可彼此連接，以封裝嵌入式重接線圖案層30a來防止其暴露。此外，下部封裝構件60可穿透一部分的嵌入式重接線圖案層30a，且因此更緊密地連接至上部封裝構件20。因此，可進一步增加上部及下部封裝構件20及60間的黏著強度。
參照第5圖，半導體封裝5可包括複數個上部半導體晶片10a。上部半導體晶片10a可電連接至嵌入式重接線圖案層30，類似於第1圖的上部半導體晶片10。
參照第6圖，半導體封裝6可包括複數個上部半導體晶片10a。上部半導體晶片10a可電連接至嵌入式重接線圖案層30a，類似於第1圖的上部半導體晶片10。此外，上部封裝構件20及下部封裝構件60可彼此連接，以封裝嵌入式重接線圖案層30a來防止其暴露。此外，下部封裝構件60可穿透一部分的嵌入式重接線圖案層30a，且因此更緊密地連接至上部封裝構件20。因此，可進一步增加上部及下部封裝構件20及60間的黏著強度。
參照第7圖，半導體封裝7可包括複數個上部半導體晶片10a及複數個下部半導體晶片40a。上部半導體晶片10a可電連接至嵌入式重接線圖案層30，類似於第1圖的上部半導體晶片10。下部半導體晶片40a可電連接至嵌入式重接線圖案層30，類似於第1圖的下部半導體晶片40。導電柱50a可配置在下部半導體晶片40a之間，且導電柱50a可電連接至嵌入式重接線圖案層30。
參照第8圖，半導體封裝8可包括複數個上部半導體晶片10a及複數個下部半導體晶片40a。上部半導體晶片10a可電連接至嵌入式重接線圖案層30a，類似於第1圖的上部半導體晶片10。下部半導體晶片40a可電連接至嵌入式重接線圖案層30a，類似於第1圖的下部半導體晶片40。導電柱50a可配置在下部半導體晶片40a之間，且導電柱50a可電連接至嵌入式重接線圖案層30a。此外，上部封裝構件20及下部封裝構件60可彼此連接，以封裝嵌入式重接線圖案層30a來防止其暴露。此外，下部封裝構件60可穿透一部分的嵌入式重接線圖案層30a，且因此更緊密地連接至上部封裝構件20。因此，可進一步增加上部及下部封裝構件20及60間的黏著強度。
第9至18圖為剖面圖，循序地繪示根據本發明之一實施例之一製造第1圖之半導體封裝1的方法。
參照第9圖，使用黏著構件16將上部半導體晶片10附接至第一載體基材14。黏著構件16可為液體黏著劑或黏著膠帶。上部半導體晶片10的上部半導體晶片墊12可面朝下並接觸黏著構件16。第一載體基材14可包括矽、玻璃、陶瓷、塑膠或聚合物。
參照第10圖，形成上部封裝構件20，以封裝上部半導體晶片10。上部封裝構件20可完全覆蓋上部半導體晶片10。上部封裝構件20可包括例如EMC的絕緣材料。
參照第11圖，使用黏著構件17將第二載體基材18附接至上部封裝構件20。黏著構件17可為液體黏著劑或黏著膠帶。第二載體基材18可包括矽、玻璃、陶瓷、塑膠或聚合物。隨後，將第一載體基材14移除，以暴露上部半導體晶片10。結果，暴露出上部半導體晶片墊12。
參照第12圖，嵌入式重接線圖案層30係形成在暴露的上部半導體晶片10及上部封裝構件20之上。嵌入式重接線圖案層30可包括第一絕緣層32、重接線圖案34及第二絕緣層36。舉例來說，第一絕緣層32係形成在上部半導體晶片10之上，且第一絕緣層32係部分移除，以暴露上部半導體晶片墊12。其後，形成重接線圖案34，其電連接至暴露的上部半導體晶片墊12，並在第一絕緣層32之一上部表面上延伸。重接線圖案34可使用例如沈積、電鍍等的各種方法形成。第二絕緣層36係形成在重接線圖案34之上，並部分移除，以部分地暴露重接線圖案34。在後續的製造製程中，導電柱50(參見第13圖)或連接構件48(參見第14圖)可附接至暴露的重接線圖案34。
此外，可將一先前製造的基材用作嵌入式重接線圖案層30。在一些實施例中，嵌入式重接線圖案層30可藉由沖壓、黏著或迴焊製程來黏著至上部半導體晶片10及上部封裝構件20。
參照第13圖，導電柱50係形成為電連接至嵌入式重接線圖案層30。導電柱50可配置在嵌入式重接線圖案層30的暴露部分之上，並電連接至此。導電柱50可包括導電材料，例如，如銅、銅合金、鋁、鋁合金的金屬。同樣地，導電柱50可包括導電焊錫或含有導電材料的焊錫膏。雖然在第13圖中未繪示，導電柱50可藉由下列步驟形成：在嵌入式重接線圖案層30上形成一遮罩層；在遮罩層中形成開口，以部分地暴露嵌入式重接線圖案層30；以導電材料填充開口；及移除遮罩層。遮罩層可包括例如光阻。
參照第14圖，在嵌入式重接線圖案層30的下方將下部半導體晶片40附接在相對上部半導體晶片10的位置之中。下部半導體晶片40可包括絕緣層44，以暴露下部半導體晶片墊42；及焊墊46，其位於個別的下部半導體晶片墊42之上。連接構件48係配置在焊墊46及嵌入式重接線圖案層30之重接線圖案34的暴露部分之間。連接構件48可將下部半導體晶片40電連接至嵌入式重接線圖案層30。此外，上部及下部半導體晶片10及40可經由嵌入式重接線圖案層30及連接構件48彼此電連接。連接構件48可包括例如金屬的導電材料。連接構件48可為例如焊錫球，並可透過迴焊製程附接至焊墊46及嵌入式重接線圖案層30。導電柱50始於嵌入式重接線圖案層30的高度可大於下部半導體晶片40的高度。
或者，第13圖所繪示的製造製程及第14圖所繪示的製造製程可以顛倒的順序執行。
參照第15圖，形成下部封裝構件60，以封裝下部半導體晶片40及導電柱50。下部封裝構件60可封裝下部半導體晶片40，以防止其暴露。此外，下部封裝構件60可封裝嵌入式重接線圖案層30。下部封裝構件60可填充下部半導體晶片40的連接構件48之間的空隙。下部封裝構件60可包括一例如EMC的絕緣材料。
上部及下部封裝構件20及60可彼此連接，並封裝嵌入式重接線圖案層30，以防止其暴露。或者，嵌入式重接線圖案層30可經由上部封裝構件20及/或下部封裝構件60暴露。上部及下部封裝構件20及60可包括相同材料或相異材料。上部及下部封裝構件20及60可形成一單體結構。
或者，例如TSV的貫通電極可用來取代導電柱50。也就是說，在第12圖中，導電柱50可藉由下列步驟形成：在嵌入式重接線圖案層30上形成下部封裝構件60；部分地移除下部封裝構件60，以形成開口來暴露嵌入式重接線圖案層30的重接線圖案34；及以導電材料填充開口。
參照第16圖，下部封裝構件60可藉由拋光、回蝕製程或化學機械研磨(CMP)來平坦化，從而暴露出導電柱50。如上文所述，導電柱50始於嵌入式重接線圖案層30的高度可大於下部半導體晶片40的高度，且因此可使下部半導體晶片40嵌入，以便不經由下部封裝構件60暴露。
參照第17圖，外部重接線圖案層70係形成在下部封裝構件60之一下部表面上，並電連接至導電柱50。外部重接線圖案層70可包括第三絕緣層72、外部重接線圖案74、第四絕緣層76及外部焊墊78。舉例來說，第三絕緣層72係形成在下部封裝構件60之上，並部分移除，以暴露導電柱50。隨後，外部重接線圖案74係形成為電連接至暴露的導電柱50，並在第三絕緣層72之上延伸。外部重接線圖案74可使用例如沈積、電鍍等的各種方法形成。第四絕緣層76係形成在外部重接線圖案74之上，並部分移除，以部分地暴露出外部重接線圖案74。在後續的製造製程中，外部連接構件80(參見第18圖)可附接至外部重接線圖案74的暴露部分。可選擇地，外部焊墊78可進一步地形成在外部重接線圖案74的暴露部分之上。
同樣地，可將一先前製造的基材用作外部重接線圖案層70。在一些實施例中，外部重接線圖案層70可藉由沖壓、黏著或迴焊製程來黏著至導電柱50及下部封裝構件60。
參照第18圖，外部連接構件80係附接至外部重接線圖案層70，以電連接至此。外部連接構件80可附接至暴露的外部重接線圖案74或外部焊墊78。外部連接構件80可包括例如金屬的導電材料。外部連接構件80可為焊錫球。
接下來，移除第二載體基材18，從而完成第1圖之半導體封裝1的製造。
從上文敘述當明白，一半導體封裝包括半導體晶片，其係安裝在一嵌入式重接線圖案層的上部及下部側，其中的至少一個係嵌入一封裝構件中；及一外部重接線圖案層，其係形成在封裝構件之上，藉此使半導體晶片的尺寸不受限制，輸入及輸出端子可小型化，並可增加輸入及輸出端子的數目。
半導體封裝的後及側表面係完全由封裝構件覆蓋，且因此可保護其免於外部碰撞。封裝構件係形成為穿透嵌入式重接線圖案層，藉此可改善封裝構件的黏著強度。
雖然已顯示並敘述本發明的若干實施例，那些熟悉此項技術者須了解，在不偏離本發明之原理及精神的情況下，可在這些實施例中作出變化，其範圍係定義在申請專利範圍及其等同物中。
1．．．半導體封裝
2．．．半導體封裝
3．．．半導體封裝
4．．．半導體封裝
5．．．半導體封裝
6．．．半導體封裝
7．．．半導體封裝
8．．．半導體封裝
10．．．上部半導體晶片
10a．．．上部半導體晶片
12．．．上部半導體晶片墊
14．．．第一載體基材
16．．．黏著構件
17．．．黏著構件
18．．．第二載體基材
20．．．上部封裝構件
30．．．嵌入式重接線圖案層
30a．．．嵌入式重接線圖案層
32．．．第一絕緣層
34．．．重接線圖案
36．．．第二絕緣層
40．．．下部半導體晶片
40a．．．下部半導體晶片
42．．．下部半導體晶片墊
44．．．絕緣層
46．．．焊墊
48．．．連接構件
50．．．導電柱
50a．．．導電柱
60．．．下部封裝構件
70．．．外部重接線圖案層
72．．．第三絕緣層
74．．．外部重接線圖案
76．．．第四絕緣層
78．．．外部焊墊
80．．．外部連接構件
1．．．半導體封裝
10．．．上部半導體晶片
12．．．上部半導體晶片墊
20．．．上部封裝構件
30．．．嵌入式重接線圖案層
32．．．第一絕緣層
34．．．重接線圖案
36．．．第二絕緣層
40．．．下部半導體晶片
42．．．下部半導體晶片墊
44．．．絕緣層
46．．．焊墊
48．．．連接構件
50．．．導電柱
60．．．下部封裝構件
70．．．外部重接線圖案層
72．．．第三絕緣層
74．．．外部重接線圖案
76．．．第四絕緣層
78．．．外部焊墊
80．．．外部連接構件

Claims (12)

  1. 一種半導體封裝，其包括：
    一嵌入式重接線圖案層；
    一上部半導體晶片，其係配置在該嵌入式重接線圖案層的上方；
    一上部封裝構件，其封裝該上部半導體晶片；
    一下部半導體晶片，其係配置在該嵌入式重接線圖案層的下方；及
    一下部封裝構件，其封裝該下部半導體晶片，以防止其暴露。
  2. 如申請專利範圍第1項所述之半導體封裝，其進一步包括：
    一導電柱，其電連接至該嵌入式重接線圖案層；及
    外部連接構件，其電連接至該導電柱。
  3. 如申請專利範圍第2項所述之半導體封裝，其進一步包括一外部重接線圖案層，其係形成在該下部封裝構件之一下部表面上，並將該導電柱電連接至該外部連接構件。
  4. 如申請專利範圍第2項所述之半導體封裝，其中一些該外部連接構件係配置在該下部半導體晶片的下方。
  5. 如申請專利範圍第1項所述之半導體封裝，其中該上部封裝構件及該下部封裝構件係彼此連接，以封裝該嵌入式重接線圖案層來防止其暴露。
  6. 如申請專利範圍第1項所述之半導體封裝，其中該下部封裝構件穿透一部分的該嵌入式重接線圖案層，以連接至該上部封裝構件。
  7. 如申請專利範圍第1項所述之半導體封裝，其中該上部半導體晶片及該下部半導體晶片係經由該嵌入式重接線圖案層彼此電連接。
  8. 如申請專利範圍第1項所述之半導體封裝，其中該下部半導體晶片包括複數個下部半導體晶片。
  9. 如申請專利範圍第8項所述之半導體封裝，其進一步包括複數個導電柱，其電連接至該嵌入式重接線圖案層，並藉由該下部封裝構件嵌入，該導電柱包括一些配置在該下部半導體晶片間的導電柱。
  10. 如申請專利範圍第1項所述之半導體封裝，其中該上部半導體晶片包括複數個上部半導體晶片。
  11. 如申請專利範圍第1項所述之半導體封裝，其中該上部及下部半導體晶片具有相同尺寸。
  12. 一種製造半導體封裝的方法，該方法包含以下步驟：
    將一上部半導體晶片附接至一第一載體基材；
    形成一上部封裝構件，其封裝該上部半導體晶片；
    將一第二載體基材附接至該上部封裝構件；
    移除該第一載體基材，以暴露出該上部半導體晶片；
    在該已暴露的上部半導體晶片及該上部封裝構件上形成一嵌入式重接線圖案層；
    形成一導電柱，其電連接至該嵌入式重接線圖案層；
    在該嵌入式重接線圖案層的下方將一下部半導體晶片附接在一相對該上部半導體晶片的位置之中；
    形成一下部封裝構件，其封裝該下部半導體晶片及該導電柱；
    平坦化該下部封裝構件，以暴露出該導電柱；
    形成一外部重接線圖案層，其在該下部封裝構件上電連接至該導電柱；及
    附接一外部連接構件，以電連接至該外部重接線圖案層。
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TWI531044B (zh) 2016-04-21
US20140353823A1 (en) 2014-12-04
CN104025288A (zh) 2014-09-03
US9564411B2 (en) 2017-02-07
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