CN103119711A - 形成完全嵌入式非凹凸内建层封装件的方法和由此形成的结构 - Google Patents

形成完全嵌入式非凹凸内建层封装件的方法和由此形成的结构 Download PDF

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CN103119711A
CN103119711A CN2011800454704A CN201180045470A CN103119711A CN 103119711 A CN103119711 A CN 103119711A CN 2011800454704 A CN2011800454704 A CN 2011800454704A CN 201180045470 A CN201180045470 A CN 201180045470A CN 103119711 A CN103119711 A CN 103119711A
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tube core
packaging part
dielectric material
carrier
centreless
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CN103119711B (zh
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R·K·纳拉
M·J·曼努沙洛
P·马拉特卡
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Intel Corp
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Intel Corp
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Abstract

本发明描述了形成微电子封装结构的方法和由此形成的相关结构。那些方法可包括形成嵌入在无芯衬底中的管芯，其中模制复合物围住管芯并且管芯包括：在管芯第一侧上的TSV连接和在管芯第二侧上的C4焊盘，在模制复合物的第一侧和第二侧上的介电材料，以及耦合至C4焊盘和TSV焊盘的互连结构。各实施例进一步包括形成封装结构，其中多个管芯被完全地嵌入到BBUL封装件内而没有PoP焊点。

Description

形成完全嵌入式非凹凸内建层封装件的方法和由此形成的结构
发明背景
随着半导体技术因更高的处理器性能而发展，封装架构的发展可包括无芯非凹凸内建层(BBUL-C)封装件架构和其它这类组件。BBUL-C封装件的当前工艺流程涉及在由铜箔覆盖的临时芯层/载体上建立衬底，所述铜箔在封装件从芯层分离后被蚀刻除去。
附图说明
尽管说明书以特别指出和独立地要求本发明某些实施例的权利要求书作为结尾，但本发明的优势可从下面结合附图对本发明描述中得到更好的理解，在附图中：
图1a-1g表示形成根据本发明一实施例的结构的方法。
图2a-2j表示形成根据本发明一实施例的结构的方法。
具体实施方式
下面的详细描述参照附图，附图以解说方式示出本发明可投入实践的特定实施例。充分详细地描述这些实施例，以使本领域技术人员将这些实施例投入实践。要理解各实施例，尽管是不同的，但不一定是相互排斥的。例如，这里结合一个实施例描述的特定特征、结构或特性可在其它实施例中实现而不脱离实施例的精神和范围。另外要理解，可修正各公开实施例中的各个要素的位置或配置而不脱离实施例的精神和范围。因此，下面的详细描述不具有限定意义，并且各实施例的范围仅由适当解释的所附权利要求连同这些权利要求授权的等效物的全部范围来定义。在附图中，相同的附图标记贯穿若干附图地表示相同或相似的功能。
描述了形成和利用微电子封装结构的方法和相关结构，例如所述的完全嵌入式无芯BBUL封装件结构。那些方法可包括形成嵌入在无芯衬底中的管芯，其中模制复合物围住管芯并且管芯包括在管芯第一侧上的TSV连接和在管芯第二侧上的C4焊盘，其中介电材料被设置在模制复合物的第一侧和第二侧上，并且互连结构通过管芯两侧上的介电材料被耦合至C4焊盘和TSV焊盘。实施例的方法允许使用非凹凸内建层(BBUL)技术形成双侧的、完全内嵌式封装件。
实施例的方法和相关结构进一步包括形成内嵌在无芯衬底中的第一管芯、毗邻于第一管芯的第一介电材料以及嵌入在无芯衬底中的第二管芯，其中第二管芯被设置在第一管芯之上并且第二介电材料毗邻于第二管芯。互连结构进一步将第一管芯连接于无芯衬底外部上的焊料连接，其中无芯衬底不包括将第二管芯耦合至无芯封装件的PoP(封装件上的封装件)焊点。实施例的方法进一步使封装件结构成形，其中整个封装件完全由BBUL工艺制成，而不由涉及BBUL封装工艺和BGA/引线接合封装工艺的混合工艺制成。
图1a-1g示出形成微电子结构(例如封装件结构)的方法的实施例。图1a示出载体材料100。在一个实施例中，载体材料100可包括多层铜箔，该铜箔可充当临时载体，例如微电子管芯载体100。在其它实施例中，载体材料100可包括任何适当的导电载体材料100。在一实施例中，载体材料100可选择地包括粘合层102。
在一实施例中，管芯106可设置在载体材料100上，该载体材料100在一实施例中可包括临时管芯载体100。管芯106可包括受控塌陷芯片连接(C4)焊盘104和通硅通路(TSV)焊盘105。在一个实施例中，C4焊盘可设置在管芯106的第一侧103上，而TSV焊盘可设置在管芯106的第二侧101上。在管芯载体100上，管芯106可设置成使C4侧朝上，或者在其它实施例中，可使TSV焊盘105侧向上。在一个实施例中，粘合剂102可要么涂布在管芯106上要么涂布在载体100上。在一些情形下，可使用102粘合膜和/或附连工艺将管芯106附连至临时载体100。
在一个实施例中，可将模制复合物108施加至管芯106周围/嵌入管芯106(图1b)。在一个实施例中，可涂布和固化模制复合物108以过模制管芯106。可施加模制复合物108以使管芯106完全地嵌入到模制复合物108中。然后可去除模制复合物108的一部分以使C4焊盘104和TSV焊盘105露出(图1c)。在一实施例中，可执行模制复合物108的背面研磨以使C4焊盘104和TSV焊盘105露出，并可在背面研磨去除工艺中将临时载体100从管芯106去除。在一个实施例中，管芯106可在C4和TSV焊盘104、105露出之后保持完全地嵌入在模制复合物108中。模制复合物108可充当底部以随后形成根据本文实施例形成的微电子封装件结构的内建层，并进一步用来减小之后处理这种封装件结构期间的翘曲。剩余的模制复合物108可包括第一表面107和第二表面109。
介电材料110、110’可形成在围住管芯106的模制复合物108的第一表面107和第二表面109上(图1d)。在一实施例中，介电材料110、110’可例如通过层压工艺形成/附连。介电材料110、110’可为后继的内建工艺提供水平面。
在一实施例中，通路112形成在模制复合物108的第一表面107上的介电材料110内，以连接至管芯106的C4焊盘104，而通路112’也可形成在模制复合物108的第二表面109的介电材料110’内，以连接至管芯106的TSV焊盘105。通路112、112’可随后用导电材料113填充(图1e)。在一个实施例中，可使用半加性工艺(SAP)来形成互连结构114(该互连结构114可例如包括第一金属层)以连接性地耦合至管芯106上的C4焊盘104，并也可形成互连结构114’以连接性地耦合至管芯106的TSV焊盘105。在一实施例中，互连结构114可设置在模制复合物108的第一表面107上并可通过导电通路113连接至C4焊盘104。互连结构114’可设置在模制复合物108的第二表面109上并可通过导电通路113’连接至TSV焊盘105。
后继的层可例如使用SAP内建工艺来形成，其中可根据具体设计需求在彼此之上形成诸如介电层110”、110’’’的介电层、导电通路113”、113’’’以及互连结构114”、114’’’，以通过利用内建工艺来形成无芯封装件结构120(图1f)。在一实施例中，无芯封装件结构120可包括BBUL无芯封装件结构120，而管芯106可完全地内嵌到无芯封装件结构120中。
在一实施例中，无芯封装件结构120可包括在管芯106两侧上的双侧封装件120，管芯106被嵌入在模制复合物108中。
在一实施例中，可使用阻焊剂116、116’形成开口118、118’以连接性地耦合至在封装件结构120的最外层上的C4和/或TSV焊盘104、105。在一实施例中，可使用阻焊剂使封装件结构120的最外层上的焊盘向上开口。在一个实施例中，焊球122可形成在开口118’(和/或118)中以耦合至管芯106(图1g)。在一个实施例中，焊球122可包括球栅阵列(BGA)球122，它可附连至封装件结构120。在一实施例中，可通过开口118(和/或118’，回头参见图1g)将附加管芯和/或封装件124附连/耦合至无芯封装件结构120的外部。在另一实施例中，例如可贯穿介电层地形成贯通模制通路(未示出)以增加对无芯封装件结构120的供电。
因此，实现了使用BBUL技术制造双侧的完全嵌入式封装件结构的方法。在层叠的管芯/封装件应用中可利用无芯封装件结构120。由于模制复合物的存在，各实施例提供更坚固的封装件结构，并实现完全嵌入式管芯解决方案，由此减少封装件的Z高度。各实施例在改善翘曲的同时进一步利于对层叠的封装件应用的TSV集成，同时提供底部封装件和层叠的封装件的同时处理。各实施例允许图形处理器、无线CPU/处理器、芯片集多芯片/3D封装件结构/系统——包括CPU结合其它器件，例如存储器(例如闪存/DRAM/SRAM/等)以及例如主板的板——的封装、组装和/或测试方案。
图2a-2j示出形成微电子结构(例如BBUL封装件结构)的方法的实施例。图2a示出载体材料200。在一个实施例中，载体材料200可包括多层铜箔，该铜箔可充当载体，例如微电子管芯载体。在其它实施例中，载体材料200可包括任何适当的导电载体材料200。在一实施例中，载体材料200可包括粘合层202，例如管芯背侧膜(DBF)，它可事先附连于载体200的第一侧201和载体的第二侧203。
诸如第一存储器管芯206的第一管芯206可例如使用事先附连的DBF202被安装/附连至载体200的第一侧201。例如第二存储器管芯206’的第二管芯可例如使用事先附连的DBF202被安装在载体200的第二侧203上。第一和第二管芯206、206’可包括导电结构204、204’，所述导电结构204、204’各自例如包括C4互连结构204、204’。介电材料210可设置在/层压在载体200的第一侧201(图2b)。介电材料210’可被设置在/层压在载体203的第二侧上，以使第一管芯206和第二管芯206’分别完全地嵌入到介电材料210、210’内。在一实施例中，第一存储器管芯206在BBUL工艺中可充当第一嵌入式管芯206。
通路212、212’可例如通过UV/CO2激光器贯穿介电材料210、210’地形成，从而使管芯206、206’上的导电结构204、204’露出(图2c)。
通路212、212’可随后用导电材料213、213’填充(图2d)。在一实施例中，可使用半加性工艺(SAP)来形成互连结构214(该互连结构例如可包括第一金属层)以可连接性地耦合至第一管芯206上的C4焊盘204。也可形成互连结构214’以连接性地耦合至第二管芯206’的C4焊盘204’。在一实施例中，互连结构214可设置在介电材料210上/上方和第一管芯206上/上方，并可通过导电通路213耦合至C4焊盘204。互连结构214’可设置在介电材料210’上/上方和第二管芯206’上/上方，并可通过导电通路213’耦合至C4焊盘204’。
然后可例如使用SAP内建工艺形成后继的层，其中可利用SAP内建工艺根据具体应用的设计需求在彼此之上形成进一步的介电材料210”、210’’’、导电通路213”、213’’’以及互连结构214”、214’’’(图2e)。在一实施例中，例如CPU管芯216的第三管芯216可被安装/附连至第一管芯206上方，或载体200的第一表面201上/上方。例如可包括CPU管芯的第四管芯216’可被附连/安装在第二管芯206’上方(图2f)。附加的介电材料211、211’可分别围绕第三管芯216和第四管芯216’地形成。后继的层则可例如使用SAP内建处理来形成，其中可根据具体设计需求在彼此之上形成附加的导电通路213”、213’’’以及互连结构214’、214”’(图2g)。在一实施例中，可根据具体应用在第三和第四管芯216、216’上形成进一步的通路和金属化层，其中可利用SAP内建工艺形成多于两级的金属化。
在一实施例中，可使用阻焊剂216、216’/将其布图在第三和第四管芯216、216’上/上方以使焊盘215、215’向上开口(图2h)。在一实施例中，第一管芯206和第三管芯216可沿临时载体200与第二管芯206’和第四管芯216’分离以形成第一封装件结构220和第二封装件结构220’。在一实施例中，第一和第三管芯206、216可包括第一BBUL封装件结构220，其在从载体200分离之后没有封装件上封装件(PoP)焊点。在一实施例中，第二和第四管芯206’、216’可包括另一第二BBUL封装件220’，其在从载体200分离之后没有PoP焊点。
在一实施例中，焊球222可形成在焊盘215上以耦合至第一封装件220的管芯206、216(图2i)。焊球222’可形成在焊盘215’上，以耦合至第二封装件上的管芯206’、216’(未示出)。在一实施例中，焊球222可包括球栅阵列(BGA)球222，它可附连至封装件结构220。因此，其中没有PoP焊点的BBUL封装件结构220可包括BBUL无芯封装件结构220，而第一和第二管芯206、206’可完全地内嵌在无芯BBUL封装件结构220中。
在一实施例中，例如第五管芯221和第六管芯221’的附加管芯可分别形成在第一封装件220中的第一管芯206和第二封装件220’中的第三管芯206’(未示出)的毗邻位置(图2j，其示出第一封装件220)。在一实施例中，第五管芯221可被设置在载体200的第一侧上的介电材料210中，而第六管芯221’可被设置在第二封装件220’的载体200的第二侧上的介电材料210’中(未示出)。
因此，本文包含的实施例包括BBUL工艺和结构，其中多个管芯被完全地内嵌在BBUL封装件之内。在一实施例中，例如顶部存储器管芯的顶部管芯可以是本文实施例的BBUL工艺中的第一嵌入式管芯。本文实施例的优点包括最终封装件的总处理成本减少，由于PoP衬底和CAM步骤(例如将存储器管芯附连至PoP封装件)的去除。包含BBUL封装件的最终“纯的”非PoP焊点的总Z高度得以减小。PoP封装件焊料接点可靠性问题(可能由于铜PoP焊区的定位缺乏)得以消除。此外，通过内嵌式叠层管芯，本文中各实施例的BBUL封装件结构减少了翘曲，由此提高了表面安装至主板期间的生产率。本文中各实施例的整个封装件完全通过BBUL工艺单独制成，而不像现有技术工艺/结构中通过包含BBUL封装件处理和BGA/线接合封装件处理的组合的混合工艺制成。
现有技术的BBUL封装件事实上可包括BBUL封装件和PoP封装件的组合，其中PoP封装件被表面安装到BBUL上。也就是说，在现有技术中只有下层封装件是BBUL工艺/封装件，而顶部PoP封装件是非BBUL封装件，PoP部分中的顶部管芯不被完全地嵌入到BBUL封装件内。本文的实施例完全消除了PoP封装件。各实施例对CPU/处理器、包含CPU以及其它器件、存储器(例如闪存、DRAM/、RAM/等)、板(例如主板等)的芯片集多芯片/3D封装件提供封装、组装和/或测试方案。
尽管前面的说明书具有可用于本发明方法中的某些特定步骤和材料，然而本领域内技术人员将理解，可作出许多修正和替代。因此，所有这些修正、改变、替代和添加都应当被认为是落在本发明由所附权利要求书定义的精神和范围内。另外要理解，诸如封装件结构的各种微电子结构是本领域内技术人员熟知的。因此，本文给出的附图仅示出与本发明的实践相关的示例性微电子器件的一部分。因此，本发明不仅限于本文描述的结构。

Claims (24)

1.一种方法，包括：
将第一管芯附连至载体的第一侧；
将第二管芯附连至所述载体的第二侧；
在所述载体的所述第一侧上形成介电材料以及在所述载体的所述第二侧上形成介电材料；
贯穿所述载体的所述第一侧上的介电材料形成通路连接和互连结构以连接于所述第一管芯，并贯穿所述第二侧上的介电材料形成通路连接和互连结构以连接于所述第二管芯；
将第三管芯附连在所述载体的所述第一侧上的介电材料上，并将第四管芯附连在所述载体的所述第二侧上的介电材料上；
在所述第三管芯上形成附加的介电材料和互连结构并在所述第四管芯上形成附加的介电材料和互连结构；以及
沿所述载体将所述第一和第三管芯从所述第二和第四管芯分离以形成两个独立的封装件结构。
2.如权利要求1所述的方法，其特征在于，还包括将所述第一和第三管芯完全地嵌入到第一封装件中，并将所述第二和第四管芯完全地嵌入到第二封装件中。
3.如权利要求2所述的方法，其特征在于，所述第一和第二封装件不包括PoP焊点。
4.如权利要求1所述的方法，其特征在于，所述第一和第二管芯包括存储器管芯。
5.如权利要求1所述的方法，其特征在于，所述第一和第二管芯包括CPU管芯。
6.如权利要求4所述的方法，其特征在于，还包括将第五管芯附连成毗邻于所述载体的第一侧上的介电材料上的所述第三管芯，并将第六管芯附连成毗邻于所述载体的第二侧上的介电材料上的所述第四管芯。
7.如权利要求1所述的方法，其特征在于，所述载体材料包括铜。
8.如权利要求1所述的方法，其特征在于，所述两个封装件中的每一个包括无芯非凹凸内建层封装件。
9.一种形成封装件结构的方法，包括：
将管芯附连至载体材料；
在所述管芯上方形成模制复合物；
去除一部分模制物以使所述管芯的第一侧和第二侧上的焊盘露出；
在所述模制复合物的第一表面和第二表面上形成介电材料；
通过在设置在所述模制复合物的所述第一和第二表面上的介电材料上建立层以形成无芯衬底。
10.如权利要求9所述的方法，其特征在于，还包括：
形成通路和互连以连接至所述管芯的所述第一侧和第二侧上的焊盘。
11.如权利要求9所述的方法，其特征在于，所述结构包括双侧封装件，并且所述管芯被完全地嵌入到所述双侧封装件中。
12.如权利要求9所述的方法，其特征在于，所述结构包括无芯非凹凸内建层封装件的一部分，并且第二管芯被附连至所述封装件。
13.如权利要求10所述的方法，其特征在于，所述管芯包括在所述管芯的第一侧上的TSV焊盘以及在所述管芯的第二侧上的C4焊盘。
14.一种结构，包括：
内嵌到无芯衬底中的管芯，其中模制复合物围住所述管芯并且所述管芯包括在所述管芯的第一侧上的TSV连接和在所述管芯的第二侧上的C4焊盘；
在所述模制复合物的第一侧和第二侧上的介电材料；以及
耦合至所述C4焊盘和所述TSV焊盘的互连结构。
15.如权利要求14所述的结构，其特征在于，所述结构包括双侧封装件，并且所述管芯被完全地嵌入到所述双侧封装件中。
16.如权利要求14所述的结构，其特征在于，所述结构包括无芯非凹凸内建层封装件的一部分。
17.如权利要求16所述的结构，其特征在于，第二管芯和第二封装件中的至少一者被附连至所述封装件的外部。
18.如权利要求14所述的结构，其特征在于，焊料互连结构被耦合至所述封装件外部上的管芯。
19.一种结构，包括：
内嵌在无芯衬底中的第一管芯；
毗邻于所述第一管芯的第一介电材料；
内嵌在所述无芯衬底中的第二管芯，所述第二管芯被设置在所述第一管芯上方；
毗邻于所述第二管芯的第二介电材料；
将所述第一管芯连接于所述无芯衬底外部上的焊料连接的互连结构，所述无芯衬底不包括将所述第二管芯耦合至所述无芯封装件的PoP焊点。
20.如权利要求19所述的结构，其特征在于，所述第一和第二管芯被完全地嵌入到所述无芯封装件中。
21.如权利要求19所述的结构，其特征在于，所述无芯衬底包括无芯非凹凸内建封装件结构的一部分。
22.如权利要求19所述的结构，其特征在于，所述第一管芯包括存储器管芯。
23.如权利要求19所述的结构，其特征在于，所述第二管芯包括CPU管芯。
24.如权利要求19所述的结构，其特征在于，至少一个附加管芯毗邻所述第二管芯地被设置在所述第一管芯上方，所述至少一个附加管芯不通过PoP焊点附连至封装件并且所述至少一个附加管芯完全地嵌入到所述封装件中。
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