CN108573934B - 半导体装置封装及其制造方法 - Google Patents

半导体装置封装及其制造方法 Download PDF

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CN108573934B
CN108573934B CN201710896445.6A CN201710896445A CN108573934B CN 108573934 B CN108573934 B CN 108573934B CN 201710896445 A CN201710896445 A CN 201710896445A CN 108573934 B CN108573934 B CN 108573934B
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layer
molding
electronic component
circuit layer
semiconductor device
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CN108573934A (zh
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陈天赐
陈光雄
王圣民
王奕程
许文政
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

一种半导体装置封装，其包含：第一电路层、至少一个电子组件、第一模制层、电子组件和第二模制层。所述至少一个电子组件安置在所述第一电路层的第一表面上方并且电连接到所述第一电路层。所述第一模制层安置在所述第一电路层的所述第一表面上方。所述第一模制层囊封所述至少一个电子组件的边缘，并且所述第一模制层的下表面和所述至少一个电子组件的下表面是基本上共平面的。所述电子组件安置在所述第一电路层的第二表面上方并且电连接到所述第一电路层。所述第二模制层安置在所述第一电路层的第二表面上方并且囊封所述电子组件。

Description

半导体装置封装及其制造方法
技术领域
本发明涉及半导体装置封装及其制造方法，并且更确切地说涉及包含安置在电路层的两个相对表面上方的具有不同热膨胀系数的两个模制层的半导体装置封装及其制造方法。
背景技术
三维(3D)半导体装置封装可以经受翘曲，这是由于其在结构性层之间的不对称结构和特性失配，例如，热膨胀系数(CTE)的失配。
为了缓解翘曲，可增加半导体封装的厚度。然而，半导体装置封装的厚度的增大带来了与电子产品大小的最小化趋势的冲突。
发明内容
在一些实施例中，半导体装置封装包含：第一电路层、至少一个电子组件、第一模制层、电子组件和第二模制层。第一电路层包含第一表面以及与第一表面相对的第二表面。至少一个电子组件安置在第一电路层的第一表面上方并且电连接到第一电路层。第一模制层安置在第一电路层的第一表面上方。第一模制层囊封至少一个电子组件的边缘，并且第一模制层的下表面和至少一个电子组件的下表面是基本上共平面的。电子组件安置在第一电路层的第二表面上方并且电连接到第一电路层。第二模制层安置在第一电路层的第二表面上方并且囊封电子组件。
在一些实施例中，半导体装置封装包含：第一电路层、至少一个电子组件、第一模制层、电子组件和第二模制层。第一电路层包含第一表面以及与第一表面相对的第二表面。至少一个电子组件安置在第一电路层的第一表面上方并且电连接到第一电路层。第一模制层安置在第一电路层的第一表面上方。第一模制层囊封至少一个电子组件。电子组件安置在第一电路层的第二表面上方并且电连接到第一电路层。第二模制层安置在第一电路层的第二表面上方并且囊封电子组件。第一模制层的热膨胀系数(CTE)不同于第二模制层的CTE。
在一些实施例中，制造半导体装置封装的方法包含：在载体上方安置至少一个电子组件；在载体上方安置第一模制层以囊封至少一个电子组件；在第一模制层和至少一个电子组件上方安置第一电路层；在第一电路层上方安置电子组件；以及在第一电路层上方安置第二模制层以囊封电子组件。
附图说明
当结合附图阅读时，从以下具体实施方式最好地理解本发明的一些实施例的方面。应注意，各种结构可能未按比例绘制，且各种结构的尺寸可出于论述的清楚起见而任意增大或减小。
图1是根据本发明的一些实施例的半导体装置封装的截面图；
图2A、图2B、图2C、图2D、图2E、图2F、图2G和图2H说明根据本发明的一些实施例的半导体装置封装的制造方法的实例；
图3是根据本发明的一些实施例的半导体装置封装的截面图；
图4A、图4B、图4C、图4D、图4E和图4F说明根据本发明的一些实施例的半导体装置封装的制造方法的实例；
图5是根据本发明的一些实施例的半导体装置封装的截面图；以及
图6A、图6B、图6C和图6D说明根据本发明的一些实施例的半导体装置封装的制造方法的实例。
具体实施方式
以下揭示内容提供用于实施所提供的标的物的不同特征的许多不同实施例或实例。下文描述组件和布置的具体实例以解释本发明的某些方面。当然，这些仅仅是实例且并不意图为限制性的。举例来说，在以下描述中，第一特征在第二特征上方或第二特征上的形成可包含第一特征和第二特征直接接触地形成或安置的实施例，并且还可包含额外特征可在第一特征与第二特征之间形成或安置使得第一特征和第二特征可不直接接触的实施例。此外，本发明可在各种实例中重复参考标号和/或字母。此重复是出于简单和清楚的目的，且本身并不指示所论述的各种实施例和/或配置之间的关系。
除非另外说明，否则例如“上方”、“下方”、“上”、“左”、“右”、“下”、“顶部”、“底部”、“垂直”、“水平”、“侧面”、“高于”、“低于”、“上部”、“在……上方”、“在……之下”等等的空间描述是相对于图中所示的取向来指示的。应理解，本文中所使用的空间描述仅是出于说明的目的，且本文中所描述的结构的实际实施方案可以任何取向或方式在空间上布置，其限制条件为本发明的实施例的优点不因此布置而有偏差。
以下描述涉及半导体装置封装。在一些实施例中，半导体装置封装包含：电路层，其具有第一表面和第二表面；电子组件，其在第一表面上方；第一模制层，其在第一表面上方；电气组件，其在第二表面上方；以及第二模制层，其在第二表面上方，其中电子组件的下表面和第一模制层的下表面是基本上共平面的。在一些实施例中，第一模制层的热膨胀系数(CTE)不同于第二模制层的CTE。以下描述还涉及制造半导体装置封装的方法，如下文所论述。
图1是根据本发明的一些实施例的半导体装置封装1的截面图。如图1中所示，半导体装置封装1包含第一电路层20、至少一个电子组件12、第一模制层14、一或多个电子组件24和第二模制层28。第一电路层20包含第一表面201以及与第一表面201相对的第二表面202。在一些实施例中，第一电路层20包含再分布层(RDL)，所述再分布层经配置以重新布置电子组件24的输入/输出(I/O)触点。在一些实施例中，第一电路层20包含堆叠在彼此上的一或多个导电布线层和一或多个介电层。在一些实施例中，接近第一表面201或第二表面202的导电布线层被配置为接合垫，例如，突块下金属层(UBM)。
至少一个电子组件12安置在第一电路层20的第一表面201上方并且电连接到第一电路层20。在一些实施例中，电子组件12包含导电柱、导电桩、导电垫或类似物。电子组件12的材料包含例如铜或类似物的金属、例如铜合金的合金或任何其它合适的导电材料。
第一模制层14安置在第一电路层20的第一表面201上方，并且第一模制层14囊封至少一个电子组件12。在一些实施例中，第一模制层14囊封至少一个电子组件12的边缘12E，但是暴露至少一个电子组件12的下表面12B。在一些实施例中，第一模制层14的下表面14B和至少一个电子组件12的下表面12B基本上共平面。在一些实施例中，第一模制层14包含填充物14F，并且第一模制层14中的填充物14F中的至少一个具有邻近于第一模制层14的下表面14B的切割平面。
电子组件24安置在第一电路层20的第二表面202上方并且电连接到第一电路层20。在一些实施例中，电子组件24包含半导体裸片，所述半导体裸片包含形成或安置于其中的集成电路(IC)。在一些实施例中，电子组件24包含(但不限于)：有源组件，例如，专用IC(ASIC)；存储器组件，例如，高带宽存储器(HBM)组件或另一有源组件；和/或无源组件，例如，电容器、电感器、电阻器或类似物。在一些实施例中，电子组件24是通过贴片技术(SMT)安装在第一电路层20的第二表面202上的倒装芯片组件。借助于实例，在一些实施例中，电子组件24经由导电凸块23(例如，焊料凸块、焊料球、焊料膏或类似物)接合在第二表面202上。
第二模制层28安置在第一电路层20的第二表面202上方并且囊封电子组件24。在一些实施例中，第二模制层28覆盖电子组件24的边缘和上表面。
在一些实施例中，第一模制层14的CTE不同于第二模制层28的CTE。第一模制层14的CTE与第二模制层28的CTE之间的关系经配置以匹配以便缓解翘曲。在一些实施例中，第一模制层14的CTE大于第二模制层28的CTE。第一模制层14与第二模制层28之间的CTE差异可以通过选择不同类型或材料的第一模制层14和第二模制层28、通过选择不同材料或大小的第一模制层14和第二模制层28的填充物或通过其它合适的方法来实施。在一些实施例中，第一模制层14和第二模制层28选自不同的模制化合物，例如，薄膜模制化合物、液体模制化合物或粒状模制化合物，以便具有不同CTE。借助于实例，在一些实施例中，第一模制层14是薄膜模制化合物，并且第二模制层28是液体模制化合物或粒状模制化合物。在一些实施例中，第一模制层14和第二模制层28包含不同模制材料。借助于实例，在一些实施例中，第一模制层14包含味之素累积薄膜(ABF)，并且第二模制层28的材料包含联二苯。在一些实施例中，第一模制层14的填充物14F和第二模制层28的填充物28F在材料上是不同的。借助于实例，在一些实施例中，第一模制层14的填充物14F包含氧化铝填充物，并且第二模制层28的填充物28F包含氧化硅填充物。在一些实施例中，第一模制层14的填充物14F和第二模制层28的填充物28F在大小上是不同的。借助于实例，在一些实施例中，第一模制层14的填充物14F的大小大于第二模制层28的填充物28F的大小。
在一些实施例中，底部填充层25填充在电子组件24与第一电路层20之间。在一些实施例中，第二模制层28被配置为模制底部填充(MUF)层，并且填充在电子组件24与第一电路层20之间。
在一些实施例中，半导体装置封装1进一步包含安置在第二模制层28上方的第二电路层30。在一些实施例中，第二电路层30包含RDL。在一些实施例中，第二电路层30包含堆叠在彼此上的一或多个导电布线层和一或多个介电层。在一些实施例中，半导体装置封装1进一步包含安置在第一电路层20与第二电路层30之间的至少一个互连件22。在一些实施例中，互连件22通过第二模制层28囊封，并且电连接到第一电路层20和第二电路层30。在一些实施例中，互连件22的材料包含例如铜或类似物的金属、例如铜合金的合金，或任何其它合适的导电材料。
在一些实施例中，半导体装置封装1进一步包含至少一个电触点32，所述电触点安置在电子组件12上方并且电连接到电子组件12。在一些实施例中，电触点32包含例如焊料凸块、焊料球、焊膏或类似物的导电凸块，经配置以电连接到例如电路板或类似物的另一电子装置。
图2A、图2B、图2C、图2D、图2E、图2F、图2G和图2H说明根据本发明的一些实施例的半导体装置封装1的制造方法的实例。如图2A中所描绘，至少一个电子组件12形成或安置在载体10上方。载体10被配置为临时固持器，并且随后将被移除。在一些实施例中，载体10是晶片，例如，半导体晶片。电子组件12的下表面12B面向载体10。在一些实施例中，电子组件12通过电镀、沉积或其它合适的方法形成或安置在载体10上方。如图2B中所描绘，第一模制层14安置在载体10上方以囊封至少一个电子组件12。在一些实施例中，第一模制层14通过模制、附接或通过其它合适的方法安置。在一些实施例中，第一模制层14覆盖电子组件12的边缘12E和上表面。
如图2C中所描绘，第一模制层14的一部分被移除，例如，通过研磨，以暴露至少一个电子组件12的上表面12A，并且随后第一电路层20形成或安置在第一模制层14和至少一个电子组件12的上表面12A上方。第一电路层20包含：第一表面201，其面向且电连接到电子组件12；以及第二表面202，其与第一表面201相对。在一些实施例中，至少一个互连件22形成或安置在第一电路层20的第二表面202上方并且电连接到第一电路层20，如图2D中所描绘。在一些实施例中，互连件22通过电镀、沉积或通过其它合适的方法形成或安置在第一电路层20上方。
如图2E中所描绘，一或多个电子组件24形成或安置在第一电路层20上方并且电连接到第一电路层20。在一些实施例中，电子组件24经由导电凸块23接合在第一电路层20的第二表面202上。在一些实施例中，底部填充层25填充在电子组件24与第一电路层20之间以保护导电凸块23。
如图2F中所描绘，第二模制层28安置在第一电路层20上方以囊封电子组件24。在一些实施例中，第二模制层28通过模制、附接或通过其它合适的方法安置。在一些实施例中，第二模制层28的一部分被移除，例如，通过研磨，以暴露互连件22。
在一些实施例中，第二电路层30形成或安置在第二模制层28和至少一个互连件22上方，如图2G中所描绘。在一些实施例中，第二电路层30通过互连件22电连接到第一电路层20。如图2H中所描绘，载体10被从第一电路层20中移除。在一些实施例中，第一模制层14的一部分和至少一个电子组件12的一部分被移除，例如，通过研磨，以暴露至少一个电子组件12的下表面12B。因此，至少一个电子组件12的下表面12B和第一模制层14的下表面14B基本上共平面，并且第一模制层14中的填充物14F中的至少一个具有邻近于第一模制层14的下表面14B的切割平面。
在一些实施例中，至少一个电触点32形成或安置在至少一个电子组件12的下表面12B上方以形成半导体装置封装1，如图1中所示。
本发明的半导体装置封装和制造方法不限于上述实施例，并且可以包含其它不同实施例。为了简化对本发明的实施例中的每一个之间的比较的描述以及比较的便利性，用相同编号来标记以下实施例中的每一个中的相同组件。
图3是根据本发明的一些实施例的半导体装置封装2的截面图。如图3中所示，不同于半导体装置封装1，电子组件24通过粘合剂层21(例如，裸片附接薄膜(DAF))接合到第一电路层20的第二表面202。在一些实施例中，电子组件24包含导体24C，例如，在与邻近于粘合剂层21的表面相对的电子组件24的上表面上并且电连接到第二电路层30的导电桩或导电衬垫。电子组件24通过第二电路层30和互连件22电连接到第一电路层20。在一些实施例中，半导体装置封装2进一步包含堆叠在第二电路层30上方并且电连接到第二电路层30的封装40。封装40可以是任何类型的半导体装置封装或IC。在一些实施例中，封装40包含安置在第二电路层30上方并且电连接到第二电路层30的至少一个互连件22'和一或多个电子组件42。在一些实施例中，电子组件42通过导电凸块44接合在第二电路层30上。在一些实施例中，底部填充层46填充在电子组件42与第二电路层30之间以保护导电凸块44。在一些实施例中，第三模制层48安置在第二电路层30上方以囊封电子组件42。在一些实施例中，第三模制层48暴露互连件22，以与另一装置连接。
在一些实施例中，第一模制层14、第二模制层28和第三模制层48具有不同的CTE。第一模制层14的CTE、第二模制层28的CTE和第三模制层48的CTE经配置以匹配以便缓解翘曲。在一些实施例中，第一模制层14的CTE大于第二模制层28的CTE，并且第二模制层28的CTE大于第三模制层48的CTE。第一模制层14、第二模制层28和第三模制层48之中的CTE差异可以通过选择不同类型或材料的第一模制层14、第二模制层28和第三模制层48、通过选择不同材料或大小的第一模制层14、第二模制层28和第三模制层48的填充物或通过其它合适的方法实施。在一些实施例中，第一模制层14、第二模制层28和第三模制层48选自不同的模制化合物，例如，薄膜模制化合物、液体模制化合物或粒状模制化合物以便具有不同的CTE。借助于实例，在一些实施例中，第一模制层14是薄膜模制化合物，第二模制层28是液体模制化合物，并且第三模制层48是粒状模制化合物。在一些实施例中，第一模制层14、第二模制层28和第三模制层48的填充物在材料上是不同的。在一些实施例中，第一模制层14、第二模制层28和第三模制层48的填充物在大小上是不同的。借助于实例，在一些实施例中，第一模制层14的填充物的大小大于第二模制层28的填充物的大小，并且第二模制层28的填充物的大小大于第三模制层48的填充物的大小。
图4A、图4B、图4C、图4D、图4E和图4F说明根据本发明的一些实施例的半导体装置封装2的制造方法的实例。如图4A中所描绘，至少一个电子组件12形成或安置在载体10上方。电子组件12的下表面12B面向载体10。在一些实施例中，电子组件12通过电镀、沉积或其它合适的方法形成或安置在载体10上方。如图4B中所描绘，第一模制层14安置在载体10上方以囊封至少一个电子组件12。在一些实施例中，第一模制层14通过模制、附接或通过其它合适的方法安置。在一些实施例中，第一模制层14覆盖电子组件12的边缘12E和上表面。
如图4C中所描绘，第一模制层14的一部分被移除，例如，通过研磨，以暴露至少一个电子组件12的上表面12A，并且随后第一电路层20形成或安置在第一模制层14和至少一个电子组件12上方。在一些实施例中，至少一个互连件22形成或安置在第一电路层20的第二表面202上方并且电连接到第一电路层20。在一些实施例中，互连件22通过电镀、沉积或通过其它合适的方法形成或安置在第一电路层20上方。
如图4D中所描绘，一或多个电子组件24形成或安置在第一电路层20上方。在一些实施例中，电子组件24经由例如DAF的粘合剂层21接合到第一电路层20的第二表面202。电子组件24包含在与邻近于粘合剂层21的表面相对的电子组件24的上表面上的导体24C，例如，导电桩或导电衬垫。随后，第二模制层28安置在第一电路层20上方以囊封电子组件24和互连件22。在一些实施例中，第二模制层28通过模制、附接或通过其它合适的方法安置。在一些实施例中，第二模制层28的一部分被移除，例如，通过研磨，以暴露互连件22和导体24C。
在一些实施例中，第二电路层30形成或安置在第二模制层28和至少一个互连件22上方，如图4E中所描绘。在一些实施例中，第二电路层30通过互连件22电连接到第一电路层20。在一些实施例中，第二电路层30通过导体24C电连接到电子组件24。
如图4F中所描绘，至少一个互连件22'安置在第二电路层30上方并且电连接到第二电路层30，并且随后一或多个电子组件42形成或安置在第二电路层30上方并且电连接到第二电路层30。在一些实施例中，电子组件42通过导电凸块44接合在第二电路层30上。在一些实施例中，底部填充层46填充在电子组件42与第二电路层30之间以保护导电凸块44。第三模制层48安置在第二电路层30上方以囊封电子组件42。在一些实施例中，第三模制层48通过模制、附接或通过其它合适的方法安置。在一些实施例中，第三模制层48的一部分被移除，例如，通过研磨，以暴露互连件22'以与另一装置连接。
在一些实施例中，至少一个互连件22'、电子组件42、导电凸块44、底部填充层46和第三模制层48可以是预先成形的封装40以安置在第二电路层30上方并且电连接到第二电路层30。载体10被从第一电路层20中移除。在一些实施例中，第一模制层14的一部分和至少一个电子组件12的一部分被移除，例如，通过研磨，以暴露至少一个电子组件12的下表面12B。因此，至少一个电子组件12的下表面12B和第一模制层14的下表面14B基本上共平面，并且第一模制层14中的填充物中的至少一个具有邻近于第一模制层14的下表面14B的切割平面。在一些实施例中，至少一个电触点32形成或安置在至少一个电子组件12的下表面12B上方以形成半导体装置封装2，如图3中所示。
图5是根据本发明的一些实施例的半导体装置封装3的截面图。如图5中所示，半导体装置封装3包含电路层70、电子组件54、至少一个互连件52和第一模制层56。电路层70包含第一表面701以及与第一表面701相对的第二表面702。在一些实施例中，电路层70包含RDL。电子组件54安置在第一表面701上方并且电连接到电路层70。在一些实施例中，电子组件54是通过SMT安装在电路层70的第一表面701上的倒装芯片组件。借助于实例，在一些实施例中，电子组件54经由导电凸块53(例如，焊料凸块、焊料球、焊料膏或类似物)接合到第一表面701。互连件52安置在第一表面701上方并且电连接到电路层70。第一模制层56安置在电路层70的第一表面701上方。在一些实施例中，第一模制层56囊封互连件52和电子组件54。
在一些实施例中，半导体装置封装3进一步包含安置在电路层70的第二表面702上方并且电连接到电路层70的封装60。封装60可以是任何类型的半导体装置封装或IC。在一些实施例中，封装60包含安置在电路层70上方并且电连接到电路层70的至少一个互连件62和一或多个电子组件64。在一些实施例中，电子组件64经由导电凸块66接合到电路层70。在一些实施例中，底部填充层67填充在电子组件64与电路层70之间以保护导电凸块66。在一些实施例中，第二模制层68安置在电路层70上方以囊封电子组件64。在一些实施例中，第二模制层68暴露互连件62以与另一装置连接。在一些实施例中，半导体装置封装3进一步包含安置在封装60上方并且通过封装60的互连件62电连接到电路层70的至少一个电触点72。在一些实施例中，电触点72包含例如焊料凸块、焊料球、焊膏或类似物的导电凸块，经配置以电连接到例如电路板或类似物的另一电子装置。
在一些实施例中，第一模制层56和第二模制层68具有不同CTE。第一模制层56和第二模制层68的CTE经配置以匹配以便缓解翘曲。在一些实施例中，第二模制层68的CTE大于第一模制层56的CTE。第一模制层56与第二模制层68之间的CTE差异可以通过选择不同类型或材料的第一模制层56和第二模制层68、通过选择第一模制层56和第二模制层68的不同材料或大小的填充物或通过其它合适的方法来实施。在一些实施例中，第一模制层56和第二模制层68选自不同的模制化合物，例如，薄膜模制化合物、液体模制化合物或粒状模制化合物，以便具有不同CTE。借助于实例，在一些实施例中，第一模制层56是粒状模制化合物或液体模制化合物，并且第二模制层68是液体模制化合物或薄膜模制化合物。在一些实施例中，第一模制层56和第二模制层68包含不同模制材料。在一些实施例中，第一模制层56和第二模制层模制层68的填充物在材料上是不同的。在一些实施例中，第一模制层56和第二模制层68的填充物在大小上是不同的。借助于实例，在一些实施例中，第二模制层68的填充物的大小大于第一模制层56的填充物的大小。
图6A、图6B、图6C和图6D说明根据本发明的一些实施例的半导体装置封装3的制造方法的实例。如图6A中所描绘，至少一个互连件52形成或安置在载体50上方。如图6B中所描绘，电子组件54形成或安置在载体50上方。在一些实施例中，电子组件54经由粘合剂层51接合到载体50。在一些实施例中，电子组件54包含在与邻近于粘合剂层51的表面相对的电子组件54的表面上的导电凸块53。
如图6C中所描绘，第一模制层56形成或安置在载体50上方以囊封电子组件54和互连件52。在一些实施例中，第一模制层56的一部分被移除，例如，通过研磨，以暴露互连件52和导电凸块53。电路层70随后形成或安置在第一模制层56上方并且通过导电凸块53电连接到互连件52和电子组件54。
如图6D中所描绘，至少一个互连件62安置在电路层70上方并且电连接到电路层70，并且随后一或多个电子组件64形成或安置在电路层70上方并且电连接到电路层70。在一些实施例中，电子组件64经由导电凸块66接合到电路层70。在一些实施例中，底部填充层67可以填充在电子组件64与电路层70之间以保护导电凸块66。第二模制层68安置在电路层70上方以囊封电子组件64。在一些实施例中，第二模制层68通过模制、附接或通过其它合适的方法安置。在一些实施例中，载体50、粘合剂层51和第二模制层68的一部分被移除，例如，通过研磨，以暴露互连件62以连接到电触点72以形成半导体装置封装3，如图5中所示。
在一些实施例中，至少一个互连件62、电子组件64、导电凸块66、底部填充层67和模制层68可以是预先成形的封装60以安置在电路层70上方并且电连接到电路层70。
本发明的各种实施例的半导体装置封装与晶片级封装(WLP)兼容。半导体装置封装与封装上封装结构、混合封装结构以及2.5D/3D封装兼容。模制层具有平坦表面，这允许具有精细线宽和间距的RDL的累积，并且可以减少临时接合设备的使用。模制层和互连件的减小的高度缩短了不同电子组件或封装之间的信号路径，这改善了容量和性能，并且减少了半导体装置封装的电力消耗。翘曲可以通过调节不同模制层之中的材料、成分或类型而受到控制。电子组件可以是双侧暴露组件，这增大了半导体装置封装的应用。
除非上下文另外明确规定，否则如本文所用，单数术语“一(a/an)”和“所述”可包含多个指示物。
如本文所使用，术语“导电(conductive)”、“导电(electrically conductive)”和“电导率”是指传送电流的能力。导电材料通常指示呈现对于电流流动的极少或零对抗的材料。电导率的一个量度为西门子/米(S/m)。通常，导电材料为电导率大于约104S/m(例如，至少105S/m或至少106S/m)的一种材料。材料的电导率有时可随温度而变化。除非另外说明，否则材料的电导率是在室温下测量的。
如本文中所使用，术语“大致”、“基本上”、“实质”和“约”用于描述和解释小的变化。当与事件或情况结合使用时，所述术语可指事件或情况精确发生的例子以及事件或情况极近似地发生的例子。举例来说，当结合数值使用时，术语可指代小于或等于所述数值的±10％的变化范围，例如，小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％，或小于或等于±0.05％。举例来说，如果两个数值之间的差小于或等于所述值的平均值的±10％(例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％，或小于或等于±0.05％)，那么可认为所述两个数值“基本上”相同或相等。举例来说，“基本上”平行可以指相对于0°的小于或等于±10°的角变化范围，例如，小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°，或小于或等于±0.05°。举例来说，“基本上”垂直可以指相对于90°的小于或等于±10°的角变化范围，例如，小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°，或小于或等于±0.05°。
如果两个表面之间的位移不大于5微米(μm)、不大于2μm、不大于1μm或不大于0.5μm，那么可认为这两个表面共面或基本上共面。
此外，有时在本文中以范围格式呈现量、比率和其它数值。应理解，此类范围格式是用于便利和简洁起见，且应灵活地理解，不仅包含明确地规定为范围限制的数值，而且包含涵盖于所述范围内的所有个体数值或子范围，如同明确地规定每一数值和子范围一般。
尽管已参考本发明的具体实施例描述并说明本发明，但这些描述和说明并不限制本发明。所属领域的技术人员应理解，在不脱离如由所附权利要求书界定的本发明的真实精神和范围的情况下，可做出各种改变且可取代等效物。所述图式可能未必按比例绘制。归因于制造过程和容限，本发明中的艺术再现与实际设备之间可能存在区别。可能存在并未特定说明的本发明的其它实施例。应将本说明书和图式视为说明性的而非限制性的。可以作出修改，以使特定情况、材料、物质组成、方法或过程适应于本发明的目标、精神和范围。所有此类修改意图在所附权利要求书的范围内。虽然本文中所揭示的方法已参考按特定次序执行的特定操作加以描述，但应理解，可在不脱离本发明的教示的情况下组合、细分或重新排序这些操作以形成等效方法。因此，除非本文中特别指示，否则操作的次序和分组并非本发明的限制。

Claims (19)

1.一种半导体装置封装，其包括：
第一电路层，其包含第一表面以及与所述第一表面相对的第二表面；
至少一个第一电子组件，其安置在所述第一电路层的所述第一表面上方并且电连接到所述第一电路层；
第一模制层，其安置在所述第一电路层的所述第一表面上方，其中所述第一模制层囊封所述至少一个第一电子组件的边缘，并且所述第一模制层的下表面和所述至少一个第一电子组件的下表面是实质上共平面的；
第二电子组件，其安置在所述第一电路层的所述第二表面上方并且电连接到所述第一电路层；以及
第二模制层，其安置在所述第一电路层的所述第二表面上方并且囊封所述第二电子组件，其中所述第一模制层和所述第二模制层包含不同的模制材料，其中所述第一模制层的热膨胀系数(CTE)不同于所述第二模制层的热膨胀系数。
2.根据权利要求1所述的半导体装置封装，其进一步包括：
第二电路层，其安置在所述第二模制层上方；以及
至少一个互连件，其安置在所述第一电路层与所述第二电路层之间，通过所述第二模制层囊封，并且电连接到所述第一电路层和所述第二电路层。
3.根据权利要求1所述的半导体装置封装，其进一步包括安置在所述至少一个第一电子组件上方并且电连接到所述至少一个第一电子组件的至少一个电触点。
4.根据权利要求1所述的半导体装置封装，其中：
所述第一模制层和所述第二模制层中的每一者包含多个填充物，并且所述第一模制层的填充物和所述第二模制层的填充物在大小上是不同的。
5.一种半导体装置封装，其包括：
第一电路层，其包含第一表面以及与所述第一表面相对的第二表面；
至少一个第一电子组件，其安置在所述第一电路层的所述第一表面上方并且电连接到所述第一电路层；
第一模制层，其安置在所述第一电路层的所述第一表面上方并且囊封所述至少一个第一电子组件；
第二电子组件，其安置在所述第一电路层的所述第二表面上方并且电连接到所述第一电路层；以及
第二模制层，其安置在所述第一电路层的所述第二表面上方并且囊封所述第二电子组件，
其中所述第一模制层包括与所述第一电路层的所述第一表面相对的下表面，所述第一模制层包括多个填充物，并且所述第一模制层中的所述填充物中的至少一者具有邻近于所述第一模制层的所述下表面的切割平面，其中所述第一模制层的热膨胀系数(CTE)不同于所述第二模制层的热膨胀系数。
6.根据权利要求5所述的半导体装置封装，其中所述第一模制层和所述第二模制层选自薄膜模制化合物、液体模制化合物或粒状模制化合物。
7.根据权利要求6所述的半导体装置封装，其中所述第一模制层包含所述薄膜模制化合物，并且所述第二模制层包含所述液体模制化合物或所述粒状模制化合物。
8.根据权利要求5所述的半导体装置封装，其中所述第一模制层和所述第二模制层包含不同的模制材料。
9.根据权利要求8所述的半导体装置封装，其中所述第一模制层包含味之素累积薄膜(ABF)，并且所述第二模制层的材料包含联二苯。
10.根据权利要求5所述的半导体装置封装，其中所述第二模制层包含多个填充物，并且所述第一模制层的填充物和所述第二模制层的填充物在材料上是不同的。
11.根据权利要求10所述的半导体装置封装，其中所述第一模制层的填充物包含氧化铝填充物，并且所述第二模制层的填充物包含氧化硅填充物。
12.根据权利要求5所述的半导体装置封装，其中所述第二模制层包含多个填充物，并且所述第一模制层的填充物和所述第二模制层的填充物在大小上是不同的。
13.根据权利要求12所述的半导体装置封装，其中所述第一模制层的填充物的大小大于所述第二模制层的填充物的大小。
14.根据权利要求5所述的半导体装置封装，其中所述第一模制层的所述下表面和所述至少一个第一电子组件的下表面是实质上共平面的。
15.根据权利要求5所述的半导体装置封装，其进一步包括：
第二电路层，其安置在所述第二模制层上方；以及
至少一个互连件，其安置在所述第一电路层与所述第二电路层之间，通过所述第二模制层囊封，并且电连接到所述第一电路层和所述第二电路层。
16.一种制造半导体装置封装的方法，其包括：
在载体上方安置至少一个第一电子组件；
在所述载体上方安置第一模制层以囊封所述至少一个第一电子组件；
在所述第一模制层和所述至少一个第一电子组件上方安置第一电路层；
在所述第一电路层上方安置第二电子组件；以及
在所述第一电路层上方安置第二模制层以囊封所述第二电子组件，
其中所述第一模制层的热膨胀系数(CTE)不同于所述第二模制层的热膨胀系数。
17.根据权利要求16所述的方法，其进一步包括：
移除所述载体；以及
在所述至少一个第一电子组件的下表面上方安置至少一个电触点。
18.根据权利要求17所述的方法，其进一步包括移除所述第一模制层的一部分和所述至少一个第一电子组件的一部分以暴露所述至少一个第一电子组件的所述下表面，其中所述至少一个第一电子组件的所述下表面和所述第一模制层的下表面是实质上共平面的。
19.根据权利要求16所述的方法，其进一步包括：
在安置所述第二模制层之前在所述第一电路层上方安置至少一个互连件；以及
在所述第二模制层和所述至少一个互连件上方安置第二电路层。
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