CN112151528A - 包括相对表面上的接触指的半导体装置 - Google Patents

包括相对表面上的接触指的半导体装置 Download PDF

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Publication number
CN112151528A
CN112151528A CN201910578954.3A CN201910578954A CN112151528A CN 112151528 A CN112151528 A CN 112151528A CN 201910578954 A CN201910578954 A CN 201910578954A CN 112151528 A CN112151528 A CN 112151528A
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China
Prior art keywords
semiconductor device
substrate
contact fingers
die
grid array
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CN201910578954.3A
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English (en)
Inventor
陈建德
张聪
黄湘茹
杨旭一
谭玉英
陈含笑
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Western Digital Technologies Inc
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Western Digital Technologies Inc
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Priority to CN201910578954.3A priority Critical patent/CN112151528A/zh
Priority to US16/814,864 priority patent/US11139277B2/en
Publication of CN112151528A publication Critical patent/CN112151528A/zh
Pending legal-status Critical Current

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Abstract

公开了一种平面网格阵列半导体装置，其被配置为可移除地插入主机装置和从主机装置移除。平面网格阵列半导体装置可以包括：一个或多个接触指的第一集合，在平面网格阵列半导体装置的第一表面上；以及，一个或多个接触指的第二集合，在所述平面网格阵列半导体装置的第二表面上。为了电耦接一个或多个接触指的第二集合，可以提供在一个或多个接触指的第二集合与衬底和至少一个半导体裸芯中的至少一者之间物理地延伸的一个或多个电连接体。

Description

包括相对表面上的接触指的半导体装置
技术领域
本技术总体上涉及一种半导体装置，更特别地，涉及一种平面网格阵列半导体装置。
背景技术
对便携式消费电子产品的要求的强劲增长驱动了对高容量储存装置的需求。非易失性半导体存储器装置(诸如闪存存储器储存卡)正在变得广泛地用于满足对数字信息储存和交换的不断增长的要求。它们的便携性、多功能性和坚固的设计，与它们的高可靠性和大容量一起，已经使这种存储器装置理想地用在包括例如数码相机、数字音乐播放器、视频游戏控制机，PDA和蜂窝电话的各种电子装置中。
尽管许多变化的封装配置是已知的，而闪速存储器储存卡通常可以被制造为系统级封装(SiP)或多芯片模块(MCM)，其中存储器和控制器裸芯被安装和互连在小足印衬底上。该衬底通常可以包括刚性的电介质基质，其具有在一侧或两侧上蚀刻的导电层。在裸芯和(多个)导电层之间形成电连接体，并且(多个)导电层提供将裸芯连接到主机装置的电引线结构。一旦制成裸芯和衬底之间的电连接体，则组件典型地被包装在提供保护性封装体的模塑料中。
已知提供了具有接触指的所谓的LGA(land grid array，平面网格阵列)的存储器卡，该接触指使得卡能够可移除地插入主机装置中。在插入时，主机装置插槽中的引脚与接触指接合，以允许在存储器卡和主机装置之间通信。这样的卡包括SD卡、Nano卡、多媒体卡和SIM卡。
在始终需要以更小形式因子提供更大的数据容量和传输速度的情况下，已知跨越LGA卡的整个表面来提供接触指。这在卡的制造中出现挑战。例如，在形成接触指之后，诸如控制器裸芯的组件安装在接触指之上的衬底上。在接触指之上安装这样的组件可能损坏或破坏接触指。
发明内容
如背景技术章节所述，可能难以设计接触指覆盖装置的整个底表面的半导体装置。本技术提供了通过使接触指的可用表面面积加倍，大大增加了可以放置接触指的位置的灵活性的技术优点。另外，在需要时，本技术提供了技术优势，大大增加了可以放置接触指的可用表面积。
综上，在一个示例中，本技术涉及一种半导体装置，包括：衬底，包含第一表面和相对的第二表面；一个或多个接触指的第一集合，在衬底的第一表面上；至少一个半导体裸芯，安装在衬底的第二表面上并且电耦接到衬底；模塑料，包封至少一个半导体裸芯；一个或多个接触指的第二集合，在模塑料的表面上；以及一个或多个电连接体，在一个或多个接触指的第二集合与衬底和至少一个半导体中的至少一者之间物理地延伸。
在另一个示例中，本技术涉及一种平面网格阵列半导体装置，配置为可移除地插入主机装置和从主机装置移除，平面网格阵列半导体装置包含：衬底；至少一个半导体裸芯，安装在衬底上并且电耦接到衬底；模塑料，包封至少一个半导体裸芯；衬底的表面和模塑料的表面限定平面网格阵列半导体装置的第一和第二相对的主表面；一个或多个接触指的第一集合，在平面网格阵列半导体装置的第一表面上并且电耦接到衬底；一个或多个接触指的第二集合，在平面网格阵列半导体装置的第二表面上；以及一个或多个电连接体，在一个或多个接触指的第二集合与衬底和至少一个半导体中的至少一者之间物理地延伸。
在另一个示例中，本技术涉及平面网格阵列半导体装置，配置为可移除地插入主机装置和从主机装置移除，平面网格阵列半导体装置包含：衬底，包含第一表面和相对的第二表面；接触指构件的第一集合，在平面网格阵列半导体装置的第一表面上，以用于与主机装置的针脚相接；至少一个半导体裸芯，安装在衬底的第二表面上并且电耦接到衬底；模塑料，包封至少一个半导体裸芯；接触指构件的第二集合，在限定平面网格阵列半导体装置的第二表面的模塑料的表面上，以用于与主机装置的针脚相接；以及电连接体构件，在一个或多个接触指的第二集合与衬底和至少一个半导体裸芯中的至少一者之间物理延伸，以用于在平面网格阵列半导体装置内电连接接触指构件的第二集合。
附图说明
图1是根据本技术的实施例的半导体装置的整体制造工艺的流程图。
图2是根据本技术的实施例的衬底的仰视图。
图3是根据本技术的实施例的在制造工艺期间的一步骤的半导体装置的边视图。
图4是在制造工艺期间的一步骤的根据本技术的替代实施例的半导体装置的边视图。
图5是根据本技术的实施例的在制造工艺期间的另一步骤的半导体装置的边视图。
图6是根据本技术的实施例的在制造工艺期间的又一步骤的半导体装置的边视图。
图7是根据本技术的实施例的在制造工艺期间的另一步骤的半导体装置的边视图。
图8是根据本技术的实施例的在制造工艺期间的又一步骤的半导体装置的边视图。
图9是根据本技术的实施例的在制造工艺期间的根据替代实施例的半导体装置的边视图。
图10是根据本技术的实施例的在制造工艺期间的另一步骤的半导体装置的边视图。
图11是根据本技术的实施例的在制造工艺期间的又一步骤的半导体装置的边视图。
图12是根据本技术的实施例的完成的半导体装置的边视图。
图13是根据本技术的实施例的完成的半导体装置的俯视图。
具体实施例
现在将参考附图描述本技术，该技术在实施例中涉及配置为可移除地插入到主机装置和从主机装置可移除的平面网格阵列半导体装置。平面网格阵列半导体装置可以包括衬底，在衬底上安装并电耦接到衬底的至少一个半导体裸芯以及包封至少一个半导体裸芯的模塑料。衬底的表面和模塑料的表面限定了平面网格阵列半导体装置的第一和第二相对的主表面。
根据本技术，一个或多个接触指的第一集合可以形成在平面网格阵列半导体装置的第一表面上，并且一个或多个接触指的第二集合可以形成在在平面网格阵列半导体装置的第二表面上。为了将一个或多个接触指的第二集合电耦接在平面网格阵列半导体装置的第二表面上，一个或多个电连接体可以配备为在一个或多个接触指的第二集合和至少一个衬底和至少一个半导体裸芯之间物理地延伸。一个或多个电连接体可以由穿过封装体、焊料球或柱或者穿模通孔(TMV)的垂直引线来形成。
应当理解，本技术可以以许多不同形式来实施，并且不应该被解释为受限于在此提出的实施例。而是，提供这些实施例使得本公开将彻底和完整，并且将本技术完全传达给本领域技术人员。实际上，该技术旨在于覆盖这些实施例的替代、修改和等同物，这些实施例被包括在由所附权利要求所限定的技术的范围和精神内。此外，在本技术的以下详细描述中，提出了许多具体细节以便提供对本技术的透彻理解。然而，本领域普通技术人员将清楚，可以在没有这样的具体细节的情况下实践本技术。
本文所使用的术语“顶部”和“底部”、“上部”和“下部”以及“垂直”和“水平”仅作为示例和说明性目的，并不意味着限制该技术的描述因为所参考的项目可能在位置和取向上被交换。而且，如本文所用的，术语“实质上”，“近似”和/或“大约”意味着指定的尺寸或参数可以在给定应用的可接受的制造公差内变化。在一个实施例中，可接受的制造公差为±2.5％。
现在将参考图1的流程图以及图1和图2到图13的底视图、边视图和俯视图来解释本技术的实施例。尽管图2至图13各自示出了单独的半导体装置140或其一部分，应当理解，装置140可以与衬底面板上的多个其他封装体一起批量处理以实现规模经济。衬底面板上的装置140的行数和列数可以变化。
用于制造半导体装置140的衬底面板以多个衬底100开始(同样，一个这样的衬底在图2至图13中示出)。衬底100可以是各种不同的芯片载体介质，包括印刷电路板(PCB)、引线框架或带自动粘合(TAB)带。在衬底100是PCB的情况下，衬底可以由具有顶部和底部导电层的芯以及在顶部和底部层之间延伸的金属互连体来形成。芯可以由各种电介质材料来形成，例如聚酰亚胺层层压件、包括FR4和FR5的环氧树脂、双马来酰亚胺三嗪(BT)等。顶表面和底表面上的导电层可以由铜或铜合金、镀铜或镀铜合金、合金42(42Fe/58Ni)、镀铜钢或其他适用于衬底面板的金属和材料来形成。
图1是根据本技术的实施例的形成半导体装置140的制造工艺的流程图。在步骤200中，衬底100可以形成为在衬底的底表面104中包括接触指的第一集合102，如图2中所示的半导体装置140的仰视图所示。可以在底表面104上形成焊掩模或其他保护性涂层106，使接触指102暴露。衬底100的底表面104上的导电层可以在例如光刻工艺的各种工艺中被蚀刻，以限定接触指102。电迹线和通孔(未示出)可以将接触指102与衬底100的上表面上的接触垫电耦接(下面描述)。
图2和图3中所示的接触指102的数量、形状和相对位置仅作为示例并且可以在其他实施例中变化。可以提供接触指102以支持多种存储器卡标准(包括例如多媒体卡(MMC)、Nano卡、SIM卡等)中的任何一种，并且可以根据多种总线标准(包括例如SD和外围组件互连快速(PCIe)总线标准)中的任何一种来配置。
在实施例中，如图2所示，接触指102可以配备在衬底100的底表面104的一半上。然而，可以想到，在其他实施例中，接触指102配备在底表面104上的相对的一半上、两半上或着以各种其他图案分布在底表面104上。
在实施例中，如图3中所示,可以蚀刻衬底100的上表面105上的导电层以限定接触垫108的图案。电迹线和通孔(未示出)可以将接触垫108彼此和在衬底100的底表面104上的接触指102电耦接。接触垫108可以配备为接收引线键合体、倒装芯片焊料球和各种其他电接触体。图3中所示的接触垫108的具体数量和位置仅是示例性的，并且在其他实施例中可以变化。
在步骤202中，如图3所示，控制器裸芯110可以安装到衬底100的上表面105，并且例如使用引线键合体112电耦接到其上。可以理解，根据其他方案，控制器裸芯110可以电耦接到衬底100。例如，图4示出了替代的实施例，其中控制器裸芯110倒装芯片式地安装到衬底100，例如使用接触垫114的图案。控制器裸芯110可以例如是ASIC，但是在其他实施例中可以是用于与主机装置接口连接的其他半导体裸芯。
在步骤204中，除了控制器裸芯110之外，可以将无源组件(未示出)安装到衬底。这样的无源组件可以例如包括电容器、电阻器和电感器。
在步骤208中，如图5所示，可以在衬底100的表面105处安装一个或多个附加的半导体裸芯116。半导体裸芯116可以例如是闪速存储器裸芯，诸如2D NAND闪速存储器或3DBiCS(位成本可扩展)、V-NAND或其他3D闪存存储器，但是可以使用其他类型的裸芯116。这些其他类型的半导体裸芯包括但不限于诸如SDRAM、DDR SDRAM、LPDDR和GDDR的RAM。
在包括多个半导体裸芯116的情况下，半导体裸芯116可以以多种配置中的任何一种彼此上下堆叠。在图5和图6中所示的示例中，在步骤208中，可以安装一对半导体裸芯116，并且在步骤210中，然后使用例如在裸芯116上的裸芯接合垫和衬底100上的接触垫108之间耦接的引线键合体124来彼此电耦接以及电耦接到衬底，如图6所示。可以重复步骤208和210以垂直堆叠并将偏移半导体裸芯116的附加对引线键合，以形成例如如图7中所示的裸芯堆叠体120。
在图5-7的特定配置中，薄膜间隔体层(未示出)可以配备在如已知的每个半导体裸芯对的顶部上，当安装半导体裸芯的下一对时，将引线键合体的空间留给成对的上部裸芯。在其他配置中，半导体裸芯116可以按每个裸芯116在相同方向上偏移来安装，使在下面暴露的裸芯的裸芯接合垫。该配置与图7相比在水平方向上占据更多空间，但是可以省略薄膜间隔体层，从而与图7相比在垂直方向上占据更少的空间。
每个裸芯可以包括底表面上的裸芯附接膜(DAF)层。当彼此堆叠并且衬底100例如达到150℃时，可能加热裸芯116，以软化b-阶段DAF层并促进适当的堆叠。图7中的堆叠体120中所示出的裸芯116的数量仅是示例性的，并且实施例可以包括不同数量的半导体裸芯，包括例如1个、2个、4个、8个、16个、32个、或64个裸芯。在其他实施例中可以存在其他数目的裸芯。还应理解，裸芯堆叠体120可以物理地安装在各种其他偏移配置中，并且使用除引线键合体之外例如穿硅通孔(TSV)的技术来电耦接。
众所周知，可以提供一个或多个间隔体118以使半导体裸芯116在衬底100上方间隔开，以为控制器裸芯110及其引线键合体留出空间。在其他实施例中，控制器裸芯110可以安装在衬底100内，靠近衬底100上的裸芯116安装或者安装在裸芯116的顶部上。在这样的实施例中，可以省略间隔体118。
根据本技术的方面，接下来可以在步骤214中形成垂直电连接体126和130，如图8所示。例如，一个或多个垂直电连接体126可以形成为从堆叠体120中的上部裸芯116之一的一个或多个裸芯接合垫垂直延伸(即，总体上垂直于衬底100的表面105)。可以存在多个这样的垂直电连接体126(进入图8的页面)。一个或多个垂直电连接体130可以例如形成为从衬底100上的一个或多个接触垫108垂直延伸。可以存在多个这样的垂直电连接体130(进入图8的页面)。
图8示出了在衬底100的左侧和右侧处的一个或多个垂直电连接体130的两个集合。在另外的实施例中，可以存在从衬底100延伸的一个或多个垂直电连接体130的单个集合，取决于半导体装置的上表面上的接触指构造，如下所述。同样取决于半导体装置的上表面上的接触指的配置，可以省略一个或多个垂直电连接体126或一个或多个垂直电连接体130。
垂直电连接体126、130可以通过各种技术形成。在一个实施例中，垂直电连接体126和/或130可以由形成引线键合体124的相同引线键合体劈刀(未示出)形成。在这样的实施例中，垂直电连接体126和/或130可以由与引线键合体124相同的材料形成，引线键合体124的材料可以是例如金(Au)或其合金。
在另一实施例中，垂直电连接体126和/或130可以形成为安装在半导体裸芯116和/或衬底100上并从半导体裸芯116和/或衬底100延伸的固体材料的柱状物或柱。在如图9所示的另一个实施例中，垂直电连接体126和/或130可以是细长的焊料球、柱状物或柱，或者是彼此上下叠置的多个焊料球、柱状物或柱。在这样的实施例中，垂直电连接体126和/或130可以由多种材料形成，包括例如金(Au)、铜(Cu)、锡(Sn)或其合金。如以下段落中所解释的，垂直电连接体126、130可以至少延伸到在半导体裸芯116之上形成的模塑料的上表面的高度。
在形成垂直电连接体126、130之后，也称为半导体装置140的半导体裸芯116和电连接体124、126和130可以在如图10中所示的步骤216中被包封在模塑料134中。半导体装置140可以放置在包括上模板和下模板的模塑模具(未示出)内。然后可以在例如压缩模塑工艺中，将熔融的模塑料134注入模塑模具中以将半导体装置140的组件包覆在保护性外壳中。模塑料134可包括例如固体环氧树脂、酚醛树脂、熔融二氧化硅、晶体二氧化硅、碳黑和/或金属氢氧化物。预想到其他模塑料。模塑料可根据其他已知的工艺施加，包括通过FFT(自由流动薄(flow free thin))模塑、转移模塑或注塑技术。
在上述实施例中，在步骤214中形成垂直电连接体126、130，并且然后在步骤216中包封电连接体和半导体裸芯110、116。然而，在另一实施例中，可以在形成垂直电连接体126和/或130之前包封半导体装置140。在这样的实施例中，在包封之后，电连接体126和/或130可以通过穿模通孔(TMV)形成。包封例如通过激光钻孔下至最上部的半导体裸芯和/或衬底的表面，并且然后钻出的孔可以被电镀和/或用电导体填充，以形成垂直电连接体126和/或130。
在包封步骤之后，在模塑料134的上表面上形成接触指的第二集合，该接触指的第二集合电耦接到垂直电连接体126和/或130。现在将参考图11至13中的步骤220至226来描述接触指的第二集合的形成。在步骤220中，出于将垂直电连接体126和130暴露在模塑料134的上表面136处的目的，模塑料134的上表面136可以经历研磨和抛光工艺以减小模塑料134的厚度。
在步骤224中，如图11所示，导电层144形成在模塑料134的上表面136的顶部上。导电层144可以由铜或铜合金、镀铜或镀铜合金、合金42(42Fe/58Ni)、镀铜钢或其他适合用作接触指的金属和材料形成。在实施例中，导电层144可以以与在模塑料的表面上形成EMI(电磁干扰)屏蔽的工艺相同或类似的工艺形成。
在步骤226中，导电层144可以被图案化成接触指146的第二集合，如图12的侧视图和图13的俯视图所示。在包括例如光刻工艺的各种工艺中从导电层144形成接触指146。如图12和13所示的接触指146的数量、形状和相对位置仅作为示例，并且可以在其他实施例中变化。可以提供接触指146以支持任何的多种存储器卡标准，包括例如多媒体卡(MMC)、Nano卡、SIM卡等，并且可以根据包括例如SD和PCIe总线标准的任何多种总线标准来配置。
在图12和图13中所示的实施例中，接触指146可以设置在半导体装置140的顶表面的两个半部上。然而，可以设想到将接触指146仅设置在一个半部上，或者在其他实施例中以各种其他图案分布。在仅一个半部的情况下，可以省略电连接体130的集合中的一个(从图12的角度来说的左侧集合或右侧集合)。可以在装置140的顶表面上形成一层阻焊掩模或其他保护涂层148，保持接触指146暴露，以完成半导体装置140的制造。
在使用中，半导体装置140可以是LGA半导体装置，其配置成可移除地插入主机装置中，主机装置例如蜂巢电话、计算机或相机。主机装置插槽可以包括在槽的底部上的接触针脚的第一集合，其配置成与半导体装置140的底表面上的接触指102的第一集合配合。主机装置插槽可以进一步包括槽的顶部上的接触针脚的第二集合，其配置成与半导体装置140的顶表面上的接触指146的第二集合配合。
如上所述，接触指102的第一集合可以通过在衬底100中且穿过衬底100的电迹线和通孔电耦接到控制器裸芯110和/或存储器裸芯116。在插入主机装置槽并且与接触针脚的第一集合配合时，接触指102的第一集合使得能够在主机装置和半导体装置140之间进行通信。
如上所述，接触指146的第二集合可以通过垂直电连接体126和/或130并且通过在衬底100中且穿过衬底100的电迹线和通孔来电耦接到控制器裸芯110和/或存储器裸芯116。在插入主机装置槽并且与接触针脚的第二集合配合时，接触指146的第二集合使得能够在主机装置和半导体装置140之间进行通信。
出于说明和描述的目的，已经呈现了本技术的前述详细描述。其并非旨在穷举或将技术限制于所公开的精确形式。鉴于上述教导，许多修改和变化都是可能的。选择所描述的实施例是为了最好地解释本技术的原理及其实际应用，从而使得本领域的其他技术人员能够在各种实施例中以及适合于预期的特定用途的各种修改中最佳地利用该技术。本技术的范围旨在由所附权利要求限定。

Claims (20)

1.一种半导体装置，包括：
衬底，包含第一表面和相对的第二表面；
一个或多个接触指的第一集合，在所述衬底的第一表面上；
至少一个半导体裸芯，安装在所述衬底的第二表面上并且电耦接到所述衬底；
模塑料，包封所述至少一个半导体裸芯；
一个或多个接触指的第二集合，在所述模塑料的表面上；以及
一个或多个电连接体，在所述一个或多个接触指的第二集合与所述衬底和所述至少一个半导体中的至少一者之间物理地延伸。
2.如权利要求1所述的半导体装置，其中，所述一个或多个电连接体包含垂直引线。
3.如权利要求1所述的半导体装置，其中，所述一个或多个电连接体包含导电材料的垂直柱。
4.如权利要求1所述的半导体装置，其中，所述一个或多个电连接体包含一个或多个焊料球。
5.如权利要求1所述的半导体装置，其中，所述一个或多个电连接体在所述一个或多个触指的第二集合与所述至少一个半导体裸芯中的最上部半导体裸芯之间延伸。
6.如权利要求1所述的半导体装置，其中，所述一个或多个电连接体在所述一个或多个接触指的第二集合与所述衬底之间延伸。
7.如权利要求1所述的半导体装置，其中，所述一个或多个接触指的第二集合包含在所述模塑料的表面的两个半部上的多个接触指。
8.如权利要求1所述的半导体装置，其中，所述一个或多个接触指的第二集合包含在所述模塑料的表面的一个半部上的多个接触指。
9.如权利要求1所述的半导体装置，其中，所述至少一个半导体裸芯包含多个闪速存储器裸芯。
10.如权利要求9所述的半导体装置，其中，所述至少一个半导体裸芯还包含安装在所述衬底的第二表面上的区域内的控制器裸芯。
11.如权利要求10所述的半导体装置，其中，所述衬底的第一表面在与所述衬底的第二表面上的包含所述控制器裸芯的区域相对的区域中没有来自所述接触指的第一集合的接触指。
12.一种平面网格阵列半导体装置，配置为可移除地插入主机装置和从主机装置移除，所述平面网格阵列半导体装置包含：
衬底；
至少一个半导体裸芯，安装在所述衬底上并且电耦接到所述衬底；
模塑料，包封所述至少一个半导体裸芯；
所述衬底的表面和所述模塑料的表面限定所述平面网格阵列半导体装置的第一主表面和相对的第二主表面；
一个或多个接触指的第一集合，在所述平面网格阵列半导体装置的第一表面上并且电耦接到所述衬底；
一个或多个接触指的第二集合，在所述平面网格阵列半导体装置的第二表面上；以及
一个或多个电连接体，在所述一个或多个接触指的第二集合与所述衬底和所述至少一个半导体中的至少一者之间物理地延伸。
13.如权利要求12所述的半导体装置，其中，所述平面网格阵列半导体装置根据SD卡、Nano卡、多媒体卡和SIM卡标准中的一个配置。
14.如权利要求12所述的半导体装置，其中，所述平面网格阵列半导体装置根据SD和外围组件互连高速总线标准中的一个配置。
15.如权利要求12所述的半导体装置，其中，所述一个或多个电连接体包括引线、导电材料的柱、至少一个焊料球和包含导电体的穿模通孔中的一个。
16.如权利要求12所述的半导体装置，其中，所述平面网格阵列半导体装置根据SD卡、Nano卡、多媒体卡和SIM卡标准中的一个配置。
17.如权利要求12所述的半导体装置，其中，所述一个或多个电连接体在所述一个或多个触指的第二集合与所述至少一个半导体裸芯的最上部半导体裸芯之间延伸。
18.如权利要求12所述的半导体装置，其中，所述一个或多个电连接体在所述一个或多个接触指的第二集合与所述衬底之间延伸。
19.如权利要求12所述的半导体装置，其中，所述至少一个半导体裸芯包含安装在所述衬底的第一表面的区域中的控制器裸芯，并且其中，所述平面网格阵列半导体装置的第一表面在与所述衬底的第一表面上的包含所述控制器裸芯的区域相对的区域中没有来自所述接触指的第一集合的接触指。
20.一种平面网格阵列半导体装置，配置为可移除地插入主机装置和从主机装置移除，所述平面网格阵列半导体装置包含：
衬底，包含第一表面和相对的第二表面；
接触指构件的第一集合，在所述平面网格阵列半导体装置的第一表面上，以用于与所述主机装置的针脚相接；
至少一个半导体裸芯，安装在所述衬底的第二表面上并且电耦接到所述衬底；
模塑料，包封所述至少一个半导体裸芯；
接触指构件的第二集合，在所述模塑料的限定所述平面网格阵列半导体装置的第二表面的表面上，以用于与所述主机装置的针脚相接；以及
电连接体构件，在所述一个或多个接触指的第二集合与所述衬底和所述至少一个半导体裸芯中的至少一之者之间物理地延伸，以用于在所述平面网格阵列半导体装置内电连接所述接触指构件的第二集合。
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