TWI600124B - 封裝的半導體元件、層疊封裝元件以及封裝半導體元件的方法 - Google Patents

封裝的半導體元件、層疊封裝元件以及封裝半導體元件的方法 Download PDF

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TWI600124B
TWI600124B TW103145758A TW103145758A TWI600124B TW I600124 B TWI600124 B TW I600124B TW 103145758 A TW103145758 A TW 103145758A TW 103145758 A TW103145758 A TW 103145758A TW I600124 B TWI600124 B TW I600124B
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integrated circuit
molding compound
circuit die
packaged semiconductor
semiconductor component
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TW103145758A
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TW201533862A (zh
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余振華
劉重希
黃致凡
林志偉
林威宏
鄭明達
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台灣積體電路製造股份有限公司
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Description

封裝的半導體元件、層疊封裝元件以 及封裝半導體元件的方法
本發明是有關於半導體元件，且特別是有關於封裝半導體元件以及封裝半導體元件的方法。
半導體元件被用在各式各樣的電子應用裝置中，例如個人電腦、手機、數位相機及其他電子設備。典型的半導體元件的製造方法，是在半導體基材上相繼沈積絕緣或介電層、導電層或半導體層的材料，然後使用微影製程對各材料層進行圖案化，以在半導體基材上形成電路構件和元件。
通常，在單一半導體晶圓上可製作出數十或數百個積體電路元件。沿著切割線(scribe line)對積體電路進行切割，可將個別晶粒(die)獨立出來。個別晶粒接著分別被封裝於例如多晶片模組或其他類型的封裝結構中。
藉由持續降低最小特徵尺寸，使得在一給定區 域內能結合更多元件，半導體產業還在繼續提高各種電子元件(例如電晶體、二極體、電阻器、電容器等)的集成度。在一些應用中，這些較小的電子元件也需要相較於過去的封裝使用更小空間的較小封裝結構。
在一些實施方式中，封裝的半導體元件包括積體電路晶粒、環繞積體電路晶粒配置的模塑料以及配置在積體電路晶粒和模塑料上的內連線結構。模塑料比積體電路晶粒厚。
在其他實施方式中，封裝半導體元件的方法包括在積體電路晶粒上配置犧牲層以及將積體電路晶粒耦接至載體。將模塑料環繞著積體電路晶粒配置。移除犧牲層，將內連線結構形成在積體電路晶粒和模塑料上。
在其他實施方式中，封裝半導體元件的方法包刮在具有多個積體電路晶粒的晶圓上配置犧牲層，分離多個積體電路晶粒以及將多個積體電路晶粒耦接到載體。將模塑料環繞多個積體電路晶粒配置。此方法包括移除載體、移除犧牲層以及在多個積體電路晶粒和模塑料上形成內連線結構。
100‧‧‧載體
102‧‧‧晶粒結合材料
106、176‧‧‧積體電路晶粒
108‧‧‧犧牲層
110‧‧‧工件
114、130、164‧‧‧接觸墊
120‧‧‧模塑料
122‧‧‧內連線結構
124‧‧‧絕緣材料層
126‧‧‧導線
128‧‧‧導電通孔
132、178‧‧‧導電體
133‧‧‧切割線
134‧‧‧第二模塑料
138‧‧‧連通柱
140、140’、150、160、170‧‧‧封裝的半導體元件
142‧‧‧蓋體、散熱器或背側保護膜
144、174‧‧‧基材
146‧‧‧底部填充材料
152‧‧‧玻璃球
172‧‧‧焊線
180‧‧‧流程圖
182、184、186、188、190‧‧‧步驟
d1、d2、d3‧‧‧尺寸
透過以下實施方式同時閱讀隨附圖式最容易理解本揭露的各種態樣。應理解的是，如同業界的標準作 法，各種特徵未必是按比例繪示的。事實上，為了進行清楚的討論，各種特徵的尺寸可能經過任意縮放。
根據本揭露的一些實施方式，圖1到10繪示了一種封裝半導體元件的方法在各階段的剖面圖。
根據一些實施方式，圖11和12繪示封裝半導體元件的方法在各階段的剖面圖。
根據一些實施方式，圖13繪示封裝的半導體元件的剖面圖。
根據其他實施方式，圖14繪示封裝的半導體元件的剖面圖。
根據一些實施方式，圖15繪示封裝的半導體元件的剖面圖。
根據一些實施方式，圖16和17是圖15呈現的封裝的半導體元件的某些部份的更詳細視圖。
根據一些實施方式，圖18繪示封裝的半導體元件的剖面圖。
根據一些實施方式，圖19是封裝半導體元件的方法的流程圖。
以下揭露內容提供了許多不同的實施方式或實施例，使描述之標的的各種特徵得以實現。下文描述了成份和安排方式的各種實例是為了簡化本揭露。這些內容當然僅是例示而已，其意不在構成限制。例如，在下文中敘 述第一特徵形成在第二特徵上或上方，可能包括形成直接接觸的第一和第二特徵的實施方式，也可能包括其他特徵形成於第一和第二特徵之間的實施方式，此時第一和第二特徵就可能沒有直接接觸。此外，本揭露可能會在不同的實例中重複使用元件符號及/或字母。這些重複是為了進行簡單和清楚的說明，並不表示在文中討論的各種實施方式及/或組態之間存在一定關係。
此外，在本文中，為了易於描述圖式中某個元件或特徵和其他元件或特徵的關係，可能會使用空間相對術語，例如「在…下方」、「在…下」、「低於」、「在…上方」、「高於」和類似用語。這些空間相對術語意欲涵蓋元件使用或操作時的所有不同方向，不只限於圖式所繪的方向而已。所述裝置可以其他方式定向(旋轉90度或定於另一方向)，而本文使用的空間相對描述語則可相應地進行解讀。
本揭露的一些實施方式提供了封裝半導體元件的新穎方法和結構。在晶粒周圍形成模塑料(molding compound)之前，先在積體電路晶粒上形成犧牲層，之後移除犧牲層。犧牲層避免模塑料殘留物形成在積體電路晶粒上，因此抑制或是避免了凹陷形成在積體電路晶粒和模塑料之間。
根據一些實施方式，圖1到10繪示了一種封裝半導體元件的方法在各階段的剖面圖。首先參照圖1，提供工件110，其包括多個積體電路晶粒106。工件110 可包括半導體基材，其由矽或其他半導體材料構成，且可被像是絕緣層的材料覆蓋。工件110也可以包括其他沒有繪示的主動元件或電路。工件110例如可包括在單晶矽上的氧化矽。工件110可以是導電層或半導體元件，例如電晶體、二極體等。化合物半導體如GaAs、InP、Si/Ge或SiC可以用來取代矽。工件110例如可包括矽覆絕緣體(SOI)或鍺覆絕緣體(GOI)基材。工件110例如可包括含有多個積體電路晶粒106的晶圓或晶帶(strip)。或者，工件110可以包括其他類型的材料、材料層和元件形成於其上。
形成在工件110內及/或上的積體電路晶粒106可包括多個電連接器，如配置在其表面上的接觸墊114。接觸墊114例如可包括Cu、Al、其他金屬或合金、前述材料的組合或疊層。接觸墊114可配置在絕緣材料(未繪示)內，所述絕緣材料例如可包括氮化矽、二氧化矽、其他絕緣體或高分子或前述材料的組合或疊層。接觸墊114可以耦接到積體電路晶粒106的內部線路，作為實例，例如積體電路晶粒106的金屬化層或多晶矽層中的介層窗及/或導線(未繪示)。
接著參照圖2，犧牲層108形成在工件110上，例如在積體電路晶粒106上。在一些實施方式中，犧牲層108例如包括光阻材料、有機材料、高分子材料、其他在固化處理(curing)之後凝固的材料及/或前述材料的組合或疊層。在一些實施方式中，犧牲層108例如包括聚 苯並噁唑(polybenzoxazole，PBO)。在一些實施方式中，犧牲層108例如是使用旋塗(spin-on)法、化學氣相沈積法(CVD)、旋塗製程、印刷製程或其他塗布方法形成的。在一些實施方式中，犧牲層108包括厚度為尺寸d1的材料層，其中尺寸d1約2μm到約5μm。作為另一實例，在一些實施方式中，尺寸d1約1μm到約10μm。或者，犧牲層108可包括其他材料、尺寸及其他形成方法。
使用晶粒鋸、雷射或其他裝置沿著切割線(未繪示)將積體電路晶粒106分離開來，以形成多個獨立的積體電路晶粒106，如圖3即呈現單一個積體電路晶粒106。在一些實施方式中，在分離過程之前，工件110的背側可以使用如研磨(grinding)程序來加以薄化。在其他實施方式中，工件110的背側未經薄化。
接著如圖4所示，提供載體100。載體100可包括晶圓(如半導體晶圓)，或載體100可包括有機基材或其他類型的基材。載體100包括在一或多個積體電路晶粒106(如圖3所呈現的積體電路晶粒106)封裝以後要被移除的犧性成分。載體100之後例如可接受清洗並用來封裝另一半導體元件。或者，在封裝製程後可棄置載體100。
載體100包括形成於其上的箔片(foil)和晶粒結合材料102。箔片例如對之後要從積體電路晶粒106移除載體100有所幫助。晶粒結合材料例如可以幫助積體 電路晶粒106接合至載體100。在一些實施方式中，箔片和晶粒結合材料102的晶粒結合材料也包括塗布在載體100的頂表面的暫時性結合層。暫時性結合層例如可包括約1μm到約10μm的3M供應的光熱轉換(light to heat conversion，LTHC)材料。暫時性結合層例如可使用沈積製程或旋塗製程形成。或者，箔片和晶粒結合材料102可包括其他材料、尺寸及其他形成方法。在一些實施方式中，並未包括箔片和晶粒結合材料102。
如圖4所示，將如圖3所示的多個積體電路晶粒106反轉過來，貼附到載體100上。配置在積體電路晶粒106上的犧牲層108例如耦接到載體100的頂表面。在一些實施方式中，在積體電路晶粒106的分離過程的前或後，晶粒貼附膜(DAF)(未繪示)例如可以形成在犧牲層108上。在一些實施方式中，DAF例如可包括膠(glue)、黏著劑或黏著膜，其適於將積體電路晶粒106黏著到配置在載體100上的箔片和晶粒結合材料102。在一些實施方式中，不包括DAF。例如，可使用選取置放機器(pick-and-place machine)、其他機構或以手動的方式將積體電路晶粒106貼附在載體100上(例如在配置於載體100上的箔片和晶粒結合材料102上)。
在一些實施方式中，單一個積體電路晶粒106耦接於載體100上(未繪示)。在其他實施方式中，多個積體電路晶粒106耦接於載體100上。在一些實施方式中，積體電路晶粒106個別被封裝在分離的封裝中。在其 他實施方式中，多個積體電路晶粒106並列(side-by-side)封裝在單一封裝中，例如封裝於二維(2D)封裝架構。根據一些實施方式，兩個或更多個積體電路晶粒106例如可一同被封裝。
將積體電路晶粒106耦接到載體100之後，將模塑料120環繞著積體電路晶粒106配置在載體100上，如圖5所示。在一些實施方式中，模塑料120是使用層合製程(laminating process)或其他製程形成的。模塑料120例如填滿了晶粒106之間的空間且將晶粒106封合(encapsulate)起來。模塑料120例如包括模製材料，且可包括環氧樹脂、有機高分子、二氧化矽基材(silica-based)的高分子或添加了玻璃填充物了高分子。在一些實施方式中，模塑料120包括液體模塑料(LMC)，施用時是膠狀液體。或者，模塑料120可包括其他絕緣材料且可以用其他方法施用。接著，以加熱製程、紅外(IR)能量曝射製程、紫外(UV)能量曝射製程或其他方法來固化模塑料120。
在一些實施方式中，如果固化製程後模塑料120延伸至積體電路晶粒106的頂表面，則例如使用化學機械研磨(CMP)、研磨(grinding)程序、蝕刻製程及/或其他方法將模塑料120從積體電路晶粒106上移除。在一些實施方式中，例如，因為在施用模塑料120和固化製程期間犧牲層108配置在積體電路晶粒106上，在模塑料120的施用和固化製程之後，模塑料120不會存在於積 體電路晶粒106上。在一些實施方式中，模塑料120環繞著積體電路晶粒106形成。
如圖6所示，移除載體100以及箔片和晶粒結合材料102。舉例而言，載體100可使用脫附(de-bonding)製程來移除，而箔片和晶粒結合材料102的移除則例如可以是先剝離箔片然後使用清洗製程移除晶粒結合材料。
如圖7所示，移除犧牲層108。在一些實施方式中，使用有機溶劑、有機酸或其他材料移除犧牲層。在一些實施方式中，例如可使用異丙醇(IPA)、丙酮或乙醇來移除犧牲層108。在移除犧牲層108之後，積體電路晶粒106和接觸墊114的表面被曝露出來。在一些實施方式中，圖7的視圖所呈現的模塑料120的頂部可在犧牲層108的移除製程中被移除。在其他實施方式中，模塑料120的頂部未被移除。
舉例而言，在一些實施方式中，因為犧牲層108在模塑料120的施用和固化製程期間是配置在積體電路晶粒106上，模塑料120不會存在於積體電路晶粒106上。在其他實施方式中，可能有一部分模塑料120形成在犧牲層108上，而配置在犧牲層108上的模塑料120的此部份最好在犧牲層108被移除的時候被一起移除。
在一些實施方式中，模塑料120具有尺寸為d2的第一厚度，而在一些實施方式中，積體電路晶粒106具有尺寸為d3的第二厚度。尺寸d2和d3例如可包括約 100μm到約500μm。在一些實施方式中尺寸d2大於尺寸d3。舉例而言，在一些實施方式中，尺寸d2比尺寸d3多出的量值約為尺寸d1。尺寸d1例如包括犧牲層108的厚度，且尺寸d1例如也包括模塑料120和積體電路晶粒106的厚度差。
作為另一例，尺寸d1也包括積體電路晶粒106和模塑料120之間的階梯高度差的量值。換言之，尺寸d1包括圖7的視圖所示的介於模塑料120的頂表面和積體電路晶粒106的頂表面之間的距離。
在圖7所示的封裝步驟中，封裝元件的新穎結構包括封合於模塑料120中的積體電路晶粒106，但模塑料120並沒有配置在積體電路晶粒106的頂表面。模塑料120的頂表面例如高於積體電路晶粒106的頂表面，如圖7的視圖所示。
如圖8所示，內連線結構122形成在積體電路晶粒106和模塑料120上。內連線結構122包括多個絕緣材料層124和多條導線126以及在絕緣材料層124內形成的多個導電通孔128。內連線結構122可包括形成在其表面附近的多個接觸墊130。舉例而言，在一些實施方式中，接觸墊130可包括球格陣列(ball grid array，BGA)的球底座(ball mounts)。作為另一實例，在一些實施方式中，內連線結構122的一些部份包括焊球下金屬化(under-ball metallization，UBM)結構。舉例而言，在一些實施方式中，絕緣材料層124可包括聚苯並噁 唑(polybenzoxazole，PBO)或其他絕緣體，而導線126、導電通孔128和接觸墊130可包括Cu、Al、其他金屬或前述材料的合金或疊層。內連線結構122的多個絕緣材料層124、多個導線126、多個導電通孔128和接觸墊130例如可以使用減蝕刻法(subtractive etch technique)、大馬士革法(damascene technique)、其他方法或前述方法的組合來形成。內連線結構122例如配置在積體電路晶粒106和模塑料120上。
在一些實施方式中，內連線結構122例如可包括再分布層(RDL)或鈍化後內連線(post-passivation interconnect，PPI)結構。在一些實施方式中，內連線結構122例如包括封裝的半導體元件用的水平電引線(electrical connections，見圖9所示的封裝的半導體元件140)。在一些實施方式中，內連線結構122可包括扇出(fan-out)電引線。舉例而言，在兩個或更多的積體電路晶粒106封裝在一起的實施方式中，內連線結構122可包括在積體電路晶粒106之間的水平電引線。或者，內連線結構122可包括其他類型的電引線結構。
由於介於積體電路晶粒106和模塑料120之間的尺寸d1的階梯高度差，一部分內連線結構122往下延伸到低於模塑料120的頂表面，如圖8的視圖所示。例如，和積體電路晶粒106的接觸墊114耦接的絕緣材料124的較低部份和導電通孔128的較低部份即延伸到低於模塑料120的頂表面，以和積體電路晶粒106電性連接。
在一些實施方式中，多個導電體132耦接到內連線結構122，如所示圖9。舉例而言，在一些實施方式中，多個導電體132耦接到內連線結構122的某些部份。在一些實施方式中，多個導電體132可以耦接到內連線結構122的接觸墊130，如圖9所示。舉例而言，在一些實施方式中，導電體132是形成並耦接在內連線結構122的水平電引線的某些部份上。
例如，導電體132可包括共晶材料(eutectic material)，例如焊料，其與內連線結構122的接觸墊130或焊墊耦接。導電體132例如可各自包括焊塊(solder bump)或焊球(solder ball)。導電體132可作為封裝的半導體元件的電連接器。舉例而言，導電體132的共晶材料可經回流(re-flowed)以將封裝的半導體元件電性連接和機械性連接至另一元件或物件。
在本文中，使用「焊料」這樣的字眼同時包括鉛基焊料和無鉛焊料，鉛基焊料例如Pb-Sn組合物；無鉛焊料包括Insb，錫、銀和銅(「SAC」)組合物；也包括其他具有相同熔點且在電子應用上能形成導電焊料的共晶材料。就無鉛焊料而言，可使用多種組成成份的SAC焊料，例如SAC 105(Sn 98.5%，Ag 1.0%，Cu 0.5%)、SAC 305、SAC 405。無鉛的導電體132(如焊球)也可以由SnCu化合物形成，而無須使用銀(Ag)。或者，無鉛的焊料連接器可包括錫和銀(Sn-Ag)而不使用銅。導電體132可以是導電體132陣列 (被稱為「球格陣列(ball grid array)」或「BGA」)中的一個。導電體132也可以被安置成其他型態。導電體132例如也可以包括非球形的導電連接器。在一些實施方式中，未包括導電體132。
如圖10所示，在一些實施方式中，使用晶粒鋸、雷射或其他裝置分離內連線結構122和模塑料120，以形成多個封裝的半導體元件140，每一個封裝的半導體元件140包括多個積體電路晶粒106中的一者。舉例而言，內連線結構122和模塑料120可以沿著相鄰的積體電路晶粒106間的切割線133分離，如圖9所示。在一些實施方式中，可以在分離製程前先將封裝的半導體元件140貼到切割膠帶(dicing tape，未繪示)，然後在分離製程之後移除切割膠帶。
在其他實施方式中，分離內連線結構122和模塑料120以形成多個封裝的半導體元件140(見圖13、14和15)，每一個封裝的半導體元件140包括兩個或更多個積體電路晶粒106。舉例而言，被一起封裝在封裝的半導體元件140中的積體電路晶粒106可以包括相似、相同或不同的功能。模塑料120環繞著積體電路晶粒106配置，也配置在相鄰的積體電路晶粒106之間。
根據一些實施方式，圖11和12繪示封裝半導體元件的方法在各階段的剖面圖。在圖1到圖7所示的封裝製程的步驟之後，多個連通柱(through-vias)138形成在模塑料120內。舉例而言，連通柱138可以使用以 下方法形成：在施用模塑料120後，以蝕刻製程或雷射鑽孔製程在模塑料120中形成孔洞，接著可使用沈積或電鍍製程將導電材料填入孔洞中以形成連通柱138。在其他實施方式中，在積體電路晶粒106貼附到載體100之前，可以透過以下方法將連通柱138鍍(plate)在載體100上：在載體100上形成種晶層(seed layer)，在種晶層上形成光阻，以微影製程圖案化光阻，以及穿過經圖案化的光阻在種晶層上電鍍導電材料(例如Cu、Cu合金或其他金屬)以形成連通柱138。接著移除光阻。接著，進行圖4到7所示的封裝製程的步驟。或者，可使用其他方法形成連通柱138。接著，進行圖8和9所示的封裝製程步驟以形成內連線結構122和導電體132，如圖12所示，然後沿著切割線133分離封裝的半導體元件140’。
在一些實施方式中，封裝的半導體元件140(以及封裝的半導體元件140’，未繪示)的多個導電體132耦接到基材144，如圖13的剖面圖所示。在一些實施方式中基材144可包括印刷電路板(PCB)。或者，基材144可包括其他材料，例如中介層、另一積體電路晶粒或其他物件。封裝的半導體元件150包括耦接到基材144的封裝的半導體元件140。
在一些實施方式中，底部填充材料146可配置在多個導電體132之間，也配置在基材144和內連線結構122之間，如圖13所示。底部填充材料146例如可包括環氧樹脂材料、SiO2填料或其他填料或其他材料。底部 填充材料146例如可使用尖針沿著一側或多側施用於封裝的半導體元件150，或是透過形成於模塑料120和內連線結構122內的孔洞(未繪示)施用。
模塑料120在本文也被稱為第一模塑料120。在一些實施方式中，第二模塑料134環繞多個導電體132配置，如圖14所示。舉例而言，第二模塑料134可包括和前述第一模塑料120相似的材料。在一些實施方式中，第二模塑料134包括LMC。在一些實施方式中，未包括第二模塑料134。在其他實施方式中，包括第二模塑料134但未包括底部填充材料146。
在一些實施方式中，封裝的半導體元件150包括第二模塑料134，且亦包括底部填充材料146，如圖14所示。舉例而言，第二模塑料134可配置在多個導電體132之間，也配置在底部填充材料146和內連線結構122之間。
在一些實施方式中，蓋體(lid)、散熱器或背側保護膜142配置在模塑料120和積體電路晶粒106上，如圖15所示。蓋體或散熱器142例如可包括Al、Cu、其合金、陶瓷或其他材料，厚度在約100μm到約1,000μm間，或具其他尺寸。保護膜142例如可包括約10μm到約100μm的高分子、環氧樹脂或其他材料。舉例而言，蓋體、散熱器或背側保護膜142可以使用黏著劑貼附或使用沈積或塗布製程形成。或者，蓋體、散熱器或背側保護膜142可不存在。
在一些實施方式中，內連線結構122配置在積體電路晶粒106和模塑料120的第一側上(例如在圖15所示的視圖的底側)。蓋體、散熱器或背側保護膜142則配置在積體電路晶粒106和模塑料120的第二側上(例如在圖15所示的視圖的頂側)。積體電路晶粒106和模塑料120的第二側和第一側相對。
根據一些實施方式，圖16和圖17是圖15所示的封裝的半導體元件150的某些部份的更詳細視圖。圖16呈現積體電路晶粒106的下方角落(靠近模塑料120處)的剖面圖。內連線結構122包括尺寸d1(模塑料和積體電路晶粒106之間的階梯高度差；例如，在施用模塑料120之後，積體電路晶粒106的表面和模塑料120的表面不同)的部份被呈現出來。尺寸d1的階梯高度差帶來的好處是，避免或減少在靠近內連線結構122及/或模塑料120的積體電路晶粒106之間形成凹陷，此凹陷可能在模塑料120的固化製程期間或用來封裝半導體元件的研磨程序期間出現。
在一些實施方式中，模塑料120包括內含玻璃球152的填料，如圖17以剖面圖所示。舉例而言，在一些實施方式中，背側保護膜142的存在帶來的好處是，封裝製程中使用的研磨程序將不會對模塑料120的填料產生負面影響。
根據一些實施方式，圖18繪示封裝的半導體元件160的剖面圖。根據一些實施方式，封裝的半導體元 件160包括層疊封裝(package-on-package，PoP)元件。PoP元件160包括和封裝的半導體元件170耦接的本文描述的封裝的半導體元件150。根據一些實施方式，舉例而言，封裝的半導體元件150包括第一封裝的半導體元件，且封裝的半導體元件170包括和封裝的半導體元件150耦接的第二封裝的半導體元件。
封裝的半導體元件150包括形成在模塑料120內的多個連通柱138。連通柱138為封裝的半導體元件150和160提供了垂直的電性連結。接觸墊164耦接至連通柱138。接觸墊164可以形成在模塑料120上或模塑料120內，如圖18所示。封裝的半導體元件150的接觸墊164藉由導電體178耦接到封裝的半導體元件170的接觸墊(未繪示)，導電體178可包括焊球或其他材料。舉例而言，導電體178可包括和針對導電體132所述者相似的材料。
封裝的半導體元件170包括耦接至基材174的一或多個積體電路晶粒176。焊線172可以耦接至在積體電路晶粒176頂表面的接觸墊，而積體電路晶粒176又耦接到基材174上的焊墊(未繪示)。模塑料168可以配置在焊線172、積體電路晶粒176和基材174上。
或者，在一些實施方式中，PoP元件160可包括兩個耦接在一起的本文描述的封裝的半導體元件150(圖式中未繪示)。作為另一實例，在一些實施方式中，PoP元件160可包括系統單晶片(system-on-a-chip， SOC)元件。
在圖13到15和18中，沒有顯示出尺寸d1的階梯高度差，然而，根據本揭露的一些實施方式，圖13到15和18的封裝的半導體元件150和160包括圖7到12所顯示的介於模塑料120和積體電路晶粒106間的階梯高度差。
圖19是根據一些實施方式的封裝半導體元件的方法的流程圖180。在步驟182中，將犧牲層108(也見圖2)配置在積體電路晶粒106上。在步驟184中，將積體電路晶粒106耦接到載體100(圖4)。在步驟186中，將模塑料120環繞積體電路晶粒106(圖5)配置。在步驟188中，移除犧牲層108(圖7)。在步驟190中，在積體電路晶粒106和模塑料120上形成內連線結構122(圖8)。
本揭露的實施方式包括封裝半導體元件的方法，也包括使用本文描述的方法封裝的半導體元件。一些實施方式包括內含本文所述的封裝的半導體元件的PoP元件。舉例來說，一些實施方式對於執行晶圓級封裝(WLP)應用、扇出WLP(FOWLP)應用、2D封裝、3D封裝以及其他類型的封裝是特別有益的。
本揭露的一些實施方式的優點包括提供新穎的犧牲層108以及封裝製程，其結果是介於模塑料和封合於模塑料內的積體電路晶粒之間的凹陷現象得到抑制。在一些實施方式中，犧牲層108也避免或減少了模塑料在積體 電路晶粒上的溢流，避免在積體電路晶粒上形成模塑料殘留物。可能形成在犧牲層108上的殘留模塑料在移除犧牲層的時候也被移除，因此避免了從積體電路晶粒上移除多餘的模塑料所需的研磨程序。藉由避免或抑制模塑料和積體電路晶粒間的凹陷，犧牲層108也可避免內連線結構故障。藉由執行本揭露的實施方式，可以提昇封裝產率。此外，這種新穎的封裝半導體元件和方法容易在封裝製作過程中進行。
在一些實施方式中，封裝的半導體元件包括積體電路晶粒、環繞積體電路晶粒配置的模塑料以及配置在積體電路晶粒和模塑料上的內連線結構。模塑料比積體電路晶粒厚。
在其他實施方式中，封裝半導體元件的方法包括在積體電路晶粒上配置犧牲層以及將積體電路晶粒耦接至載體。將模塑料環繞著積體電路晶粒配置。移除犧牲層，將內連線結構形成在積體電路晶粒和模塑料上。
在其他實施方式中，封裝半導體元件的方法包刮在具有多個積體電路晶粒的晶圓上配置犧牲層，分離多個積體電路晶粒以及將多個積體電路晶粒耦接到載體。將模塑料環繞多個積體電路晶粒配置。此方法包括移除載體、移除犧牲層以及在多個積體電路晶粒和模塑料上形成內連線結構。
前文概述了幾種實施方式的特徵，使本技術領域中具有通常知識者更易於理解本揭露的態樣。所屬技術 領域中具有通常知識者應理解，以本揭露作為基礎，他們可以輕易地設計或修改其他製程和結構，以實現和這些本文介紹的實施方式相同的目的及/或達到相同的優點。所述技術領域中具有通常知識者也應理解，此類均等架構並不超出本揭露的意旨和範圍，他們可以在本揭露的意旨和範圍內做出各式各樣的改變、取代和變化。
180‧‧‧流程圖
182、184、186、188、190‧‧‧步驟

Claims (9)

  1. 一種封裝的半導體元件，包括：一積體電路晶粒；一模塑料，環繞著該積體電路晶粒配置，其中該積體電路晶粒和該模塑料之間具有一階梯高度差；以及一內連線結構，配置於該積體電路晶粒和該模塑料上，其中該模塑料比該積體電路晶粒厚。
  2. 如申請專利範圍第1項所述之封裝的半導體元件，其中該模塑料比該積體電路晶粒厚1μm至10μm。
  3. 如申請專利範圍第1項所述之封裝的半導體元件，其中該內連線結構配置於該積體電路晶粒的一第一側上，且其中該封裝的半導體元件更包括一蓋體、一散熱器或一背側保護膜，配置於該積體電路晶粒的一第二側上，該第二側和該第一側相對。
  4. 如申請專利範圍第1項所述之封裝的半導體元件，更包括：多個導電體，耦接至該內連線結構的部份，其中該些多個導電體耦接至一基材；一底部填充材料，配置於該些多個導電體之間以及於該基材和該內連線結構之間，其中該模塑料包括一第一模塑料，且其中該封裝的半導體元件更包括一第二模塑料， 配置於該些多個導電體之間以及於該底部填充材料和該內連線結構之間。
  5. 一種層疊封裝(package-on-package，PoP)元件，包括申請專利範圍第4項所述之封裝的半導體元件，其中該封裝的半導體元件包括一第一封裝的半導體元件，且該層疊封裝元件更包括一第二封裝的半導體元件，耦接至該第一封裝的半導體元件。
  6. 一種封裝半導體元件的方法，該方法包括：配置一犧牲層於一積體電路晶粒上，其中該積體電路晶粒具有一第一最外邊緣和一第二最外邊緣，該犧牲層覆蓋該積體電路晶粒之由該第一最外邊緣延伸至該第二最外邊緣的一表面；耦接該積體電路晶粒至一載體；配置一模塑料以環繞該積體電路晶粒；移除該犧牲層；形成一內連線結構於該積體電路晶粒和該模塑料上；以及耦接多個導電體至該內連線結構，其中配置該模塑料的步驟包括配置一第一模塑料，且其中該封裝半導體元件的方法更包括配置一第二模塑料以環繞該些多個導電體，其中配置該第二模塑料的步驟包括配置一液體模塑料(LMC)。
  7. 如申請專利範圍第6項所述之封裝半導體元件的方法，其中形成該內連線結構的步驟包括形成一再分布層(RDL)或一鈍化後內連線(PPI)結構。
  8. 一種封裝半導體元件的方法，該方法包括：配置一犧牲層於包括多個積體電路晶粒的一晶圓上；分離該些多個積體電路晶粒；耦接該些多個積體電路晶粒至一載體；配置一模塑料以環繞該些多個積體電路晶粒，其中該模塑料之一第一表面與該犧牲層之一第二表面共平面；移除該載體；移除該犧牲層，以形成一階梯高度差於該些多個積體電路晶粒的表面和該模塑料的該第一表面之間；以及形成一內連線結構於該些多個積體電路晶粒和該模塑料上。
  9. 如申請專利範圍第8項所述之封裝半導體元件的方法，其中配置該犧牲層的步驟包括配置實質上由光阻材料、有機材料、高分子材料及其組合所組成的族群選出的一材料。
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