TWI527165B - 半導體封裝結構與其製法 - Google Patents

半導體封裝結構與其製法 Download PDF

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TWI527165B
TWI527165B TW102114136A TW102114136A TWI527165B TW I527165 B TWI527165 B TW I527165B TW 102114136 A TW102114136 A TW 102114136A TW 102114136 A TW102114136 A TW 102114136A TW I527165 B TWI527165 B TW I527165B
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interposer
layer
semiconductor
semiconductor die
mold
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TW102114136A
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TW201349402A (zh
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黃暉閔
胡延章
林志偉
鄭明達
劉重希
陳承先
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台灣積體電路製造股份有限公司
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

半導體封裝結構與其製法
本發明係有關於一種半導體封裝結構，且特別是有關於一種具有中介層架構(interposer frame)之半導體封裝結構。
半導體元件使用於各種的電子應用領域，例如個人電腦、手機、數位相機及其他電子設備。半導體元件一般係利用下述方法製成，包括連續地沉積絕緣體或介電材料層、導電材料層，以及材料半導體層於基板之上，並且利用微影製程對上述各層進行圖案化，藉以形成電路元件及組件於其上。
半導體產業藉由持續降低最小特徵結構之尺寸，使各種電子元件(例如：電晶體、二極體、電阻、電容等)的積體密度(integration density)持續改善，因而能夠將更多元件整合在一指定區域中。在一些應用中，較小的電子元件比起先前的封裝尺寸，僅需佔據較小的面積與高度，而達到更小的封裝尺寸。
因此，早已開始發展新的封裝技術，例如晶圓級封裝(wafer level packaging,WLP)與封裝體層疊(package on package,PoP)。這些應用於半導體產業的新穎封裝技術面臨製造上的挑戰。
本發明提供一種半導體封裝結構，包括：一中介層架構(interposer frame)，其中該中介層架構包括複數個導電柱(conductive columns)；一半導體晶粒設置於該中介層架構一開口中，其中該開口位於該中介層架構之中；一模造成型化合物(molding compound)介於該中介層架構與該半導體晶粒之間；以及一佈線層(wiring layer)，其中該佈線層連接位於該半導體晶粒中之各種元件與該中介層架構之該些導電柱。
本發明另提供一種半導體封裝結構，包括：一中介層架構，其中該中介層架構包括複數個導電柱；一半導體晶粒設置於該中介層架構一開口中，其中該開口位於該中介層架構之中；一模造成型化合物介於該中介層架構與該半導體晶粒之間；一佈線層，其中該佈線層連接位於該半導體晶粒中之各種元件與該中介層架構之該些導電柱；以及一另一佈線層位於該半導體晶粒相對於原有之該佈線層之另外一側，其中該另一佈線層與該中介層架構之該些導電柱連接。
本發明亦提供一種半導體封裝結構之製法，包括以下步驟：提供一半導體晶粒；提供一中介層架構，其中該中介層架構包括複數個導電柱；設置該半導體晶粒於該中介層架構之一開口中；形成一模造成型化合物填充於該中介層架構與該半導體晶粒之間的空間；移除該模造成型化合物之一部份，以暴露該些導電柱；以及形成一重新分配層，其中該重新分配層連接位於該半導體晶粒中之各種元件與該些導電柱。
為讓本發明之上述和其他目的、特徵、和優點能 更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
100‧‧‧晶片封裝
110‧‧‧封裝晶粒
111‧‧‧封裝通孔(through-package vias,TPVs)
112‧‧‧凸塊結構
115‧‧‧晶粒
120‧‧‧中介層
121‧‧‧基板通孔(through-substrate vias,TSVs)
122‧‧‧外部連接器(external connectors)
130‧‧‧封裝晶粒
132‧‧‧凸塊結構
135‧‧‧晶粒
200‧‧‧晶粒封裝
210‧‧‧晶粒
220‧‧‧封裝架構(packaging frames)
221‧‧‧導電柱(conductive columns)
222‧‧‧接合線
225‧‧‧模造成型化合物(molding compound)
300‧‧‧中介層架構(interposer frame)
305‧‧‧罩幕層(mask layers)
306‧‧‧罩幕層
307‧‧‧未受蝕刻表面(un-etched surfaces)
308‧‧‧開口
310‧‧‧導電基板
320‧‧‧模造成型化合物
320’‧‧‧模造成型化合物
330‧‧‧導電柱或鑄模通孔(through-molding vias,TMVs)
340‧‧‧半導體晶粒設置區域
400‧‧‧封裝晶粒
410‧‧‧模造成型化合物
411‧‧‧中介層架構
415‧‧‧鑄模通孔
420‧‧‧承載基板(carrier)
421‧‧‧黏接層
422‧‧‧模造成型化合物
430‧‧‧重新分配層(redistribution layer,RDL)
440‧‧‧承載基板
441‧‧‧黏接層
450‧‧‧半導體晶粒
451‧‧‧內連線(interconnect)
460‧‧‧重新分配層(redistribution layer,RDL)
461‧‧‧鈍化層
465‧‧‧凸塊
500‧‧‧封裝晶粒
508‧‧‧佈線層(wiring layer)
524‧‧‧基板
526a‧‧‧絕緣層
526b‧‧‧絕緣層
526c‧‧‧絕緣層
527‧‧‧金屬墊
528‧‧‧接觸墊
532a‧‧‧絕緣層
532b‧‧‧絕緣層
534‧‧‧凸塊下方金屬化(UBM)層
542‧‧‧絕緣層
544‧‧‧凸塊下方金屬化(UBM)層
558‧‧‧佈線層
560‧‧‧焊料凸塊
415*‧‧‧鑄模通孔
450’‧‧‧半導體晶粒
670‧‧‧導電區域
671‧‧‧開口
675‧‧‧光阻層
680‧‧‧導電層
870‧‧‧釘狀凸塊(stud bumps)
871‧‧‧釘狀凸塊區域(stud bumps section)
872‧‧‧導線區域
H‧‧‧總長度
971‧‧‧開口
980‧‧‧焊料球(solder ball)
415’‧‧‧鑄模通孔
415”‧‧‧鑄模通孔
410*‧‧‧模造成型化合物
411*‧‧‧中介層架構
420*‧‧‧承載基板(carrier)
421*‧‧‧黏接層
415^‧‧‧鑄模通孔
415*‧‧‧鑄模通孔
450*‧‧‧半導體晶粒
985*‧‧‧焊料球
410^‧‧‧模造成型化合物
415A‧‧‧鑄模通孔
415B‧‧‧鑄模通孔
第1圖顯示依據本發明實施例之晶片封裝之剖面圖。
第2A圖顯示依據本發明實施例之封裝晶粒之剖面圖。
第2B圖顯示依據本發明實施例之第2A圖之俯視圖。
第3A圖到第3D圖顯示形成中介層架構(interposer frame)之連續製程之剖面圖。
第4A圖到第4I圖顯示形成封裝半導體晶粒之連續製程之剖面圖。
第5圖顯示形成封裝晶粒的一部份之剖面圖。
第6圖顯示形成封裝晶粒之剖面圖。
第7A圖到第7C圖顯示形成導電區域之連續製程之剖面圖。
第8圖顯示形成帶有導線的釘狀凸塊(stud bumps)於中介層架構(interposer frame)之鑄模通孔(TMVs)之上。
第9A圖及第9B圖顯示於中介層架構的鑄模通孔上形成導電區域之連續製程之剖面圖。
第10A圖到第10D圖顯示於中介層架構的鑄模通孔上形成導電區域之連續製程之剖面圖。
第11A圖到第11B圖顯示鑄模通孔(TMVs)之剖面圖。
依據本發明之部份實施例，第1圖顯示一晶片封裝 (chip package)之剖面圖。晶片封裝100為一封裝體層疊(package on package,PoP)結構，此封裝體層疊(package on package,PoP)結構具有封裝晶粒(packaged die)130位於封裝晶粒110之上，其中封裝晶粒130具有晶粒135，封裝晶粒110具有晶粒115。晶片封裝100亦包括一中介層120，其中中介層120具有基板通孔(through-substrate vias,TSVs)121及外部連接器(external connectors)122。封裝晶粒110與中介層120透過凸塊結構(bump structures)112彼此連接。封裝晶粒110與封裝晶粒130透過凸塊結構132彼此連接。封裝晶粒110亦具有封裝通孔(through-package vias,TPVs)111，其中封裝通孔111之長寬比(aspect ratio)較基板通孔121之長寬比為高。如此一來，形成封裝通孔111成為一大挑戰。此外，由於具有中介層120位於封裝晶粒130及封裝晶粒110之下，晶片封裝100具有相對大的高度，因此其外觀尺寸(form factor)難以滿足需求。再者，矽基中介層(silicon-based interposer)120與位於中介層120下方的印刷電路板(printed circuit board,PCB)之間熱膨脹係數(Coefficient of thermal expansion,CTE)不匹配的程度很高。新的封裝機制具有比使用中介層120更佳的外觀尺寸(form factor)，不僅能夠保留基板通孔121位於中介層120之中的結構在熱管理(thermal management)方面的優點，亦可解決上述問題。
近年來封裝架構(packaging frames)已應用於積體電路(integrated circuit,IC)封裝中。這些封裝架構具有導電柱(conductive columns)並且被安裝於封裝晶粒周圍，其中導電柱 具備與矽通孔(through-silicon vias)相仿的散熱(thermal dissipation)功能。由於封裝架構固定於封裝晶粒周圍，因此其外觀尺寸(form factor)小於中介層120。舉例而言，此種封裝架構包括但不限於下列公司之產品：新加坡ASM太平洋公司的DreamPak(DreamPak of ASM Pacific Technology Ltd.of Singapore)以及台灣台北日月光公司的無鉛-aQFN封裝(Leadless-aQFN by ASE Inc.of Taipei,Taiwan)。
依據本發明之部份實施例，第2A圖顯示具有晶粒210的晶粒封裝200之剖面圖，其中晶粒210利用封裝架構(packaging frames)220進行封裝。封裝架構220具有複數個導電柱221，其中導電柱221藉由接合線(bonding wires)222連接至位於晶粒210上之接觸插塞(contacts)(未顯示於圖中)。導電柱221提供電性連接至外部元件(未顯示於圖中)，並且增加散熱性。封裝晶粒210至少部份地受到模造成型化合物(molding compound)225所包圍。依據本發明之部份實施例，第2B圖顯示晶粒封裝200之俯視圖，其中並未顯示接合線222。封裝架構，例如封裝架構220，可提供與中介層相仿的功能，例如熱管理與電性連接至封裝基板。封裝架構的製造成本遠低於中介層。此外，由於封裝架構220緊鄰於晶粒210而設置，並非設置於晶粒210下方，因此具有封裝架構的封裝，其外觀尺寸小於具有中介層的封裝。再者，封裝架構220的製程解決難以形成封裝通孔(例如上述之封裝通孔111)的問題。此外，封裝架構220與位於其下方的印刷電路板之間熱膨脹係數(Coefficient of thermal expansion,CTE)不匹配的程度較低。
然而，使用接合線222連接位於晶粒210上之接觸插塞(contacts)至導電柱221，使得封裝可在二維等級(2-D level)下進行，而非三維等級(3-D level)。對先進的封裝製程而言，堆疊封裝於封裝之上可提高封裝密度。因此需要發展利用封裝架構形成封裝晶粒的不同機制。
依據本發明之部份實施例，第3A圖到第3D圖顯示形成中介層架構(interposer frame)300之連續製程之剖面圖。依據本發明之部份實施例，如第3A圖所示，可藉由圖案化罩幕層(mask layers)305與罩幕層306，並且蝕刻導電基板310，以形成中介層架構300。導電基板310可由金屬所組成，其中金屬可包括銅(copper)、銅合金(copper alloy)或其他種金屬或其他種合金。罩幕層305與罩幕層306可由具有化學蝕刻製程抗性的材料所組成，其中此化學蝕刻製程係用於蝕刻導電基板310以形成開口308。舉例而言，罩幕305與罩幕層306可由光阻或導電性材料所組成。依據本發明之部份實施例，用於形成開口308的蝕刻製程可以是溼式蝕刻(wet etch)。
接著，如第3B圖所示，移除罩幕層305，並且形成模造成型化合物320於導電基板310受到蝕刻的一側之上，以填充開口308，並且覆蓋於未受蝕刻表面(un-etched surfaces)307之上。形成模造成型化合物320於導電基板310受到蝕刻的一側之後，對導電基板310的另一側，亦即藉由罩幕層306而圖案化的一側，進行蝕刻。依據本發明之部份實施例，如第3C圖所示，導電基板310未受到蝕刻的的部份形成導電柱330。在本發明之部份實施例中，導電柱330的其中一側之表面為曲面。導電柱 330亦可稱為鑄模通孔(through-molding vias,TMVs)。接著，形成模造成型化合物320’於導電基板310受到蝕刻的一側之上。在本發明之部份實施例中，模造成型化合物320與模造成型化合物320’由相同的材料所組成。可實施其他的製程於導電基板310之上，以暴露出導電柱330，並且移除位於區域340之模造成型化合物320與模造成型化合物320’，其中區域340係設計為用於設置半導體晶粒(例如第2A圖所示之晶粒210)的區域。依據本發明之部份實施例，第3D圖顯示中介層架構300之完成品。在本發明之部份實施例中，並未形成模造成型化合物320’，且中介層架構300僅包括模造成型化合物320。
第3A圖到第3D圖顯示並敘述之連續製程，用以說明如何形成中介層架構300。此製程非常簡單。如此一來，形成中介層架構300的成本可以維持低成本。
依據本發明之部份實施例，第4A圖到第4I圖顯示形成封裝半導體晶粒之連續製程之剖面圖。第4A圖顯示中介層架構411貼合至承載基板(carrier)420。承載基板420包括黏接層(adhesive layer)421，藉以固定中介層架構411。在本發明之一個或多個實施例中，承載基板420承載多個中介層架構411，其中中介層架構411包括模造成型化合物410。可藉由如前文所述第3A圖到第3D圖顯示之連續製程形成中介層架構411。中介層架構411包括多個鑄模通孔(TMVs)415，其中鑄模通孔(TMVs)415受到模造成型化合物410的包圍而各自隔離。
第4B圖顯示半導體晶粒450貼合至黏接層421。半導體晶粒450包括複數個元件(未顯示於圖中)以及內連線 (interconnect)451。半導體晶粒450之前側面對黏接層421。若承載基板420承載多於一個中介層架構411，則每一個中介層架構411皆有一個半導體晶粒450與其貼合。
依據本發明之部份實施例，如第4C圖所示，在半導體晶粒450放置並安裝於黏接層421之上以後，形成模造成型化合物422以填充介於半導體晶粒450與中介層架構411之間的空間，並且覆蓋於半導體晶粒450與中介層架構411的表面之上。形成模造成型化合物422可包括施加模造成型化合物材料於半導體晶粒450與中介層架構411之上，並且固化該模造成型化合物材料。
接著，依據本發明之部份實施例，如第4D圖所示，移除模造成型化合物422之一部份，以暴露鑄模通孔(TMVs)415。移除製程可以是研磨製程(grinding process)、拋光製程(polishing process)或上述之結合。依據本發明之部份實施例，如第4E圖所示，暴露出鑄模通孔(TMVs)415以使其電性接觸重新分配層(redistribution layer,RDL)430。重新分配層(RDL)430具有導電性且能夠形成與另一封裝晶粒連接的接觸插塞(contacts)。重新分配層(RDL)430也能夠連接另一封裝晶粒與鑄模通孔(TMVs)415。形成重新分配層(RDL)430可包括形成一層或多層的鈍化層(passivation layers)以隔離導電結構。此一層或多層的鈍化層亦可緩和施加於連接部位的應力，其中此連接部位介於封裝半導體晶粒450以及其他與封裝半導體晶粒450接合的封裝晶粒之間。可形成凸塊(未顯示於圖中)於重新分配層(RDL)430之上，藉以與其他封裝晶粒產生物理性及電性 連接。下列專利申請案對於形成重新分配層(RDL)430以及形成位於重新分配層(RDL)430之上的凸塊(bumps)的方法有詳盡的描述，包括共同申請中的(co-pending)且經常被引用的專利申請案：專利申請案號No.13/228,244，專利名稱為「使用晶粒貼合薄膜(Die Attach Film)之封裝方法及結構」，且申請日為2011年9月8日，此案全部併入本文作為參考。
依據本發明之部份實施例，如第4F圖所示，在形成具有所需凸塊的重新分配層(RDL)430之後，從部份封裝之半導體晶粒450上將承載基板420連同黏接層421一起移除。部份封裝之半導體晶粒450的背側放置於另一承載基板440之上，其中承載基板440可包括黏接層441。依據本發明之部份實施例，如第4G圖所示，部份封裝之半導體晶粒450的前側接著進行製程，以形成重新分配層(RDL)460於部份封裝之半導體晶粒450的前側之上。在本發明之部份實施例中，重新分配層(RDL)460能夠利用外部接觸(例如凸塊或焊球)對位於半導體晶粒450上之各種元件產生扇出型(fan-out)的連接，其中此類連接係指超出半導體晶粒邊界之外的連接。如上文所述，形成重新分配層(RDL)460可包括形成一層或多層的鈍化層(例如鈍化層461)介於半導體晶粒450/中介層架構411與重新分配層(RDL)460之間。
接著，依據本發明之部份實施例，如第4H圖所示，形成凸塊465於重新分配層(RDL)430之上。凸塊465可用於將封裝晶粒450接合到一基板或另一封裝晶粒。如第4I圖所示，形成凸塊之後，位於承載基板440之上的多個封裝晶粒被切割為 個別獨立的封裝晶粒，其中承載基板440以及黏接層441皆已移除。
依據本發明之部份實施例，第5圖顯示形成封裝晶粒400的一部份500之剖面圖。依據本發明之部份實施例，第5圖亦顯示半導體晶粒450、重新分配層(RDL)430與重新分配層(RDL)460之更詳細的剖面圖。第5圖所顯示的半導體晶粒450、重新分配層(RDL)430與重新分配層(RDL)460之剖面圖僅用以舉例說明；除此之外，半導體晶粒450、重新分配層(RDL)430與重新分配層(RDL)460可包括其他構形(configurations)、佈局(layouts)及/或設計(designs)。在第5圖所顯示的實施例中，晶粒450包括基板524，其中基板524包括矽或其他半導體材料。絕緣層(Insulating layers)526a與絕緣層526b設置於基板524之上。絕緣層526a可包括未摻雜之氧化矽(undoped silicon oxide)、低介電常數(low-dielectric-constant,low-K)之介電材料以及經摻雜之介電薄膜(doped dielectric films)。在本發明之部份實施例中，低介電常數(low-K)之介電材料具有介電常數小於約3.5。在本發明之其他部份實施例中，介電常數值(k value)小於約2.5。絕緣層526b可由一層或多層的介電材料層所組成，其中介電材料層可包括氧化物(oxide)、氮化物(nitride)、聚亞醯胺(polyimide)、絕緣高分子(insulating polymers)及其他合適之材料。
晶粒450之接觸墊(contact pads)528可形成於基板的導電特徵(conductive features)之上，其中導電特徵可包括用以使基板524的主動特徵(active features)產生電性接觸的金屬 墊(metal pads)527、插塞(plugs)、導通孔(vias)或導電線路(conductive lines)，其中插塞、導通孔及導電線路並未顯示於圖中。接觸墊528與金屬墊527為上述內連線451的一部份。接觸墊528可形成於絕緣層526c之中，其中絕緣層526c可包括高分子層或其他絕緣材料。
佈線層(wiring layer)508包括絕緣層532a與絕緣層532b，其中絕緣層532a與絕緣層532b包括高分子或其他絕緣材料。如第5圖所示，重新分配層(RDL)460形成於絕緣層532a與絕緣層532b之中，其中一部份之重新分配層(RDL)460與位於晶粒450之上的接觸墊528產生電性接觸。如圖所示，可視需要形成凸塊下方金屬化(under bump metallization,UBM)結構(或層狀構造)534於重新分配層(RDL)460和絕緣層532b的部份之上。舉例而言，凸塊下方金屬化(UBM)結構534使凸塊(或焊球)465的連接和形成較為容易。凸塊465可由焊料所形成，亦有可能是銅柱凸塊(copper pillar bumps)。在本發明之其他實施例中，凸塊465可以是其他種類的外部接觸(external contacts)。
封裝晶粒450的一部份500之另一側包括佈線層(wiring layer)558，其中佈線層558可包括絕緣層542及重新分配層(RDL)430。絕緣層542可由高分子或其他絕緣材料所形成。重新分配層(RDL)430的部份與重新分配層(RDL)460的部份接觸一個或多個鑄模通孔(TMVs)415。如第5圖所示，可視需要形成凸塊下方金屬化(UBM)層544於重新分配層(RDL)430的部份之上。凸塊下方金屬化(UBM)結構544使非必需之凸塊(或焊球)560的連接和形成較為容易。凸塊560可由焊料所形成，亦 有可能是銅柱凸塊(copper pillar bumps)。在本發明之其他實施例中，凸塊560可以是其他種類的外部接觸(external contacts)。在本發明之部份實施例中，佈線層558、凸塊下方金屬化(UBM)層544及焊料凸塊560並非位於封裝晶粒450的背側之上。
如第6圖所示，在本發明之部份實施例中，半導體晶粒450’在封裝結構中的高度高於鑄模通孔(TMVs)415之原始高度。因此，如第6圖所示，需要將額外的導電區域670加至鑄模通孔(TMVs)415的端點上，藉以延長鑄模通孔(TMVs)415的長度。可加入額外的模造成型化合物410圍繞於導電區域670的四周。鑄模通孔(TMVs)415與導電區域670結合成為鑄模通孔(TMVs)415*。可使用不同的導電材料延長鑄模通孔(TMVs)415的長度。舉例而言，導電區域670可由電鍍的導電性材料所形成，例如：銅(copper)、銅合金(copper alloy)、焊料(solder)、焊料合金(solder alloy)、鋁(aluminum)等等。(英文多寫一次aluminum，應該是指鋁合金，請確認)依據本發明之部份實施例，第7A圖到第7C圖顯示形成導電區域670之連續製程之剖面圖。依據本發明之部份實施例，如第7A圖所示，可藉由使用光阻層(photoresist layer)675作為蝕刻罩幕(etching mask)，形成開口671於鑄模通孔(TMVs)415之上。舉例而言，接著，如第7B圖所示，移除光阻層675，並且電鍍導電層680以填充於開口671之中。導電層680可包括銅(copper)、銅合金(copper alloy)、焊料(solder)、焊料合金(solder alloy)或其他合適的材料。依據本發明之部份實施例，如第7C圖所示，接著藉由例如蝕刻製程或 化學機械研磨(chemical-mechanical polishing,CMP)製程，移除開口671外側多餘的導電材料。
依據本發明之部份實施例，如第8圖所示，亦可形成帶有導線的釘狀凸塊(stud bumps)870於鑄模通孔(TMVs)415之上，其中釘狀凸塊870作為額外的導電區域。每一個釘狀凸塊870包括一個釘狀凸塊區域(stud bumps section)871以及一個導線區域(wire section)872，其中釘狀凸塊區域871以及導線區域872係藉由植球焊接製程(stud bonding process)所形成。在本發明之部份實施例中，植球焊接製程類似於打線接合製程(wire bonding process)。依據所需的總長度H截斷導線區域872。如第4B圖所示，可在晶粒450接合於承載基板420(更精確的說法是接合於黏接層421)之後，形成帶有導線之釘狀凸塊870。接著，如第4C圖所述，形成帶有導線之釘狀凸塊870於鑄模通孔(TMVs)415之上，之後再形成模造成型化合物422。
在本發明之部份實施例中，對於低輸入/輸出之應用而言，鑄模通孔(TMVs)415’較短且較寬。依據本發明之部份實施例，第9A圖及第9B圖顯示於中介層架構的鑄模通孔上形成導電區域之連續製程之剖面圖。如第9A圖所示，可在模造成型化合物422中形成開口971於鑄模通孔(TMVs)415’之上。使用光阻層(圖中未顯示)作為罩幕(mask)，以使蝕刻製程易於進行。依據本發明之部份實施例，如第9B圖所示，形成開口971之後，將焊料球(solder ball)980置於開口971之上，接著使焊料球980熔融回流以填充於開口971之中。鑄模通孔(TMVs)415’與焊料球980結合形成鑄模通孔(TMVs)415”。
依據本發明之部份實施例，第10A圖到第10D圖顯示於中介層架構的鑄模通孔上形成導電區域之連續製程之剖面圖。第10A圖顯示中介層架構411*貼合至承載基板(carrier)420*。承載基板420*包括黏接層(adhesive layer)421*，藉以固定中介層架構411*。在本發明之部份實施例中，承載基板420*承載多個中介層架構411*，其中中介層架構411*包括模造成型化合物410*。中介層架構411*包括多個鑄模通孔(TMVs)415^，其中鑄模通孔(TMVs)415^受到模造成型化合物410*的包圍而各自隔離。
第10B圖顯示半導體晶粒450*貼合至黏接層421*，且焊料球985*接合至鑄模通孔(TMVs)415^以形成鑄模通孔(TMVs)415*。半導體晶粒450*貼合至黏接層421*的步驟可在焊料球985*接合至鑄模通孔(TMVs)415^之前或之後實施。
依據本發明之部份實施例，如第10C圖所示，在半導體晶粒450*放置並安裝於黏接層421*之上以後，形成模造成型化合物410^以填充介於半導體晶粒450*與中介層架構411*之間的空間，並且覆蓋於半導體晶粒450*與中介層架構411*之上。形成模造成型化合物410^可包括施加模造成型化合物材料於半導體晶粒450*與中介層架構411*之上，並且固化該模造成型化合物材料。
接著，依據本發明之部份實施例，如第10D圖所示，移除模造成型化合物410^之一部份以及位於鑄模通孔(TMVs)415*上的焊料球985*之一部份，以暴露鑄模通孔(TMVs)415*。移除製程可以是研磨製程(grinding process)、拋 光製程(polishing process)或上述之結合。接著，具有半導體晶粒450*埋藏於其中的中介層架構411*可繼續進行後續操作步驟，以完成封裝製程，其中後續操作步驟如同第4E圖到第4I圖所述。
在第7A圖到第10D圖中所描述的實施例僅用於舉例說明。也可採用如第6圖所描述之形成導電區域670的其他實施例。依據本發明之部份實施例，上述鑄模通孔(TMVs)415、415’、415”、415^及415*包括一寬度介於約10-600 μm。依據本發明之部份實施例，上述鑄模通孔(TMVs)415、415’、415”、415^及415*包括一高度介於約10-600 μm。
上述關於鑄模通孔(TMVs)415、415’、415”、415^ 及415*之實施例僅用於舉例說明。鑄模通孔(TMVs)415、415’、415”、415^及415*在中間部份較寬(亦即中間區域較其端點區域略寬)。然而，鑄模通孔(TMVs)也可能是其他形狀。舉例而言，依據本發明之部份實施例，鑄模通孔(TMVs)415、415’、415”、415^及415*可具有大致上為筆直的側壁，例如第11A圖中的鑄模通孔(TMVs)415A。此外，依據本發明之部份實施例，鑄模通孔(TMVs)415、415’、415”、415^及415*可以是中間區域較窄而端點區域較寬，例如第11B圖中的鑄模通孔(TMVs)415B。
使用中介層架構封裝半導體晶粒的製作方法能夠產生扇出型(fan-out)的連接結構，並且降低已封裝之半導體晶粒的外觀尺寸(form factor)。此製作方法包括使用模造成型化合物以使半導體晶粒中介層架構貼合，並且在半導體晶粒的一 側或兩側形成重新分配層。位於封裝之中的重新分配層能夠產生扇出型(fan-out)的連接結構，同時能夠形成外部連接結構。位於中介層架構之中的導電柱有助於熱管理。
在本發明之部份實施例中，提供一種半導體封裝結構。此半導體封裝結構包括一中介層架構，其中該中介層架構包括複數個導電柱。此半導體封裝結構亦包括一半導體晶粒設置於該中介層架構一開口中，其中該開口位於該中介層架構之中，以及一模造成型化合物介於該中介層架構與該半導體晶粒之間。此半導體封裝結構尚包括一佈線層(wiring layer)，其中該佈線層連接位於該半導體晶粒中之各種元件與該中介層架構之該些導電柱。
在本發明之部份實施例中，提供一種半導體封裝結構。此半導體封裝結構包括一中介層架構，其中該中介層架構包括複數個導電柱。此半導體封裝結構亦包括一半導體晶粒設置於該中介層架構一開口中，其中該開口位於該中介層架構之中，以及一模造成型化合物介於該中介層架構與該半導體晶粒之間。此半導體封裝結構尚包括一佈線層，其中該佈線層連接位於該半導體晶粒中之各種元件與該中介層架構之該些導電柱。此外，此半導體封裝結構尚包括一另一佈線層位於該半導體晶粒相對於原有之該佈線層之另外一側，其中該另一佈線層與該中介層架構之該些導電柱連接。
在本發明之又一實施例中，提供一種半導體封裝結構之製法。此半導體封裝結構之製法包括提供一半導體晶粒，以及提供一中介層架構，其中該中介層架構包括複數個導 電柱。此半導體封裝結構之製法亦包括設置該半導體晶粒於該中介層架構之一開口中，以及形成一模造成型化合物填充於該中介層架構與該半導體晶粒之間的空間。此半導體封裝結構之製法尚包括移除模造成型化合物之一部份，以暴露該些導電柱，以及形成一重新分配層，其中該重新分配層連接位於該半導體晶粒中之各種元件與該些導電柱。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
200‧‧‧晶粒封裝
210‧‧‧晶粒
220‧‧‧封裝架構(packaging frames)
221‧‧‧導電柱(conductive columns)
222‧‧‧接合線
225‧‧‧模造成型化合物(molding compound)

Claims (10)

  1. 一種半導體封裝結構，包括：一中介層架構(interposer frame)，其中該中介層架構包括複數個導電柱(conductive columns)；一半導體晶粒設置於該中介層架構一開口中，其中該開口位於該中介層架構之中；一模造成型化合物(molding compound)介於該中介層架構與該半導體晶粒之間；以及一佈線層(wiring layer)，其中該佈線層連接位於該半導體晶粒中之各種元件與該中介層架構之該些導電柱。
  2. 如申請專利範圍第1項所述之半導體封裝結構，其中該佈線層包括一絕緣層以及一重新分配層(redistribution layer)，其中該重新分配層延伸超出該半導體晶粒邊界之外。
  3. 如申請專利範圍第1項所述之半導體封裝結構，其中該些導電柱受到一模造成型化合物包圍而各自隔離。
  4. 如申請專利範圍第1項所述之半導體封裝結構，尚包括：一另一佈線層位於該半導體晶粒相對於原有之該佈線層之另外一側，其中該另一佈線層與該中介層架構之該些導電柱連接。
  5. 如申請專利範圍第1項所述之半導體封裝結構，其中該些導電柱各自包括一主要部份(main portion)以及一端點部份(end portion)貼合於該主要部份，該主要部分為一鑄模通孔。
  6. 如申請專利範圍第1項所述之半導體封裝結構，其中該些導電柱各自包括一彎曲的表面。
  7. 一種半導體封裝結構之製法，包括以下步驟：提供一半導體晶粒；提供一中介層架構，其中該中介層架構包括複數個導電柱；設置該半導體晶粒於該中介層架構之一開口中；形成一模造成型化合物填充於該中介層架構與該半導體晶粒之間的空間；移除該模造成型化合物之一部份，以暴露該些導電柱；以及形成一重新分配層，其中該重新分配層連接位於該半導體晶粒中之各種元件與該些導電柱。
  8. 如申請專利範圍第7項所述之半導體封裝結構之製法，其中該重新分配層延伸超出該半導體晶粒邊界之外。
  9. 如申請專利範圍第7項所述之半導體封裝結構之製法，尚包括：形成一另一重新分配層位於該半導體晶粒相對於原有之該重新分配層之另外一側，其中該另一重新分配層與該該些導電柱連接。
  10. 如申請專利範圍第7項所述之半導體封裝結構之製法，尚包括：形成複數個端點部份接合於該些導電柱之複數個端點區域。
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