TWI743996B - 封裝結構及其製作方法 - Google Patents

封裝結構及其製作方法 Download PDF

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TWI743996B
TWI743996B TW109132201A TW109132201A TWI743996B TW I743996 B TWI743996 B TW I743996B TW 109132201 A TW109132201 A TW 109132201A TW 109132201 A TW109132201 A TW 109132201A TW I743996 B TWI743996 B TW I743996B
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Taiwan
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hole
hole portion
roughness
conductive
layer
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TW109132201A
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TW202119567A (zh
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郭宏瑞
蔡惠榕
彭竣翔
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台灣積體電路製造股份有限公司
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Abstract

一種封裝結構包括至少一個半導體晶粒、絕緣密封體及重佈線結構。所述至少一個半導體晶粒具有多個導電柱，其中所述多個導電柱的頂表面具有第一粗糙度。絕緣密封體包封所述至少一個半導體晶粒。重佈線結構在積層方向上設置在絕緣密封體上且電性連接到所述至少一個半導體晶粒。重佈線結構包括：多個導通孔部及多個導電體部，嵌置在介電層中，其中所述多個導電體部的頂表面具有第二粗糙度，且第二粗糙度大於第一粗糙度。

Description

封裝結構及其製作方法
本公開實施例是有關一種封裝結構及製作所述封裝結構的方法。
半導體裝置及積體電路通常是在單個半導體晶圓上製造。可以晶圓級對晶圓的晶粒進行處理並與其他半導體裝置或晶粒封裝在一起，且已經開發出用於晶圓級封裝(wafer level packaging，WLP)的各種技術。另外，此種封裝還可在進行切割(dicing)之後被整合到半導體基底或載體。因此，每一封裝內的導電端子與內部元件(例如，重佈線路結構)之間的電性連接的可靠性至關重要。
本公開實施例提供一種封裝結構，所述封裝結構包括至少一個半導體晶粒、絕緣密封體以及重佈線結構。所述至少一個半導體晶粒具有多個導電柱，其中所述多個導電柱中的頂表面具有第一粗糙度。所述絕緣密封體包封所述至少一個半導體晶粒。所述重佈線結構在積層方向上設置在所述絕緣密封體上且電性連 接到所述至少一個半導體晶粒。所述重佈線結構包括：多個導通孔部及多個導電體部，嵌置在介電層中，其中所述多個導電體部的頂表面具有第二粗糙度，且所述第二粗糙度大於所述第一粗糙度。
本公開實施例提供一種製作封裝結構的方法。所述方法包括以下步驟。在載體上提供多個半導體晶粒，其中所述多個半導體晶粒包括多個導電柱。形成包封所述多個半導體晶粒的絕緣密封體，其中所述絕緣密封體的頂表面與所述多個導電柱的頂表面實質上齊平。對所述多個導電柱執行清潔處理，其中所述清潔處理包括使用第一溶液對所述多個導電柱的所述頂表面進行清潔達20秒到80秒的第一清潔步驟，且其中在所述清潔處理之後所述多個導電柱的所述頂表面具有第一粗糙度。在積層方向上在所述絕緣密封體上形成重佈線結構，其中所述形成所述重佈線結構的步驟包括形成嵌置在介電層中的多個導通孔部及多個導電體部，且其中所述多個導電體部的頂表面具有第二粗糙度，且所述第二粗糙度大於所述第一粗糙度。然後將所述載體剝離。
實施例提供一種製作封裝結構的方法。所述方法包括以下步驟。在載體上提供至少一個半導體晶粒，其中所述至少一個半導體晶粒包括多個導電柱。形成包封所述至少一個半導體晶粒的絕緣密封體。透過移除所述絕緣密封體的部分以顯露出所述多個導電柱的頂表面來執行平坦化製程。在所述平坦化製程之後對所述多個導電柱執行單晶圓旋轉清潔處理，其中所述單晶圓旋轉 清潔處理包括在使所述載體旋轉的同時將第一溶液滴加到所述多個導電柱的所述頂表面上達20秒到80秒以對所述多個導電柱的所述頂表面進行清潔。在所述絕緣密封體上形成重佈線結構，其中所述重佈線結構透過以下步驟形成。形成交替堆疊的多個導電體部、多個第一通孔部及多個介電層，其中所述多個第一通孔部形成有從第一通孔部的第一端到第一通孔部的第二端保持不變的側向尺寸，且在形成所述多個第一通孔部中的每一者之後對所述第二端的表面執行通孔清潔處理，所述通孔清潔處理包括在使所述載體旋轉的同時將所述第一溶液滴加到所述第一通孔部的所述第二端的所述表面上達20秒到80秒以對所述第二端的所述表面進行清潔。然後將所述載體剝離。
102:載體
104:緩衝層
104A:剝離層
104B:介電層
105:晶粒貼合膜
106A:第一半導體晶粒/半導體晶粒
106a-AS、106b-AS:主動表面
106a-BS、106b-BS:背側表面
106a-1、106b-1:半導體基底
106a-2、106b-2:導電焊盤
106a-3、106b-3:鈍化層
106a-4、106b-4:導電柱
106a-4-TS、106a-AM-TS、106b-4-TS、106b-AM-TS、108-TS、110-TS、112-B-TS、112-C-TS、112-V-TS:頂表面
106a-5、106b-5:保護層
106a-AM、106b-AM:對準標記
106B、106B’:第二半導體晶粒/半導體晶粒
108:貫穿絕緣層孔
110:絕緣材料
110’:絕緣密封體
112-Bx、112-Cx:導電體部
112-D:第二介電層/介電層
112-Vx:第一通孔部
112-V1、112-W1:第一端
112-V2、112-W2:第二端
112-Wx:第二通孔部
116、250:導電焊盤
116、118、270:導電球
210:基底
220:半導體晶片
230:接合線
240:焊盤
260:絕緣密封體
280:底部填充膠
301:條帶
302:框架
DR1:積層方向
LD1、LD2:側向尺寸
M1:第一金屬層/金屬層
M2:第二金屬層/金屬層
M3:第三金屬層/金屬層
Mx:焊料層
Pk2:第二封裝
PoP:疊層封裝結構
PS1、PS2、PS3、PS4、PS5、PS6、PS7:封裝結構
RDL1:第一重佈線層
RDL2:第二重佈線層
RDS:重佈線結構
Rh:凹槽高度
Rx:凹槽
SD1:平面晶種層
SD2:非平面晶種層
SN1:第一溶液
SN2:第二溶液
結合附圖閱讀以下詳細說明，會最好地理解本公開的各個方面。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為使論述清晰起見，可任意增大或減小各種特徵的臨界尺寸(critical dimension)。
圖1A到圖1K是根據本公開一些示例性實施例的製作封裝結構的方法中的各個階段的示意性剖面圖。
圖2A到圖2C是根據本公開一些示例性實施例的製作封裝結構的方法中的各個階段處的半導體晶粒的放大剖面圖。
圖3是根據本公開一些其他示例性實施例的封裝結構的示意 性剖面圖。
圖4是根據本公開一些示例性實施例的疊層封裝(package-on-package，PoP)結構的示意性剖面圖。
圖5是根據本公開一些其他示例性實施例的封裝結構的示意性剖面圖。
圖6是根據本公開一些其他示例性實施例的封裝結構的示意性剖面圖。
圖7是根據本公開一些其他示例性實施例的封裝結構的示意性剖面圖。
圖8是根據本公開一些其他示例性實施例的封裝結構的示意性剖面圖。
圖9是根據本公開一些其他示例性實施例的封裝結構的示意性剖面圖。
以下公開提供用於實施所提供主題的不同特徵的許多不同實施例或實例。以下闡述元件及排列的具體實例以簡化本公開。當然，這些僅為實例且不旨在進行限制。舉例來說，以下說明中將第二特徵形成在第一特徵之上或第一特徵上可包括其中第二特徵與第一特徵被形成為直接接觸的實施例，且也可包括其中第二特徵與第一特徵之間可形成有附加特徵從而使得所述第二特徵與所述第一特徵可不直接接觸的實施例。另外，本公開可能在各種實例中重複使用元件符號及/或字母。這種重複使用是出於簡 潔及清晰的目的，而不是自身指示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如“在...之下(beneath)”、“在...下方(below)”、“下部的(lower)”、“在...上(on)”、“在...之上(over)”、“上覆在...之上(overlying)”、“在...上方(above)”、“上部的(upper)”等空間相對性用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外還囊括裝置在使用或操作中的不同取向。設備可具有其他取向(旋轉90度或處於其他取向)，且本文中所使用的空間相對性描述語可同樣相應地進行解釋。
還可包括其他特徵及製程。舉例來說，可包括測試結構以說明對三維(three-dimensional，3D)封裝或三維積體電路(three-dimensional integrated circuit，3DIC)裝置進行驗證測試。所述測試結構可包括例如在重佈線層中或基底上形成的測試焊盤(test pad)，以便能夠對3D封裝或3DIC進行測試、使用探針及/或探針卡(probe card)等。可對中間結構以及最終結構執行驗證測試。另外，本文中所公開的結構及方法可與包含對已知良好晶粒(known good die)進行中間驗證的測試方法結合使用以提高良率並降低成本。
圖1A到圖1K是根據本公開一些示例性實施例的製作封裝結構的方法中的各個階段的示意性剖面圖。參照圖1A，提供上 面塗覆有緩衝層104的載體102。在一些實施例中，載體102可為玻璃載體或用於承載用於製作封裝結構的方法的半導體晶圓或重構晶圓的任何合適的載體。
在一些實施例中，緩衝層104包括剝離層104A及介電層104B，其中剝離層104A位於載體102與介電層104B之間。在某些實施例中，剝離層104A設置在載體102上，且剝離層104A的材料可為適於將載體102與上面的層(例如，介電層104B)或設置在載體102上的任何晶圓結合以及將載體102從上面的層(例如，介電層104B)或設置在載體102上的任何晶圓剝離的任何材料。在一些實施例中，剝離層104A可包括釋放層(例如光-熱轉換(“light-to-heat conversion，LTHC”)層)或黏合劑層(例如紫外線可固化黏合劑層或熱可固化黏合劑層)。在一些實施例中，介電層104B可形成在剝離層104A上方。介電層104B可由介電材料(例如苯並環丁烯(“benzocyclobutene，BCB”)、聚苯並惡唑(“polybenzoxazole，PBO”)、或任何其他合適的聚合物系介電材料)製成。
應注意的是，載體102、剝離層104A及介電層104B的材料並不僅限於實施例的說明。在一些替代實施例中，可選擇性地省略介電層104B。換句話說，在載體102之上僅形成剝離層104A。在某些實施例中，可在剝離層104A上直接形成用於貼合到以上組件的晶粒貼合膜(未示出)。
參照圖1B，在提供緩衝層104之後，在載體102之上的 緩衝層104上提供多個貫穿絕緣層孔108及多個半導體晶粒(第一半導體晶粒106A及第二半導體晶粒106B)。在一些實施例中，貫穿絕緣層孔108是集成扇出型(“integrated fan-out，InFO”)穿孔。在一個實施例中，形成貫穿絕緣層孔108包括：形成具有開口的遮罩圖案(未示出)；接著透過電鍍或沉積形成填滿所述開口的金屬材料(未示出)；以及移除遮罩圖案以在緩衝層104上形成貫穿絕緣層孔108。遮罩圖案的材料可包括正性光阻或負性光阻。在一個實施例中，貫穿絕緣層孔108的材料可包括金屬材料，例如銅或銅合金等。然而，本公開並不僅限於此。
在替代實施例中，可透過如下方式形成貫穿絕緣層孔108：在緩衝層104上形成晶種層(未示出)；形成具有開口的遮罩圖案，所述開口暴露出晶種層的部分；透過鍍覆在晶種層的被暴露出的部分上形成金屬材料以形成貫穿絕緣層孔108；移除遮罩圖案；以及接著移除晶種層的被貫穿絕緣層孔108暴露出的部分。舉例來說，晶種層可為鈦/銅複合層。為簡潔起見，在圖1B中示出僅四個貫穿絕緣層孔108。然而應注意的是，貫穿絕緣層孔108的數目並不僅限於此，且可根據要求來選擇。
如圖1B中所示，可在緩衝層104上拾取並放置第一半導體晶粒106A及第二半導體晶粒106B。在某些實施例中，第一半導體晶粒106A具有主動表面106a-AS及與主動表面106a-AS相對的背側表面106a-BS。舉例來說，第一半導體晶粒106A的背側表面106a-BS可透過晶粒貼合膜105貼合到緩衝層104。類似地，第 二半導體晶粒106B具有主動表面106b-AS及與主動表面106b-AS相對的背側表面106b-BS。舉例來說，第二半導體晶粒106B的背側表面106b-BS可透過晶粒貼合膜105貼合到緩衝層104。透過使用晶粒貼合膜105，可確保第一半導體晶粒106A、第二半導體晶粒106B及緩衝層104之間的更好的貼合。在示例性實施例中，示出僅兩個半導體晶粒(106A/106B)。然而，本公開並不僅限於此。應注意的是，設置在緩衝層104上的半導體晶粒(106A/106B)的數目可基於產品要求來調節。
在示例性實施例中，第一半導體晶粒106A及第二半導體晶粒106B分別包括半導體基底(106a-1/106b-1)、多個導電焊盤(106a-2/106b-2)、鈍化層(106a-3/106b-3)、多個導電柱(106a-4/106b-4)、保護層(106a-5/106b-5)及對準標記(106a-AM/106b-AM)。如圖1B中所示，所述多個導電焊盤(106a-2/106b-2)設置在半導體基底(106a-1/106b-1)上。鈍化層(106a-3/106b-3)形成在半導體基底(106a-1/106b-1)之上且具有局部地暴露出半導體基底(106a-1/106b-1)上的導電焊盤(106a-2/106b-2)的開口。半導體基底(106a-1/106b-1)可為塊狀矽基底或絕緣體上矽(silicon-on-insulator，SOI)基底，且還包括形成在其中的主動元件(例如，電晶體等)及可選的被動元件(例如，電阻器、電容器、電感器等)。導電焊盤(106a-2/106b-2)可為鋁焊盤、銅焊盤、或其他合適的金屬焊盤。鈍化層(106a-3/106b-3)可為氧化矽層、氮化矽層、氮氧化矽層、或由 任何合適的介電材料形成的介電層。此外，在一些實施例中，在鈍化層(106a-3/106b-3)之上選擇性地形成後鈍化層(未示出)。後鈍化層覆蓋鈍化層(106a-3/106b-3)且具有多個接觸開口。導電焊盤(106a-2/106b-2)被後鈍化層的接觸開口局部地暴露出。後鈍化層可為苯並環丁烯(BCB)層、聚醯亞胺層、聚苯並惡唑(PBO)層、或由其它合適的聚合物形成的介電層。在一些實施例中，導電柱(106a-4/106b-4)透過鍍覆形成在導電焊盤(106a-2/106b-2)上。在某些實施例中，隨著導電柱(106a-4/106b-4)的形成，可在鈍化層(106a-3/106b-3)上形成對準標記(106a-AM/106b-AM)。舉例來說，對準標記(106a-AM/106b-AM)與導電柱(106a-4/106b-4)由相同的材料形成。在一些實施例中，保護層(106a-5/106b-5)形成在鈍化層(106a-3/106b-3)上或後鈍化層上，且覆蓋導電柱(106a-4/106b-4)及對準標記(106a-AM/106b-AM)以保護這些元件。
在一些實施例中，當在緩衝層104上放置多個半導體晶粒(106A/106B)時，然後可將半導體晶粒(106A/106B)排列成陣列，且當將半導體晶粒(106A/106B)排列成陣列時，可將貫穿絕緣層孔108分類成群組。半導體晶粒(106A/106B)的數目可與貫穿絕緣層孔108的群組的數目對應。在圖示的實施例中，可在形成貫穿絕緣層孔108之後在緩衝層104上拾取並放置半導體晶粒(106A/106B)。然而，本公開並不僅限於此。在一些替代實施例中，可在形成貫穿絕緣層孔108之前在緩衝層104上拾取並放 置半導體晶粒(106A/106B)。
此外，在一些實施例中，第一半導體晶粒106A及第二半導體晶粒106B可選自應用專用積體電路(application-specific integrated circuit，ASIC)晶片、類比晶片(例如，無線及射頻晶片)、數位晶片(例如，基帶晶片)、集成被動裝置(integrated passive device，IPD)、電壓調節器晶片、感測器晶片、記憶體晶片等。舉例來說，在一個實施例中，第一半導體晶粒106A與第二半導體晶粒106B可為相同類型的半導體晶粒。在替代實施例中，第一半導體晶粒106A與第二半導體晶粒106B可為不同類型的半導體晶粒。本公開並不僅限於此。
參照圖1C，在下一步驟中，在緩衝層104上及半導體晶粒(106A/106B)之上形成絕緣材料110。在一些實施例中，絕緣材料110被形成為覆蓋貫穿絕緣層孔108。在一些實施例中，透過例如模壓成型(compression molding)製程形成絕緣材料110、填充半導體晶粒(106A/106B)與貫穿絕緣層孔108之間的間隙以包封半導體晶粒(106A/106B)。絕緣材料110還填充相鄰的貫穿絕緣層孔108之間的間隙，以包封貫穿絕緣層孔108。在此階段處，導電柱(106a-4/106b-4)、保護層(106a-5/106b-5)、對準標記(106a-AM/106b-AM)及貫穿絕緣層孔108被絕緣材料110包封且很好地保護起來。換句話說，不顯露出導電柱(106a-4/106b-4)、對準標記(106a-AM/106b-AM)及貫穿絕緣層孔108。
在一些實施例中，絕緣材料110包含聚合物(例如環氧 樹脂、酚醛樹脂(phenolic resin)、含矽樹脂或其他合適的樹脂)、具有低介電常數(permittivity，Dk)及低損耗正切(loss tangent，Df)性質的介電材料、或其他合適的材料。在替代實施例中，絕緣材料110可包含可接受的絕緣密封體材料。在一些實施例中，絕緣材料110還可包含可被添加到絕緣材料110中來改善絕緣材料110的熱膨脹係數(coefficient of thermal expansion，CTE)的無機填料或無機化合物(例如，二氧化矽、黏土等)。本公開並不僅限於此。
參照圖1D，在一些實施例中，局部地移除絕緣材料110以暴露出導電柱(106a-4/106b-4)、對準標記(106a-AM/106b-AM)及貫穿絕緣層孔108。在一些實施例中，透過平坦化步驟對絕緣材料110及保護層(106a-5/106b-5)進行研磨或拋光。舉例來說，透過機械研磨製程及/或化學機械拋光(chemical mechanical polishing，CMP)製程執行平坦化步驟，直到顯露出導電柱(106a-4/106b-4)的頂表面(106a-4-TS/106b-TS)及對準標記(106a-AM/106b-AM)的頂表面(106a-AM-TS/106b-AM-TS)。在一些實施例中，可局部地對貫穿絕緣層孔108進行拋光，使得貫穿絕緣層孔108的頂表面108-TS與導電柱(106a-4/106b-4)的頂表面(106a-4-TS/106b-4-TS)及對準標記(106a-AM/106b-AM)的頂表面(106a-AM-TS/106b-AM-TS)實質上齊平，或者與第一半導體晶粒106A及第二半導體晶粒106B的主動表面(106a-AS/106b-AS)實質上齊平。換句話說，也可對導電柱 (106a-4/106b-4)、對準標記(106a-AM/106b-AM)及貫穿絕緣層孔108進行輕微研磨/拋光。在圖示的實施例中，對絕緣材料110進行拋光以形成絕緣密封體110’。
參照圖1E，在一些實施例中，在機械研磨或化學機械拋光(CMP)步驟之後，可執行清潔處理。舉例來說，執行清潔處理以清潔及移除平坦化步驟所產生的殘留物，以及形成實質上平坦及光滑的表面。在一些實施例中，清潔處理包括使用第一溶液SN1對導電柱(106a-4/106b-4)的頂表面(106a-4-TS/106b-4-TS)進行清潔、對對準標記(106a-AM/106b-AM)的頂表面(106a-AM-TS/106b-AM-TS)進行清潔、以及對貫穿絕緣層孔108的頂表面108-TS進行清潔達20秒到80秒的第一清潔步驟。舉例來說，在某些實施例中，如透過在使載體102旋轉的同時將第一溶液SN1滴加到導電柱(106a-4/106b-4)的頂表面(106a-4-TS/106b-4-TS)上達20秒到80秒，以對導電柱(106a-4/106b-4)的頂表面(106a-4-TS/106b-4-TS)進行清潔的第一清潔步驟來執行單晶圓旋轉清潔處理(single wafer spin cleaning process)。可以使用單晶圓旋轉清潔處理的類似方式對對準標記(106a-AM/106b-AM)的頂表面(106a-AM-TS/106b-AM-TS)及貫穿絕緣層孔108的頂表面108-TS進行清潔。在一些實施例中，使用第一溶液SN1執行第一清潔步驟達至少20秒，以確保所應用表面的粗糙度降低到一定程度，且使用第一溶液SN1執行第一清潔步驟達少於80秒，以防止對所應用表面的過度蝕刻或損壞。
在一些實施例中，第一溶液SN1的pH處於pH0.5到pH5的範圍內。在一些實施例中，第一溶液SN1包括選自由乙酸、甲酸、檸檬酸、抗壞血酸、氫氟酸、氫氯酸、磷酸及硝酸組成的群組的至少一種酸。在一些實施例中，酸的濃度處於0.05重量百分比到10重量百分比的範圍內。在一些替代實施例中，第一溶液SN1包括選自由乙醇胺、羥乙基乙二胺、氫氧化銨及氯化銨組成的群組的至少一種胺系溶液。在一些實施例中，胺系溶液的濃度處於10重量百分比到35重量百分比的範圍內。在某些實施例中，上述酸及胺系溶液可單獨使用，或者結合使用於第一溶液SN1中。在一個示例性實施例中，第一溶液SN1是檸檬酸溶液。
此外，在一些實施例中，清潔處理選擇性地包括使用第二溶液SN2對導電柱(106a-4/106b-4)的頂表面(106a-4-TS/106b-4-TS)進行清潔、對對準標記(106a-AM/106b-AM)的頂表面(106a-AM-TS/106b-AM-TS)進行清潔、以及對貫穿絕緣層孔108的頂表面108-TS進行清潔達20秒到80秒的第二清潔步驟。舉例來說，在某些實施例中，可如透過在使載體102旋轉的同時將第二溶液SN2滴加到導電柱(106a-4/106b-4)的頂表面(106a-4-TS/106b-4-TS)上達20秒到80秒，以對導電柱(106a-4/106b-4)的頂表面(106a-4-TS/106b-4-TS)進行清潔的第二清潔步驟來執行另一單晶圓旋轉清潔處理。可以使用單晶圓旋轉清潔處理的類似的方式對對準標記(106a-AM/106b-AM)的頂表面 (106a-AM-TS/106b-AM-TS)及貫穿絕緣層孔108的頂表面108-TS進行清潔。在一些實施例中，使用第二溶液SN2執行第二清潔步驟達至少20秒，以確保所應用表面的粗糙度降低到一定程度，且使用第二溶液SN2執行第二清潔步驟達少於80秒，以防止對所應用表面的過度蝕刻或損壞。
在一些實施例中，第二溶液SN2的pH處於pH1.5到pH6的範圍內。在一些實施例中，第二溶液SN2包括選自由乙酸、甲酸、檸檬酸、抗壞血酸、氫氟酸、氫氯酸、磷酸及硝酸組成的群組的至少一種酸。在一些實施例中，酸的濃度處於0.01重量百分比到3重量百分比的範圍內。在一些替代實施例中，第二溶液SN2包括選自由乙醇胺、羥乙基乙二胺、氫氧化銨及氯化銨組成的群組的至少一種胺系溶液。在一些實施例中，胺系溶液的濃度處於10重量百分比到35重量百分比的範圍內。在某些實施例中，上述酸及胺系溶液可單獨使用，或者結合使用於第二溶液SN2中。在一些實施例中，第二溶液SN2可與第一溶液SN1相同。在替代實施例中，第二溶液SN2可與第一溶液SN1不同。
在執行清潔處理(單晶圓旋轉清潔處理)之後，所述多個導電柱(106a-4/106b-4)的頂表面(106a-4-TS/106b-4-TS)可具有粗糙度Rg1。在一些實施例中，在清潔處理之前，所述多個導電柱(106a-4/106b-4)的頂表面(106a-4-TS/106b-4-TS)的粗糙度處於1.5μm到5μm的範圍內。在某些實施例中，在清潔處理之後，粗糙度Rg1處於0.1μm到1μm的範圍內。在一些實施例中， 對準標記(106a-AM/106b-AM)的頂表面(106a-AM-TS/106b-AM-TS)可具有粗糙度Rg2，且貫穿絕緣層孔108的頂表面108-TS可具有粗糙度Rg3。舉例來說，粗糙度Rg2及粗糙度Rg3可實質上等於粗糙度Rg1。在一些實施例中，在清潔處理之後，絕緣密封體110’的頂表面110-TS、貫穿絕緣層孔108的頂表面108-TS、導電柱(106a-4/106b-4)的頂表面(106a-4-TS/106b-4-TS)、對準標記(106a-AM/106b-AM)的頂表面(106a-AM-TS/106b-AM-TS)以及拋光後的保護層(106a-5/106b-5)的頂表面實質上共面且彼此齊平。
圖1F是根據本公開一些其他實施例的清潔處理之後的半導體晶粒106A的放大剖面圖。如圖1G中所示，在一些實施例中，在清潔處理之後，在保護層106a-5中可存在凹槽Rx。換句話說，在保護層106a-5與導電柱106a-4之間可能存在臺階高度差。在某些實施例中，凹槽Rx可具有處於0.1μm到5.0μm的範圍內的凹槽高度Rh。然而，本公開並不僅限於此。在一些替代實施例中，在保護層106a-5中不存在凹槽，且保護層106a-5與導電柱106a-4實質上共面。
參照圖1G及圖1H，闡述在絕緣密封體110’上形成重佈線結構的步驟。如圖1G中所示，在第一步驟中，在積層方向DR1上在導電柱(106a-4/106b-4)之上以及在貫穿絕緣層孔108之上形成多個導通孔部(第一通孔部112-Vx)。在一些實施例中，透過在絕緣密封體110’之上形成平面晶種層SD1來形成導通孔部(第 一通孔部112-Vx)；形成具有開口的遮罩圖案，所述開口暴露出平面晶種層SD1的部分；在平面晶種層SD1的被暴露出的部分上形成導電材料，以透過鍍覆形成導通孔部(第一通孔部112-Vx)；移除遮罩圖案；且接著移除平面晶種層SD1的被導通孔部(第一通孔部112-Vx)暴露出的部分。此後，可形成介電材料(未示出)以覆蓋導通孔部(第一通孔部112-Vx)，其中透過平坦化步驟進一步對介電材料進行研磨或拋光以形成介電層112-D。在一些實施例中，透過機械研磨製程及/或化學機械拋光(CMP)製程執行平坦化步驟，直到顯露出導通孔部(第一通孔部112-Vx)的頂表面112-V-TS。
在圖示的實施例中，導通孔部(第一通孔部112-Vx)形成有在積層方向DR1上從導通孔部(第一通孔部112-Vx)的第一端112-V1到導通孔部(第一通孔部112-Vx)的第二端112-V2保持不變的側向尺寸LD1。在一些實施例中，在平坦化步驟之後，可執行通孔清潔處理(例如單晶圓旋轉清潔處理)以使用第一溶液SN1對導通孔部(第一通孔部112-Vx)的第二端112-V2的頂表面112-V-TS進行清潔達20秒到80秒以形成實質上平坦及光滑的表面。在某些實施例中，可選擇性地執行另一通孔清潔處理(例如單晶圓旋轉清潔處理)，以使用第二溶液SN2對導通孔部的第二端112-V2的頂表面112-V-TS進行清潔達20秒到80秒，以形成實質上平坦及光滑的表面。此處提到的第一溶液SN1及第二溶液SN2與圖1E中提到的第一溶液SN1及第二溶液SN2相同，因此 此處將省略其詳細說明。在通孔清潔處理之後，導通孔部(第一通孔部112-Vx)的第二端112-V2的頂表面112-V-TS可具有粗糙度Rg4。舉例來說，通孔清潔處理之後的粗糙度Rg4處於0.1μm到1μm的範圍內。在某些實施例中，粗糙度Rg4可實質上等於粗糙度Rg1。
參照圖1H，在下一步驟中，可透過執行鍍覆及平坦化製程以類似於上面圖1G中所述的方式，在積層方向DR1上形成且堆疊平面晶種層SD1、多個導電體部112-Bx、多個導通孔部(第一通孔部112-Vx)及第二介電層112-D。在示例性實施例中，在平坦化製程之後，顯露出嵌置在第二介電層112-D中的導通孔部(第一通孔部112-Vx)的頂表面112-V-TS。此後，可執行相同的通孔清潔處理，以透過使用用於清潔的第一溶液SN1及可選的第二溶液SN1對最上面的導通孔部(第一通孔部112-Vx)的表面進行清潔。這樣一來，在通孔清潔處理之後，導通孔部(第一通孔部112-Vx)的第二端112-V2的頂表面112-V-TS可具有粗糙度Rg4。另一方面，由於導電體部112-Bx的頂表面112-B-TS被介電層112-D覆蓋且未透過通孔清潔處理進行清潔，因此它可具有粗糙度Rg5，其中粗糙度Rg5大於粗糙度Rg4。在一些實施例中，粗糙度Rg1、粗糙度Rg2、粗糙度Rg3、粗糙度Rg4全部小於粗糙度Rg5。
參照圖1I，在一些實施例中，接著可重複形成圖1G及圖1H中闡述的平面晶種層SD1、導通孔部(第一通孔部112-Vx)、 導電體部112-Bx及介電層112-D，以形成重佈線結構RDS。在一些實施例中，在積層方向DR1上交替堆疊平面晶種層SD1、導通孔部(第一通孔部112-Vx)、導電體部112-Bx及介電層112-D，以構成重佈線結構RDS。此外，在示例性實施例中，所有導通孔部(第一通孔部112-Vx)可具有粗糙度Rg4的頂表面112-V-TS，而導電體部112-Bx可具有粗糙度Rg5的頂表面112-B-TS，且粗糙度Rg4小於粗糙度Rg5。在一些實施例中，平面晶種層SD1的部分可設置在導通孔部(第一通孔部112-Vx)上且與導通孔部(第一通孔部112-Vx)實體接觸。
如圖1I中所示，儘管本文中示出三層導通孔部(第一通孔部112-Vx)/導電體部112-Bx及四層介電層112-D，然而，本公開的範圍並不僅限於此。在其他實施例中，導通孔部(第一通孔部112-Vx)/導電體部112-Bx及介電層112-D的層的數目可基於產品要求來調節。在一些實施例中，重佈線結構RDS透過導通孔部(第一通孔部112-Vx)及導電體部112-Bx電性連接到貫穿絕緣層孔108及半導體晶粒(106A/106B)。
在示例性實施例中，介電層112-D的材料可為可使用微影及/或蝕刻製程來圖案化的聚醯亞胺、聚苯並惡唑(PBO)、苯並環丁烯(BCB)、例如氮化矽等氮化物、例如氧化矽等氧化物、磷矽酸鹽玻璃(phosphosilicate glass，PSG)、硼矽酸鹽玻璃(borosilicate glass，BSG)、硼摻雜磷矽酸鹽玻璃(boron-doped phosphosilicate glass，BPSG)、其組合等。在一些實施例中，介電 層112-D的材料可透過合適的製作技術(例如旋轉塗布、化學氣相沉積(chemical vapor deposition，CVD)、等離子體增強型化學氣相沉積(plasma-enhanced chemical vapor deposition，PECVD)等)形成。本公開並不僅限於此。
此外，在一些實施例中，導通孔部(第一通孔部112-Vx)及導電體部112-Bx的材料可由透過電鍍或沉積形成的導電材料(例如可使用微影及蝕刻製程來圖案化的鋁、鈦、銅、鎳、鎢、及/或其合金)製成。在說明書通篇中，用語“銅”旨在包括實質上純的元素銅、含有不可避免的雜質的銅、以及含有少量例如鉭、銦、錫、鋅、錳、鉻、鈦、鍺、鍶、鉑、鎂、鋁或鋯等元素的銅合金。
仍然參照圖1I，在形成重佈線結構RDS之後，可在導電體部112-Bx的最頂層的被暴露出的頂表面上設置用於與導電球(或導電凸塊)電性連接的多個導電焊盤114。在一些實施例中，導電焊盤114是例如用於球安裝的球下金屬(under-ball metallurgy，UBM)圖案。如圖1I中所示，導電焊盤114形成在重佈線結構RDS上且電性連接到重佈線結構RDS。在一些實施例中，導電焊盤114的材料可包括銅、鎳、鈦、鎢、或其合金等，且可透過例如電鍍製程形成導電焊盤114。導電焊盤114的數目在本公開中不受限制，且可基於設計佈局來選擇。在一些替代實施例中，可省略導電焊盤114。換句話說，在後續步驟中形成的導電球116(或導電凸塊)可直接設置在重佈線結構RDS上。
在形成導電焊盤114之後，在導電焊盤114上及重佈線結構RDS之上設置多個導電球116。在一些實施例中，可透過植球製程或回焊製程在導電焊盤114上設置導電球116。在一些實施例中，導電球116是例如焊料球或球柵陣列(ball grid array，BGA)球。在一些實施例中，導電球116透過導電焊盤114連接到重佈線結構RDS。在某些實施例中，導電球116中的一些導電球116可透過重佈線結構RDS電性連接到半導體晶粒(106A/106B)。此外，導電球116中的一些導電球116可透過重佈線結構RDS電性連接到貫穿絕緣層孔108。導電球116的數目並不限於本公開，且可基於導電焊盤114的數目來指定及選擇。
參照圖1J，在一些實施例中，在形成重佈線結構RDS及導電球116之後，可將圖1I中所示的結構翻轉且貼合到由框架302支撐的條帶301(例如，切割帶)。如圖1J中所示，載體102被剝離且與介電層104B隔開。在一些實施例中，剝離製程包括將例如雷射或紫外光等光投射到剝離層104A(例如，LTHC釋放層)上，使得載體102可容易地與剝離層104A一起移除。在剝離步驟期間，在剝離載體102及剝離層104A之前，使用條帶301來固定封裝結構。在剝離製程之後，顯露或暴露出介電層104B的背側表面。
參照圖1K，在一些實施例中，在剝離製程之後，可將介電層104B圖案化，以形成暴露出貫穿絕緣層孔108的底表面的多個開口(未示出)。形成的開口的數目與貫穿絕緣層孔108的數目對應。此後，可在貫穿絕緣層孔108的被開口暴露出的底表面上 放置多個導電球118。導電球118例如被回焊成與貫穿絕緣層孔108的底表面結合。隨後，可執行切割製程以將整個晶圓結構剖切(切穿重佈線結構RDS、絕緣密封體110’及介電層104B)成多個封裝結構PS1。至此，完成根據本公開的一些實施例的具有雙側端子的封裝結構PS1。
圖2A到圖2C是根據本公開一些示例性實施例的製作封裝結構的方法中的各個階段處的半導體晶粒的放大剖面圖。此處闡述的方法類似於圖1C到圖1F中闡述的方法，因此相同的元件符號用於表示相同或類似的元件，且此處將省略其詳細說明。實施例之間的不同之處在於導電柱(106a-4/106b-4)的設計。在圖1C到圖1F中所示的實施例中，導電柱(106a-4/106b-4)由單一材料(例如銅柱)製成。然而，本公開並不僅限於此，且導電柱(106a-4/106b-4)可由多種材料製成。
舉例來說，參照圖2A，在一些實施例中，在執行平坦化製程(與圖1C中所示的步驟對應)之前，第一半導體晶粒106A的導電柱106a-4可包括第一金屬層M1、第二金屬層M2、第三金屬層M3及焊料層Mx。在一個示例性實施例中，第一金屬層M1是銅層，第二金屬層是鎳層，且第三金屬層M3是銅層。此外，在此階段處，保護層106a-5完全覆蓋導電柱106a-4。
參照圖2B，執行平坦化步驟以移除焊料層Mx及第三金屬層M3的部分，使得第二金屬層M2的頂表面(106a-4-TS)被顯露或暴露出。在一些實施例中，剩餘量的第三金屬層M3可保留 在第二金屬層M2上。在某些實施例中，剩餘的第三金屬層M3可被視為第二金屬層M2的側面部分(flank portion)。在替代實施例中，可透過平坦化步驟完全移除第三金屬層M3。在執行平坦化步驟之後，可執行類似於圖1E中所述的使用第一溶液SN1(以及可選的第二溶液SN2)的清潔處理(單晶圓旋轉清潔處理)來對導電柱106a-4的頂表面106a-4-TS(其為第二金屬層M2的表面)進行清潔。
參照圖2C，在執行清潔處理之後，形成具有銅層(金屬層M1)、鎳層(金屬層M2)及側面部分(金屬層M3)的導電柱106a-4。在一些實施例中，鎳層(金屬層M2)的頂表面(106a-4-TS)具有第一粗糙度Rg1。在某些實施例中，清潔處理之後的粗糙度Rg1處於0.1μm到1μm的範圍內。在某些實施例中，鎳層(金屬層M2)的頂表面(106a-4-TS)與側面部分(金屬層M3)的頂表面及保護層106a-5的頂表面實質上共面。此後，可執行圖1G到圖1K中闡述的相同步驟，以在其上形成重佈線結構RDS，且完成封裝結構的形成。
圖3是根據本公開一些其他示例性實施例的封裝結構的示意性剖面圖。圖3中所示的封裝結構PS2類似於圖1K中所示的封裝結構PS1，因此，相同的元件符號用於表示相同或類似的元件，且此處將省略其詳細說明。實施例之間的不同之處在於，在圖3中省略了貫穿絕緣層孔108。由於在封裝結構PS2中省略了貫穿絕緣層孔108，因此也可省略放置在貫穿絕緣層孔108上的導 電球118。類似於上述實施例，執行清潔處理(單晶圓旋轉清潔處理)以對導電柱(106a-4/106b-4)的表面、對準標記(106a-AM/106b-AM)的表面及第一通孔部112-Vx的表面進行處理。因此，導電柱(106a-4/106b-4)的表面、對準標記(106a-AM/106b-AM)的表面、及第一通孔部112-Vx的表面可具有較小的粗糙度，且可防止形成在導電柱(106a-4/106b-4)、對準標記(106a-AM/106b-AM)及第一通孔部112-Vx上的通孔或連接結構的塌陷問題。
圖4是根據本公開一些示例性實施例的疊層封裝(PoP)結構的示意性剖面圖。參照圖4，在製作第一封裝(例如圖1K中所示的封裝結構PS1)之後，可在封裝結構PS1(第一封裝)上堆疊第二封裝Pk2，以形成疊層封裝(PoP)結構。在一些實施例中，從封裝結構PS1省略導電球118，使得第二封裝Pk2可透過導電球270堆疊在封裝結構PS1上且電性連接到封裝結構PS1。如圖4中所示，第二封裝Pk2透過導電球270電性連接到封裝結構PS1的貫穿絕緣層孔108。
在一些實施例中，第二封裝Pk2具有基底210、安裝在基底210的一個表面(例如，頂表面)上且堆疊在彼此頂部上的多個半導體晶片220。在一些實施例中，使用接合線230在半導體晶片220與焊盤240(例如結合焊盤)之間提供電性連接。在一些實施例中，形成絕緣密封體260來包封半導體晶片220及接合線230，以保護這些元件。在一些實施例中，可使用貫穿絕緣層孔(未 示出)來提供焊盤240與導電焊盤250(例如結合焊盤)之間的電性連接，導電焊盤250位於基底210的另一表面(例如，底表面)上。在某些實施例中，導電焊盤250透過這些貫穿絕緣層孔(未示出)電性連接到半導體晶片220。在一些實施例中，封裝結構Pk2的導電焊盤250電性連接到導電球270。在一些實施例中，進一步提供底部填充膠280來填充導電球270之間的空間，以保護導電球270。在將第二封裝Pk2堆疊在封裝結構PS1(第一封裝)上且在第二封裝Pk2與封裝結構PS1(第一封裝)之間提供電性連接之後，可製作疊層封裝結構PoP。
圖5是根據本公開一些其他示例性實施例的封裝結構的示意性剖面圖。圖5中所示的封裝結構PS3類似於圖1K中所示的封裝結構PS1，因此，相同的元件符號用於表示相同或類似的元件，且此處將省略其詳細說明。實施例之間的不同之處在於第二半導體晶粒106B’及重佈線結構RDS的設計。如圖5中所示，第二半導體晶粒106B’包括具有第一金屬層M1(例如銅層)及第二金屬層M2(例如鎳層)的導電柱106b-4。換句話說，可透過圖2A到圖2C中闡述的方法製作半導體晶粒106B’。舉例來說，可使用清潔處理(單晶圓旋轉清潔處理)對第二金屬層M2(鎳層)的頂表面進行處理，且第二金屬層M2(鎳層)的頂表面具有第一粗糙度Rg1。
此外，在示例性實施例中，透過形成交替堆疊的介電層112-D、非平面晶種層SD2、導通孔部(第二通孔部112-Wx)及 導電體部112-Cx來形成重佈線結構RDS。在一些實施例中，非平面晶種層SD2共形地形成在介電層112-D之上，以具有位於不同水平面上的頂表面。在一些實施例中，導通孔部(第二通孔部112-Wx)設置在非平面晶種層SD2上且接觸非平面晶種層SD2。在一些實施例中，導通孔部(第二通孔部112-Wx)的側向尺寸LD2在積層方向DR1上從導通孔部(第二通孔部112-Wx)的第一端112-W1到導通孔部(第二通孔部112-Wx)的第二端112-W2增大。在某些實施例中，導電體部112-Cx可直接設置在導通孔部(第二通孔部112-Wx)上，且可與導通孔部(第二通孔部112-Wx)在相同的步驟中形成。
在一些實施例中，導通孔部(第二通孔部112-Wx)及導電體部112-Cx由與針對圖1G到圖1I中的導通孔部(第一通孔部112-Vx)及導電體部112-Bx所述的相同材料製成。然而，在某些實施例中，如圖5中所示的導通孔部(第二通孔部112-Wx)及導電體部112-Cx可具有比圖1G到圖1I中所示的導通孔部(第一通孔部112-Vx)及導電體部112-Bx的線寬/間距大的線寬/間距。另外，由於導電體部112-Cx與導通孔部(第二通孔部112-Wx)是在同一步驟中製造，因此不對導通孔部(第二通孔部112-Wx)的表面執行通孔清潔處理。在一些實施例中，導電體部112-Cx的頂表面112-C-TS也沒有透過通孔清潔處理進行清潔，且因此可具有粗糙度Rg5(與導電體部112-Bx相同)。
圖6是根據本公開一些其他示例性實施例的封裝結構的 示意性剖面圖。圖6中所示的封裝結構PS4類似於圖5中所示的封裝結構PS3，因此，相同的元件符號用於表示相同或類似的元件，且此處將省略其詳細說明。實施例之間的不同之處在於，在圖6中省略了貫穿絕緣層孔108。由於在封裝結構PS4中省略了貫穿絕緣層孔108，因此也可省略放置在貫穿絕緣層孔108上的導電球118。類似於上述實施例，執行清潔處理(單晶圓旋轉清潔處理)以對導電柱(106a-4/106b-4)的表面及對準標記(106a-AM/106b-AM)的表面進行處理。因此，導電柱(106a-4/106b-4)的表面及對準標記(106a-AM/106b-AM)的表面可具有較小的粗糙度，且可防止形成在導電柱(106a-4/106b-4)及對準標記(106a-AM/106b-AM)上的通孔或連接結構的塌陷問題。
圖7是根據本公開一些其他示例性實施例的封裝結構的示意性剖面圖。圖7中所示的封裝結構PS5類似於圖1K中所示的封裝結構PS1，且類似於圖5中所示的封裝結構PS3，因此，相同的元件符號用於表示相同或類似的元件，且此處將省略其詳細說明。實施例之間的不同之處在於重佈線結構RDS的設計。如圖7中所示，重佈線結構RDS可包括第一重佈線層RDL1及堆疊在第一重佈線層RDL1上的第二重佈線層RDL2。
在一些實施例中，第一重佈線層RDL1由介電層112-D、非平面晶種層SD2、第二通孔部112-Wx及導電體部112-Cx構成，如圖5中所述。在某些實施例中，第二重佈線層RDL2由介電層 112-D、平面晶種層SD1、第一通孔部112-Vx及導電體部112-Bx構成，如圖1A到圖1K中所述。換句話說，在示例性實施例中，重佈線結構RDS可包括具有不同設計的導通孔部(第一通孔部112-Vx/第二通孔部112-Wx)。在一些實施例中，第一重佈線層RDL1的平面晶種層SD1與第二重佈線層RDL2的非平面晶種層SD2是隔開的且彼此不會接觸。在某些實施例中，平面晶種層SD1設置在第一通孔部112-Vx上且接觸第一通孔部112-Vx，而第二通孔部112-Wx設置在非平面晶種層SD2上且接觸非平面晶種層SD2。
類似於上述實施例，執行清潔處理(單晶圓旋轉清潔處理)以對導電柱(106a-4/106b-4)的表面、對準標記(106a-AM/106b-AM)的表面、貫穿絕緣層孔108的表面、及第一通孔部112-Vx的表面進行處理。因此，導電柱(106a-4/106b-4)的表面、對準標記(106a-AM/106b-AM)的表面、貫穿絕緣層孔108的表面、及第一通孔部112-Vx的表面可具有較小的粗糙度，且可防止形成在導電柱(106a-4/106b-4)、對準標記(106a-AM/106b-AM)、貫穿絕緣層孔108、及第一通孔部112-Vx上的通孔或連接結構的塌陷問題。在某些實施例中，所述多個導電柱(106a-4/106b-4)可具有粗糙度Rg1，對準標記(106a-AM/106b-AM)可具有粗糙度Rg2，貫穿絕緣層孔108可具有粗糙度Rg3，第一通孔部112-Vx可具有粗糙度Rg4，且導電體部(112-Bx/112-Cx)可具有粗糙度Rg5。在一個示例性實施例 中，粗糙度Rg5大於粗糙度Rg1到Rg4，而粗糙度Rg1、粗糙度Rg2、粗糙度Rg3、粗糙度Rg4可實質上相等。
圖8是根據本公開一些其他示例性實施例的封裝結構的示意性剖面圖。圖8中所示的封裝結構PS6類似於圖7中所示的封裝結構PS5，因此，相同的元件符號用於表示相同或類似的元件，且此處將省略其詳細說明。實施例之間的不同之處在於，在圖8中省略了貫穿絕緣層孔108。由於在封裝結構PS6中省略了貫穿絕緣層孔108，因此也可省略放置在貫穿絕緣層孔108上的導電球118。類似於上述實施例，執行清潔處理(單晶圓旋轉清潔處理)以對導電柱(106a-4/106b-4)的表面、對準標記(106a-AM/106b-AM)的表面、及第一通孔部112-Vx的表面進行處理。因此，導電柱(106a-4/106b-4)的表面、對準標記(106a-AM/106b-AM)的表面、及第一通孔部112-Vx的表面可具有較小的粗糙度，且可防止形成在導電柱(106a-4/106b-4)、對準標記(106a-AM/106b-AM)、第一通孔部112-Vx上的通孔或連接結構的塌陷問題。
圖9是根據本公開一些其他示例性實施例的封裝結構的示意性剖面圖。圖9中所示的封裝結構PS7類似於圖8中所示的封裝結構PS6，因此，相同的元件符號用於表示相同或類似的元件，且此處將省略其詳細說明。實施例之間的不同之處在於重佈線結構RDS的設計。在圖8中所示的實施例中，透過形成具有第二通孔部112-Wx的第一重佈線層RDL1接著形成具有第一通孔部 112-Vx的第二重佈線層RDL2來形成重佈線結構RDS。然而，本公開並不僅限於此。
舉例來說，如圖9中所示，在一些實施例中，第一重佈線層RDL1由介電層112-D、平面晶種層SD1、第一通孔部112-Vx及導電體部112-Bx構成，如圖1A到圖1K中所述。在某些實施例中，第二重佈線層RDL2由介電層112-D、非平面晶種層SD2、第二通孔部112-Wx及導電體部112-Cx構成，如圖5中所述。換句話說，透過形成具有第一通孔部112-Vx的第一重佈線層RDL1接著形成具有第二通孔部112-Wx的第二重佈線層RDL2來形成圖9的重佈線結構RDS。類似於上述實施例，執行清潔處理(單晶圓旋轉清潔處理)以對導電柱(106a-4/106b-4)的表面、對準標記(106a-AM/106b-AM)的表面、及第一通孔部112-Vx的表面進行處理。因此，導電柱(106a-4/106b-4)的表面、對準標記(106a-AM/106b-AM)的表面、及第一通孔部112-Vx的表面可具有較小的粗糙度，且可防止形成在導電柱(106a-4/106b-4)、對準標記(106a-AM/106b-AM)、第一通孔部112-Vx上的通孔或連接結構的塌陷問題。
在上述實施例中，使用指定的清潔溶液(第一溶液/第二溶液)執行至少一個清潔處理(單晶圓旋轉清潔處理)以對導電柱的表面、對準標記的表面、貫穿絕緣層孔的表面及導通孔部(第一通孔部)的表面進行清潔。這樣一來，導電柱的表面、對準標記的表面、貫穿絕緣層孔的表面及導通孔部(第一通孔部)的表 面可具有較小的粗糙度。由於表面更光滑，因此可防止形成在導電柱、貫穿絕緣層孔及導通孔部(第一通孔部)上的通孔或連接結構的塌陷問題。類似地，由於表面更光滑，因此對準標記將具有更好的對準輪廓。總體而言，封裝結構的可靠度可得到改善。
根據本公開的一些實施例，提供一種封裝結構，所述封裝結構包括至少一個半導體晶粒、絕緣密封體以及重佈線結構。所述至少一個半導體晶粒具有多個導電柱，其中所述多個導電柱中的頂表面具有第一粗糙度。所述絕緣密封體包封所述至少一個半導體晶粒。所述重佈線結構在積層方向上設置在所述絕緣密封體上且電性連接到所述至少一個半導體晶粒。所述重佈線結構包括：多個導通孔部及多個導電體部，嵌置在介電層中，其中所述多個導電體部的頂表面具有第二粗糙度，且所述第二粗糙度大於所述第一粗糙度。
在一些實施例中，所述的封裝結構，還包括貫穿絕緣層孔，所述貫穿絕緣層孔嵌置在所述絕緣密封體內，且電性連接到所述重佈線結構，其中所述貫穿絕緣層孔的表面具有實質上等於所述第一粗糙度的粗糙度。在一些實施例中，所述多個導電柱中的所述至少一者包括銅層及鎳層，且所述鎳層具有所述第一粗糙度的所述頂表面。
根據本公開的一些其他實施例，闡述一種製作封裝結構的方法。所述方法包括以下步驟。在載體上提供多個半導體晶粒，其中所述多個半導體晶粒包括多個導電柱。形成包封所述多個半 導體晶粒的絕緣密封體，其中所述絕緣密封體的頂表面與所述多個導電柱的頂表面實質上齊平。對所述多個導電柱執行清潔處理，其中所述清潔處理包括使用第一溶液對所述多個導電柱的所述頂表面進行清潔達20秒到80秒的第一清潔步驟，且其中在所述清潔處理之後所述多個導電柱的所述頂表面具有第一粗糙度。在積層方向上在所述絕緣密封體上形成重佈線結構，其中所述形成所述重佈線結構的步驟包括形成嵌置在介電層中的多個導通孔部及多個導電體部，且其中所述多個導電體部的頂表面具有第二粗糙度，且所述第二粗糙度大於所述第一粗糙度。然後將所述載體剝離。
在一些實施例中，所述第一溶液的pH處於pH0.5到pH5的範圍內。在一些實施例中，所述第一溶液是檸檬酸溶液。在一些實施例中，所述清潔處理還包括執行第二清潔步驟，所述第二清潔步驟使用第二溶液對所述導電柱的所述頂表面進行清潔。在一些實施例中，所述第二溶液包括選自由乙酸、甲酸、檸檬酸、抗壞血酸、氫氟酸、氫氯酸、磷酸及硝酸組成的群組的至少一種酸。
在本公開的再一實施例中，闡述一種製作封裝結構的方法。所述方法包括以下步驟。在載體上提供至少一個半導體晶粒，其中所述至少一個半導體晶粒包括多個導電柱。形成包封所述至少一個半導體晶粒的絕緣密封體。透過移除所述絕緣密封體的部分以顯露出所述多個導電柱的頂表面來執行平坦化製程。在所述 平坦化製程之後對所述多個導電柱執行單晶圓旋轉清潔處理，其中所述單晶圓旋轉清潔處理包括在使所述載體旋轉的同時將第一溶液滴加到所述多個導電柱的所述頂表面上達20秒到80秒以對所述多個導電柱的所述頂表面進行清潔。在所述絕緣密封體上形成重佈線結構，其中所述重佈線結構透過以下步驟形成。形成交替堆疊的多個導電體部、多個第一通孔部及多個介電層，其中所述多個第一通孔部形成有從第一通孔部的第一端到第一通孔部的第二端保持不變的側向尺寸，且在形成所述多個第一通孔部中的每一者之後對所述第二端的表面執行通孔清潔處理，所述通孔清潔處理包括在使所述載體旋轉的同時將所述第一溶液滴加到所述第一通孔部的所述第二端的所述表面上達20秒到80秒以對所述第二端的所述表面進行清潔。然後將所述載體剝離。
在一些實施例中，所述第一溶液包括選自由乙酸、甲酸、檸檬酸、抗壞血酸、氫氟酸、氫氯酸、磷酸及硝酸組成的群組的至少一種酸。在一些實施例中，所述第一溶液包括選自由乙醇胺、羥乙基乙二胺、氫氧化銨及氯化銨組成的群組的至少一種胺系溶液。在一些實施例中，所述單晶圓旋轉清潔處理還包括：在使所述載體旋轉的同時將第二溶液滴加到所述多個導電柱的所述頂表面上達20秒到80秒以對所述多個導電柱的所述頂表面進行清潔。在一些實施例中，所述第二溶液包括選自由乙酸、甲酸、檸檬酸、抗壞血酸、氫氟酸、氫氯酸、磷酸及硝酸組成的群組的至少一種酸。
以上概述了若干實施例的特徵，以使所屬領域中的技術人員可更好地理解本公開的各個方面。所屬領域中的技術人員應理解，他們可容易地使用本公開作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到，這些等效構造並不背離本公開的精神及範圍，而且他們可在不背離本公開的精神及範圍的條件下在本文中作出各種改變、代替及變更。
102:載體
104:緩衝層
104A:剝離層
104B:介電層
105:晶粒貼合膜
106A:第一半導體晶粒/半導體晶粒
106a-AS、106b-AS:主動表面
106a-BS、106b-BS:背側表面
106a-1、106b-1:半導體基底
106a-2、106b-2:導電焊盤
106a-3、106b-3:鈍化層
106a-4、106b-4:導電柱
106a-4-TS、106a-AM-TS、106b-4-TS、106b-AM-TS、108-TS、110-TS:頂表面
106a-5、106b-5:保護層
106a-AM、106b-AM:對準標記
106B:第二半導體晶粒/半導體晶粒
108:貫穿絕緣層孔
110’:絕緣密封體
SN1:第一溶液
SN2:第二溶液

Claims (9)

  1. 一種封裝結構，包括：至少一個半導體晶粒，具有多個導電柱，其中所述多個導電柱中的至少一者的頂表面具有第一粗糙度；絕緣密封體，包封所述至少一個半導體晶粒；重佈線結構，在積層方向上設置在所述絕緣密封體上，其中所述重佈線結構電性連接到所述至少一個半導體晶粒且包括：多個導通孔部及多個導電體部，嵌置在介電層中，其中所述多個導電體部的頂表面具有第二粗糙度，且所述第二粗糙度大於所述第一粗糙度，且所述多個導通孔部包括第一通孔部，且所述第一通孔部的側向尺寸在所述積層方向上從所述第一通孔部的第一端到所述第一通孔部的第二端保持不變，且所述第一通孔部的所述第二端的表面具有第三粗糙度，且所述第三粗糙度小於所述第二粗糙度。
  2. 如請求項1所述的封裝結構，其中所述多個導通孔部還包括第二通孔部，且所述第二通孔部的側向尺寸在所述積層方向上從所述第二通孔部的第一端到所述第二通孔部的第二端增大。
  3. 如請求項2所述的封裝結構，其中所述重佈線結構還包括彼此隔開的多個平面晶種層與多個非平面晶種層，所述多個平面晶種層設置在所述第一通孔部上且接觸所述第一通孔部，且 所述第二通孔部設置在所述多個非平面晶種層上且接觸所述多個非平面晶種層。
  4. 一種製作封裝結構的方法，包括：在載體上提供至少一個半導體晶粒，其中所述至少一個半導體晶粒包括導電柱；形成包封所述至少一個半導體晶粒的絕緣密封體，並將所述絕緣密封體平坦化，以顯露出所述導電柱的頂表面；對所述導電柱執行清潔處理，其中所述清潔處理包括使用第一溶液對所述導電柱的所述頂表面進行清潔的第一清潔步驟，且其中在所述清潔處理之後所述導電柱的所述頂表面具有第一粗糙度，且所述第一溶液至少包括檸檬酸；在積層方向上在所述絕緣密封體上形成重佈線結構，其中形成所述重佈線結構的步驟包括形成嵌置在介電層中的多個導通孔部及多個導電體部，且其中所述多個導電體部的頂表面具有第二粗糙度，且所述第二粗糙度大於所述第一粗糙度；以及將所述載體剝離。
  5. 如請求項4所述的製作封裝結構的方法，其中所述第一溶液更包括選自由乙酸、甲酸、抗壞血酸、氫氟酸、氫氯酸、磷酸及硝酸所組成的群組的至少一種酸。
  6. 如請求項4所述的製作封裝結構的方法，其中所述第一溶液更包括選自由乙醇胺、羥乙基乙二胺、氫氧化銨及氯化銨組成的群組的至少一種胺系溶液。
  7. 如請求項4所述的製作封裝結構的方法，其中形成所述導通孔部的步驟包括：形成第一通孔部，所述第一通孔部具有在所述積層方向上從所述第一通孔部的第一端到所述第一通孔部的第二端保持不變的側向尺寸，並執行通孔清潔處理，所述通孔清潔處理使用所述第一溶液對所述第一通孔部的所述第二端的表面進行清潔，且其中在所述通孔清潔處理之後所述第一通孔部的所述第二端的所述表面具有第三粗糙度，且所述第三粗糙度小於所述第二粗糙度。
  8. 一種製作封裝結構的方法，包括：在載體上提供至少一個半導體晶粒，其中所述至少一個半導體晶粒包括多個導電柱；形成包封所述至少一個半導體晶粒的絕緣密封體；執行平坦化製程以移除所述絕緣密封體的部分並且顯露出所述多個導電柱的頂表面；在所述平坦化製程之後對所述多個導電柱執行單晶圓旋轉清潔處理，其中所述單晶圓旋轉清潔處理包括在使所述載體旋轉的同時將第一溶液滴加到所述多個導電柱的所述頂表面上達20秒到80秒以對所述多個導電柱的所述頂表面進行清潔；以及在所述絕緣密封體上形成重佈線結構，其中形成所述重佈線結構的步驟包括：形成交替堆疊的多個導電體部、多個第一通孔部及多個介電層，其中所述多個第一通孔部形成有從所述多個第一通孔部 的第一端到所述多個第一通孔部的第二端保持不變的側向尺寸，且在形成所述多個第一通孔部中的每一者之後對所述第二端的表面執行通孔清潔處理，所述通孔清潔處理包括在使所述載體旋轉的同時將所述第一溶液滴加到所述第一通孔部的所述第二端的所述表面上達20秒到80秒以對所述第二端的所述表面進行清潔；以及將所述載體剝離。
  9. 如請求項8所述的製作封裝結構的方法，還包括：形成與所述多個導電體部及所述多個介電層交替堆疊的多個第二通孔部，其中所述多個第二通孔部形成有從所述多個第二通孔部的第一端到所述多個第二通孔部的第二端增大的側向尺寸。
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