CN112635421A - 封装结构及其制作方法 - Google Patents

封装结构及其制作方法 Download PDF

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Publication number
CN112635421A
CN112635421A CN202011001038.2A CN202011001038A CN112635421A CN 112635421 A CN112635421 A CN 112635421A CN 202011001038 A CN202011001038 A CN 202011001038A CN 112635421 A CN112635421 A CN 112635421A
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China
Prior art keywords
roughness
layer
conductive
portions
conductive pillars
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CN202011001038.2A
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郭宏瑞
蔡惠榕
彭竣翔
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN112635421A publication Critical patent/CN112635421A/zh
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Abstract

一种封装结构包括至少一个半导体管芯、绝缘密封体及重布线结构。所述至少一个半导体管芯具有多个导电柱，其中所述多个导电柱的顶表面具有第一粗糙度。绝缘密封体包封所述至少一个半导体管芯。重布线结构在积层方向上设置在绝缘密封体上且电连接到所述至少一个半导体管芯。重布线结构包括：多个导通孔部及多个导电体部，嵌置在介电层中，其中所述多个导电体部的顶表面具有第二粗糙度，且第二粗糙度大于第一粗糙度。

Description

封装结构及其制作方法
技术领域
本公开实施例是有关一种封装结构及其制作方法。
背景技术
半导体装置及集成电路通常是在单个半导体晶片上制造。可以晶片级对晶片的管芯进行处理并与其他半导体装置或管芯封装在一起，且已经开发出用于晶片级封装(waferlevel packaging，WLP)的各种技术。另外，此种封装还可在进行切割(dicing)之后被整合到半导体衬底或载体。因此，每一封装内的导电端子与内部组件(例如，重布线路结构)之间的电连接的可靠性至关重要。
发明内容
本公开实施例提供一种封装结构，所述封装结构包括至少一个半导体管芯、绝缘密封体以及重布线结构。所述至少一个半导体管芯具有多个导电柱，其中所述多个导电柱中的顶表面具有第一粗糙度。所述绝缘密封体包封所述至少一个半导体管芯。所述重布线结构在积层方向上设置在所述绝缘密封体上且电连接到所述至少一个半导体管芯。所述重布线结构包括：多个导通孔部及多个导电体部，嵌置在介电层中，其中所述多个导电体部的顶表面具有第二粗糙度，且所述第二粗糙度大于所述第一粗糙度。
本公开实施例提供一种制作封装结构的方法。所述方法包括以下步骤。在载体上提供多个半导体管芯，其中所述多个半导体管芯包括多个导电柱。形成包封所述多个半导体管芯的绝缘密封体，其中所述绝缘密封体的顶表面与所述多个导电柱的顶表面实质上齐平。对所述多个导电柱执行清洁工艺，其中所述清洁工艺包括使用第一溶液对所述多个导电柱的所述顶表面进行清洁达20秒到80秒的第一清洁步骤，且其中在所述清洁工艺之后所述多个导电柱的所述顶表面具有第一粗糙度。在积层方向上在所述绝缘密封体上形成重布线结构，其中所述形成所述重布线结构的步骤包括形成嵌置在介电层中的多个导通孔部及多个导电体部，且其中所述多个导电体部的顶表面具有第二粗糙度，且所述第二粗糙度大于所述第一粗糙度。然后将所述载体剥离。
本公开实施例提供一种制作封装结构的方法。所述方法包括以下步骤。在载体上提供至少一个半导体管芯，其中所述至少一个半导体管芯包括多个导电柱。形成包封所述至少一个半导体管芯的绝缘密封体。通过移除所述绝缘密封体的部分以显露出所述多个导电柱的顶表面来执行平坦化工艺。在所述平坦化工艺之后对所述多个导电柱执行单晶片旋转清洁工艺，其中所述单晶片旋转清洁工艺包括在使所述载体旋转的同时将第一溶液滴加到所述多个导电柱的所述顶表面上达20秒到80秒以对所述多个导电柱的所述顶表面进行清洁。在所述绝缘密封体上形成重布线结构，其中所述重布线结构通过以下步骤形成。形成交替堆叠的多个导电体部、多个第一通孔部及多个介电层，其中所述多个第一通孔部形成有从第一通孔部的第一端到第一通孔部的第二端保持恒定的侧向尺寸，且在形成所述多个第一通孔部中的每一者之后对所述第二端的表面执行通孔清洁工艺，所述通孔清洁工艺包括在使所述载体旋转的同时将所述第一溶液滴加到所述第一通孔部的所述第二端的所述表面上达20秒到80秒以对所述第二端的所述表面进行清洁。然后将所述载体剥离。
附图说明
结合附图阅读以下详细说明，会最好地理解本公开的各个方面。应注意，根据本行业中的标准惯例，各种特征并非按比例绘制。事实上，为使论述清晰起见，可任意增大或减小各种特征的临界尺寸(critical dimension)。
图1A到图1K是根据本公开一些示例性实施例的制作封装结构的方法中的各个阶段的示意性剖视图。
图2A到图2C是根据本公开一些示例性实施例的制作封装结构的方法中的各个阶段处的半导体管芯的放大剖视图。
图3是根据本公开一些其他示例性实施例的封装结构的示意性剖视图。
图4是根据本公开一些示例性实施例的叠层封装(package-on-package，PoP)结构的示意性剖视图。
图5是根据本公开一些其他示例性实施例的封装结构的示意性剖视图。
图6是根据本公开一些其他示例性实施例的封装结构的示意性剖视图。
图7是根据本公开一些其他示例性实施例的封装结构的示意性剖视图。
图8是根据本公开一些其他示例性实施例的封装结构的示意性剖视图。
图9是根据本公开一些其他示例性实施例的封装结构的示意性剖视图。
[符号的说明]
102：载体
104：缓冲层
104A：剥离层
104B：介电层
105：管芯贴合膜
106A：第一半导体管芯/半导体管芯
106a-AS、106b-AS：有效表面
106a-BS、106b-BS：背侧表面
106a-1、106b-1：半导体衬底
106a-2、106b-2：导电焊盘
106a-3、106b-3：钝化层
106a-4、106b-4：导电柱
106a-4-TS、106a-AM-TS、106b-4-TS、106b-AM-TS、108-TS、110-TS、112-B-TS、112-C-TS、112-V-TS：顶表面
106a-5、106b-5：保护层
106a-AM、106b-AM：对准标记
106B、106B’：第二半导体管芯/半导体管芯
108：贯穿绝缘层孔
110：绝缘材料
110’：绝缘密封体
112-Bx、112-Cx：导电体部
112-D：第二介电层/介电层
112-Vx：第一通孔部
112-V1、112-W1：第一端
112-V2、112-W2：第二端
112-Wx：第二通孔部
114、250：导电焊盘
116、118、270：导电球
210：衬底
220：半导体芯片
230：结合线
240：焊盘
260：绝缘密封体
280：底部填充胶
301：带
302：框架
DR1：积层方向
LD1、LD2：侧向尺寸
M1：第一金属层/金属层
M2：第二金属层/金属层
M3：第三金属层/金属层
Mx：焊料层
Pk2：第二封装
PoP：叠层封装结构
PS1、PS2、PS3、PS4、PS5、PS6、PS7：封装结构
RDL1：第一重布线层
RDL2：第二重布线层
RDS：重布线结构
Rh：凹槽高度
Rx：凹槽
SD1：平面晶种层
SD2：非平面晶种层
SN1：第一溶液
SN2：第二溶液
具体实施方式
以下公开提供用于实施所提供主题的不同特征的许多不同实施例或实例。以下阐述组件及排列的具体实例以简化本公开。当然，这些仅为实例且不旨在进行限制。举例来说，以下说明中将第二特征形成在第一特征之上或第一特征上可包括其中第二特征与第一特征被形成为直接接触的实施例，且也可包括其中第二特征与第一特征之间可形成有附加特征从而使得所述第二特征与所述第一特征可不直接接触的实施例。另外，本公开可能在各种实例中重复使用参考编号和/或字母。这种重复使用是出于简洁及清晰的目的，而不是自身指示所论述的各种实施例和/或配置之间的关系。
此外，为易于说明，本文中可能使用例如“在…之下(beneath)”、“在…下方(below)”、“下部的(lower)”、“在…上(on)”、“在…之上(over)”、“上覆在…之上(overlying)”、“在…上方(above)”、“上部的(upper)”等空间相对性用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对性用语旨在除图中所绘示的取向外还囊括装置在使用或操作中的不同取向。设备可具有其他取向(旋转90度或处于其他取向)，且本文中所使用的空间相对性描述语可同样相应地进行解释。
还可包括其他特征及工艺。举例来说，可包括测试结构以帮助对三维(three-dimensional，3D)封装或三维集成电路(three-dimensional integrated circuit，3DIC)装置进行验证测试。所述测试结构可包括例如在重布线层中或衬底上形成的测试焊盘(test pad)，以便能够对3D封装或3DIC进行测试、使用探针和/或探针卡(probe card)等。可对中间结构以及最终结构执行验证测试。另外，本文中所公开的结构及方法可与包含对已知良好管芯(known good die)进行中间验证的测试方法结合使用以提高良率并降低成本。
图1A到图1K是根据本公开一些示例性实施例的制作封装结构的方法中的各个阶段的示意性剖视图。参照图1A，提供上面涂覆有缓冲层104的载体102。在一些实施例中，载体102可为玻璃载体或用于承载用于制作封装结构的方法的半导体晶片或重构晶片的任何合适的载体。
在一些实施例中，缓冲层104包括剥离层104A及介电层104B，其中剥离层104A位于载体102与介电层104B之间。在某些实施例中，剥离层104A设置在载体102上，且剥离层104A的材料可为适于将载体102与上面的层(例如，介电层104B)或设置在载体102上的任何晶片结合以及将载体102从上面的层(例如，介电层104B)或设置在载体102上的任何晶片剥离的任何材料。在一些实施例中，剥离层104A可包括释放层(例如光-热转换(“light-to-heatconversion，LTHC”)层)或粘合剂层(例如紫外线可固化粘合剂层或热可固化粘合剂层)。在一些实施例中，介电层104B可形成在剥离层104A上方。介电层104B可由介电材料(例如苯并环丁烯(“benzocyclobutene，BCB”)、聚苯并恶唑(“polybenzoxazole，PBO”)、或任何其他合适的聚合物系介电材料)制成。
应注意，载体102、剥离层104A及介电层104B的材料并不仅限于实施例的说明。在一些替代实施例中，可可选地省略介电层104B；换句话说，在载体102之上形成仅剥离层104A。在某些实施例中，可在剥离层104A上直接形成用于贴合到以上组件的管芯贴合膜(未示出)。
参照图1B，在提供缓冲层104之后，在载体102之上的缓冲层104上提供多个贯穿绝缘层孔108及多个半导体管芯(第一半导体管芯106A及第二半导体管芯106B)。在一些实施例中，贯穿绝缘层孔108是集成扇出型(“integrated fan-out，InFO”)穿孔。在一个实施例中，形成贯穿绝缘层孔108包括：形成具有开口的掩模图案(未示出)；接着通过电镀或沉积形成填满所述开口的金属材料(未示出)；以及移除掩模图案以在缓冲层104上形成贯穿绝缘层孔108。掩模图案的材料可包括正性光刻胶或负性光刻胶。在一个实施例中，贯穿绝缘层孔108的材料可包括金属材料，例如铜或铜合金等。然而，本公开并不仅限于此。
在替代实施例中，可通过如下方式形成贯穿绝缘层孔108：在缓冲层104上形成晶种层(未示出)；形成具有开口的掩模图案，所述开口暴露出晶种层的部分；通过镀覆在晶种层的被暴露出的部分上形成金属材料以形成贯穿绝缘层孔108；移除掩模图案；以及接着移除晶种层的被贯穿绝缘层孔108暴露出的部分。举例来说，晶种层可为钛/铜复合层。为简明起见，在图1B中示出仅四个贯穿绝缘层孔108。然而应注意，贯穿绝缘层孔108的数目并不仅限于此，且可根据要求来选择。
如图1B中所示，可在缓冲层104上拾取并放置第一半导体管芯106A及第二半导体管芯106B。在某些实施例中，第一半导体管芯106A具有有效表面106a-AS及与有效表面106a-AS相对的背侧表面106a-BS。举例来说，第一半导体管芯106A的背侧表面106a-BS可通过管芯贴合膜105贴合到缓冲层104。类似地，第二半导体管芯106B具有有效表面106b-AS及与有效表面106b-AS相对的背侧表面106b-BS。举例来说，第二半导体管芯106B的背侧表面106b-BS可通过管芯贴合膜105贴合到缓冲层104。通过使用管芯贴合膜105，会确保第一半导体管芯106A、第二半导体管芯106B及缓冲层104之间的更好的贴合。在示例性实施例中，示出仅两个半导体管芯(106A/106B)。然而，本公开并不仅限于此。应注意，设置在缓冲层104上的半导体管芯(106A/106B)的数目可基于产品要求来调节。
在示例性实施例中，第一半导体管芯106A及第二半导体管芯106B分别包括半导体衬底(106a-1/106b-1)、多个导电焊盘(106a-2/106b-2)、钝化层(106a-3/106b-3)、多个导电柱(106a-4/106b-4)、保护层(106a-5/106b-5)及对准标记(106a-AM/106b-AM)。如图1B中所示，所述多个导电焊盘(106a-2/106b-2)设置在半导体衬底(106a-1/106b-1)上。钝化层(106a-3/106b-3)形成在半导体衬底(106a-1/106b-1)之上且具有局部地暴露出半导体衬底(106a-1/106b-1)上的导电焊盘(106a-2/106b-2)的开口。半导体衬底(106a-1/106b-1)可为块状硅衬底或绝缘体上硅(silicon-on-insulator，SOI)衬底，且还包括形成在其中的有源组件(例如，晶体管等)及可选的无源组件(例如，电阻器、电容器、电感器等)。导电焊盘(106a-2/106b-2)可为铝焊盘、铜焊盘、或其他合适的金属焊盘。钝化层(106a-3/106b-3)可为氧化硅层、氮化硅层、氮氧化硅层、或由任何合适的介电材料形成的介电层。此外，在一些实施例中，在钝化层(106a-3/106b-3)之上可选地形成后钝化层(未示出)。后钝化层覆盖钝化层(106a-3/106b-3)且具有多个接触开口。导电焊盘(106a-2/106b-2)被后钝化层的接触开口局部地暴露出。后钝化层可为苯并环丁烯(BCB)层、聚酰亚胺层、聚苯并噁唑(PBO)层、或由其它合适的聚合物形成的介电层。在一些实施例中，导电柱(106a-4/106b-4)通过镀覆形成在导电焊盘(106a-2/106b-2)上。在某些实施例中，随着导电柱(106a-4/106b-4)的形成，可在钝化层(106a-3/106b-3)上形成对准标记(106a-AM/106b-AM)。举例来说，对准标记(106a-AM/106b-AM)与导电柱(106a-4/106b-4)由相同的材料形成。在一些实施例中，保护层(106a-5/106b-5)形成在钝化层(106a-3/106b-3)上或后钝化层上，且覆盖导电柱(106a-4/106b-4)及对准标记(106a-AM/106b-AM)以保护这些组件。
在一些实施例中，当在缓冲层104上放置多个半导体管芯(106A/106B)时，然后可将半导体管芯(106A/106B)排列成阵列，且当将半导体管芯(106A/106B)排列成阵列时，可将贯穿绝缘层孔108分类成群组。半导体管芯(106A/106B)的数目可与贯穿绝缘层孔108的群组的数目对应。在图示的实施例中，可在形成贯穿绝缘层孔108之后在缓冲层104上拾取并放置半导体管芯(106A/106B)。然而，本公开并不仅限于此。在一些替代实施例中，可在形成贯穿绝缘层孔108之前在缓冲层104上拾取并放置半导体管芯(106A/106B)。
此外，在一些实施例中，第一半导体管芯106A及第二半导体管芯106B可选自应用专用集成电路(application-specific integrated circuit，ASIC)芯片、模拟芯片(例如，无线及射频芯片)、数字芯片(例如，基带芯片)、集成无源装置(integrated passivedevice，IPD)、电压调节器芯片、传感器芯片、存储器芯片等。举例来说，在一个实施例中，第一半导体管芯106A与第二半导体管芯106B可为相同类型的半导体管芯。在替代实施例中，第一半导体管芯106A与第二半导体管芯106B可为不同类型的半导体管芯。本公开并不仅限于此。
参照图1C，在下一步骤中，在缓冲层104上及半导体管芯(106A/106B)之上形成绝缘材料110。在一些实施例中，绝缘材料110被形成为覆盖贯穿绝缘层孔108。在一些实施例中，通过例如模压成型(compression molding)工艺形成绝缘材料110、填充半导体管芯(106A/106B)与贯穿绝缘层孔108之间的间隙以包封半导体管芯(106A/106B)。绝缘材料110还填充相邻的贯穿绝缘层孔108之间的间隙，以包封贯穿绝缘层孔108。在此阶段处，导电柱(106a-4/106b-4)、保护层(106a-5/106b-5)、对准标记(106a-AM/106b-AM)及贯穿绝缘层孔108被绝缘材料110包封且很好地保护起来。换句话说，不显露出导电柱(106a-4/106b-4)、对准标记(106a-AM/106b-AM)及贯穿绝缘层孔108。
在一些实施例中，绝缘材料110包含聚合物(例如环氧树脂、酚醛树脂(phenolicresin)、含硅树脂或其他合适的树脂)、具有低介电常数(permittivity，Dk)及低损耗正切(loss tangent，Df)性质的介电材料、或其他合适的材料。在替代实施例中，绝缘材料110可包含可接受的绝缘密封体材料。在一些实施例中，绝缘材料110还可包含可被添加到绝缘材料110中来优化绝缘材料110的热膨胀系数(coefficient of thermal expansion，CTE)的无机填料或无机化合物(例如，二氧化硅、粘土等)。本公开并不仅限于此。
参照图1D，在一些实施例中，局部地移除绝缘材料110以暴露出导电柱(106a-4/106b-4)、对准标记(106a-AM/106b-AM)及贯穿绝缘层孔108。在一些实施例中，通过平坦化步骤对绝缘材料110及保护层(106a-5/106b-5)进行研磨或抛光。举例来说，通过机械研磨工艺和/或化学机械抛光(chemical mechanical polishing，CMP)工艺执行平坦化步骤，直到显露出导电柱(106a-4/106b-4)的顶表面(106a-4-TS/106b-TS)及对准标记(106a-AM/106b-AM)的顶表面(106a-AM-TS/106b-AM-TS)。在一些实施例中，可局部地对贯穿绝缘层孔108进行抛光，使得贯穿绝缘层孔108的顶表面108-TS与导电柱(106a-4/106b-4)的顶表面(106a-4-TS/106b-4-TS)及对准标记(106a-AM/106b-AM)的顶表面(106a-AM-TS/106b-AM-TS)实质上齐平，或者与第一半导体管芯106A及第二半导体管芯106B的有效表面(106a-AS/106b-AS)实质上齐平。换句话说，也可对导电柱(106a-4/106b-4)、对准标记(106a-AM/106b-AM)及贯穿绝缘层孔108进行轻微研磨/抛光。在图示的实施例中，对绝缘材料110进行抛光以形成绝缘密封体110’。
参照图1E，在一些实施例中，在机械研磨或化学机械抛光(CMP)步骤之后，可执行清洁工艺。举例来说，执行清洁工艺以清洁及移除平坦化步骤所产生的残留物，以及形成实质上平坦及光滑的表面。在一些实施例中，清洁工艺包括使用第一溶液SN1对导电柱(106a-4/106b-4)的顶表面(106a-4-TS/106b-4-TS)进行清洁、对对准标记(106a-AM/106b-AM)的顶表面(106a-AM-TS/106b-AM-TS)进行清洁、以及对贯穿绝缘层孔108的顶表面108-TS进行清洁达20秒到80秒的第一清洁步骤。举例来说，在某些实施例中，如通过在使载体102旋转的同时将第一溶液SN1滴加到导电柱(106a-4/106b-4)的顶表面(106a-4-TS/106b-4-TS)上达20秒到80秒，以对导电柱(106a-4/106b-4)的顶表面(106a-4-TS/106b-4-TS)进行清洁的第一清洁步骤来执行单晶片旋转清洁工艺(single wafer spin cleaning process)。可以使用单晶片旋转清洁工艺的类似方式对对准标记(106a-AM/106b-AM)的顶表面(106a-AM-TS/106b-AM-TS)及贯穿绝缘层孔108的顶表面108-TS进行清洁。在一些实施例中，使用第一溶液SN1执行第一清洁步骤达至少20秒，以确保所应用表面的粗糙度降低到一定程度，且使用第一溶液SN1执行第一清洁步骤达少于80秒，以防止对所应用表面的过度刻蚀或损坏。
在一些实施例中，第一溶液SN1的pH处于pH 0.5到pH 5的范围内。在一些实施例中，第一溶液SN1包括选自由乙酸、甲酸、柠檬酸、抗坏血酸、氢氟酸、氢氯酸、磷酸及硝酸组成的群组的至少一种酸。在一些实施例中，酸的浓度处于0.05重量百分比到10重量百分比的范围内。在一些替代实施例中，第一溶液SN1包括选自由乙醇胺、羟乙基乙二胺、氢氧化铵及氯化铵组成的群组的至少一种胺系溶液。在一些实施例中，胺系溶液的浓度处于10重量百分比到35重量百分比的范围内。在某些实施例中，上述酸及胺系溶液可单独使用，或者结合使用于第一溶液SN1中。在一个示例性实施例中，第一溶液SN1是柠檬酸溶液。
此外，在一些实施例中，清洁工艺可可选地包括使用第二溶液SN2对导电柱(106a-4/106b-4)的顶表面(106a-4-TS/106b-4-TS)进行清洁、对对准标记(106a-AM/106b-AM)的顶表面(106a-AM-TS/106b-AM-TS)进行清洁、以及对贯穿绝缘层孔108的顶表面108-TS进行清洁达20秒到80秒的第二清洁步骤。举例来说，在某些实施例中，可如通过在使载体102旋转的同时将第二溶液SN2滴加到导电柱(106a-4/106b-4)的顶表面(106a-4-TS/106b-4-TS)上达20秒到80秒，以对导电柱(106a-4/106b-4)的顶表面(106a-4-TS/106b-4-TS)进行清洁的第二清洁步骤来执行另一单晶片旋转清洁工艺。可以使用单晶片旋转清洁工艺的类似的方式对对准标记(106a-AM/106b-AM)的顶表面(106a-AM-TS/106b-AM-TS)及贯穿绝缘层孔108的顶表面108-TS进行清洁。在一些实施例中，使用第二溶液SN2执行第二清洁步骤达至少20秒，以确保所应用表面的粗糙度降低到一定程度，且使用第二溶液SN2执行第二清洁步骤达少于80秒，以防止对所应用表面的过度刻蚀或损坏。
在一些实施例中，第二溶液SN2的pH处于pH 1.5到pH 6的范围内。在一些实施例中，第二溶液SN2包括选自由乙酸、甲酸、柠檬酸、抗坏血酸、氢氟酸、氢氯酸、磷酸及硝酸组成的群组的至少一种酸。在一些实施例中，酸的浓度处于0.01重量百分比到3重量百分比的范围内。在一些替代实施例中，第二溶液SN2包括选自由乙醇胺、羟乙基乙二胺、氢氧化铵及氯化铵组成的群组的至少一种胺系溶液。在一些实施例中，胺系溶液的浓度处于10重量百分比到35重量百分比的范围内。在某些实施例中，上述酸及胺系溶液可单独使用，或者结合使用于第二溶液SN2中。在一些实施例中，第二溶液SN2可与第一溶液SN1相同。在替代实施例中，第二溶液SN2可与第一溶液SN1不同。
在执行清洁工艺(单晶片旋转清洁工艺)之后，所述多个导电柱(106a-4/106b-4)的顶表面(106a-4-TS/106b-4-TS)可具有粗糙度Rg1。在一些实施例中，在清洁工艺之前，所述多个导电柱(106a-4/106b-4)的顶表面(106a-4-TS/106b-4-TS)的粗糙度处于1.5μm到5μm的范围内。在某些实施例中，在清洁工艺之后，粗糙度Rg1处于0.1μm到1μm的范围内。在一些实施例中，对准标记(106a-AM/106b-AM)的顶表面(106a-AM-TS/106b-AM-TS)可具有粗糙度Rg2，且贯穿绝缘层孔108的顶表面108-TS可具有粗糙度Rg3。举例来说，粗糙度Rg2及粗糙度Rg3可实质上等于粗糙度Rg1。在一些实施例中，在清洁工艺之后，绝缘密封体110’的顶表面110-TS、贯穿绝缘层孔108的顶表面108-TS、导电柱(106a-4/106b-4)的顶表面(106a-4-TS/106b-4-TS)、对准标记(106a-AM/106b-AM)的顶表面(106a-AM-TS/106b-AM-TS)以及抛光后的保护层(106a-5/106b-5)的顶表面实质上共面且彼此齐平。
图1F是根据本公开一些其他实施例的清洁工艺之后的半导体管芯106A的放大剖视图。如图1G中所示，在一些实施例中，在清洁工艺之后，在保护层106a-5中可存在凹槽Rx。换句话说，在保护层106a-5与导电柱106a-4之间可能存在台阶高度差。在某些实施例中，凹槽Rx可具有处于0.1μm到5.0μm的范围内的凹槽高度Rh。然而，本公开并不仅限于此。在一些替代实施例中，在保护层106a-5中不存在凹槽，且保护层106a-5与导电柱106a-4实质上共面。
参照图1G及图1H，阐述在绝缘密封体110’上形成重布线结构的步骤。如图1G中所示，在第一步骤中，在积层方向DR1上在导电柱(106a-4/106b-4)之上以及在贯穿绝缘层孔108之上形成多个导通孔部(第一通孔部112-Vx)。在一些实施例中，通过在绝缘密封体110’之上形成平面晶种层SD1来形成导通孔部(第一通孔部112-Vx)；形成具有开口的掩模图案，所述开口暴露出平面晶种层SD1的部分；在平面晶种层SD1的被暴露出的部分上形成导电材料，以通过镀覆形成导通孔部(第一通孔部112-Vx)；移除掩模图案；且接着移除平面晶种层SD1的被导通孔部(第一通孔部112-Vx)暴露出的部分。此后，可形成介电材料(未示出)以覆盖导通孔部(第一通孔部112-Vx)，其中通过平坦化步骤进一步对介电材料进行研磨或抛光以形成介电层112-D。在一些实施例中，通过机械研磨工艺和/或化学机械抛光(CMP)工艺执行平坦化步骤，直到显露出导通孔部(第一通孔部112-Vx)的顶表面112-V-TS。
在图示的实施例中，导通孔部(第一通孔部112-Vx)形成有在积层方向DR1上从导通孔部(第一通孔部112-Vx)的第一端112-V1到导通孔部(第一通孔部112-Vx)的第二端112-V2保持恒定的侧向尺寸LD1。在一些实施例中，在平坦化步骤之后，可执行通孔清洁工艺(例如单晶片旋转清洁工艺)以使用第一溶液SN1对导通孔部(第一通孔部112-Vx)的第二端112-V2的顶表面112-V-TS进行清洁达20秒到80秒以形成实质上平坦及光滑的表面。在某些实施例中，可可选地执行另一通孔清洁工艺(例如单晶片旋转清洁工艺)，以使用第二溶液SN2对导通孔部的第二端112-V2的顶表面112-V-TS进行清洁达20秒到80秒，以形成实质上平坦及光滑的表面。此处提到的第一溶液SN1及第二溶液SN2与图1E中提到的第一溶液SN1及第二溶液SN2相同，因此此处将省略其详细说明。在通孔清洁工艺之后，导通孔部(第一通孔部112-Vx)的第二端112-V2的顶表面112-V-TS可具有粗糙度Rg4。举例来说，通孔清洁工艺之后的粗糙度Rg4处于0.1μm到1μm的范围内。在某些实施例中，粗糙度Rg4可实质上等于粗糙度Rg1。
参照图1H，在下一步骤中，可通过执行镀覆及平坦化工艺以类似于上面图1G中所述的方式，在积层方向DR1上形成且堆叠平面晶种层SD1、多个导电体部112-Bx、多个导通孔部(第一通孔部112-Vx)及第二介电层112-D。在示例性实施例中，在平坦化工艺之后，显露出嵌置在第二介电层112-D中的导通孔部(第一通孔部112-Vx)的顶表面112-V-TS。此后，可执行相同的通孔清洁工艺，以通过使用用于清洁的第一溶液SN1及可选的第二溶液SN1对最上面的导通孔部(第一通孔部112-Vx)的表面进行清洁。这样一来，在通孔清洁工艺之后，导通孔部(第一通孔部112-Vx)的第二端112-V2的顶表面112-V-TS可具有粗糙度Rg4。另一方面，由于导电体部112-Bx的顶表面112-B-TS被介电层112-D覆盖且未通过通孔清洁工艺进行清洁，因此它可具有粗糙度Rg5，其中粗糙度Rg5大于粗糙度Rg4。在一些实施例中，粗糙度Rg1、粗糙度Rg2、粗糙度Rg3、粗糙度Rg4全部小于粗糙度Rg5。
参照图1I，在一些实施例中，接着可重复形成图1G及图1H中阐述的平面晶种层SD1、导通孔部(第一通孔部112-Vx)、导电体部112-Bx及介电层112-D，以形成重布线结构RDS。在一些实施例中，在积层方向DR1上交替堆叠平面晶种层SD1、导通孔部(第一通孔部112-Vx)、导电体部112-Bx及介电层112-D，以构成重布线结构RDS。此外，在示例性实施例中，所有导通孔部(第一通孔部112-Vx)可具有具有粗糙度Rg4的顶表面112-V-TS，而导电体部112-Bx可具有具有粗糙度Rg5的顶表面112-B-TS，且粗糙度Rg4小于粗糙度Rg5。在一些实施例中，平面晶种层SD1的部分可设置在导通孔部(第一通孔部112-Vx)上且与导通孔部(第一通孔部112-Vx)实体接触。
如图1I中所示，尽管本文中示出三层导通孔部(第一通孔部112-Vx)/导电体部112-Bx及四层介电层112-D，然而，本公开的范围并不仅限于此。在其他实施例中，导通孔部(第一通孔部112-Vx)/导电体部112-Bx及介电层112-D的层的数目可基于产品要求来调节。在一些实施例中，重布线结构RDS通过导通孔部(第一通孔部112-Vx)及导电体部112-Bx电连接到贯穿绝缘层孔108及半导体管芯(106A/106B)。
在示例性实施例中，介电层112-D的材料可为可使用光刻和/或刻蚀工艺来图案化的聚酰亚胺、聚苯并噁唑(PBO)、苯并环丁烯(BCB)、例如氮化硅等氮化物、例如氧化硅等氧化物、磷硅酸盐玻璃(phosphosilicate glass，PSG)、硼硅酸盐玻璃(borosilicate glass，BSG)、硼掺杂磷硅酸盐玻璃(boron-doped phosphosilicate glass，BPSG)、其组合等。在一些实施例中，介电层112-D的材料可通过合适的制作技术(例如旋转涂布、化学气相沉积(chemical vapor deposition，CVD)、等离子体增强型化学气相沉积(plasma-enhancedchemical vapor deposition，PECVD)等)形成。本公开并不仅限于此。
此外，在一些实施例中，导通孔部(第一通孔部112-Vx)及导电体部112-Bx的材料可由通过电镀或沉积形成的导电材料(例如可使用光刻及刻蚀工艺来图案化的铝、钛、铜、镍、钨、和/或其合金)制成。在说明书通篇中，用语“铜”旨在包括实质上纯的元素铜、含有不可避免的杂质的铜、以及含有少量例如钽、铟、锡、锌、锰、铬、钛、锗、锶、铂、镁、铝或锆等元素的铜合金。
仍然参照图1I，在形成重布线结构RDS之后，可在导电体部112-Bx的最顶层的被暴露出的顶表面上设置用于与导电球(或导电凸块)电连接的多个导电焊盘114。在一些实施例中，导电焊盘114是例如用于球安装的球下金属(under-ball metallurgy，UBM)图案。如图1I中所示，导电焊盘114形成在重布线结构RDS上且电连接到重布线结构RDS。在一些实施例中，导电焊盘114的材料可包括铜、镍、钛、钨、或其合金等，且可通过例如电镀工艺形成导电焊盘114。导电焊盘114的数目在本公开中不受限制，且可基于设计布局来选择。在一些替代实施例中，可省略导电焊盘114。换句话说，在后续步骤中形成的导电球116(或导电凸块)可直接设置在重布线结构RDS上。
在形成导电焊盘114之后，在导电焊盘114上及重布线结构RDS之上设置多个导电球116。在一些实施例中，可通过植球工艺或回焊工艺在导电焊盘114上设置导电球116。在一些实施例中，导电球116是例如焊料球或球栅阵列(ball grid array，BGA)球。在一些实施例中，导电球116通过导电焊盘114连接到重布线结构RDS。在某些实施例中，导电球116中的一些导电球116可通过重布线结构RDS电连接到半导体管芯(106A/106B)。此外，导电球116中的一些导电球116可通过重布线结构RDS电连接到贯穿绝缘层孔108。导电球116的数目并不限于本公开，且可基于导电焊盘114的数目来指定及选择。
参照图1J，在一些实施例中，在形成重布线结构RDS及导电球116之后，可将图1I中所示的结构翻转且贴合到由框架302支撑的带301(例如，切割带)。如图1J中所示，载体102被剥离且与介电层104B隔开。在一些实施例中，剥离工艺包括将例如激光或紫外光等光投射到剥离层104A(例如，LTHC释放层)上，使得载体102可容易地与剥离层104A一起移除。在剥离步骤期间，在剥离载体102及剥离层104A之前，使用带301来固定封装结构。在剥离工艺之后，显露或暴露出介电层104B的背侧表面。
参照图1K，在一些实施例中，在剥离工艺之后，可将介电层104B图案化，以形成暴露出贯穿绝缘层孔108的底表面的多个开口(未示出)。形成的开口的数目与贯穿绝缘层孔108的数目对应。此后，可在贯穿绝缘层孔108的被开口暴露出的底表面上放置多个导电球118。导电球118例如被回焊成与贯穿绝缘层孔108的底表面结合。随后，可执行切割工艺以将整个晶片结构剖切(切穿重布线结构RDS、绝缘密封体110’及介电层104B)成多个封装结构PS1。至此，完成根据本公开的一些实施例的具有双侧端子的封装结构PS1。
图2A到图2C是根据本公开一些示例性实施例的制作封装结构的方法中的各个阶段处的半导体管芯的放大剖视图。此处阐述的方法类似于图1C到图1F中阐述的方法，因此相同的参考编号用于指代相同或相似的部件，且此处将省略其详细说明。实施例之间的不同之处在于导电柱(106a-4/106b-4)的设计。在图1C到图1F中所示的实施例中，导电柱(106a-4/106b-4)由单一材料(例如铜柱)制成。然而，本公开并不仅限于此，且导电柱(106a-4/106b-4)可由多种材料制成。
举例来说，参照图2A，在一些实施例中，在执行平坦化工艺(与图1C中所示的步骤对应)之前，第一半导体管芯106A的导电柱106a-4可包括第一金属层M1、第二金属层M2、第三金属层M3及焊料层Mx。在一个示例性实施例中，第一金属层M1是铜层，第二金属层是镍层，且第三金属层M3是铜层。此外，在此阶段处，保护层106a-5完全覆盖导电柱106a-4。
参照图2B，执行平坦化步骤以移除焊料层Mx及第三金属层M3的部分，使得第二金属层M2的顶表面(106a-4-TS)被显露或暴露出。在一些实施例中，剩余量的第三金属层M3可保留在第二金属层M2上。在某些实施例中，剩余的第三金属层M3可被视为第二金属层M2的侧面部分(flank portion)。在替代实施例中，可通过平坦化步骤完全移除第三金属层M3。在执行平坦化步骤之后，可执行类似于图1E中所述的使用第一溶液SN1(以及可选的第二溶液SN2)的清洁工艺(单晶片旋转清洁工艺)来对导电柱106a-4的顶表面106a-4-TS(其为第二金属层M2的表面)进行清洁。
参照图2C，在执行清洁工艺之后，形成具有铜层(金属层M1)、镍层(金属层M2)及侧面部分(金属层M3)的导电柱106a-4。在一些实施例中，镍层(金属层M2)的顶表面(106a-4-TS)具有第一粗糙度Rg1。在某些实施例中，清洁工艺之后的粗糙度Rg1处于0.1μm到1μm的范围内。在某些实施例中，镍层(金属层M2)的顶表面(106a-4-TS)与侧面部分(金属层M3)的顶表面及保护层106a-5的顶表面实质上共面。此后，可执行图1G到图1K中阐述的相同步骤，以在其上形成重布线结构RDS，且完成封装结构的形成。
图3是根据本公开一些其他示例性实施例的封装结构的示意性剖视图。图3中所示的封装结构PS2类似于图1K中所示的封装结构PS1，因此，相同的参考编号用于指代相同或相似的部件，且此处将省略其详细说明。实施例之间的不同之处在于，在图3中省略了贯穿绝缘层孔108。由于在封装结构PS2中省略了贯穿绝缘层孔108，因此也可省略放置在贯穿绝缘层孔108上的导电球118。类似于上述实施例，执行清洁工艺(单晶片旋转清洁工艺)以对导电柱(106a-4/106b-4)的表面、对准标记(106a-AM/106b-AM)的表面及第一通孔部112-Vx的表面进行处理。因此，导电柱(106a-4/106b-4)的表面、对准标记(106a-AM/106b-AM)的表面、及第一通孔部112-Vx的表面可具有较小的粗糙度，且可防止形成在导电柱(106a-4/106b-4)、对准标记(106a-AM/106b-AM)及第一通孔部112-Vx上的通孔或连接结构的塌陷问题。
图4是根据本公开一些示例性实施例的叠层封装(PoP)结构的示意性剖视图。参照图4，在制作第一封装(例如图1K中所示的封装结构PS1)之后，可在封装结构PS1(第一封装)上堆叠第二封装Pk2，以形成叠层封装(PoP)结构。在一些实施例中，从封装结构PS1省略导电球118，使得第二封装Pk2可通过导电球270堆叠在封装结构PS1上且电连接到封装结构PS1。如图4中所示，第二封装Pk2通过导电球270电连接到封装结构PS1的贯穿绝缘层孔108。
在一些实施例中，第二封装Pk2具有衬底210、安装在衬底210的一个表面(例如，顶表面)上且堆叠在彼此顶部上的多个半导体芯片220。在一些实施例中，使用结合线230在半导体芯片220与焊盘240(例如结合焊盘)之间提供电连接。在一些实施例中，形成绝缘密封体260来包封半导体芯片220及结合线230，以保护这些组件。在一些实施例中，可使用贯穿绝缘层孔(未示出)来提供焊盘240与导电焊盘250(例如结合焊盘)之间的电连接，导电焊盘250位于衬底210的另一表面(例如，底表面)上。在某些实施例中，导电焊盘250通过这些贯穿绝缘层孔(未示出)电连接到半导体芯片220。在一些实施例中，封装结构Pk2的导电焊盘250电连接到导电球270。在一些实施例中，进一步提供底部填充胶280来填充导电球270之间的空间，以保护导电球270。在将第二封装Pk2堆叠在封装结构PS1(第一封装)上且在第二封装Pk2与封装结构PS1(第一封装)之间提供电连接之后，可制作叠层封装结构PoP。
图5是根据本公开一些其他示例性实施例的封装结构的示意性剖视图。图5中所示的封装结构PS3类似于图1K中所示的封装结构PS1，因此，相同的参考编号用于指代相同或相似的部件，且此处将省略其详细说明。实施例之间的不同之处在于第二半导体管芯106B’及重布线结构RDS的设计。如图5中所示，第二半导体管芯106B’包括具有第一金属层M1(例如铜层)及第二金属层M2(例如镍层)的导电柱106b-4。换句话说，可通过图2A到图2C中阐述的方法制作半导体管芯106B’。举例来说，可使用清洁工艺(单晶片旋转清洁工艺)对第二金属层M2(镍层)的顶表面进行处理，且第二金属层M2(镍层)的顶表面具有第一粗糙度Rg1。
此外，在示例性实施例中，通过形成交替堆叠的介电层112-D、非平面晶种层SD2、导通孔部(第二通孔部112-Wx)及导电体部112-Cx来形成重布线结构RDS。在一些实施例中，非平面晶种层SD2共形地形成在介电层112-D之上，以具有位于不同水平面上的顶表面。在一些实施例中，导通孔部(第二通孔部112-Wx)设置在非平面晶种层SD2上且接触非平面晶种层SD2。在一些实施例中，导通孔部(第二通孔部112-Wx)的侧向尺寸LD2在积层方向DR1上从导通孔部(第二通孔部112-Wx)的第一端112-W1到导通孔部(第二通孔部112-Wx)的第二端112-W2增大。在某些实施例中，导电体部112-Cx可直接设置在导通孔部(第二通孔部112-Wx)上，且可与导通孔部(第二通孔部112-Wx)在相同的步骤中形成。
在一些实施例中，导通孔部(第二通孔部112-Wx)及导电体部112-Cx由与针对图1G到图1I中的导通孔部(第一通孔部112-Vx)及导电体部112-Bx所述的相同材料制成。然而，在某些实施例中，如图5中所示的导通孔部(第二通孔部112-Wx)及导电体部112-Cx可具有比图1G到图1I中所示的导通孔部(第一通孔部112-Vx)及导电体部112-Bx的线宽/间距大的线宽/间距。另外，由于导电体部112-Cx与导通孔部(第二通孔部112-Wx)是在同一步骤中制造，因此不对导通孔部(第二通孔部112-Wx)的表面执行通孔清洁工艺。在一些实施例中，导电体部112-Cx的顶表面112-C-TS也没有通过通孔清洁工艺进行清洁，且因此可具有粗糙度Rg5(与导电体部112-Bx相同)。
图6是根据本公开一些其他示例性实施例的封装结构的示意性剖视图。图6中所示的封装结构PS4类似于图5中所示的封装结构PS3，因此，相同的参考编号用于指代相同或相似的部件，且此处将省略其详细说明。实施例之间的不同之处在于，在图6中省略了贯穿绝缘层孔108。由于在封装结构PS4中省略了贯穿绝缘层孔108，因此也可省略放置在贯穿绝缘层孔108上的导电球118。类似于上述实施例，执行清洁工艺(单晶片旋转清洁工艺)以对导电柱(106a-4/106b-4)的表面及对准标记(106a-AM/106b-AM)的表面进行处理。因此，导电柱(106a-4/106b-4)的表面及对准标记(106a-AM/106b-AM)的表面可具有较小的粗糙度，且可防止形成在导电柱(106a-4/106b-4)及对准标记(106a-AM/106b-AM)上的通孔或连接结构的塌陷问题。
图7是根据本公开一些其他示例性实施例的封装结构的示意性剖视图。图7中所示的封装结构PS5类似于图1K中所示的封装结构PS1，且类似于图5中所示的封装结构PS3，因此，相同的参考编号用于指代相同或相似的部件，且此处将省略其详细说明。实施例之间的不同之处在于重布线结构RDS的设计。如图7中所示，重布线结构RDS可包括第一重布线层RDL1及堆叠在第一重布线层RDL1上的第二重布线层RDL2。
在一些实施例中，第一重布线层RDL1由介电层112-D、非平面晶种层SD2、第二通孔部112-Wx及导电体部112-Cx构成，如图5中所述。在某些实施例中，第二重布线层RDL2由介电层112-D、平面晶种层SD1、第一通孔部112-Vx及导电体部112-Bx构成，如图1A到图1K中所述。换句话说，在示例性实施例中，重布线结构RDS可包括具有不同设计的导通孔部(第一通孔部112-Vx/第二通孔部112-Wx)。在一些实施例中，第一重布线层RDL1的平面晶种层SD1与第二重布线层RDL2的非平面晶种层SD2是隔开的且彼此不会接触。在某些实施例中，平面晶种层SD1设置在第一通孔部112-Vx上且接触第一通孔部112-Vx，而第二通孔部112-Wx设置在非平面晶种层SD2上且接触非平面晶种层SD2。
类似于上述实施例，执行清洁工艺(单晶片旋转清洁工艺)以对导电柱(106a-4/106b-4)的表面、对准标记(106a-AM/106b-AM)的表面、贯穿绝缘层孔108的表面、及第一通孔部112-Vx的表面进行处理。因此，导电柱(106a-4/106b-4)的表面、对准标记(106a-AM/106b-AM)的表面、贯穿绝缘层孔108的表面、及第一通孔部112-Vx的表面可具有较小的粗糙度，且可防止形成在导电柱(106a-4/106b-4)、对准标记(106a-AM/106b-AM)、贯穿绝缘层孔108、及第一通孔部112-Vx上的通孔或连接结构的塌陷问题。在某些实施例中，所述多个导电柱(106a-4/106b-4)可具有粗糙度Rg1，对准标记(106a-AM/106b-AM)可具有粗糙度Rg2，贯穿绝缘层孔108可具有粗糙度Rg3，第一通孔部112-Vx可具有粗糙度Rg4，且导电体部(112-Bx/112-Cx)可具有粗糙度Rg5。在一个示例性实施例中，粗糙度Rg5大于粗糙度Rg1到Rg4，而粗糙度Rg1、粗糙度Rg2、粗糙度Rg3、粗糙度Rg4可实质上相等。
图8是根据本公开一些其他示例性实施例的封装结构的示意性剖视图。图8中所示的封装结构PS6类似于图7中所示的封装结构PS5，因此，相同的参考编号用于指代相同或相似的部件，且此处将省略其详细说明。实施例之间的不同之处在于，在图8中省略了贯穿绝缘层孔108。由于在封装结构PS6中省略了贯穿绝缘层孔108，因此也可省略放置在贯穿绝缘层孔108上的导电球118。类似于上述实施例，执行清洁工艺(单晶片旋转清洁工艺)以对导电柱(106a-4/106b-4)的表面、对准标记(106a-AM/106b-AM)的表面、及第一通孔部112-Vx的表面进行处理。因此，导电柱(106a-4/106b-4)的表面、对准标记(106a-AM/106b-AM)的表面、及第一通孔部112-Vx的表面可具有较小的粗糙度，且可防止形成在导电柱(106a-4/106b-4)、对准标记(106a-AM/106b-AM)、第一通孔部112-Vx上的通孔或连接结构的塌陷问题。
图9是根据本公开一些其他示例性实施例的封装结构的示意性剖视图。图9中所示的封装结构PS7类似于图8中所示的封装结构PS6，因此，相同的参考编号用于指代相同或相似的部件，且此处将省略其详细说明。实施例之间的不同之处在于重布线结构RDS的设计。在图8中所示的实施例中，通过形成具有第二通孔部112-Wx的第一重布线层RDL1接着形成具有第一通孔部112-Vx的第二重布线层RDL2来形成重布线结构RDS。然而，本公开并不仅限于此。
举例来说，如图9中所示，在一些实施例中，第一重布线层RDL1由介电层112-D、平面晶种层SD1、第一通孔部112-Vx及导电体部112-Bx构成，如图1A到图1K中所述。在某些实施例中，第二重布线层RDL2由介电层112-D、非平面晶种层SD2、第二通孔部112-Wx及导电体部112-Cx构成，如图5中所述。换句话说，通过形成具有第一通孔部112-Vx的第一重布线层RDL1接着形成具有第二通孔部112-Wx的第二重布线层RDL2来形成图9的重布线结构RDS。类似于上述实施例，执行清洁工艺(单晶片旋转清洁工艺)以对导电柱(106a-4/106b-4)的表面、对准标记(106a-AM/106b-AM)的表面、及第一通孔部112-Vx的表面进行处理。因此，导电柱(106a-4/106b-4)的表面、对准标记(106a-AM/106b-AM)的表面、及第一通孔部112-Vx的表面可具有较小的粗糙度，且可防止形成在导电柱(106a-4/106b-4)、对准标记(106a-AM/106b-AM)、第一通孔部112-Vx上的通孔或连接结构的塌陷问题。
在上述实施例中，使用指定的清洁溶液(第一溶液/第二溶液)执行至少一个清洁工艺(单晶片旋转清洁工艺)以对导电柱的表面、对准标记的表面、贯穿绝缘层孔的表面及导通孔部(第一通孔部)的表面进行清洁。这样一来，导电柱的表面、对准标记的表面、贯穿绝缘层孔的表面及导通孔部(第一通孔部)的表面可具有较小的粗糙度。由于表面更光滑，因此可防止形成在导电柱、贯穿绝缘层孔及导通孔部(第一通孔部)上的通孔或连接结构的塌陷问题。类似地，由于表面更光滑，因此对准标记将具有更好的对准轮廓。总体而言，封装结构的可靠度可得到改善。
根据本公开的一些实施例，提供一种封装结构，所述封装结构包括至少一个半导体管芯、绝缘密封体以及重布线结构。所述至少一个半导体管芯具有多个导电柱，其中所述多个导电柱中的顶表面具有第一粗糙度。所述绝缘密封体包封所述至少一个半导体管芯。所述重布线结构在积层方向上设置在所述绝缘密封体上且电连接到所述至少一个半导体管芯。所述重布线结构包括：多个导通孔部及多个导电体部，嵌置在介电层中，其中所述多个导电体部的顶表面具有第二粗糙度，且所述第二粗糙度大于所述第一粗糙度。
在一些实施例中，所述的封装结构，还包括贯穿绝缘层孔，所述贯穿绝缘层孔嵌置在所述绝缘密封体内且电连接到所述重布线结构，其中所述贯穿绝缘层孔的表面具有实质上等于所述第一粗糙度的粗糙度。在一些实施例中，其中所述多个导电柱中的所述至少一者包括铜层及镍层，且所述镍层具有所述第一粗糙度的所述顶表面。
根据本公开的一些其他实施例，阐述一种制作封装结构的方法。所述方法包括以下步骤。在载体上提供多个半导体管芯，其中所述多个半导体管芯包括多个导电柱。形成包封所述多个半导体管芯的绝缘密封体，其中所述绝缘密封体的顶表面与所述多个导电柱的顶表面实质上齐平。对所述多个导电柱执行清洁工艺，其中所述清洁工艺包括使用第一溶液对所述多个导电柱的所述顶表面进行清洁达20秒到80秒的第一清洁步骤，且其中在所述清洁工艺之后所述多个导电柱的所述顶表面具有第一粗糙度。在积层方向上在所述绝缘密封体上形成重布线结构，其中所述形成所述重布线结构的步骤包括形成嵌置在介电层中的多个导通孔部及多个导电体部，且其中所述多个导电体部的顶表面具有第二粗糙度，且所述第二粗糙度大于所述第一粗糙度。然后将所述载体剥离。
在一些实施例中，所述第一溶液的pH处于pH 0.5到pH 5的范围内。在一些实施例中，所述第一溶液是柠檬酸溶液。在一些实施例中，所述清洁工艺还包括执行第二清洁步骤，所述第二清洁步骤使用第二溶液对所述导电柱的所述顶表面进行清洁。在一些实施例中，所述第二溶液包括选自由乙酸、甲酸、柠檬酸、抗坏血酸、氢氟酸、氢氯酸、磷酸及硝酸组成的群组的至少一种酸。
在本公开的再一实施例中，阐述一种制作封装结构的方法。所述方法包括以下步骤。在载体上提供至少一个半导体管芯，其中所述至少一个半导体管芯包括多个导电柱。形成包封所述至少一个半导体管芯的绝缘密封体。通过移除所述绝缘密封体的部分以显露出所述多个导电柱的顶表面来执行平坦化工艺。在所述平坦化工艺之后对所述多个导电柱执行单晶片旋转清洁工艺，其中所述单晶片旋转清洁工艺包括在使所述载体旋转的同时将第一溶液滴加到所述多个导电柱的所述顶表面上达20秒到80秒以对所述多个导电柱的所述顶表面进行清洁。在所述绝缘密封体上形成重布线结构，其中所述重布线结构通过以下步骤形成。形成交替堆叠的多个导电体部、多个第一通孔部及多个介电层，其中所述多个第一通孔部形成有从第一通孔部的第一端到第一通孔部的第二端保持恒定的侧向尺寸，且在形成所述多个第一通孔部中的每一者之后对所述第二端的表面执行通孔清洁工艺，所述通孔清洁工艺包括在使所述载体旋转的同时将所述第一溶液滴加到所述第一通孔部的所述第二端的所述表面上达20秒到80秒以对所述第二端的所述表面进行清洁。然后将所述载体剥离。
在一些实施例中，所述第一溶液包括选自由乙酸、甲酸、柠檬酸、抗坏血酸、氢氟酸、氢氯酸、磷酸及硝酸组成的群组的至少一种酸。在一些实施例中，所述第一溶液包括选自由乙醇胺、羟乙基乙二胺、氢氧化铵及氯化铵组成的群组的至少一种胺系溶液。在一些实施例中，所述单晶片旋转清洁工艺还包括：在使所述载体旋转的同时将第二溶液滴加到所述多个导电柱的所述顶表面上达20秒到80秒以对所述多个导电柱的所述顶表面进行清洁。在一些实施例中，所述第二溶液包括选自由乙酸、甲酸、柠檬酸、抗坏血酸、氢氟酸、氢氯酸、磷酸及硝酸组成的群组的至少一种酸。
以上概述了若干实施例的特征，以使所属领域中的技术人员可更好地理解本公开的各个方面。所属领域中的技术人员应理解，他们可容易地使用本公开作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的和/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到，这些等效构造并不背离本公开的精神及范围，而且他们可在不背离本公开的精神及范围的条件下在本文中作出各种改变、代替及变更。

Claims (10)

1.一种封装结构，包括：
至少一个半导体管芯，具有多个导电柱，其中所述多个导电柱中的至少一者的顶表面具有第一粗糙度；
绝缘密封体，包封所述至少一个半导体管芯；
重布线结构，在积层方向上设置在所述绝缘密封体上，其中所述重布线结构电连接到所述至少一个半导体管芯且包括：
多个导通孔部及多个导电体部，嵌置在介电层中，其中所述多个导电体部的顶表面具有第二粗糙度，且所述第二粗糙度大于所述第一粗糙度。
2.根据权利要求1所述的封装结构，其中所述多个导通孔部包括第一通孔部，且所述第一通孔部的侧向尺寸在所述积层方向上从所述第一通孔部的第一端到所述第一通孔部的第二端保持恒定，且所述第一通孔部的所述第二端的表面具有第三粗糙度，且所述第三粗糙度小于所述第二粗糙度。
3.根据权利要求2所述的封装结构，其中所述多个导通孔部还包括第二通孔部，且所述第二通孔部的侧向尺寸在所述积层方向上从所述第二通孔部的第一端到所述第二通孔部的第二端增大。
4.根据权利要求3所述的封装结构，其中所述重布线结构还包括彼此隔开的多个平面晶种层与多个非平面晶种层，所述多个平面晶种层设置在所述第一通孔部上且接触所述第一通孔部，且所述第二通孔部设置在所述多个非平面晶种层上且接触所述多个非平面晶种层。
5.一种制作封装结构的方法，包括：
在载体上提供至少一个半导体管芯，其中所述至少一个半导体管芯包括导电柱；
形成包封所述至少一个半导体管芯的绝缘密封体，并将所述绝缘密封体平坦化，以显露出所述导电柱的顶表面；
对所述导电柱执行清洁工艺，其中所述清洁工艺包括使用第一溶液对所述导电柱的所述顶表面进行清洁的第一清洁步骤，且其中在所述清洁工艺之后所述导电柱的所述顶表面具有第一粗糙度；
在积层方向上在所述绝缘密封体上形成重布线结构，其中形成所述重布线结构的步骤包括形成嵌置在介电层中的多个导通孔部及多个导电体部，且其中所述多个导电体部的顶表面具有第二粗糙度，且所述第二粗糙度大于所述第一粗糙度；以及
将所述载体剥离。
6.根据权利要求5所述的制作封装结构的方法，其中所述第一溶液包括选自由乙酸、甲酸、柠檬酸、抗坏血酸、氢氟酸、氢氯酸、磷酸及硝酸组成的群组的至少一种酸。
7.根据权利要求5所述的制作封装结构的方法，其中所述第一溶液包括选自由乙醇胺、羟乙基乙二胺、氢氧化铵及氯化铵组成的群组的至少一种胺系溶液。
8.根据权利要求5所述的制作封装结构的方法，其中形成所述导通孔部的步骤包括：形成第一通孔部，所述第一通孔部具有在所述积层方向上从所述第一通孔部的第一端到所述第一通孔部的第二端保持恒定的侧向尺寸，并执行通孔清洁工艺，所述通孔清洁工艺使用所述第一溶液对所述第一通孔部的所述第二端的表面进行清洁，且其中在所述通孔清洁工艺之后所述第一通孔部的所述第二端的所述表面具有第三粗糙度，且所述第三粗糙度小于所述第二粗糙度。
9.一种制作封装结构的方法，包括：
在载体上提供至少一个半导体管芯，其中所述至少一个半导体管芯包括多个导电柱；
形成包封所述至少一个半导体管芯的绝缘密封体；
执行平坦化工艺以移除所述绝缘密封体的部分并且显露出所述多个导电柱的顶表面；
在所述平坦化工艺之后对所述多个导电柱执行单晶片旋转清洁工艺，其中所述单晶片旋转清洁工艺包括在使所述载体旋转的同时将第一溶液滴加到所述多个导电柱的所述顶表面上达20秒到80秒以对所述多个导电柱的所述顶表面进行清洁；以及
在所述绝缘密封体上形成重布线结构，其中形成所述重布线结构的步骤包括：
形成交替堆叠的多个导电体部、多个第一通孔部及多个介电层，其中所述多个第一通孔部形成有从所述多个第一通孔部的第一端到所述多个第一通孔部的第二端保持恒定的侧向尺寸，且在形成所述多个第一通孔部中的每一者之后对所述第二端的表面执行通孔清洁工艺，所述通孔清洁工艺包括在使所述载体旋转的同时将所述第一溶液滴加到所述第一通孔部的所述第二端的所述表面上达20秒到80秒以对所述第二端的所述表面进行清洁；以及
将所述载体剥离。
10.根据权利要求9所述的制作封装结构的方法，还包括：形成与所述多个导电体部及所述多个介电层交替堆叠的多个第二通孔部，其中所述多个第二通孔部形成有从所述多个第二通孔部的第一端到所述多个第二通孔部的第二端增大的侧向尺寸。
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