WO2023245761A1 - 半导体结构的处理方法以及字线结构的形成方法 - Google Patents

半导体结构的处理方法以及字线结构的形成方法 Download PDF

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WO2023245761A1
WO2023245761A1 PCT/CN2022/105173 CN2022105173W WO2023245761A1 WO 2023245761 A1 WO2023245761 A1 WO 2023245761A1 CN 2022105173 W CN2022105173 W CN 2022105173W WO 2023245761 A1 WO2023245761 A1 WO 2023245761A1
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metal layer
semiconductor structure
layer
top surface
metal
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PCT/CN2022/105173
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English (en)
French (fr)
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吴润平
张俊
马丽
金泰均
朴淳秉
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长鑫存储技术有限公司
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Priority to US17/949,278 priority Critical patent/US20230022780A1/en
Publication of WO2023245761A1 publication Critical patent/WO2023245761A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B08—CLEANING
    • B08B—CLEANING IN GENERAL; PREVENTION OF FOULING IN GENERAL
    • B08B3/00—Cleaning by methods involving the use or presence of liquid or steam
    • B08B3/04—Cleaning involving contact with liquid
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B08—CLEANING
    • B08B—CLEANING IN GENERAL; PREVENTION OF FOULING IN GENERAL
    • B08B3/00—Cleaning by methods involving the use or presence of liquid or steam
    • B08B3/04—Cleaning involving contact with liquid
    • B08B3/041—Cleaning travelling work
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B08—CLEANING
    • B08B—CLEANING IN GENERAL; PREVENTION OF FOULING IN GENERAL
    • B08B3/00—Cleaning by methods involving the use or presence of liquid or steam
    • B08B3/04—Cleaning involving contact with liquid
    • B08B3/08—Cleaning involving contact with liquid the liquid having chemical or dissolving effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing, and in particular, to a method of processing a semiconductor structure and a method of forming a word line structure.
  • Buried word line (Buried Word line, BWL, also called buried gate) provides a new option for increasing the integration density of semiconductor devices.
  • Buried word lines refer to burying word lines inside the semiconductor substrate, which can significantly reduce the parasitic capacitance between the word line and the bit line and greatly improve the reliability of the voltage reading operation of the semiconductor device.
  • embodiments of the present disclosure provide a processing method and a processing device for a semiconductor structure.
  • a method for processing a semiconductor structure including:
  • the semiconductor structure including a groove and a metal layer located in the groove, the edge position of the top surface of the metal layer being higher than the center position of the top surface of the metal layer;
  • each metal surface planarization process in the at least one metal surface planarization process includes:
  • the semiconductor structure is cleaned using a second reagent.
  • the first reagent includes an acidic reagent and the second reagent includes at least one of a basic reagent and a neutral reagent.
  • the first reagent includes at least one of SC2 solution, sulfuric acid and hydrogen peroxide mixed solution, and hydrochloric acid and hydrogen peroxide mixed solution.
  • the second reagent includes at least one of SC1 solution, deionized water solution, ammonia water, and hydrogen peroxide.
  • the ratio of sulfuric acid to hydrogen peroxide in the mixed solution of sulfuric acid and hydrogen peroxide ranges from 5:1 to 8:1.
  • the at least one metal surface planarization process includes 4 to 8 metal surface planarization processes.
  • the time for etching the top surface of the metal layer using the first reagent ranges from 8 seconds to 50 seconds.
  • the time range for cleaning the semiconductor structure using the second reagent ranges from 25s to 35s.
  • the at least one metal surface planarization process includes multiple metal surface planarization processes, and the total time of etching the top surface of the metal layer in the multiple metal surface planarization processes is The range is 45s ⁇ 90s.
  • the material of the metal layer includes at least one of titanium nitride, molybdenum, or tungsten.
  • the semiconductor structure rotates at a rotation speed ranging from 500 rpm to 800 rpm.
  • the semiconductor structure rotates at a first rotation speed
  • the rotation speed of the semiconductor structure is the second rotation speed
  • the first rotational speed is smaller than the second rotational speed.
  • the semiconductor structure rotates at a first rotation speed
  • the rotation speed of the semiconductor structure is the second rotation speed
  • the first rotational speed is equal to the second rotational speed.
  • the metal layer includes gaps; after at least one metal surface planarization process, the top surface of the metal layer is located above the gaps.
  • a method for forming a word line structure including:
  • the metal layer is processed using the semiconductor structure processing method described in any of the above embodiments.
  • a polysilicon layer is formed on the metal layer, the polysilicon layer is located in the groove; and an isolation layer is formed on the polysilicon layer.
  • the semiconductor structure is rotated and the metal surface planarization process is performed on the semiconductor structure at least once, so that the first reagent impacts the edge position of the top surface of the metal layer under the action of centrifugal force, The residual metal at the edge of the top surface of the metal layer of the semiconductor structure is removed, so that the top surface of the metal layer after treatment is smoother than the top surface of the metal layer before treatment.
  • Figure 1 is a schematic flowchart of a method for processing a semiconductor structure provided by an embodiment of the present disclosure
  • FIGS. 2a to 2g are schematic structural diagrams of the semiconductor structure during processing according to embodiments of the present disclosure.
  • FIG. 3 is a schematic flowchart of a method for forming a word line structure provided by an embodiment of the present disclosure.
  • 1-semiconductor structure 10-substrate; 100-groove; 110-metal layer; 110'-metal layer pre-layer; 111-top surface; 112-gap; 120-dielectric material layer; 130-polysilicon layer; 140- Isolation layer.
  • the conductive materials such as titanium nitride, etc.
  • the conductive materials need to be etched back to a certain extent.
  • the inventor of the present disclosure found that during the etching back process of the titanium nitride (TiN) metal layer in the word line groove, due to the inconsistent etching rate of the center and edge of the metal layer, the etching rate will be reduced.
  • the surface of the etched metal layer is uneven, forming a "rabbit ear" topography (that is, a topography with a low center and high edges, see Figure 2d), which in turn leads to the threshold voltage (Vt) and gate-induced drain leakage current (Gate -Induced Drain Leakage, GIDL) is higher.
  • Vt threshold voltage
  • GIDL gate-induced drain leakage current
  • inventions of the present disclosure provide a semiconductor structure processing method. Please refer to Figure 1 for details. As shown in the figure, the method includes the following steps:
  • Step 101 Provide a semiconductor structure, the semiconductor structure including a groove and a metal layer located in the groove, the edge position of the top surface of the metal layer being higher than the center position of the top surface of the metal layer;
  • Step 102 Put the semiconductor structure in a rotating state; and perform at least one metal surface planarization process on the semiconductor structure, so that the top surface of the metal layer after treatment is smaller than the metal layer before treatment.
  • the top surface is smoother; wherein each metal surface planarization process in the at least one metal surface planarization process includes: using a first reagent to etch the top surface of the metal layer; and, The semiconductor structure is cleaned using a second reagent.
  • FIGS. 2a to 2g are schematic structural diagrams of a semiconductor structure during processing according to embodiments of the present disclosure.
  • step 101 is performed to provide a semiconductor structure 1 , which includes a groove 100 and a metal layer 110 located in the groove.
  • the edge of the top surface 111 of the metal layer 110 The position is higher than the center position of the top surface 111 of the metal layer 110 .
  • a semiconductor structure 1 which includes a substrate 10 .
  • a groove 100 may be formed in the substrate 10 .
  • the substrate 10 may be a wafer in a semiconductor manufacturing process stage.
  • the substrate 10 may be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, an SOI (Silicon On Insulator) substrate or a GOI (Germanium on Insulator, Germanium On Insulator) substrate, etc., can also be a substrate including other element semiconductors or compound semiconductors, such as glass substrates or III-V compound substrates (such as gallium nitride substrates or gallium arsenide substrates, etc.), It can also be a stacked structure, such as Si/SiGe, etc., or other epitaxial structures, such as SGOI (silicon germanium on insulator), etc.
  • the substrate may be a silicon substrate.
  • a mask layer (not shown in the figure) can first be grown on the upper surface of the substrate, and then the mask layer can be patterned to display the groove pattern to be etched on the mask layer.
  • the mask layer is patterned through a photolithography process.
  • the mask layer may be a photoresist mask or a hard mask patterned based on a photolithography mask; when the mask layer is a photoresist mask, the mask layer may be exposed, developed and removed. and other steps to pattern the mask layer. Then, grooves with a certain depth are etched according to the groove pattern to be etched.
  • a dry etching process may be used to form the groove 100 .
  • a dielectric material layer 120 is formed on the bottom surface and sidewalls of the groove 100 and the surface of the substrate 10 .
  • the dielectric material layer 120 can be formed using one or more thin film deposition processes; for example, the deposition processes include but are not limited to chemical vapor deposition (Chemical Vapor Deposition, CVD) process, plasma enhanced chemical vapor deposition Deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) process, Atomic Layer Deposition (ALD) process or a combination thereof.
  • CVD chemical Vapor Deposition
  • PECVD plasma enhanced chemical vapor deposition Deposition
  • ALD Atomic Layer Deposition
  • the materials of the dielectric material layer 120 include but are not limited to oxides, nitrides, metal oxides, oxynitrides, etc.; optionally, the materials of the dielectric material layer 120 include high-K dielectric materials, and the high-K dielectric The material may contain the element hafnium.
  • the high-K dielectric material may include but is not limited to aluminum oxide (Al 2 O 3 ), tantalum oxide (Ta 2 O 3 ), titanium oxide (TiO 2 ), yttrium oxide (Y 2 O 3 ), zirconium oxide (ZrO 2 ), zirconium silicon oxide ( ZrSix O y ), hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSi x O y ), hafnium silicon oxynitride (HfSiON), hafnium Zirconate (HfZrO 4 ), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), hafnium aluminum oxide (HfAl x O y ) and/or praseodymium oxide (Pr 2 O 3 ), etc.
  • Al 2 O 3 aluminum oxide
  • Ta 2 O 3 tanta
  • the dielectric material layer is located between the substrate and a subsequently formed metal layer.
  • a metal material is deposited in the groove 100 to form a metal layer pre-layer 110'.
  • the metal layer pre-layer 110' is not only formed on the sidewalls and bottom of the dielectric material layer 120, but also formed on the dielectric material layer 120 on the surface of the substrate 10, and the metal layer The pre-layer 110' can fill the groove 100 completely.
  • the metal layer pre-layer 110' can be formed using one or more thin film deposition processes; for example, the deposition processes include but are not limited to chemical vapor deposition (Chemical Vapor Deposition, CVD) process, plasma enhanced Chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) process, atomic layer deposition (Atomic Layer Deposition, ALD) process or a combination thereof.
  • the deposition processes include but are not limited to chemical vapor deposition (Chemical Vapor Deposition, CVD) process, plasma enhanced Chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) process, atomic layer deposition (Atomic Layer Deposition, ALD) process or a combination thereof.
  • the metal layer pre-layer 110' is etched to form a metal layer 110.
  • all of the metal layer pre-layer 110' located on the surface of the substrate 10 and part of the metal layer pre-layer 110' located in the groove 100 can be etched away to form a metal layer. 110.
  • the etching process is a plasma etching process.
  • the plasma etching process includes at least one of an etching process such as reactive ion etching (RIE) or high density plasma etching (High Density Plasma, HDP).
  • RIE reactive ion etching
  • HDP High Density Plasma
  • voids 112 may be formed in the metal layer pre-layer 110' due to the process.
  • the existence of the gap 112 may also cause metal residues at the edge of the top surface of the metal layer during the etching process to form the metal layer.
  • metal remains at the edge of the top surface of the metal layer, so that the edge of the top surface 111 of the metal layer 110 is higher than the center of the top surface 111 of the metal layer 110 , forming the following The “rabbit ears” shape shown in Figure 2d.
  • the "rabbit ear” shaped surface of the metal layer will affect the performance of the device, so the "rabbit ear” shaped surface of the metal layer must be processed to make it smooth.
  • step 102 is performed to put the semiconductor structure 1 in a rotating state; and, perform at least one metal surface planarization process on the semiconductor structure 1, so that the processed metal layer 110
  • the top surface 111 is smoother than the top surface 111 of the metal layer 110 before treatment; wherein each metal surface planarization process in the at least one metal surface planarization process includes: using a first reagent
  • the top surface 111 of the metal layer 110 is etched; and a second reagent is used to clean the semiconductor structure 1 .
  • the semiconductor structure 1 has undergone at least one metal surface planarization process, so that the top surface 111 of the metal layer 110 of the semiconductor structure 1 shown in Figure 2e Compared with the semiconductor structure 1 shown in FIG. 2d, the top surface 111 of the metal layer 110 is smoother.
  • the angle between the “rabbit ear” shape of the edge position of the top surface 111 of the metal layer 110 of the semiconductor structure 1 shown in FIG. 2d and the side wall of the groove 100 is ⁇ 1, and the edge position of the top surface 111 is higher than the middle position.
  • the height is h1; the angle between the “rabbit ear” shape of the edge position of the top surface 111 of the metal layer 110 of the semiconductor structure 1 shown in Figure 2e and the side wall of the groove 100 is ⁇ 2, and the edge position of the top surface 111 is high
  • the height out of the middle position is h2, where ⁇ 1 is smaller than ⁇ 2 and h1 is larger than h2.
  • the top surface 111 of the metal layer 110 of the semiconductor structure 1 undergoes at least one metal surface planarization process, the top surface 111 finally reaches a substantially flat state.
  • the material of the metal layer 110 includes at least one of titanium nitride, molybdenum or tungsten. . It can be understood that the material of the metal layer provided in the embodiment of the present disclosure is only used as a lower and feasible implementation mode in the embodiment of the present disclosure and does not constitute a limitation on the present disclosure. The material of the metal layer is also Other materials available.
  • the top surface 111 of the metal layer 110 is located above the gap 112 to ensure that the top surface 111 of the metal layer 110 finally reaches a substantially flat state.
  • the rotation speed of the semiconductor structure ranges from 500 rpm to 800 rpm.
  • the rotation speed of the semiconductor structure is within this range, which can ensure that the cleaning agent achieves the best effect when etching the residual metal at the edge of the top surface of the metal layer. Otherwise, if the rotation speed is too fast, the cleaning agent will not interact with the metal. The residual metal on the top surface of the layer will be thrown out. If the rotation speed is too slow, the cleaning agent will not fully contact the residual metal, and it will not be able to effectively remove the residual metal.
  • the rotation speed of the semiconductor structure is the first rotation speed; while using the second reagent to etch the semiconductor structure During the cleaning process, the semiconductor structure rotates at a second rotation speed; wherein the first rotation speed is smaller than the second rotation speed.
  • the rotation speed of the semiconductor structure is lower. In this way, the first reagent can be in full contact with the residual metal and better play an oxidative corrosion role; using the second reagent is used to etch the top surface of the metal layer.
  • the reagent cleans the semiconductor structure, the semiconductor structure rotates at a higher speed. In this way, the centrifugal force is greater, and the second reagent can better flush the semiconductor structure, so that the oxidation reaction product between the first reagent and the residual metal is flushed.
  • the rotation speed of the semiconductor structure is the first rotation speed; while using the second reagent to etch the semiconductor structure During the cleaning process, the semiconductor structure rotates at a second rotation speed; wherein the first rotation speed is equal to the second rotation speed.
  • the rotation speed when using the first reagent to etch the top surface of the metal layer is the same as the rotation speed when using the second reagent to clean the semiconductor structure. In this way, the entire cleaning process does not need to adjust the rotation speed, and only needs to maintain one rotation speed. , can save costs more and the process is simpler.
  • the first reagent includes an acidic reagent
  • the second reagent includes at least one of an alkaline reagent and a neutral reagent.
  • Acidic reagents can etch the top surface of the metal layer of the semiconductor structure due to its oxidative corrosion effect, while alkaline reagents and neutral reagents can rinse the semiconductor structure to remove the Residual acidic reagents and residues after etching.
  • the alkaline reagent can also neutralize the residual acidic reagent.
  • the first reagent includes SC2 solution (a mixed solution of deionized water, HCl and H 2 O 2 ), a mixed solution of sulfuric acid and hydrogen peroxide (SPM), and a mixed solution of hydrochloric acid and hydrogen peroxide (HPM).
  • SC2 solution a mixed solution of deionized water, HCl and H 2 O 2
  • SPM sulfuric acid and hydrogen peroxide
  • HPM hydrochloric acid and hydrogen peroxide
  • At least one of the second reagents includes at least one of SC1 solution (a mixed solution of deionized water, NH 4 OH and H 2 O 2 ), deionized water solution, ammonia and hydrogen peroxide.
  • SC2 solution, sulfuric acid and hydrogen peroxide mixed solution and hydrochloric acid and hydrogen peroxide mixed solution can corrode the remaining metal at the edge of the top surface of the metal layer through oxidation.
  • SC1 solution, deionized water solution, ammonia and hydrogen peroxide can rinse the sulfuric acid and hydrogen peroxide mixed solution and The residue after metal oxidation makes the surface of the metal layer smooth.
  • the materials of the first reagent and the second reagent provided in the embodiments of the present disclosure are only used as a feasible implementation method in the embodiments of the present disclosure and do not constitute a limitation on the present disclosure.
  • the first reagent and the second reagent can be selected according to the material of the metal layer and the like.
  • the ratio of sulfuric acid to hydrogen peroxide in the mixed solution of sulfuric acid and hydrogen peroxide ranges from 5:1 to 8:1.
  • the ratio of sulfuric acid and hydrogen peroxide in the mixed solution of sulfuric acid and hydrogen peroxide is within this range, the mixed solution of sulfuric acid and hydrogen peroxide can better oxidize and corrode the residual metal.
  • the mass fraction of sulfuric acid in the mixed solution of sulfuric acid and hydrogen peroxide is 96%, and the mass fraction of hydrogen peroxide is 30%.
  • the SC2 solution, sulfuric acid and hydrogen peroxide mixed solution, and hydrochloric acid and hydrogen peroxide mixed solution can be used.
  • the mixed solution with hydrogen peroxide and the mixed solution of hydrochloric acid and hydrogen peroxide are maintained at the preset temperature, which can ensure a high etching speed during the etching process.
  • one or more of SC2 solution, sulfuric acid and hydrogen peroxide mixed solution, and hydrochloric acid and hydrogen peroxide mixed solution are used to remove the edge position of the top surface of the metal layer
  • SC2 solution, sulfuric acid and hydrogen peroxide mixed solution, and hydrochloric acid and hydrogen peroxide mixed solution are used to remove the edge position of the top surface of the metal layer
  • the contact between the etching liquid and the surface of the metal layer is more uniform than the contact between the etching gas and the surface of the metal layer.
  • the metal layer is etched with one or more of the solution, a mixed solution of sulfuric acid and hydrogen peroxide, and a mixed solution of hydrochloric acid and hydrogen peroxide, and the surface after removing the residual metal has a higher flatness.
  • the at least one metal surface planarization treatment includes 4 to 8 metal surface planarization treatments.
  • the number of cycles is within this range, the effect of removing residual metal at the edge of the top surface of the metal layer is best. Otherwise, if the number of cycles is too few, the remaining metal will not be completely removed, and if the number of cycles is too many, too much metal will be removed. The part within the layer other than the residual metal affects the performance of the device.
  • a mixed solution of sulfuric acid and hydrogen peroxide is used as the first reagent, and deionized water is used as the second reagent to perform planarization treatment on the metal layer.
  • the table below shows the comparison of the number and time of metal surface planarization treatments and the treatment effects.
  • E/A in the table represents the thickness of the metal layer that is etched away during the metal surface planarization process. The larger the value of E/A, the thickness of the metal layer that is etched away. The larger the value of E/A, the smaller the thickness of the etched metal layer. 600:80, 600:90 and 600:100 in the table all refer to the ratio coefficient of sulfuric acid and hydrogen peroxide in the mixed solution of sulfuric acid and hydrogen peroxide.
  • the time range for etching the top surface of the metal layer using the first reagent ranges from 8 seconds to 50 seconds.
  • the at least one metal surface planarization process includes multiple metal surface planarization processes, and the total time of etching the top surface of the metal layer in the multiple metal surface planarization processes is The range is 45s ⁇ 90s.
  • the total time for etching the top surface of the metal layer in the metal surface planarization process is within this range to ensure the best etching effect on the top surface of the metal layer. On the one hand, it reduces the metal layer from being etched away.
  • the thickness improves the flatness of the surface of the etched metal layer.
  • the time range for cleaning the semiconductor structure using the second reagent ranges from 25 s to 35 s.
  • the best cleaning effect can be achieved. Otherwise, if the time is too short, the cleaning will be insufficient and there may be remaining residues that have not been rinsed. If the time is too long, the cleaning time will be insufficient. If it takes too long, it will waste cleaning agent and increase costs.
  • a polysilicon layer 130 is formed on the top surface 111 of the metal layer 110 .
  • the polysilicon layer 130 may be formed using one or more thin film deposition processes; for example, the deposition processes include but are not limited to chemical vapor deposition (Chemical Vapor Deposition, CVD) process, plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) process, atomic layer deposition (Atomic Layer Deposition, ALD) process or a combination thereof.
  • the deposition processes include but are not limited to chemical vapor deposition (Chemical Vapor Deposition, CVD) process, plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) process, atomic layer deposition (Atomic Layer Deposition, ALD) process or a combination thereof.
  • an isolation layer 140 is formed on the polysilicon layer 130 .
  • the isolation layer 140 may be made of silicon nitride.
  • the isolation layer 140 can be formed using one or more thin film deposition processes; for example, the deposition processes include but are not limited to chemical vapor deposition (Chemical Vapor Deposition, CVD) process, plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) process, atomic layer deposition (Atomic Layer Deposition, ALD) process or a combination thereof.
  • the deposition processes include but are not limited to chemical vapor deposition (Chemical Vapor Deposition, CVD) process, plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) process, atomic layer deposition (Atomic Layer Deposition, ALD) process or a combination thereof.
  • the semiconductor structure is rotated and the metal surface planarization process is performed on the semiconductor structure at least once, so that the first reagent impacts the edge position of the top surface of the metal layer under the action of centrifugal force, The residual metal at the edge of the top surface of the metal layer of the semiconductor structure is removed, so that the top surface of the metal layer after treatment is smoother than the top surface of the metal layer before treatment.
  • Embodiments of the present disclosure provide a method for forming a word line structure. Please refer to Figure 3 for details. As shown in the figure, the method includes the following steps:
  • Step 301 Provide a substrate
  • Step 302 Form a groove in the substrate, and form a dielectric material layer on the bottom surface and side walls of the groove and the surface of the substrate;
  • Step 303 Form a metal layer pre-layer on the dielectric material layer
  • Step 304 Etch the metal layer pre-layer to form a metal layer located in the groove; the edge position of the top surface of the metal layer is higher than the center position of the top surface of the metal layer;
  • Step 305 Use the semiconductor structure processing method described in any of the above embodiments to process the metal layer.
  • FIG. 2a the structural schematic diagram of the word line structure during the formation process
  • FIG. 2g the structural schematic diagram of the word line structure during the formation process
  • step 301 is performed to provide a substrate 10.
  • the substrate 10 may be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, an SOI (Silicon On Insulator) substrate or a GOI (Germanium on Insulator, Germanium On Insulator) substrate, etc., can also be a substrate including other element semiconductors or compound semiconductors, such as glass substrates or III-V compound substrates (such as gallium nitride substrates or gallium arsenide substrates, etc.), It can also be a stacked structure, such as Si/SiGe, etc., or other epitaxial structures, such as SGOI (silicon germanium on insulator), etc.
  • the substrate may be a silicon substrate.
  • step 302 is performed to form a groove 100 in the substrate 10 , and form a dielectric material layer 120 on the bottom surface and sidewalls of the groove 100 and the surface of the substrate 10 .
  • a mask layer (not shown in the figure) can first be grown on the upper surface of the substrate, and then the mask layer can be patterned to display the groove pattern to be etched on the mask layer.
  • the mask layer is patterned through a photolithography process.
  • the mask layer may be a photoresist mask or a hard mask patterned based on a photolithography mask; when the mask layer is a photoresist mask, the mask layer may be exposed, developed and removed. and other steps to pattern the mask layer. Then, grooves with a certain depth are etched according to the groove pattern to be etched.
  • a dry etching process may be used to form the groove 100 .
  • the dielectric material layer 120 can be formed using one or more thin film deposition processes; for example, the deposition processes include but are not limited to chemical vapor deposition (Chemical Vapor Deposition, CVD) process, plasma enhanced chemical vapor deposition process. Deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) process, Atomic Layer Deposition (ALD) process or a combination thereof.
  • CVD chemical Vapor Deposition
  • PECVD plasma enhanced chemical vapor deposition
  • ALD Atomic Layer Deposition
  • the materials of the dielectric material layer 120 include but are not limited to oxides, nitrides, metal oxides, oxynitrides, etc.; optionally, the materials of the dielectric material layer 120 include high-K dielectric materials, and the high-K dielectric The material may contain the element hafnium.
  • the high-K dielectric material may include but is not limited to aluminum oxide (Al 2 O 3 ), tantalum oxide (Ta 2 O 3 ), titanium oxide (TiO 2 ), yttrium oxide (Y 2 O 3 ), zirconium oxide (ZrO 2 ), zirconium silicon oxide ( ZrSix O y ), hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSi x O y ), hafnium silicon oxynitride (HfSiON), hafnium Zirconate (HfZrO 4 ), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), hafnium aluminum oxide (HfAl x O y ) and/or praseodymium oxide (Pr 2 O 3 ), etc.
  • Al 2 O 3 aluminum oxide
  • Ta 2 O 3 tanta
  • the dielectric material layer is located between the substrate and a subsequently formed metal layer.
  • a metal layer pre-layer 110' is formed on the dielectric material layer 120.
  • the metal layer pre-layer 110' is not only formed on the sidewalls and bottom of the dielectric material layer 120, but also formed on the dielectric material layer 120 on the surface of the substrate 10, and the metal layer The pre-layer 110' can fill the groove 100 completely.
  • the metal layer pre-layer 110' can be formed using one or more thin film deposition processes; for example, the deposition processes include but are not limited to chemical vapor deposition (Chemical Vapor Deposition, CVD) process, plasma enhanced Chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) process, atomic layer deposition (Atomic Layer Deposition, ALD) process or a combination thereof.
  • the deposition processes include but are not limited to chemical vapor deposition (Chemical Vapor Deposition, CVD) process, plasma enhanced Chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) process, atomic layer deposition (Atomic Layer Deposition, ALD) process or a combination thereof.
  • step 304 is performed to etch the metal layer pre-layer 110' to form a metal layer 110 located in the groove; the edge position of the top surface 111 of the metal layer 110 is higher than the metal layer 110. The center position of the top surface 111 of layer 110 .
  • all of the metal layer pre-layer 110' located on the surface of the substrate 10 and part of the metal layer pre-layer 110' located in the groove 100 can be etched away to form a metal layer. 110.
  • the etching process is a plasma etching process.
  • the plasma etching process includes at least one of an etching process such as reactive ion etching (RIE) or high density plasma etching (High Density Plasma, HDP).
  • RIE reactive ion etching
  • HDP High Density Plasma
  • voids 112 may be formed in the metal layer pre-layer 110' due to the process.
  • the existence of the gap 112 may also cause metal residues at the edge of the top surface of the metal layer during the etching process to form the metal layer.
  • metal remains at the edge of the top surface of the metal layer, so that the edge of the top surface 111 of the metal layer 110 is higher than the center of the top surface 111 of the metal layer 110 , forming the following The “rabbit ears” shape shown in Figure 2d.
  • the "rabbit ear” shaped surface of the metal layer will affect the performance of the device, so the "rabbit ear” shaped surface of the metal layer must be processed to make it smooth.
  • step 305 is performed to process the metal layer using the semiconductor structure processing method described in any of the above embodiments.
  • the method further includes: forming a polysilicon layer 130 on the metal layer 110, the polysilicon layer 130 being located in the groove 100; and forming an isolation layer 140 on the polysilicon layer 130.
  • the polysilicon layer 130 is formed on the top surface 111 of the metal layer 110.
  • one or more thin film deposition processes may be used to form a polysilicon material layer, and then be etched back to form the polysilicon layer 130; for example, the deposition process includes but is not limited to chemical vapor deposition (Chemical Vapor Deposition). Vapor Deposition (CVD) process, Plasma Enhanced Chemical Vapor Deposition (PECVD) process, Atomic Layer Deposition (ALD) process or a combination thereof.
  • CVD chemical vapor deposition
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • ALD Atomic Layer Deposition
  • an isolation layer 140 is formed on the polysilicon layer 130 .
  • the isolation layer 140 may be made of silicon nitride.
  • the isolation layer 140 can be formed using one or more thin film deposition processes; for example, the deposition processes include but are not limited to chemical vapor deposition (Chemical Vapor Deposition, CVD) process, plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) process, atomic layer deposition (Atomic Layer Deposition, ALD) process or a combination thereof.
  • the deposition processes include but are not limited to chemical vapor deposition (Chemical Vapor Deposition, CVD) process, plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) process, atomic layer deposition (Atomic Layer Deposition, ALD) process or a combination thereof.
  • the above word line structure is a buried word line structure, which may include a dielectric material layer, a metal layer, a polysilicon layer and an isolation layer formed in the groove.
  • the semiconductor structure is rotated and the metal surface planarization process is performed on the semiconductor structure at least once, so that the first reagent impacts the edge position of the top surface of the metal layer under the action of centrifugal force, The residual metal at the edge of the top surface of the metal layer of the semiconductor structure is removed, so that the top surface of the metal layer after treatment is smoother than the top surface of the metal layer before treatment.

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Abstract

本公开实施例公开了一种半导体结构的处理方法以及字线结构的形成方法，其中，所述半导体结构的处理方法，包括：提供半导体结构，所述半导体结构包括凹槽以及位于所述凹槽中的金属层，所述金属层的顶表面的边缘位置高于所述金属层的所述顶表面的中心位置；使所述半导体结构处于旋转状态；以及，对所述半导体结构进行至少一次金属表面平坦化处理，以使处理后的所述金属层的所述顶表面比处理前的所述金属层的所述顶表面更加平整；其中，所述至少一次金属表面平坦化处理中的每次金属表面平坦化处理包括：采用第一试剂对所述金属层的所述顶表面进行刻蚀；以及，采用第二试剂对所述半导体结构进行清洗。

Description

半导体结构的处理方法以及字线结构的形成方法
相关申请的交叉引用
本公开基于申请号为202210726017.X、申请日为2022年06月23日、发明名称为“半导体结构的处理方法以及字线结构的形成方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体制造领域，尤其涉及一种半导体结构的处理方法以及字线结构的形成方法。
背景技术
埋入式字线(Buried Word line，BWL，也可称为埋入式栅极)为增加半导体器件的集成密度提供了一种新的选择。埋入式字线是指将字线埋设在半导体衬底的内部，可以显著地减少在字线与位线之间的寄生电容，大幅地改善半导体器件的电压读出操作的可靠性。
发明内容
有鉴于此，本公开实施例提供一种半导体结构的处理方法以及处理装置。
根据本公开实施例的第一方面，提供了一种半导体结构的处理方法，包括：
提供半导体结构，所述半导体结构包括凹槽以及位于所述凹槽中的金属层，所述金属层的顶表面的边缘位置高于所述金属层的所述顶表面的中心位置；
使所述半导体结构处于旋转状态；以及，
对所述半导体结构进行至少一次金属表面平坦化处理，以使处理后的所述金属层的所述顶表面比处理前的所述金属层的所述顶表面更加平整；
其中，所述至少一次金属表面平坦化处理中的每次金属表面平坦化处理包括：
采用第一试剂对所述金属层的所述顶表面进行刻蚀；以及，
采用第二试剂对所述半导体结构进行清洗。
在一些实施例中，所述第一试剂包括酸性试剂，所述第二试剂包括碱 性试剂和中性试剂中的至少之一。
在一些实施例中，所述第一试剂包括SC2溶液、硫酸和双氧水混合溶液以及盐酸和双氧水混合溶液中的至少一种。
在一些实施例中，所述第二试剂包括SC1溶液、去离子水溶液、氨水以及过氧化氢中的至少一种。
在一些实施例中，所述硫酸和双氧水混合溶液中硫酸与双氧水的配比的范围为5:1～8:1。
在一些实施例中，所述至少一次金属表面平坦化处理包括4～8次金属表面平坦化处理。
在一些实施例中，进行一次采用第一试剂对所述金属层的所述顶表面进行刻蚀的时间范围为8s～50s。
在一些实施例中，进行一次采用第二试剂对所述半导体结构进行清洗的时间范围为25s～35s。
在一些实施例中，所述至少一次金属表面平坦化处理包括多次金属表面平坦化处理，所述多次金属表面平坦化处理中对所述金属层的所述顶表面进行刻蚀的时间总和的范围为45s～90s。
在一些实施例中，所述金属层的材料包括氮化钛、钼或钨中的至少一种。
在一些实施例中，所述半导体结构旋转的转速范围为500rpm～800rpm。
在一些实施例中，在采用第一试剂对所述金属层的所述顶表面进行刻蚀的过程中，所述半导体结构旋转的转速为第一转速；
在采用第二试剂对所述半导体结构进行清洗的过程中，所述半导体结构旋转的转速为第二转速；其中，
所述第一转速小于所述第二转速。
在一些实施例中，在采用第一试剂对所述金属层的所述顶表面进行刻蚀的过程中，所述半导体结构旋转的转速为第一转速；
在采用第二试剂对所述半导体结构进行清洗的过程中，所述半导体结构旋转的转速为第二转速；其中，
所述第一转速等于所述第二转速。
在一些实施例中，所述金属层内包括空隙；在进行至少一次金属表面平坦化处理后，所述金属层的顶表面位于所述空隙的上方。
根据本公开实施例的第二方面，提供了一种字线结构的形成方法，包括：
提供衬底；
在所述衬底内形成凹槽，在所述凹槽的底面和侧壁以及所述衬底的表面形成介质材料层；
在所述介质材料层上形成金属层预层；
刻蚀所述金属层预层，形成位于所述凹槽中的金属层；所述金属层的 顶表面的边缘位置高于所述金属层的所述顶表面的中心位置；
采用上述任一项实施例中所述的半导体结构的处理方法对所述金属层进行处理。
在一些实施例中，在所述金属层上形成多晶硅层，所述多晶硅层位于所述凹槽中；在所述多晶硅层上形成隔离层。
本公开实施例中，在清洗的过程中，通过旋转半导体结构，并且对半导体结构进行至少一次金属表面平坦化处理，使得第一试剂在离心力的作用下，冲击金属层的顶表面的边缘位置，使得半导体结构的金属层的顶表面的边缘位置残留的金属被去除，使处理后的金属层的顶表面比处理前的金属层的顶表面更加平整。
附图说明
为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的半导体结构的处理方法的流程示意图；
图2a至图2g为本公开实施例提供的半导体结构在处理过程中的结构示意图；
图3为本公开实施例提供的字线结构的形成方法的流程示意图。
附图标记说明：
1-半导体结构；10-衬底；100-凹槽；110-金属层；110’-金属层预层；111-顶表面；112-空隙；120-介质材料层；130-多晶硅层；140-隔离层。
具体实施方式
下面将参照附图更详细地描述本公开公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、层或部分。
空间关系术语例如“在……下”、“在……下面”、“下面的”、“在……之下”、“在……之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在……下面”和“在……下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
为了彻底理解本公开，将在下列的描述中提出详细的步骤以及详细的结构，以便阐释本公开的技术方案。本公开的较佳实施例详细描述如下，然而除了这些详细描述外，本公开还可以具有其他实施方式。
在埋入式字线的制造过程中，需要对字线凹槽内沉积的导电材料(如氮化钛等)进行一定程度的回刻蚀。本公开的发明人发现：在对字线凹槽内的氮化钛(TiN)金属层进行回刻蚀的过程中，由于对金属层的中心和边缘的刻蚀速率不完全一致，会导致刻蚀后的金属层表面不平坦，形成“兔耳”形貌(即中心低、边缘高的形貌，参见图2d所示)，进而导致阈值电压(Vt)和栅诱导漏极漏电流(Gate-Induced Drain Leakage，GIDL)较高。
基于此，本公开实施例提供了一种半导体结构处理方法。具体请参见 图1，如图所示，所述方法包括以下步骤：
步骤101：提供半导体结构，所述半导体结构包括凹槽以及位于所述凹槽中的金属层，所述金属层的顶表面的边缘位置高于所述金属层的所述顶表面的中心位置；
步骤102：使所述半导体结构处于旋转状态；以及，对所述半导体结构进行至少一次金属表面平坦化处理，以使处理后的所述金属层的所述顶表面比处理前的所述金属层的所述顶表面更加平整；其中，所述至少一次金属表面平坦化处理中的每次金属表面平坦化处理包括：采用第一试剂对所述金属层的所述顶表面进行刻蚀；以及，采用第二试剂对所述半导体结构进行清洗。
下面结合具体实施例对本公开实施例提供的半导体结构的处理方法再作进一步详细的说明。
图2a至图2g为本公开实施例提供的半导体结构在处理过程中的结构示意图。
首先，参见图2a至图2d，执行步骤101，提供半导体结构1，所述半导体结构1包括凹槽100以及位于所述凹槽中的金属层110，所述金属层110的顶表面111的边缘位置高于所述金属层110的所述顶表面111的中心位置。
先参见图2a，提供半导体结构1，所述半导体结构1包括衬底10。例如，可以在所述衬底10内形成凹槽100。
在一实施例中，所述衬底10可以为半导体制造工艺阶段的晶圆。
在一实施例中，所述衬底10可以为硅衬底、锗衬底、硅锗衬底、碳化硅衬底、SOI(绝缘体上硅，Silicon On Insulator)衬底或GOI(绝缘体上锗，Germanium On Insulator)衬底等，还可以为包括其他元素半导体或化合物半导体的衬底，例如玻璃衬底或III-V族化合物衬底(例如氮化镓衬底或砷化镓衬底等)，还可以为叠层结构，例如Si/SiGe等，还可以其他外延结构，例如SGOI(绝缘体上锗硅)等。在本公开实施例中，所述衬底可以为硅衬底。
例如，可以先在衬底的上表面生长一层掩模层(图中未显示)，接着对该掩模层进行图案化，以在掩模层上显示出要刻蚀的凹槽图形，可以通过光刻工艺对该掩模层进行图案化。该掩模层可以是光致抗蚀剂掩模或者基于光刻掩模进行图案化的硬掩模；当该掩模层是光致抗蚀剂掩模时，具体通过曝光、显影和去胶等步骤对该掩模层进行图案化。接着按照要刻蚀的凹槽图形刻蚀出具有一定深度的凹槽。
这里，例如可以采用干法刻蚀工艺形成凹槽100。
接着，参见图2b，在形成凹槽100之后，在所述凹糟100的底面和侧壁以及所述衬底10的表面形成介质材料层120。
在实际操作中，所述介质材料层120可以使用一种或多种薄膜沉积工艺形成；例如，所述沉积工艺包括但不限于化学气相沉积(Chemical Vapor  Deposition，CVD)工艺、等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition，PECVD)工艺、原子层沉积(Atomic Layer Deposition，ALD)工艺或其组合。
所述介质材料层120的材料包括但不限于氧化物、氮化物、金属氧化物及氮氧化物等；可选的，所述介质材料层120的材料包括高K介质材料，所述高K介质材料可以包含铪元素。具体的，所述高K介质材料可以包括但不限于铝氧化物(Al 2O 3)、钽氧化物(Ta 2O 3)、钛氧化物(TiO 2)、钇氧化物(Y 2O 3)、锆氧化物(ZrO 2)、锆硅氧化物(ZrSi xO y)、铪氧化物(HfO 2)、铪硅氧化物(HfSi xO y)、铪硅氮氧化物(HfSiON)、铪锆酸盐(HfZrO 4)、镧氧化物(La 2O 3)、镧铝氧化物(LaAl xO y)、镧铪氧化物(LaHf xO y)、铪铝氧化物(HfAl xO y)和/或镨氧化物(Pr 2O 3)等。
可以理解的是，所述介质材料层位于所述衬底和后续形成的金属层之间。
接着，参见图2c，在形成介质材料层120之后，在所述凹槽100内沉积金属材料以形成金属层预层110’。
例如，不仅在所述介质材料层120的侧壁和底面上形成金属层预层110’，还在位于衬底10表面的介质材料层120上形成金属层预层110’，并且所述金属层预层110’可填充满所述凹槽100。
在实际操作中，所述金属层预层110’可以使用一种或多种薄膜沉积工艺形成；例如，所述沉积工艺包括但不限于化学气相沉积(Chemical Vapor Deposition，CVD)工艺、等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition，PECVD)工艺、原子层沉积(Atomic Layer Deposition，ALD)工艺或其组合。
接着，参见图2d，对所述金属层预层110’进行刻蚀，以形成金属层110。
在实际操作中，可以刻蚀去除位于所述衬底10表面之上的全部所述金属层预层110’，以及位于所述凹槽100内的部分金属层预层110’，以形成金属层110。
所述刻蚀工艺为等离子体刻蚀工艺。例如，所述等离子体刻蚀工艺包含由反应性离子刻蚀(Reaction Ion Etching，RIE)或高密度等离子体刻蚀(High Density Plasma，HDP)等刻蚀工艺中的至少一种。
在图2c所示的附图中，在形成金属层预层110’的过程中，由于工艺导致，可能会在金属层预层110’内形成空隙112。空隙112的存在，可能也会导致刻蚀形成金属层的过程中，使得金属层顶表面的边缘位置有金属残留。
由于刻蚀过程中，金属层顶表面的边缘位置会有金属残留，使得所述金属层110的顶表面111的边缘位置高于所述金属层110的所述顶表面111的中心位置，形成为如图2d所示的“兔耳”形状。“兔耳”形状的金属层表面会对器件的性能产生影响，因此要对金属层的“兔耳”形状的表面进行处理，使其平整。
接着，参见图2e和图2f，执行步骤102，使所述半导体结构1处于旋转状态；以及，对所述半导体结构1进行至少一次金属表面平坦化处理，以使处理后的所述金属层110的所述顶表面111比处理前的所述金属层110的所述顶表面111更加平整；其中，所述至少一次金属表面平坦化处理中的每次金属表面平坦化处理包括：采用第一试剂对所述金属层110的所述顶表面111进行刻蚀；以及，采用第二试剂对所述半导体结构1进行清洗。
先参见图2d和图2e，从图2d到图2e的过程中，所述半导体结构1进行了至少一次金属表面平坦化处理，使得图2e所示的半导体结构1的金属层110的顶表面111相比于图2d所示的半导体结构1的金属层110的顶表面111更加平整。
例如，参见图2d和图2e。图2d所示的半导体结构1的金属层110的顶表面111的边缘位置的“兔耳”形状与凹槽100的侧壁的夹角为α1，且顶表面111的边缘位置高出中间位置的高度为h1；图2e所示的半导体结构1的金属层110的顶表面111的边缘位置的“兔耳”形状与凹槽100的侧壁的夹角为α2，且顶表面111的边缘位置高出中间位置的高度为h2，其中，α1小于α2，h1大于h2。
可以理解的是，当所述半导体结构1的金属层110的顶表面111的边缘位置的“兔耳”形状与凹槽100的侧壁的夹角越大时，说明金属层110的顶表面111的边缘位置高出中间位置的高度越小，也即边缘位置的“兔耳”形状的坡度越缓，如此，说明通过对所述半导体结构1进行至少一次金属表面平坦化处理，能够使得处理后的金属层110的顶表面111比处理前的金属层110的顶表面111更加平整。
接着，参见图2f，所述半导体结构1的金属层110的顶表面111在经过至少一次金属表面平坦化处理后，顶表面111最终基本达到平整状态。
在一实施例中，所述金属层110的材料包括氮化钛、钼或钨中的至少一种。。可以理解的是，本公开实施例中提供的金属层的材料仅作为本公开实施例中的一种下位的、可行的具体实施方式，并不构成对本公开的限制，所述金属层的材料也可为其他材料。
在一实施例中，在进行至少一次金属表面平坦化处理后，所述金属层110的顶表面111位于所述空隙112的上方，以确保金属层110的顶表面111最终基本达到平整状态。
在一实施例中，所述半导体结构旋转的转速范围为500rpm～800rpm。所述半导体结构旋转的转速在此范围内，能保证清洗剂在刻蚀金属层的顶表面的边缘位置的残余金属时，达到最好的效果，否则，如果转速过快，清洗剂未与金属层的顶表面的残余金属作用，就被甩出去，如果转速过慢，清洗剂与残余金属未充分接触，没法起到很好的去除残余金属的作用。
在一实施例中，在采用第一试剂对所述金属层的所述顶表面进行刻蚀的过程中，所述半导体结构旋转的转速为第一转速；在采用第二试剂对所 述半导体结构进行清洗的过程中，所述半导体结构旋转的转速为第二转速；其中，所述第一转速小于所述第二转速。
采用第一试剂对金属层的顶表面进行刻蚀时，半导体结构旋转的转速低一些，如此，能够使第一试剂与残余金属接触的更充分，更好起到氧化腐蚀的作用；采用第二试剂对半导体结构进行清洗时，半导体结构旋转的转速更高一些，如此，离心力更大，第二试剂能更好的冲洗半导体结构，使第一试剂与残余金属的氧化反应物被冲洗干净。
在一实施例中，在采用第一试剂对所述金属层的所述顶表面进行刻蚀的过程中，所述半导体结构旋转的转速为第一转速；在采用第二试剂对所述半导体结构进行清洗的过程中，所述半导体结构旋转的转速为第二转速；其中，所述第一转速等于所述第二转速。
采用第一试剂对金属层的顶表面进行刻蚀时的转速与采用第二试剂对所述半导体结构进行清洗时的转速一样，如此，整个清洗过程可以不用调节转速，只需保持一个转速即可，能更节约成本，工艺也更加简单。
在一实施例中，所述第一试剂包括酸性试剂，所述第二试剂包括碱性试剂和中性试剂中的至少之一。酸性试剂因其氧化腐蚀作用可以对所述半导体结构的金属层的顶表面进行刻蚀，而碱性试剂和中性试剂在酸性试剂刻蚀之后，可以对所述半导体结构进行冲洗作用，以去除残余的酸性试剂以及刻蚀后的残余物。其中，碱性试剂还可以中和残余的酸性试剂。
例如，在一实施例中，所述第一试剂包括SC2溶液(去离子水、HCl和H 2O 2的混合溶液)、硫酸和双氧水混合溶液(SPM)以及盐酸和双氧水混合溶液(HPM)中的至少一种，所述第二试剂包括SC1溶液(去离子水、NH 4OH和H 2O 2的混合溶液)、去离子水溶液、氨水以及过氧化氢中的至少一种。SC2溶液、硫酸和双氧水混合溶液以及盐酸和双氧水混合溶液能够通过氧化腐蚀金属层的顶表面的边缘位置残留的金属，SC1溶液、去离子水溶液、氨水以及过氧化氢能够冲洗硫酸和双氧水混合溶液与金属氧化后的残留物，使得金属层的表面平整。可以理解的是，本公开实施例中提供的第一试剂和第二试剂的材料仅作为本公开实施例中的一种可行的具体实施方式，并不构成对本公开的限制，所述第一试剂和所述第二试剂可以根据金属层的材料等进行选择。
在一实施例中，所述硫酸和双氧水混合溶液中硫酸与双氧水的配比的范围为5:1～8:1。硫酸和双氧水混合溶液中硫酸与双氧水的配比在此范围内时，硫酸和双氧水混合溶液能够更好的起到氧化腐蚀残余金属的作用。
在一具体实施例中，所述硫酸和双氧水混合溶液中硫酸的质量分数为96％，双氧水的质量分数为30％。
在一实施例中，采用SC2溶液、硫酸和双氧水混合溶液以及盐酸和双氧水混合溶液中的一种或多种来去除金属层顶表面的边缘位置残留的金属的过程中，可以将SC2溶液、硫酸和双氧水混合溶液以及盐酸和双氧水混 合溶液保持在预设温度，可以确保在刻蚀过程中，具有较高的刻蚀速度。
本公开实施例中，在进行至少一次金属表面平坦化处理的过程中，采用SC2溶液、硫酸和双氧水混合溶液以及盐酸和双氧水混合溶液中的一种或多种来去除金属层顶表面的边缘位置残留的金属时，与采用气体刻蚀金属层表面残留的金属的方式相比，刻蚀液体与金属层表面的接触相比于刻蚀气体与金属层表面的接触更均匀，如此可以使采用SC2溶液、硫酸和双氧水混合溶液以及盐酸和双氧水混合溶液中的一种或多种对金属层进行刻蚀，去除残留金属后的表面具有更高的平整度。
在一实施例中，所述至少一次金属表面平坦化处理包括4～8次金属表面平坦化处理。循环次数在此范围内时，去除金属层的顶表面的边缘位置残留的金属的效果最好，否则，如果次数过少，残余金属未全部去除，而次数过多，又会过多地去除金属层内除残余金属之外的部分，影响器件的性能。
例如，在一个具体示例中，采用硫酸和双氧水混合溶液作为第一试剂，去离子水作为第二试剂，对所述金属层进行平坦化处理。下表示出了金属表面平坦化处理次数和时间与处理效果的对比。如下表所示，表中E/A表示在金属表面平坦化处理过程中，被刻蚀掉的金属层的厚度，其中，E/A的数值越大，表示被刻蚀掉的金属层的厚度越大，E/A的数值越小，表示被刻蚀掉的金属层的厚度越小。表中600:80、600:90和600:100均指硫酸和双氧水混合溶液中硫酸与双氧水的配比系数。
Figure PCTCN2022105173-appb-000001
从表中可以看出，当金属层的顶表面进行金属表面平坦化处理次数为1次，硫酸与双氧水的配比系数为600:90，且刻蚀时间为47s时，E/A的数值为6.43，即被刻蚀掉的金属层的厚度为6.43nm；当金属层的顶表面进行金属表面平坦化处理次数为4次，且硫酸与双氧水的配比系数为600:90，每次刻蚀的时间为15s时，E/A的数值为6.57，即被刻蚀掉的金属层的厚度为6.57nm；当金属层的顶表面进行金属表面平坦化处理次数为6次，硫酸与双氧水的配比系数为600:90，且每次刻蚀的时间为11.3s时，E/A的数值为6.73，即被刻蚀掉的金属层的厚度为6.73nm；当金属层的顶表面进行金属表面平坦化处理次数为8次，硫酸与双氧水的配比系数为600:90，且每次刻蚀的时间为9.1s时，E/A的数值为7.1，即被刻蚀掉的金属层的厚度为7.1nm；当金属层的顶表面进行金属表面平坦化处理次数为4次，且硫酸与 双氧水的配比系数为600:80，每次刻蚀的时间为20.5s时，E/A的数值为6.98，即被刻蚀掉的金属层的厚度为6.98nm；当金属层的顶表面进行金属表面平坦化处理次数为4次，且硫酸与双氧水的配比系数为600:100，每次刻蚀的时间为11.5s时，E/A的数值为7.26，即被刻蚀掉的金属层的厚度为7.26nm。
在一实施例中，进行一次采用第一试剂对所述金属层的所述顶表面进行刻蚀的时间范围为8s～50s。在一实施例中，所述至少一次金属表面平坦化处理包括多次金属表面平坦化处理，所述多次金属表面平坦化处理中对所述金属层的所述顶表面进行刻蚀的时间总和的范围为45s～90s。金属表面平坦化处理中对金属层的顶表面进行刻蚀的时间总和在此范围内也是为了保证对金属层的顶表面的刻蚀效果达到最好，一方面，减小金属层被刻蚀掉的厚度，另一方面，提高刻蚀后的金属层的表面的平整度。
在一实施例中，进行一次采用第二试剂对所述半导体结构进行清洗的时间范围为25s～35s。每次对半导体结构进行清洗的时间在此范围内时，能起到最佳的清洗效果，否则，如果时间过短，会导致清洗不充分，可能有剩余的残留物未被冲洗，如果时间过长，又会浪费清洗剂，增加成本。
接着，参见图2g，所述金属层110的顶表面111在经过至少一次金属表面平坦化处理后，在金属层110的顶表面111上形成多晶硅层130。
在实际操作中，所述多晶硅层130可以使用一种或多种薄膜沉积工艺形成；例如，所述沉积工艺包括但不限于化学气相沉积(Chemical Vapor Deposition，CVD)工艺、等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition，PECVD)工艺、原子层沉积(Atomic Layer Deposition，ALD)工艺或其组合。
继续参见图2g，在形成多晶硅层130后，在所述多晶硅层130上形成隔离层140。所述隔离层140的材料可以为氮化硅。
在实际操作中，所述隔离层140可以使用一种或多种薄膜沉积工艺形成；例如，所述沉积工艺包括但不限于化学气相沉积(Chemical Vapor Deposition，CVD)工艺、等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition，PECVD)工艺、原子层沉积(Atomic Layer Deposition，ALD)工艺或其组合。
本公开实施例中，在清洗的过程中，通过旋转半导体结构，并且对半导体结构进行至少一次金属表面平坦化处理，使得第一试剂在离心力的作用下，冲击金属层的顶表面的边缘位置，使得半导体结构的金属层的顶表面的边缘位置残留的金属被去除，使处理后的金属层的顶表面比处理前的金属层的顶表面更加平整。
本公开实施例提供了一种字线结构的形成方法。具体请参见图3，如图所示，所述方法包括以下步骤：
步骤301：提供衬底；
步骤302：在所述衬底内形成凹槽，在所述凹槽的底面和侧壁以及所述衬底的表面形成介质材料层；
步骤303：在所述介质材料层上形成金属层预层；
步骤304：刻蚀所述金属层预层，形成位于所述凹槽中的金属层；所述金属层的顶表面的边缘位置高于所述金属层的所述顶表面的中心位置；
步骤305：采用上述任一项实施例中所述的半导体结构的处理方法对所述金属层进行处理。
下面结合具体实施例对本公开实施例提供的字线结构的形成方法再作进一步详细的说明。
例如，所述字线结构在形成过程中的结构示意图可参照图2a至图2g。
首先，参见图2a，执行步骤301，提供衬底10。
在一实施例中，所述衬底10可以为硅衬底、锗衬底、硅锗衬底、碳化硅衬底、SOI(绝缘体上硅，Silicon On Insulator)衬底或GOI(绝缘体上锗，Germanium On Insulator)衬底等，还可以为包括其他元素半导体或化合物半导体的衬底，例如玻璃衬底或III-V族化合物衬底(例如氮化镓衬底或砷化镓衬底等)，还可以为叠层结构，例如Si/SiGe等，还可以其他外延结构，例如SGOI(绝缘体上锗硅)等。在本公开实施例中，所述衬底可以为硅衬底。
接着，参见图2a和图2b，执行步骤302，在所述衬底10内形成凹槽100，在所述凹槽100的底面和侧壁以及所述衬底10的表面形成介质材料层120。
例如，可以先在衬底的上表面生长一层掩模层(图中未显示)，接着对该掩模层进行图案化，以在掩模层上显示出要刻蚀的凹槽图形，可以通过光刻工艺对该掩模层进行图案化。该掩模层可以是光致抗蚀剂掩模或者基于光刻掩模进行图案化的硬掩模；当该掩模层是光致抗蚀剂掩模时，具体通过曝光、显影和去胶等步骤对该掩模层进行图案化。接着按照要刻蚀的凹槽图形刻蚀出具有一定深度的凹槽。
这里，例如可以采用干法刻蚀工艺形成凹槽100。
在实际操作中，所述介质材料层120可以使用一种或多种薄膜沉积工艺形成；例如，所述沉积工艺包括但不限于化学气相沉积(Chemical Vapor Deposition，CVD)工艺、等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition，PECVD)工艺、原子层沉积(Atomic Layer Deposition，ALD)工艺或其组合。
所述介质材料层120的材料包括但不限于氧化物、氮化物、金属氧化物及氮氧化物等；可选的，所述介质材料层120的材料包括高K介质材料，所述高K介质材料可以包含铪元素。具体的，所述高K介质材料可以包括但不限于铝氧化物(Al 2O 3)、钽氧化物(Ta 2O 3)、钛氧化物(TiO 2)、钇氧化物(Y 2O 3)、锆氧化物(ZrO 2)、锆硅氧化物(ZrSi xO y)、铪氧化物(HfO 2)、铪硅氧化物(HfSi xO y)、铪硅氮氧化物(HfSiON)、铪锆酸盐(HfZrO 4)、镧氧化物 (La 2O 3)、镧铝氧化物(LaAl xO y)、镧铪氧化物(LaHf xO y)、铪铝氧化物(HfAl xO y)和/或镨氧化物(Pr 2O 3)等。
可以理解的是，所述介质材料层位于所述衬底和后续形成的金属层之间。
接着，参见图2c，在所述介质材料层120上形成金属层预层110’。
例如，不仅在所述介质材料层120的侧壁和底面上形成金属层预层110’，还在位于衬底10表面的介质材料层120上形成金属层预层110’，并且所述金属层预层110’可填充满所述凹槽100。
在实际操作中，所述金属层预层110’可以使用一种或多种薄膜沉积工艺形成；例如，所述沉积工艺包括但不限于化学气相沉积(Chemical Vapor Deposition，CVD)工艺、等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition，PECVD)工艺、原子层沉积(Atomic Layer Deposition，ALD)工艺或其组合。
接着，参见图2d，执行步骤304，刻蚀所述金属层预层110’，形成位于所述凹槽中的金属层110；所述金属层110的顶表面111的边缘位置高于所述金属层110的所述顶表面111的中心位置。
在实际操作中，可以刻蚀去除位于所述衬底10表面之上的全部所述金属层预层110’，以及位于所述凹槽100内的部分金属层预层110’，以形成金属层110。
所述刻蚀工艺为等离子体刻蚀工艺。例如，所述等离子体刻蚀工艺包含由反应性离子刻蚀(Reaction Ion Etching，RIE)或高密度等离子体刻蚀(High Density Plasma，HDP)等刻蚀工艺中的至少一种。
在图2c所示的附图中，在形成金属层预层110’的过程中，由于工艺导致，可能会在金属层预层110’内形成空隙112。空隙112的存在，可能也会导致刻蚀形成金属层的过程中，使得金属层顶表面的边缘位置有金属残留。
由于刻蚀过程中，金属层顶表面的边缘位置会有金属残留，使得所述金属层110的顶表面111的边缘位置高于所述金属层110的所述顶表面111的中心位置，形成为如图2d所示的“兔耳”形状。“兔耳”形状的金属层表面会对器件的性能产生影响，因此要对金属层的“兔耳”形状的表面进行处理，使其平整。
接着，参见图2d至图2f，执行步骤305，采用上述任一项实施例中所述的半导体结构的处理方法对所述金属层进行处理。
这里对金属层的处理方法的更多细节可参照上述半导体结构的处理方法中的实施例，这里不再赘述。
接着，参见图2g，所述方法还包括：在所述金属层110上形成多晶硅层130，多晶硅层130位于凹槽100中；在所述多晶硅层130上形成隔离层140。
例如，所述金属层110的顶表面111在经过至少一次金属表面平坦化处 理，变得更加平整后，在金属层110的顶表面111上形成多晶硅层130。
在实际操作中，可以使用一种或多种薄膜沉积工艺形成多晶硅材料层，再对其进行回刻蚀以形成所述多晶硅层130；例如，所述沉积工艺包括但不限于化学气相沉积(Chemical Vapor Deposition，CVD)工艺、等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition，PECVD)工艺、原子层沉积(Atomic Layer Deposition，ALD)工艺或其组合。
继续参见图2g，在形成多晶硅层130后，在所述多晶硅层130上形成隔离层140。所述隔离层140的材料可以为氮化硅。
在实际操作中，所述隔离层140可以使用一种或多种薄膜沉积工艺形成；例如，所述沉积工艺包括但不限于化学气相沉积(Chemical Vapor Deposition，CVD)工艺、等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition，PECVD)工艺、原子层沉积(Atomic Layer Deposition，ALD)工艺或其组合。
可以理解的是，上述字线结构为埋入式字线结构，其可以包括形成在凹槽中的介质材料层、金属层、多晶硅层和隔离层。
以上所述，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围，凡在本公开的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本公开的保护范围之内。
工业实用性
本公开实施例中，在清洗的过程中，通过旋转半导体结构，并且对半导体结构进行至少一次金属表面平坦化处理，使得第一试剂在离心力的作用下，冲击金属层的顶表面的边缘位置，使得半导体结构的金属层的顶表面的边缘位置残留的金属被去除，使处理后的金属层的顶表面比处理前的金属层的顶表面更加平整。

Claims (16)

  1. 一种半导体结构的处理方法，包括：
    提供半导体结构，所述半导体结构包括凹槽以及位于所述凹槽中的金属层，所述金属层的顶表面的边缘位置高于所述金属层的所述顶表面的中心位置；
    使所述半导体结构处于旋转状态；以及，
    对所述半导体结构进行至少一次金属表面平坦化处理，以使处理后的所述金属层的所述顶表面比处理前的所述金属层的所述顶表面更加平整；
    其中，所述至少一次金属表面平坦化处理中的每次金属表面平坦化处理包括：
    采用第一试剂对所述金属层的所述顶表面进行刻蚀；以及，
    采用第二试剂对所述半导体结构进行清洗。
  2. 根据权利要求1所述的方法，其中，
    所述第一试剂包括酸性试剂，所述第二试剂包括碱性试剂和中性试剂中的至少之一。
  3. 根据权利要求2所述的方法，其中，
    所述第一试剂包括SC2溶液、硫酸和双氧水混合溶液以及盐酸和双氧水混合溶液中的至少一种。
  4. 根据权利要求2所述的方法，其中，
    所述第二试剂包括SC1溶液、去离子水溶液、氨水以及过氧化氢中的至少一种。
  5. 根据权利要求3所述的方法，其中，
    所述硫酸和双氧水混合溶液中硫酸与双氧水的配比的范围为5:1～8:1。
  6. 根据权利要求1所述的方法，其中，
    所述至少一次金属表面平坦化处理包括4～8次金属表面平坦化处理。
  7. 根据权利要求1所述的方法，其中，
    进行一次采用第一试剂对所述金属层的所述顶表面进行刻蚀的时间范围为8s～50s。
  8. 根据权利要求1所述的方法，其中，
    进行一次采用第二试剂对所述半导体结构进行清洗的时间范围为25s～35s。
  9. 根据权利要求1所述的方法，其中，
    所述至少一次金属表面平坦化处理包括多次金属表面平坦化处理，所述多次金属表面平坦化处理中对所述金属层的所述顶表面进行刻蚀的时间总和的范围为45s～90s。
  10. 根据权利要求1所述的方法，其中，所述金属层的材料包括氮化钛、钼或钨中的至少一种。
  11. 根据权利要求1所述的方法，其中，
    所述半导体结构旋转的转速范围为500rpm～800rpm。
  12. 根据权利要求1所述的方法，其中，
    在采用第一试剂对所述金属层的所述顶表面进行刻蚀的过程中，所述半导体结构旋转的转速为第一转速；
    在采用第二试剂对所述半导体结构进行清洗的过程中，所述半导体结构旋转的转速为第二转速；其中，
    所述第一转速小于所述第二转速。
  13. 根据权利要求1所述的方法，其中，
    在采用第一试剂对所述金属层的所述顶表面进行刻蚀的过程中，所述半导体结构旋转的转速为第一转速；
    在采用第二试剂对所述半导体结构进行清洗的过程中，所述半导体结构旋转的转速为第二转速；其中，
    所述第一转速等于所述第二转速。
  14. 根据权利要求1所述的方法，其中，
    所述金属层内包括空隙；
    在进行至少一次金属表面平坦化处理后，所述金属层的顶表面位于所述空隙的上方。
  15. 一种字线结构的形成方法，包括：
    提供衬底；
    在所述衬底内形成凹槽，在所述凹槽的底面和侧壁以及所述衬底的表面形成介质材料层；
    在所述介质材料层上形成金属层预层；
    刻蚀所述金属层预层，形成位于所述凹槽中的金属层；所述金属层的顶表面的边缘位置高于所述金属层的所述顶表面的中心位置；
    采用权利要求1至14中的任一项所述的半导体结构的处理方法对所述金属层进行处理。
  16. 根据权利要求15所述的方法，其中，还包括：
    在所述金属层上形成多晶硅层，所述多晶硅层位于所述凹槽中；
    在所述多晶硅层上形成隔离层。
PCT/CN2022/105173 2022-06-23 2022-07-12 半导体结构的处理方法以及字线结构的形成方法 WO2023245761A1 (zh)

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