TWI736229B - 封裝結構、疊層封裝結構及其製作方法 - Google Patents

封裝結構、疊層封裝結構及其製作方法 Download PDF

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TWI736229B
TWI736229B TW109113446A TW109113446A TWI736229B TW I736229 B TWI736229 B TW I736229B TW 109113446 A TW109113446 A TW 109113446A TW 109113446 A TW109113446 A TW 109113446A TW I736229 B TWI736229 B TW I736229B
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semiconductor die
layer
conductive
package
semiconductor
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TW109113446A
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TW202107643A (zh
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陳憲偉
陳明發
葉松峯
史朝文
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台灣積體電路製造股份有限公司
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    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Abstract

一種封裝結構包括第一半導體晶粒、第二半導體晶粒、絕緣封裝體及重佈線層。第一半導體晶粒具有第一導電杆及橫向環繞第一導電杆的第一保護層。第二半導體晶粒嵌入在第一半導體晶粒的第一保護層中且被第一導電杆環繞，其中第二半導體晶粒包括第二導電杆。絕緣封裝體包封第一半導體晶粒及第二半導體晶粒。重佈線層設置在絕緣封裝體上且與第一導電杆及第二導電杆連接，其中第一半導體晶粒與第二半導體晶粒透過第一導電杆、重佈線層及第二導電杆電性連接。

Description

封裝結構、疊層封裝結構及其製作方法
本揭露是有關於一種封裝結構、疊層封裝結構及其製作方法。
各種電子應用中皆會用到半導體元件，例如個人電腦、手機、數位照相機及其他電子裝備。半導體元件通常是透過以下步驟製作：在半導體基底之上依序沉積絕緣材料層或介電材料層、導電材料層及半導體材料層，並使用微影將各種材料層圖案化以在上面形成電路部件及元件。許多半導體積體電路通常製造在單個半導體晶圓上。可在晶圓級下處理並封裝晶圓的晶粒，且已針對晶圓級封裝開發出各種技術。
根據本揭露的一些實施例，提供一種封裝結構，所述封裝結構包括：第一半導體晶粒、至少一個第二半導體晶粒、絕緣封裝體及重佈線層。所述第一半導體晶粒具有多個第一導電杆及 橫向環繞所述多個第一導電杆的第一保護層。所述至少一個第二半導體晶粒嵌入在所述第一半導體晶粒的所述第一保護層中且被所述多個第一導電杆環繞，其中所述至少一個第二半導體晶粒包括多個第二導電杆。所述絕緣封裝體包封所述第一半導體晶粒及所述至少一個第二半導體晶粒。所述重佈線層設置在所述絕緣封裝體上且與所述多個第一導電杆及所述多個第二導電杆連接，其中所述第一半導體晶粒與所述至少一個第二半導體晶粒透過所述多個第一導電杆、所述重佈線層及所述多個第二導電杆電性連接。
根據本揭露的一些實施例，提供一種疊層封裝結構，所述疊層封裝結構包括第一封裝及第二封裝。所述第二封裝包括電性連接到所述第一封裝的多個導電球。所述第一封裝包括至少一個堆疊晶粒單元、絕緣封裝體及重佈線層。所述至少一個堆疊晶粒單元包括第一半導體晶粒及至少一個第二半導體晶粒。所述第一半導體晶粒具有：多個第一導電接墊；第一鈍化層，覆蓋所述多個第一導電接墊的一些部分；多個穿孔，設置在所述第一鈍化層上且電性連接到所述多個第一導電接墊；及保護層，設置在所述第一鈍化層上且覆蓋所述多個穿孔。所述至少一個第二半導體晶粒堆疊在所述第一半導體晶粒上，其中所述至少一個第二半導體晶粒包括：多個第二導電接墊；第二鈍化層，覆蓋所述多個第二導電接墊的一些部分；及多個導電杆，設置在所述第二鈍化層上且電性連接到所述多個第二導電接墊，其中所述第一半導體晶粒的所述保護層覆蓋所述至少一個第二半導體晶粒。所述絕緣封 裝體具有第一表面及與所述第一表面相對的第二表面，其中所述絕緣封裝體包封所述至少一個堆疊晶粒單元。所述重佈線層設置在所述絕緣封裝體的所述第一表面上且電性連接到所述多個穿孔及所述多個導電杆。
根據本揭露的一些實施例，闡述一種製作封裝結構的方法。所述方法包括以下步驟。形成堆疊晶粒單元。所述形成所述堆疊晶粒單元的步驟包括以下步驟。提供具有多個第一半導體晶粒的半導體晶圓，其中所述多個第一半導體晶粒中的每一者包括第一鈍化層及形成在所述第一鈍化層上的多個第一導電杆。在由所述多個第一導電杆環繞的區域中將第二半導體晶粒固定到所述多個第一半導體晶粒中的每一者的所述第一鈍化層上，其中所述第二半導體晶粒包括多個第二導電杆。在所述多個第一半導體晶粒中的每一者的所述第一鈍化層的表面上形成第一保護層，以覆蓋所述多個第一導電杆及所述第二半導體晶粒。分割所述半導體晶圓以分離開所述多個第一半導體晶粒來形成所述堆疊晶粒單元。將所述堆疊晶粒單元接合到載體上。形成絕緣封裝體以包封所述堆疊晶粒單元。在所述絕緣封裝體及所述堆疊晶粒單元上形成重佈線層，其中所述重佈線層電性連接到所述多個第一導電杆及所述多個第二導電杆。
30:第三半導體晶粒
31:第三導電杆
32:第三半導體基底
33:第三保護層
34、104、204:內連線層
36:第三導電接墊
38:第三鈍化層
100:第一半導體晶粒
102:第一半導體基底
106:第一導電接墊
108:第一鈍化層
110:第一導電杆
110-TS、210-TS:頂部
112:保護性材料
112’:保護層
112-TS、212-TS、306-TS、308-TS:頂表面
200:第二半導體晶粒
202:第二半導體基底
206:第二導電接墊
208:第二鈍化層
210:第二導電杆
212:第二保護層
302:載體
304:剝離層
306:貫穿絕緣層孔
308:絕緣材料
308’、560:絕緣封裝體
310、550:導電接墊
312:導電球
401:條帶
402:框架
510:基底
520:半導體晶片
530:接合打線
540:接墊
570:導電球
580:填充底膠
CD1、CD2:導電層
DAF:晶粒貼合膜
DI1、DI2:介電層
DL:分割線
IPD:整合被動元件
PK1A、PK1B、PK1C、PK1D、PK1E、PK1F、PK1G、PK1H、PK1I:封裝結構
PK2:第二封裝/封裝結構
POP1、POP2:疊層封裝結構
RDL1、RDL2:重佈線層
S1:第一表面
S2:第二表面
SU1、SU2:堆疊晶粒單元
WF1、WF2:半導體晶圓
結合附圖閱讀以下詳細說明，會最好地理解本發明實施 例的各個方面。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。
圖1A到圖1F是根據本揭露的一些示例性實施例的製作堆疊晶粒單元的方法的各個階段的示意性剖視圖。
圖2A到圖2G是根據本揭露的一些示例性實施例的製作封裝結構的方法的各個階段的示意性剖視圖。
圖3是根據本揭露的一些其他示例性實施例的封裝結構的示意性剖視圖。
圖4是根據本揭露的一些其他示例性實施例的封裝結構的示意性剖視圖。
圖5是根據本揭露的一些其他示例性實施例的封裝結構的示意性剖視圖。
圖6是根據本揭露的一些其他示例性實施例的封裝結構的示意性剖視圖。
圖7是根據本揭露的一些其他示例性實施例的封裝結構的示意性剖視圖。
圖8是根據本揭露的一些其他示例性實施例的封裝結構的示意性剖視圖。
圖9是根據本揭露的一些其他示例性實施例的封裝結構的示意性剖視圖。
圖10是根據本揭露的一些其他示例性實施例的封裝結構的示 意性剖視圖。
圖11是根據本揭露的一些示例性實施例的疊層封裝(package-on-package，PoP)結構的示意性剖視圖。
圖12是根據本揭露的一些其他示例性實施例的疊層封裝(PoP)結構的示意性剖視圖。
以下公開內容提供許多不同的實施例或實例以實施所提供主題的不同特徵。下文闡述元件及排列的具體實例以使本揭露簡明。當然，這些僅是實例並不旨在進行限制。舉例來說，在以下說明中，第二特徵形成在第一特徵之上或形成在第一特徵上可包括第二特徵與第一特徵形成為直接接觸的實施例，且還可包括額外特徵可形成在第二特徵與第一特徵之間使得第二特徵與第一特徵不可直接接觸的實施例。另外，本揭露可在各種實例中重複使用參考編號及/或字母。此重複是出於簡明及清晰目的，本質上並不規定所述的各種實施例及/或配置之間的關係。
此外，為便於說明起見，本文中可使用例如“在...下方”、“在...之下”、“下部”、“在...上”、“在...之上”、“上覆在”、“在...上方”、“上部”等空間相對用語來闡述一個元件或特徵與另外的元件或特徵之間的關係，如圖中所示。除了圖中所繪示的定向之外，所述空間相對用語還旨在囊括元件在使用或操作中的不同定向。可以其他方式對設備進行定向(旋轉90度或處於其他定向)，且 同樣地可對本文中所使用的空間相對描述符加以相應地解釋。
還可包括其他特徵及製程。舉例來說，可包括測試結構以輔助對三維(three dimensional，3D)封裝或三維積體電路(three dimensional integrated circuit，3DIC)元件進行驗證測試。所述測試結構可包括例如形成在重佈線層中或形成在基底上的測試接墊，所述測試接墊允許使用探針及/或探針卡等來對3D封裝或3DIC進行測試。可對中間結構及最終結構執行驗證測試。另外，本文中所公開的結構及方法可與測試方法結合使用，所述測試方法包括在中間階段驗證出已知良好的晶粒以提高良率且降低成本。
圖1A到圖1F是根據本揭露的一些示例性實施例的製作堆疊晶粒單元的方法的各個階段的示意性剖視圖。參考圖1A，提供具有多個第一半導體晶粒100的半導體晶圓WF1。如圖1A中所示，第一半導體晶粒100中的每一者包括第一半導體基底102、內連線層104、多個第一導電接墊106、第一鈍化層108及多個第一導電杆110(或穿孔)。在一些實施例中，第一半導體基底102可以是塊狀矽基底或絕緣體上矽(silicon-on-insulator，SOI)基底，且第一半導體基底102中還形成有主動元件(例如，電晶體等)且視情況形成有被動元件(例如，電阻器、電容器、電感器等)。內連線層104設置在第一半導體基底102上且可例如包括交替堆疊的多個金屬化層及層間電介質。第一導電接墊106可以是鋁接墊、銅接墊或其他適合的金屬接墊。第一導電接墊106例如是電 性連接到內連線層104。第一鈍化層108可以是氧化矽層、氮化矽層、氮氧化矽層或由任何適合的介電材料形成的介電層。第一鈍化層108覆蓋第一導電接墊106且具有多個接觸開口，其中第一鈍化層108的接觸開口部分地暴露出第一導電接墊106。在一些實施例中，第一導電杆110(穿孔)透過鍍覆形成在第一導電接墊106上。
參考圖1B，提供具有多個第二半導體晶粒200的另一半導體晶圓WF2。在示例性實施例中，第二半導體晶粒200中的每一者包括第二半導體基底202、內連線層204、多個第二導電接墊206、第二鈍化層208、多個第二導電杆210及第二保護層212。第二半導體晶粒200中的每一者的尺寸或大小是小於圖1A中所示的第一半導體晶粒100中的每一者的尺寸或大小。
在示例性實施例中，第二半導體基底202可以是塊狀矽基底或絕緣體上矽(SOI)基底，且第二半導體基底202中還形成有主動元件(例如，電晶體等)且視情況形成有被動元件(例如，電阻器、電容器、電感器等)。內連線層204設置在第二半導體基底202上，且可例如包括交替堆疊的多個金屬化層及層間電介質。第二導電接墊206可以是鋁接墊、銅接墊或其他適合的金屬接墊。第二導電接墊206例如電性連接到內連線層204。第二鈍化層208可以是氧化矽層、氮化矽層、氮氧化矽層或由任何適合的介電材料形成的介電層。第二鈍化層208覆蓋第二導電接墊206且具有多個接觸開口，其中第二鈍化層208的接觸開口部分地暴露出第 二導電接墊206。在一些實施例中，第二導電杆210透過鍍覆形成在第二導電接墊206上。在一些實施例中，第二保護層212形成在第二鈍化層208上，且覆蓋第二導電杆210以保護第二導電杆210。在某些實施例中，可沿著分割線DL分割半導體晶圓WF2以將所述多個第二半導體晶粒200彼此分離開。儘管對第二半導體晶粒200的說明類似於對第一半導體晶粒100的說明，但應注意，基於設計要求，其中所使用的材料可相同或有所不同。
參考圖1C，在將第二半導體晶粒200分離開之後，將第二半導體晶粒200中的至少一者堆疊在第一半導體晶粒100上。舉例來說，在由所述多個第一導電杆110(穿孔)環繞的區域中將第二半導體晶粒200的背面側固定或接合到第一半導體晶粒100中的每一者的第一鈍化層108上。在示例性實施例中，透過熔融接合(fusion bonding)將第二半導體晶粒200固定到第一鈍化層108上。在一些實施例中，在100℃到300℃的溫度範圍下執行熔融接合以產生將第二半導體晶粒200接合到第一半導體晶粒100中的每一者的第一鈍化層108上的化學鍵。在某些實施例中，化學鍵形成在第一鈍化層108的表面與第二半導體基底202的表面(第二半導體晶粒200的背面側)之間。在一些示例性實施例中，所形成的化學鍵是共價鍵。在一些替代實施例中，透過晶粒貼合膜(未示出)將第二半導體晶粒200固定或接合到第一半導體晶粒100中的每一者的第一鈍化層108上。
參考圖1D，在接合第二半導體晶粒200之後，在第一鈍 化層108的表面之上形成保護性材料112以覆蓋所述多個第一導電杆110(穿孔)及第二半導體晶粒200。在一些實施例中，保護性材料112還覆蓋第二半導體晶粒200的第二保護層212。在某些實施例中，保護性材料112填充到鄰近的第一導電杆110的間隙中，且填充第二半導體晶粒200與第一導電杆110之間的間隙。換句話說，第一導電杆110與第二半導體晶粒200之間嵌入保護性材料112且受到保護性材料112的良好保護。在一些實施例中，保護性材料112包含聚合物、介電材料、模塑化合物、樹脂材料等。然而，本揭露並不僅限於此，且可使用其他適合的保護性材料。在一個實施例中，保護性材料112(用於形成第一保護性層)與第二保護層212的材料不同。在另一實施例中，保護性材料112與第二保護層212包含相同的材料。本揭露並不僅限於此。
參考圖1E，在下一步驟中，透過機械研磨製程及/或化學機械拋光(chemical mechanical polishing，CMP)製程研磨或拋光第二半導體晶粒200的保護性材料112及第二保護層212，直到顯露出第一導電杆110(穿孔)的頂部110-TS及第二導電杆210的頂部210-TS為止。在一些實施例中，將第一導電杆110(穿孔)及第二導電杆210部分地拋光，以使得第一導電杆110(穿孔)的頂部110-TS及第二導電杆210的頂部210-TS與第二保護層212的頂表面212-TS齊平。在一些實施例中，對保護性材料112進行拋光以形成保護層112’(第一保護層)。在拋光製程之後，保護層112’的頂表面112-TS與第一導電杆110(穿孔)的頂部110-TS、 第二導電杆210的頂部210-TS及第二保護層212的頂表面212-TS共面。此外，由於是在不同的步驟中形成保護層112’及第二保護層212，因此應注意，不論是使用相同的材料還是不同的材料，保護層112’的表面與第二保護層212的表面之間皆將會存在介面。
參考圖1F，在拋光製程之後，可沿著分割線DL(圖1E中示出)分割半導體晶圓WF1以將所述多個第一半導體晶粒100彼此分離開，從而形成堆疊晶粒單元SU1。在示例性實施例中，堆疊晶粒單元SU1包括堆疊在第一半導體晶粒100上的至少一個第二半導體晶粒200。在某些實施例中，第二半導體晶粒200嵌入在第一半導體晶粒100的保護層112’內且被所述多個第一導電杆110(穿孔)橫向環繞。儘管僅示出一個第二半導體晶粒200堆疊在第一半導體晶粒100上，但本揭露並不僅限於此。在一些其他實施例中，可基於設計要求來調整堆疊在第一半導體晶粒100上的半導體晶粒的數目。至此，實現根據本揭露的一些示例性實施例的堆疊晶粒單元SU1。
圖2A到圖2G是根據本揭露的一些示例性實施例的製作封裝結構的方法的各個階段的示意性剖視圖。參考圖2A，提供載體302。在一些實施例中，載體302可以是承載半導體晶圓或重構的晶圓以供進行封裝結構製造方法的玻璃載體或任何適合的載體。在一些實施例中，載體302塗布有剝離層304。剝離層304的材料可以是適合於接合載體302及從設置在載體302上的上方層或任何晶圓剝離載體302的任何材料。
在一些實施例中，剝離層304可包含由介電材料製成的介電材料層，所述介電材料包括任何適合的聚合物系介電材料(例如，苯環丁烷(“BCB”)、聚苯並噁唑(“PBO”))。在替代實施例中，剝離層304可包括由在受熱時會失去黏著性的環氧樹脂系熱釋放材料製成的介電材料層，例如光熱轉換(light-to-heat-conversion，LTHC)釋放塗布膜。在另一實施例中，剝離層304可包括由在暴露於UV光下時會失去黏著性的紫外線(ultra-violet，UV)膠製成的介電材料層。在某些實施例中，剝離層304可以液體的形式被施配並被固化，或可以是層壓到載體302上的層壓膜，或可以是諸如此類的材料。剝離層304的頂表面與接觸載體302的底表面相對，可以是齊平的且可具有高共面程度。在某些實施例中，剝離層304是例如具有良好的耐化學性的LTHC層，且此層使得能夠透過施加雷射照射來從載體302進行室溫剝離，然而本揭露並不僅限於此。
在替代實施例中，可在剝離層304上塗布緩衝層(未示出)，其中剝離層304夾在緩衝層與載體302之間，且緩衝層的頂表面也可具備高共面程度。在一些實施例中，緩衝層可以是介電材料層。在一些實施例中，緩衝層可以是由聚醯亞胺、PBO、BCB或任何其他適合的聚合物系介電材料製成的聚合物層。在一些實施例中，緩衝層可以是味之素構成膜(Ajinomoto Buildup Film，ABF)、阻焊膜(Solder Resist，SR)等。換句話說，緩衝層是選用性的且可基於需求省略，因此本揭露並不僅限於此。
如圖2A中進一步說明，在載體302之上形成重佈線層RDL1。舉例來說，在剝離層304上形成重佈線層RDL1，且重佈線層RDL1的形成包括依序地交替形成一個或多個介電層DI1以及一個或多個導電層CD1。在一些實施例中，重佈線層RDL1包括兩個介電層DI1及一個導電層CD1，如圖2A中所示，其中導電層CD1夾在介電層DI1之間。然而，本揭露並不僅限於此。重佈線層RDL1中所包括的介電層DI1及導電層CD1的數目並不僅限於此，且可基於需求來決定並選擇。舉例來說，介電層DI1及導電層CD1的數目可以是一個或一個以上。
在某些實施例中，介電層DI1的材料可以是聚醯亞胺、聚苯並噁唑(PBO)、苯環丁烷(BCB)、氮化物(例如氮化矽)、氧化物(例如氧化矽)、磷矽酸鹽玻璃(phosphosilicate glass，PSG)、硼矽酸鹽玻璃(borosilicate glass，BSG)、摻雜硼的磷矽酸鹽玻璃(boron-doped phosphosilicate glass，BPSG)、其組合等，可使用微影及/或蝕刻製程將介電層DI1的材料圖案化。在一些實施例中，介電層DI1的材料可透過適合的製作技術形成，例如旋轉塗布、化學氣相沉積(chemical vapor deposition，CVD)、等離子加強化學氣相沉積(plasma-enhanced chemical vapor deposition，PECVD)等。本揭露並不僅限於此。
在一些實施例中，導電層CD1的材料可由透過電鍍或沉積形成的導電材料(例如，鋁、鈦、銅、鎳、鎢及/或其合金)製成，可使用微影及蝕刻製程將所述導電層的材料圖案化。在一些 實施例中，導電層CD1可以是圖案化的銅層或其他適合的圖案化的金屬層。在本說明通篇，用語“銅”旨在包括實質上純元素銅、含有不可避免的雜質的銅及含有微量元素(例如，鉭、銦、錫、鋅、錳、鉻、鈦、鍺、鍶、鉑、鎂、鋁或鋯等)的銅合金。
參考圖2B，在形成重佈線層RDL1之後，在重佈線層RDL1上且在載體302之上安置圖1F中所獲得的至少一個堆疊晶粒單元SU1、及多個貫穿絕緣層孔306。在一些實施例中，貫穿絕緣層孔306是整合扇出型(integrated fan-out，“InFO”)穿孔。在一個實施例中，貫穿絕緣層孔306的形成包括：形成具有開口的罩幕圖案(未示出)，然後透過電鍍或沉積形成金屬材料(未示出)來填充所述開口，並移除所述罩幕圖案以在重佈線層RDL1上形成貫穿絕緣層孔306。在某些實施例中，貫穿絕緣層孔306填充到顯露出重佈線層RDL1的導電層CD1的通孔開口中，以使得貫穿絕緣層孔306可電性連接到重佈線層RDL1。在一些實施例中，所述罩幕圖案的材料可包括正性光阻或負性光阻。在一個實施例中，貫穿絕緣層孔306的材料可包括金屬材料，例如銅或銅合金等。然而，本揭露並不僅限於此。
在替代實施例中，貫穿絕緣層孔306可透過以下步驟形成：在重佈線層RDL1上形成晶種層(未示出)；形成具有開口的罩幕圖案，所述開口暴露出晶種層的一些部分；透過鍍覆在晶種層的暴露出部分上形成金屬材料以形成貫穿絕緣層孔306；移除罩幕圖案；且然後移除晶種層的被貫穿絕緣層孔306暴露出的部分。 舉例來說，晶種層可以是鈦/銅複合層。為簡明起見，圖2B中僅示出了兩個貫穿絕緣層孔306。然而應注意，貫穿絕緣層孔306的數目並不僅限於此，且可基於要求來選擇。
此外，在一些實施例中，至少一個堆疊晶粒單元SU1被放置在重佈線層RDL1上。在某些實施例中，透過將第一半導體晶粒100的第一半導體基底102貼合到重佈線層RDL1的介電層DI1來將堆疊晶粒單元SU1放置在重佈線層RDL1上。舉例來說，透過晶粒貼合膜(未示出)將第一半導體基底102貼合到重佈線層RDL1。透過使用晶粒貼合膜來確保堆疊晶粒單元SU1與重佈線層RDL1之間較好地黏著。在示例性實施例中，僅示出一個堆疊晶粒單元SU1。然而應注意，放置在重佈線層RDL1上的堆疊晶粒單元SU1的數目並不僅限於此，且此可基於設計要求來調整。
在一些實施例中，當一個以上堆疊晶粒單元SU1放置在重佈線層RDL1上時，可將堆疊晶粒單元SU1排列成陣列，且當堆疊晶粒單元SU1排列成陣列時，可將貫穿絕緣層孔306分類成群組。堆疊晶粒單元SU1的數目可與貫穿絕緣層孔306的群組的數目對應。在示例性實施例中，可在形成貫穿絕緣層孔306之後，將堆疊晶粒單元SU1拾放在重佈線層RDL1上。然而，本揭露並不僅限於此。在一些替代實施例中，可在形成貫穿絕緣層孔306之前將堆疊晶粒單元SU1拾放在重佈線層RDL1上。
此外，在示例性實施例中，堆疊晶粒單元SU1至少包括堆疊在第一半導體晶粒100上的第二半導體晶粒200。舉例來說， 第一半導體晶粒100及第二半導體晶粒200可從以下選擇：專用積體電路(application-specific integrated circuit，ASIC)晶片、類比晶片(例如，無線射頻晶片)、數位晶片(例如，基帶晶片)、整合被動元件(integrated passive device，IPD)、電壓調節器晶片、感測器晶片、記憶體晶片等。本揭露並不僅限於此。
參考圖2C，在下一步驟中，在重佈線層RDL1上且在堆疊晶粒單元SU1之上形成絕緣材料308。在一些實施例中，絕緣材料308是透過例如模壓成型製程形成，所述模壓成型製程填充堆疊晶粒單元SU1與絕緣穿孔306之間的間隙以包封堆疊晶粒單元SU1。絕緣材料308也填充鄰近的貫穿絕緣層孔306之間的間隙以包封貫穿絕緣層孔306。在此階段，第一導電杆110(穿孔)、保護層112’、第二導電杆210及第二保護層212被絕緣材料308包封且受到絕緣材料308的良好保護。換句話說，第一導電杆110(穿孔)、第一半導體晶粒100的保護層112’、以及第二導電杆210、第二半導體晶粒200的第二保護層212未顯露出且未受到絕緣材料308的良好保護。
在一些實施例中，絕緣材料308包括聚合物(例如，環氧樹脂、酚醛樹脂、含矽樹脂或其他適合的樹脂)、具有低電容率(Dk)及低介質損耗值(Df)性質的介電材料或其他適合的材料。在替代實施例中，絕緣材料308可包括可接受的絕緣密封材料。在一些實施例中，絕緣材料308還可包括無機填充物或無機化合物(例如，二氧化矽、黏土等)，所述無機填充物或無機化合物可 添加在絕緣材料308中以優化絕緣材料308的熱膨脹係數(CTE)。本揭露並不僅限於此。
參考圖2D，在一些實施例中，部分地移除絕緣材料308以暴露出貫穿絕緣層孔306、第一導電杆110(穿孔)及第二導電杆210。在一些實施例中，透過平面化步驟來研磨或拋光絕緣材料308。舉例來說，透過機械研磨製程及/或化學機械拋光(CMP)製程執行平面化步驟，直到顯露出第一導電杆110(穿孔)的頂部110-TS及第二導電杆210的頂部210-TS為止。在一些實施例中，可部分地拋光貫穿絕緣層孔306，以使得貫穿絕緣層孔306的頂表面306-TS與第一導電杆110(穿孔)的頂部110-TS及第二導電杆210的頂部210-TS齊平。換句話說，還可輕微研磨/拋光貫穿絕緣層孔306、第一導電杆110(穿孔)及第二導電杆210。
在所示的實施例中，對絕緣材料308進行拋光以形成絕緣封裝體308’。在一些實施例中，絕緣封裝體308’的頂表面308-TS、貫穿絕緣層孔306的頂表面306-TS、第一導電杆110(穿孔)的頂部110-TS、保護層112’的頂表面112-TS、第二導電杆210的頂部210-TS、第二保護層212的頂表面212-TS彼此共面且齊平。在一些實施例中，在進行機械研磨或化學機械拋光(CMP)步驟之後，可視情況執行清潔步驟。舉例來說，執行清潔步驟來清潔並移除平面化步驟所產生的殘餘物。然而，本揭露並不僅限於此，且可透過任何其他適合的方法執行平面化步驟。
參考圖2E，在進行研磨/拋光步驟之後，在絕緣封裝體 308’、貫穿絕緣層孔306及堆疊晶粒單元SU1上形成重佈線層RDL2。舉例來說，絕緣封裝體308’具有第一表面S1及與第一表面S1相對的第二表面S2，其中重佈線層RDL2形成在絕緣封裝體308’的第一表面S1上，且重佈線層RDL1形成在第二表面S2上。在一些實施例中，重佈線層RDL2透過第一導電杆110及第二導電杆210分別電性連接到貫穿絕緣層孔306且電性連接到第一半導體晶粒100及第二半導體晶粒200。在某些實施例中，重佈線層RDL2將第一半導體晶粒100的第一導電杆110電性連接到第二半導體晶粒200的第二導電杆210。換句話說，第一半導體晶粒100與第二半導體晶粒200透過第一導電杆110、重佈線層RDL2及第二導電杆210電性連接。在一些實施例中，堆疊晶粒單元SU1透過重佈線層RDL2電性連接到貫穿絕緣層孔306。
此外，在一些實施例中，重佈線層RDL2的形成包括依序地交替形成一個或多個介電層DI2以及一個或多個導電層CD2。在某些實施例中，導電層CD2夾在介電層DI2之間。儘管本文中僅示出了三層導電層CD2及四層介電層DI2，然而本揭露的範圍並不受實施例限制。在其他實施例中，可基於產品要求來調整導電層CD2及介電層DI2的數目。在一些實施例中，導電層CD2電性連接到第一半導體晶粒100的第一導電杆110(穿孔)，且電性連接到第二半導體晶粒200的第二導電杆210。此外，導電層CD2電性連接到貫穿絕緣層孔306。在一些實施例中，重佈線層RDL2的介電層DI2及導電層CD2的材料與關於重佈線層RDL1 所述的介電層DI1及導電層CD1的材料類似。因此，本文中將不再對介電層DI2及導電層CD2加以贅述。
在形成重佈線層RDL2之後，可在導電層CD2的最頂層的暴露出頂表面上設置多個導電接墊310以用於與導電球電性連接。在某些實施例中，導電接墊310例如是用於球安裝的球下金屬(under-ball metallurgy，UBM)圖案。如圖2E中所示，導電接墊310形成在重佈線層RDL2上且電性連接到重佈線層RDL2。在一些實施例中，導電接墊310的材料可包括銅、鎳、鈦、鎢或其合金等，且可例如透過電鍍製程形成。導電接墊310的數目並不限於本揭露，且可基於設計佈局來做出選擇。在一些替代實施例中，可省略導電接墊310。換句話說，在後續步驟中形成的導電球312可直接設置在重佈線層RDL2上。
在形成導電接墊310之後，在導電接墊310上且在重佈線層RDL2之上設置多個導電球312。在一些實施例中，可透過植球製程或回焊製程在導電接墊310上設置導電球312。在一些實施例中，導電球312是例如焊球或球柵陣列(ball grid array，BGA)球。在一些實施例中，導電球312透過導電接墊310連接到重佈線層RDL2。在某些實施例中，導電球312中的一些可透過重佈線層RDL2電性連接到堆疊晶粒單元SU1。此外，導電球312中的一些可透過重佈線層RDL2電性連接到貫穿絕緣層孔306。導電球312的數目並不限於本揭露，且可基於導電接墊310的數目決定並選擇。
參考圖2F，在形成重佈線層RDL2且放置導電球312之後，可將圖2E中所示的結構倒置並將其貼合到框架402所支撐的條帶401(例如，分割條帶)。如圖2F中所示，將載體302與重佈線層RDL1剝離並分離開。在一些實施例中，剝離製程包括將光(例如，雷射或UV光)投射在剝離層304(例如，LTHC釋放層)上，以使得可容易地將載體302與剝離層304一起移除。在剝離步驟期間，使用條帶401先穩固封裝結構，再剝離載體302及剝離層304。在剝離製程之後，會顯露出或暴露出重佈線層RDL1的背面側表面。在某些實施例中，會顯露出或暴露出重佈線層RDL1的介電層DI1。
參考圖2G，在剝離製程之後，沿著分割線DL(圖2F中示出)執行分割製程以將整個晶圓結構(切割穿過絕緣封裝體308’及重佈線層RDL1及重佈線層RDL2)切割成多個封裝結構PK1A。在示例性實施例中，分割製程是包括機械刀鋸割或雷射切割在內的晶圓分割製程。在後續製程中，可基於要求將分離開的封裝結構PK1A例如設置到電路基底上或安置到其他元件上。
圖3是根據本揭露的一些其他示例性實施例的封裝結構的示意性剖視圖。圖3中所示的封裝結構PK1B與圖2G中所示的封裝結構PK1A類似，因此使用相同的參考編號來指代相同或相似的部件，且本文中將不再對其加以詳細說明。實施例之間的差異在於，在封裝結構PK1B中將第二半導體晶粒200固定到堆疊晶粒單元SU1中的第一半導體晶粒100。在先前實施例中，透過 熔融接合將第二半導體晶粒200固定到第一鈍化層108上。然而，本揭露並不僅限於此。參考圖3，在一些實施例中，可使用晶粒貼合膜DAF將第二半導體晶粒200固定到第一半導體晶粒100的第一鈍化層108上。換句話說，晶粒貼合膜DAF位於第二半導體晶粒200的第二半導體基底202與第一半導體晶粒100的第一鈍化層108之間。
圖4是根據本揭露的一些其他示例性實施例的封裝結構的示意性剖視圖。圖4中所示的封裝結構PK1C與圖2G中所示的封裝結構PK1A類似，因此使用相同的參考編號來指代相同或相似的部件，且本文中將不再對其加以詳細說明。實施例之間的差異在於封裝結構PK1C的第二半導體晶粒200省略了第二保護層212。參考圖4，第二半導體晶粒200具有暴露出或顯露出的第二導電杆210。因此，在將第二半導體晶粒200固定到第一半導體晶粒100上且形成保護層112’之後，保護層112’將覆蓋且實體接觸第二半導體晶粒200的第二導電杆210。換句話說，保護層112’足以保護第一導電杆110(穿孔)及第二導電杆210兩者。此外，由於省略了第二保護層212，因此封裝結構PK1C中也將不存在保護層112’的表面與第二保護層212的表面之間的介面。
圖5是根據本揭露的一些其他示例性實施例的封裝結構的示意性剖視圖。圖5中所示的封裝結構PK1D與圖2G中所示的封裝結構PK1A類似，因此使用相同的參考編號來指代相同或相似的部件，且本文中將不再對其加以詳細說明。所述實施例之間 的差異在於固定到第一半導體晶粒100上的第二半導體晶粒200的數目。參考圖5，兩個第二半導體晶粒200固定在第一半導體晶粒100的第一鈍化層108上。在一些實施例中，兩個第二半導體晶粒200嵌入在第一半導體晶粒100的保護層112’中。此外，第二半導體晶粒200中的每一者被所述多個第一導電杆110(穿孔)環繞。在某些實施例中，由於第一導電杆110位於第二半導體晶粒200之間，因此第二半導體晶粒200中的一者與第二半導體晶粒200中的另一者是分離開的。此外，所述兩個第二半導體晶粒200位於同一平面上且位於第一半導體晶粒100的同一表面上，且彼此實質上共面。
圖6是根據本揭露的一些其他示例性實施例的封裝結構的示意性剖視圖。圖6中所示的封裝結構PK1E與圖2G中所示的封裝結構PK1A類似，因此使用相同的參考編號來指代相同或相似的部件，且本文中將不再對其加以詳細說明。所述實施例之間的差異在於封裝結構PK1E還包括第三半導體晶粒30。參考圖6，在一些實施例中，第三半導體晶粒30鄰近于第二半導體晶粒200而設置在第一半導體晶粒100的第一鈍化層108上。在一些實施例中，第三半導體晶粒30的尺寸小於第二半導體晶粒200及第一半導體晶粒100的尺寸。然而，本揭露並不僅限於此，且可基於要求選擇第三半導體晶粒30的尺寸。在某些實施例中，第三半導體晶粒30、第二半導體晶粒200及第一半導體晶粒100是不同類型的半導體晶粒。然而，本揭露並不僅限於此。在替代實施例中， 第三半導體晶粒30可以是與第一半導體晶粒100或第二半導體晶粒200中的任一者相同類型的半導體晶粒，僅尺寸或大小有所不同。
在示例性實施例中，第三半導體晶粒30包括第三半導體基底32、內連線層34、多個第三導電接墊36、第三鈍化層38、多個第三導電杆31及第三保護層33。第三半導體基底32可以是塊狀矽基底或絕緣體上矽(SOI)基底，且第三半導體基底32中還形成有主動元件(例如，電晶體等)且視情況包括被動元件(例如，電阻器、電容器、電感器等)。內連線層34設置在第三半導體基底32上且可例如包括交替堆疊的多個金屬化層及層間電介質。第三導電接墊36可以是鋁接墊、銅接墊或其他適合的金屬接墊。第三導電接墊36例如電性連接到內連線層34。第三鈍化層38可以是氧化矽層、氮化矽層、氮氧化矽層或由任何適合的介電材料形成的介電層。第三鈍化層38覆蓋第三導電接墊36且具有多個接觸開口，其中第三鈍化層38的接觸開口部分地暴露出第三導電接墊36。在一些實施例中，透過鍍覆在第三導電接墊36上形成第三導電杆31。在一些實施例中，第三保護層33形成在第三鈍化層38上，且覆蓋第三導電杆31以保護第三導電杆31。此外，如圖6中所示，第三半導體晶粒30嵌入在第一半導體晶粒100的保護層112’中，且被所述多個第一導電杆110(穿孔)環繞。另外，重佈線層RDL2電性連接到第三半導體晶粒30的第三導電杆31。在某些實施例中，第三半導體晶粒30透過重佈線層RDL2電性連 接到第一半導體晶粒100及/或第二半導體晶粒。
圖7是根據本揭露的一些其他示例性實施例的封裝結構的示意性剖視圖。圖7中所示的封裝結構PK1F與圖6中所示的封裝結構PK1E類似，因此使用相同的參考編號來指代相同或相似的部件，且本文中將不再對其加以詳細說明。所述實施例之間的差異在於第三半導體晶粒30的位置。參考圖7，在堆疊晶粒單元SU1中，第三半導體晶粒30設置在第二半導體晶粒200上。第三半導體晶粒30的尺寸小於第二半導體晶粒200及第一半導體晶粒100的尺寸。此外，在某些實施例中，第三半導體晶粒30設置在第二半導體晶粒200的第二鈍化層208上，且被第二導電杆210環繞。另一方面，第二半導體晶粒200還設置在第一半導體晶粒100的第一鈍化層108上，且被第一導電杆110(穿孔)環繞。
圖8是根據本揭露的一些其他示例性實施例的封裝結構的示意性剖視圖。圖8中所示的封裝結構PK1G與圖7中所示的封裝結構PK1F類似，因此使用相同的參考編號來指代相同或相似的部件，且本文中將不再對其加以詳細說明。所述實施例之間的差異在於，在封裝結構PK1G中兩個堆疊晶粒單元(SU1/SU2)包括在封裝結構PK1G中。參考圖8，在示例性實施例中，包括堆疊晶粒單元SU1及堆疊晶粒單元SU2。堆疊晶粒單元SU1中的堆疊半導體晶粒的數目與堆疊晶粒單元SU2中的堆疊半導體晶粒的數目不同。舉例來說，堆疊晶粒單元SU1包括堆疊在一起的第一半導體晶粒100、第二半導體晶粒200及第三半導體晶粒30，而堆 疊晶粒單元SU2包括第一半導體晶粒100及第二半導體晶粒200。儘管本文中僅說明了兩個堆疊晶粒單元(SU1/SU2)，然而應注意，封裝結構中的每一者的堆疊晶粒單元的數目並不僅限於此。舉例來說，在替代實施例中，封裝結構可包括兩個或更多個堆疊晶粒單元。此外，堆疊晶粒單元中的每一者中的半導體晶粒的數目及排列可基於設計要求而相同或有所不同。
圖9是根據本揭露的一些其他示例性實施例的封裝結構的示意性剖視圖。圖9中所示的封裝結構PK1H與圖2G中所示的封裝結構PK1A類似，因此使用相同的參考編號來指代相同或相似的部件，且本文中將不再對其加以詳細說明。所述實施例之間的差異在於，封裝結構PK1H中還包括整合被動元件IPD。參考圖9，在一些實施例中，整合被動元件IPD可設置在第一半導體晶粒100的第一鈍化層108上且嵌入在保護層112’內。整合被動元件IPD可與第二半導體晶粒200設置在第一半導體晶粒100的同一表面上且位於同一平面上，且可電性連接到重佈線層RDL2。此外，第一導電杆110環繞第二半導體晶粒200及整合被動元件IPD兩者。
圖10是根據本揭露的一些其他示例性實施例的封裝結構的示意性剖視圖。圖10中所示的封裝結構PK1I與圖2G中所示的封裝結構PK1A類似，因此使用相同的參考編號來指代相同或相似的部件，且本文中將不再對其加以詳細說明。所述實施例之間的差異在於封裝結構PK1I省略了重佈線層RDL1。參考圖10，在 一些實施例中，介電層DL代替重佈線層RDL1設置在絕緣封裝體308’的第二表面S2上。在某些實施例中，介電層DL具有顯露出貫穿絕緣層孔306的開口，而介電層DL的開口中還設置有導電端子120，且導電端子120連接到貫穿絕緣層孔306。換句話說，實現無重佈線層RDL1而具有雙側端子的封裝結構PK1I。在替代實施例中，可省略導電端子120，且介電層DL可覆蓋絕緣封裝體308’的背面側(第二表面S2)及堆疊晶粒單元SU1的背面側。
圖11是根據本揭露的一些示例性實施例的疊層封裝(PoP)結構的示意性剖視圖。參考圖11，在製作第一封裝(例如，圖2G中所示的封裝結構PK1A)之後，可將第二封裝PK2堆疊在封裝結構PK1A(第一封裝)上以形成疊層封裝(PoP)結構。如圖11中所示，第二封裝PK2電性連接到封裝結構PK1A(第一封裝)的導電層CD1。在一些實施例中，第二封裝PK2具有基底510、多個半導體晶片520，所述多個半導體晶片520安裝在基底510的一個表面(例如，頂表面)上且彼此堆疊。在一些實施例中，使用接合打線530來使得半導體晶片520與接墊540(例如，接合接墊)之間電性連接。在一些實施例中，絕緣封裝體560形成為包封半導體晶片520及接合打線530以保護這些元件。在一些實施例中，可使用貫穿絕緣層孔(未示出)來使得接墊540與位於基底510的另一表面(例如底表面)上的導電接墊550(例如，接合接墊)電性連接。在某些實施例中，導電接墊550透過這些貫穿絕緣層孔(未示出)電性連接到半導體晶片520。在一些實施例 中，封裝結構PK2的導電接墊550電性連接到導電球570。此外，導電球570電性連接到封裝結構PK1A(第一封裝)中的重佈線層RDL1(背面側重佈線層)的導電層CD1。在一些實施例中，還提供填充底膠580來填充導電球570之間的空間以保護導電球570。在將第二封裝PK2堆疊在封裝結構PK1A(第一封裝)上且提供其之間的電性連接之後，可製作出疊層封裝結構POP1。
圖12是根據本揭露的一些其他示例性實施例的疊層封裝(PoP)結構的示意性剖視圖。圖12中所示的疊層封裝結構POP2與圖11中所示的疊層封裝結構POP1類似，因此使用相同的參考編號來指代相同或相似的部件，且本文中將不再對其加以詳細說明。所述實施例之間的差異在於疊層封裝結構POP2省略了重佈線層RDL1。參考圖12，在一些實施例中，由於省略了重佈線層RDL1，因此第二封裝PK2的導電球570可直接連接到封裝結構PK1A(第一封裝)的貫穿絕緣層孔306以形成疊層封裝結構POP2。
在上述實施例中，封裝結構或疊層封裝結構中包括至少一個堆疊晶粒單元。堆疊晶粒單元包括嵌入在第一半導體晶粒的保護層內的至少一個第二半導體晶粒，其中第一導電杆環繞第二半導體晶粒。此外，重佈線層分別電性連接到第一半導體晶粒的第一導電杆及第二半導體晶粒的第二導電杆。由於第二半導體晶粒堆疊在第一半導體晶粒上且嵌入在第一半導體晶粒中，因此可縮短半導體晶粒之間的通信路徑(透過重佈線層)。總的來說，封裝結構的性能及效率可得到提高。
根據本揭露的一些實施例，提供一種封裝結構，所述封裝結構包括：第一半導體晶粒、至少一個第二半導體晶粒、絕緣封裝體及重佈線層。所述第一半導體晶粒具有多個第一導電杆及橫向環繞所述多個第一導電杆的第一保護層。所述至少一個第二半導體晶粒嵌入在所述第一半導體晶粒的所述第一保護層中且被所述多個第一導電杆環繞，其中所述至少一個第二半導體晶粒包括多個第二導電杆。所述絕緣封裝體包封所述第一半導體晶粒及所述至少一個第二半導體晶粒。所述重佈線層設置在所述絕緣封裝體上且與所述多個第一導電杆及所述多個第二導電杆連接，其中所述第一半導體晶粒與所述至少一個第二半導體晶粒透過所述多個第一導電杆、所述重佈線層及所述多個第二導電杆電性連接。
在一些實施例中，所述多個第一導電杆的頂部與所述多個第二導電杆的頂部齊平。在一些實施例中，所述的封裝結構還包括穿透過所述絕緣封裝體的多個貫穿絕緣層孔，且背面側重佈線層設置在所述絕緣封裝體上且與所述多個貫穿絕緣層孔連接。
根據本揭露的一些其他實施例，提供一種疊層封裝結構，所述疊層封裝結構包括第一封裝及第二封裝。所述第二封裝包括電性連接到所述第一封裝的多個導電球。所述第一封裝包括至少一個堆疊晶粒單元、絕緣封裝體及重佈線層。所述至少一個堆疊晶粒單元包括第一半導體晶粒及至少一個第二半導體晶粒。所述第一半導體晶粒具有：多個第一導電接墊；第一鈍化層，覆蓋所述多個第一導電接墊的一些部分；多個穿孔，設置在所述第 一鈍化層上且電性連接到所述多個第一導電接墊；及保護層，設置在所述第一鈍化層上且覆蓋所述多個穿孔。所述至少一個第二半導體晶粒堆疊在所述第一半導體晶粒上，其中所述至少一個第二半導體晶粒包括：多個第二導電接墊；第二鈍化層，覆蓋所述多個第二導電接墊的一些部分；及多個導電杆，設置在所述第二鈍化層上且電性連接到所述多個第二導電接墊，其中所述第一半導體晶粒的所述保護層覆蓋所述至少一個第二半導體晶粒。所述絕緣封裝體具有第一表面及與所述第一表面相對的第二表面，其中所述絕緣封裝體包封所述至少一個堆疊晶粒單元。所述重佈線層設置在所述絕緣封裝體的所述第一表面上且電性連接到所述多個穿孔及所述多個導電杆。
在一些實施例中，兩個所述第二半導體晶粒設置在所述第一鈍化層上，且所述多個穿孔環繞兩個所述第二半導體晶粒。在一些實施例中，所述的疊層封裝結構還包括被動元件，所述被動元件設置在所述第一半導體晶粒的所述第一鈍化層上且嵌入在所述保護層中。在一些實施例中，所述至少一個第二半導體晶粒的背面側透過熔融接合貼合到所述第一半導體晶粒的所述第一鈍化層。在一些實施例中，所述第一封裝包括至少兩個堆疊晶粒單元，且所述堆疊晶粒單元中的一者中的堆疊半導體晶粒的數目不同於所述堆疊晶粒單元中的另一者中的堆疊半導體晶粒的數目。
在本揭露的又一實施例中，闡述一種製作封裝結構的方法。所述方法包括以下步驟。形成堆疊晶粒單元。所述形成所述 堆疊晶粒單元的步驟包括以下步驟。提供具有多個第一半導體晶粒的半導體晶圓，其中所述多個第一半導體晶粒中的每一者包括第一鈍化層及形成在所述第一鈍化層上的多個第一導電杆。在由所述多個第一導電杆環繞的區域中將第二半導體晶粒固定到所述多個第一半導體晶粒中的每一者的所述第一鈍化層上，其中所述第二半導體晶粒包括多個第二導電杆。在所述多個第一半導體晶粒中的每一者的所述第一鈍化層的表面上形成第一保護層，以覆蓋所述多個第一導電杆及所述第二半導體晶粒。分割所述半導體晶圓以分離開所述多個第一半導體晶粒來形成所述堆疊晶粒單元。將所述堆疊晶粒單元接合到載體上。形成絕緣封裝體以包封所述堆疊晶粒單元。在所述絕緣封裝體及所述堆疊晶粒單元上形成重佈線層，其中所述重佈線層電性連接到所述多個第一導電杆及所述多個第二導電杆。
在一些實施例中，將所述第二半導體晶粒固定到所述多個第一半導體晶粒中的每一者的所述第一鈍化層上包括：在100℃到300℃的溫度範圍下將所述第二半導體晶粒熔融接合到所述第一鈍化層上，以在所述第二半導體晶粒的背面側與所述第一鈍化層之間產生化學鍵。在一些實施例中，是透過晶粒貼合膜將所述第二半導體晶粒固定到所述多個第一半導體晶粒中的每一者的所述第一鈍化層上。在一些實施例中，所述的製作封裝結構的方法還包括對所述堆疊晶粒單元執行研磨製程，以使得所述第一保護層的頂表面、所述多個第一導電杆的頂表面及所述多個第二導 電杆的頂表面彼此齊平。在一些實施例中，所述的製作封裝結構的方法還包括在所述第二半導體晶粒的第二鈍化層上形成第二保護層以覆蓋所述多個第二導電杆，其中所述第一保護層覆蓋所述第二保護層。
上述內容概述了數個實施例的特徵，以使所屬領域的技術人員可更好地理解本揭露的各方面。所屬領域的技術人員應瞭解，其可容易地使用本揭露作為設計或修改其他製程及結構以實現與本文中所介紹的實施例相同的目的及/或達成相同的優勢的基礎。所屬領域的技術人員還應意識到這些等效構造並不背離本揭露的精神及範圍，且其可在不背離本揭露的精神及範圍的情況下在本文中做出各種變化、代替及更改。
100:第一半導體晶粒
102:第一半導體基底
110:第一導電杆
112’:保護層
200:第二半導體晶粒
210:第二導電杆
212:第二保護層
306:貫穿絕緣層孔
308’:絕緣封裝體
310:導電接墊
312:導電球
CD1、CD2:導電層
DI1、DI2:介電層
PK1A:封裝結構
RDL1、RDL2:重佈線層
S1:第一表面
S2:第二表面
SU1:堆疊晶粒單元

Claims (9)

  1. 一種封裝結構，包括：第一半導體晶粒，具有多個第一導電杆及橫向環繞所述多個第一導電杆的第一保護層；至少一個第二半導體晶粒，嵌入在所述第一半導體晶粒的所述第一保護層中且被所述多個第一導電杆環繞，其中所述至少一個第二半導體晶粒包括多個第二導電杆以及橫向環繞所述多個第二導電杆的第二保護層，且所述至少一個第二半導體晶粒的所述第二保護層位於所述多個第二導電杆與所述第一半導體晶粒的所述第一保護層之間；絕緣封裝體，包封所述第一半導體晶粒及所述至少一個第二半導體晶粒；以及重佈線層，設置在所述絕緣封裝體上且與所述多個第一導電杆及所述多個第二導電杆連接，其中所述第一半導體晶粒與所述至少一個第二半導體晶粒透過所述多個第一導電杆、所述重佈線層及所述多個第二導電杆電性連接。
  2. 如申請專利範圍第1項所述的封裝結構，其中所述至少一個第二半導體晶粒包括嵌入在所述第一半導體晶粒的所述第一保護層中的兩個或更多個第二半導體晶粒，且所述多個第一導電杆環繞所述兩個或更多個第二半導體晶粒。
  3. 如申請專利範圍第1項所述的封裝結構，還包括晶粒貼合膜，所述晶粒貼合膜位於所述至少一個第二半導體晶粒的背 面側與所述第一半導體晶粒的鈍化層之間，且所述至少一個第二半導體晶粒透過所述晶粒貼合膜貼合到所述第一半導體晶粒的所述鈍化層。
  4. 如申請專利範圍第1項所述的封裝結構，其中所述至少一個第二半導體晶粒的背面側透過熔融接合貼合到所述第一半導體晶粒的鈍化層。
  5. 一種疊層封裝結構，包括：第一封裝及堆疊在所述第一封裝上的第二封裝，其中所述第二封裝包括電性連接到所述第一封裝的多個導電球，其中所述第一封裝包括：至少一個堆疊晶粒單元，包括：第一半導體晶粒，具有：多個第一導電接墊；第一鈍化層，覆蓋所述多個第一導電接墊的一些部分；多個穿孔，設置在所述第一鈍化層上且電性連接到所述多個第一導電接墊；及保護層，設置在所述第一鈍化層上且覆蓋所述多個穿孔；及至少一個第二半導體晶粒，堆疊在所述第一半導體晶粒上，其中所述至少一個第二半導體晶粒包括多個第二導電接墊；第二鈍化層，覆蓋所述多個第二導電接墊的一些部分；多個導電杆，設置在所述第二鈍化層上且電性連接到所述多個第二導電接墊；第二保護層，所述第二保護層橫向環繞所述多個導電杆，所述至少一個第二半導體晶粒的所述第二保護層位於所述多個導電杆與所述第一半導體晶粒的所述保護層之間，其 中所述第一半導體晶粒的所述保護層覆蓋所述至少一個第二半導體晶粒；絕緣封裝體，具有第一表面及與所述第一表面相對的第二表面，其中所述絕緣封裝體包封所述至少一個堆疊晶粒單元；以及重佈線層，設置在所述絕緣封裝體的所述第一表面上且電性連接到所述多個穿孔及所述多個導電杆。
  6. 如申請專利範圍第5項所述的疊層封裝結構，其中所述第一封裝還包括：多個貫穿絕緣層孔，嵌入在所述絕緣封裝體內；以及背面側重佈線層，設置在所述絕緣封裝體的所述第二表面上，且所述第二封裝的所述多個導電球透過所述多個貫穿絕緣層孔電性連接到所述第一封裝的所述背面側重佈線層。
  7. 如申請專利範圍第5項所述的疊層封裝結構，還包括：第三半導體晶粒，堆疊在所述至少一個第二半導體晶粒上，其中所述第三半導體晶粒包括多個第三導電接墊、覆蓋所述多個第三導電接墊的一些部分的第三鈍化層，且所述至少一個第二半導體晶粒的所述多個導電杆環繞所述第三半導體晶粒。
  8. 如申請專利範圍第5項所述的疊層封裝結構，還包括：第三半導體晶粒，鄰近於所述至少一個第二半導體晶粒而設置在所述第一半導體晶粒上，其中所述第三半導體晶粒包括多個第三導電接墊、覆蓋所述多個第三導電接墊的一些部分的第三鈍化 層，且其中所述第一半導體晶粒的所述多個穿孔環繞所述第三半導體晶粒。
  9. 一種製作封裝結構的方法，包括：形成堆疊晶粒單元，包括：提供具有多個第一半導體晶粒的半導體晶圓，其中所述多個第一半導體晶粒中的每一者包括第一鈍化層及形成在所述第一鈍化層上的多個第一導電杆；在由所述多個第一導電杆環繞的區域中將第二半導體晶粒固定到所述多個第一半導體晶粒中的每一者的所述第一鈍化層上，其中所述第二半導體晶粒包括多個第二導電杆以及橫向環繞所述多個第二導電杆的第二保護層；在所述多個第一半導體晶粒中的每一者的所述第一鈍化層的表面上形成第一保護層，以橫向環繞並覆蓋所述多個第一導電杆及所述第二半導體晶粒，其中所述第二半導體晶粒的所述第二保護層位於所述多個第二導電杆與所述多個第一半導體晶粒中的每一者的所述第一保護層之間；及分割所述半導體晶圓以將所述多個第一半導體晶粒中的每一者分離開來，並形成所述堆疊晶粒單元，其中所述堆疊晶粒單元具有一個所述多個第一半導體晶粒以及所述第二半導體晶粒；將所述堆疊晶粒單元接合到載體上；形成絕緣封裝體以包封所述堆疊晶粒單元；以及 在所述絕緣封裝體及所述堆疊晶粒單元上形成重佈線層，其中所述重佈線層電性連接到所述多個第一導電杆及所述多個第二導電杆，且所述多個第一半導體晶粒中的每一者藉由所述多個第一導電杆、所述重佈線層以及所述多個第二導電杆電性連接到所述第二半導體晶粒。
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