CN111863766A - 封装结构、叠层封装结构及其制作方法 - Google Patents

封装结构、叠层封装结构及其制作方法 Download PDF

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Publication number
CN111863766A
CN111863766A CN201910560561.XA CN201910560561A CN111863766A CN 111863766 A CN111863766 A CN 111863766A CN 201910560561 A CN201910560561 A CN 201910560561A CN 111863766 A CN111863766 A CN 111863766A
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semiconductor die
conductive
layer
semiconductor
die
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CN201910560561.XA
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陈宪伟
陈明发
叶松峯
史朝文
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
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Abstract

一种封装结构包括第一半导体管芯、第二半导体管芯、绝缘包封体及重布线层。第一半导体管芯具有第一导电杆及横向环绕第一导电杆的第一保护层。第二半导体管芯嵌入在第一半导体管芯的第一保护层中且被第一导电杆环绕，其中第二半导体管芯包括第二导电杆。绝缘包封体包封第一半导体管芯及第二半导体管芯。重布线层设置在绝缘包封体上且与第一导电杆及第二导电杆连接，其中第一半导体管芯与第二半导体管芯通过第一导电杆、重布线层及第二导电杆电连接。

Description

封装结构、叠层封装结构及其制作方法
技术领域
本揭露是有关于一种封装结构、叠层封装结构及其制作方法。
背景技术
各种电子应用中皆会用到半导体器件，例如个人计算机、手机、数字照相机及其他电子装备。半导体器件通常是通过以下步骤制作：在半导体衬底之上依序沉积绝缘材料层或介电材料层、导电材料层及半导体材料层，并使用光刻将各种材料层图案化以在上面形成电路组件及元件。许多半导体集成电路通常制造在单个半导体晶片上。可处理并在晶片级下封装晶片的管芯，且已针对晶片级封装开发出各种技术。
发明内容
本揭露的一些实施例提供一种封装结构，所述封装结构包括：第一半导体管芯、至少一个第二半导体管芯、绝缘包封体及重布线层。所述第一半导体管芯具有多个第一导电杆及横向环绕所述多个第一导电杆的第一保护层。所述至少一个第二半导体管芯嵌入在所述第一半导体管芯的所述第一保护层中且被所述多个第一导电杆环绕，其中所述至少一个第二半导体管芯包括多个第二导电杆。所述绝缘包封体包封所述第一半导体管芯及所述至少一个第二半导体管芯。所述重布线层设置在所述绝缘包封体上且与所述多个第一导电杆及所述多个第二导电杆连接，其中所述第一半导体管芯与所述至少一个第二半导体管芯通过所述多个第一导电杆、所述重布线层及所述多个第二导电杆电连接。
本揭露的一些实施例提供一种叠层封装结构，所述叠层封装结构包括第一封装及第二封装。所述第二封装包括电连接到所述第一封装的多个导电球。所述第一封装包括至少一个堆叠管芯单元、绝缘包封体及重布线层。所述至少一个堆叠管芯单元包括第一半导体管芯及至少一个第二半导体管芯。所述第一半导体管芯具有：多个第一导电接垫；第一钝化层，覆盖所述多个第一导电接垫的一些部分；多个穿孔，设置在所述第一钝化层上且电连接到所述多个第一导电接垫；及保护层，设置在所述第一钝化层上且覆盖所述多个穿孔。所述至少一个第二半导体管芯堆叠在所述第一半导体管芯上，其中所述至少一个第二半导体管芯包括：多个第二导电接垫；第二钝化层，覆盖所述多个第二导电接垫的一些部分；及多个导电杆，设置在所述第二钝化层上且电连接到所述多个第二导电接垫，其中所述第一半导体管芯的所述保护层覆盖所述至少一个第二半导体管芯。所述绝缘包封体具有第一表面及与所述第一表面相对的第二表面，其中所述绝缘包封体包封所述至少一个堆叠管芯单元。所述重布线层设置在所述绝缘包封体的所述第一表面上且电连接到所述多个穿孔及所述多个导电杆。
本揭露的一些实施例阐述一种制作封装结构的方法。所述方法包括以下步骤。形成堆叠管芯单元。所述形成所述堆叠管芯单元的步骤包括以下步骤。提供具有多个第一半导体管芯的半导体晶片，其中所述多个第一半导体管芯中的每一者包括第一钝化层及形成在所述第一钝化层上的多个第一导电杆。在由所述多个第一导电杆环绕的区域中将第二半导体管芯固定到所述多个第一半导体管芯中的每一者的所述第一钝化层上，其中所述第二半导体管芯包括多个第二导电杆。在所述多个第一半导体管芯中的每一者的所述第一钝化层的表面上形成第一保护层，以覆盖所述多个第一导电杆及所述第二半导体管芯。分割所述半导体晶片以分离开所述多个第一半导体管芯来形成所述堆叠管芯单元。将所述堆叠管芯单元接合到载体上。形成绝缘包封体以包封所述堆叠管芯单元。在所述绝缘包封体及所述堆叠管芯单元上形成重布线层，其中所述重布线层电连接到所述多个第一导电杆及所述多个第二导电杆。
附图说明
结合附图进行阅读，依据以下详细说明最透彻地理解本发明实施例的各方面。注意，根据行业中的标准惯例，各种特征未按比例绘制。事实上，为论述的清晰起见，可任意地增大或减小各种特征的关键尺寸。
图1A到图1F是根据本揭露的一些示例性实施例的制作堆叠管芯单元的方法的各个阶段的示意性剖视图。
图2A到图2G是根据本揭露的一些示例性实施例的制作封装结构的方法的各个阶段的示意性剖视图。
图3是根据本揭露的一些其他示例性实施例的封装结构的示意性剖视图。
图4是根据本揭露的一些其他示例性实施例的封装结构的示意性剖视图。
图5是根据本揭露的一些其他示例性实施例的封装结构的示意性剖视图。
图6是根据本揭露的一些其他示例性实施例的封装结构的示意性剖视图。
图7是根据本揭露的一些其他示例性实施例的封装结构的示意性剖视图。
图8是根据本揭露的一些其他示例性实施例的封装结构的示意性剖视图。
图9是根据本揭露的一些其他示例性实施例的封装结构的示意性剖视图。
图10是根据本揭露的一些其他示例性实施例的封装结构的示意性剖视图。
图11是根据本揭露的一些示例性实施例的叠层封装(package-on-package，PoP)结构的示意性剖视图。
图12是根据本揭露的一些其他示例性实施例的叠层封装(PoP)结构的示意性剖视图。
[符号的说明]
30：第三半导体管芯
31：第三导电杆
32：第三半导体衬底
33：第三保护层
34、104、204：内连线层
36：第三导电接垫
38：第三钝化层
100：第一半导体管芯
102：第一半导体衬底
106：第一导电接垫
108：第一钝化层
110：第一导电杆
110-TS、210-TS：顶部
112：保护性材料
112’：保护层
112-TS、212-TS、306-TS、308-TS：顶表面
200：第二半导体管芯
202：第二半导体衬底
206：第二导电接垫
208：第二钝化层
210：第二导电杆
212：第二保护层
302：载体
304：剥离层
306：绝缘体穿孔
308：绝缘材料
308’、560：绝缘包封体
310、550：导电接垫
312：导电球
401：条带
402：框架
510：衬底
520：半导体芯片
530：接合打线
540：接垫
570：导电球
580：填充底胶
CD1、CD2：导电层
DAF：管芯贴合膜
DI1、DI2：介电层
DL：分割线
IPD：集成无源器件
PK1A、PK1B、PK1C、PK1D、PK1E、PK1F、PK1G、PK1H、PK1I：封装结构
PK2：第二封装/封装结构
POP1、POP2：叠层封装结构
RDL1、RDL2：重布线层
S1：第一表面
S2：第二表面
SU1、SU2：堆叠管芯单元
WF1、WF2：半导体晶片
具体实施方式
以下公开内容提供许多不同的实施例或实例以实施所提供主题的不同特征。下文阐述组件及排列的具体实例以使本揭露简明。当然，这些仅是实例并不旨在进行限制。举例来说，在以下说明中，第二特征形成在第一特征之上或形成在第一特征上可包括第二特征与第一特征形成为直接接触的实施例，且还可包括额外特征可形成在第二特征与第一特征之间使得第二特征与第一特征不可直接接触的实施例。另外，本揭露可在各种实例中重复使用参考编号及/或字母。此重复是出于简明及清晰目的，本质上并不规定所述的各种实施例及/或配置之间的关系。
此外，为便于说明起见，本文中可使用例如“在…下方”、“在…之下”、“下部”、“在…上”、“在……之上”、“上覆在”、“在…上方”、“上部”等空间相对用语来阐述一个元件或特征与另外的元件或特征之间的关系，如图中所说明。除了图中所绘示的定向之外，所述空间相对用语还旨在囊括器件在使用或操作中的不同定向。可以其他方式对设备进行定向(旋转90度或处于其他定向)，且同样地可对本文中所使用的空间相对描述符加以相应地解释。
还可包括其他特征及工艺。举例来说，可包括测试结构以辅助对三维(threedimensional，3D)封装或三维集成电路(three dimensional integrated circuit，3DIC)器件进行验证测试。所述测试结构可包括例如形成在重布线层中或形成在衬底上的测试接垫，所述测试接垫允许使用探针及/或探针卡等来对3D封装或3DIC进行测试。可对中间结构及最终结构执行验证测试。另外，本文中所公开的结构及方法可与测试方法结合使用，所述测试方法包括在中间阶段验证出已知良好的管芯以提高良率且降低成本。
图1A到图1F是根据本揭露的一些示例性实施例的制作堆叠管芯单元的方法的各个阶段的示意性剖视图。参考图1A，提供具有多个第一半导体管芯100的半导体晶片WF1。如图1A中所说明，第一半导体管芯100中的每一者包括第一半导体衬底102、内连线层104、多个第一导电接垫106、第一钝化层108及多个第一导电杆110(或穿孔)。在一些实施例中，第一半导体衬底102可以是块状硅衬底或绝缘体上硅(silicon-on-insulator，SOI)衬底，且第一半导体衬底102中还形成有有源组件(例如，晶体管等)且视情况形成有无源组件(例如，电阻器、电容器、电感器等)。内连线层104设置在第一半导体衬底102上且可例如包括交替堆叠的多个金属化层及层间电介质。第一导电接垫106可以是铝接垫、铜接垫或其他适合的金属接垫。第一导电接垫106例如电连接到内连线层104。第一钝化层108可以是氧化硅层、氮化硅层、氮氧化硅层或由任何适合的介电材料形成的介电层。第一钝化层108覆盖第一导电接垫106且具有多个接触开口，其中第一钝化层108的接触开口部分地暴露出第一导电接垫106。在一些实施例中，第一导电杆110(穿孔)通过镀覆形成在第一导电接垫106上。
参考图1B，提供具有多个第二半导体管芯200的另一半导体晶片WF2。在示例性实施例中，第二半导体管芯200中的每一者包括第二半导体衬底202、内连线层204、多个第二导电接垫206、第二钝化层208、多个第二导电杆210及第二保护层212。第二半导体管芯200中的每一者的尺寸或大小小于图1A中所说明的第一半导体管芯100中的每一者的尺寸或大小。
在示例性实施例中，第二半导体衬底202可以是块状硅衬底或绝缘体上硅(SOI)衬底，且第二半导体衬底202中还形成有有源组件(例如，晶体管等)且视情况形成有无源组件(例如，电阻器、电容器、电感器等)。内连线层204设置在第二半导体衬底202上，且可例如包括交替堆叠的多个金属化层及层间电介质。第二导电接垫206可以是铝接垫、铜接垫或其他适合的金属接垫。第二导电接垫206例如电连接到内连线层204。第二钝化层208可以是氧化硅层、氮化硅层、氮氧化硅层或由任何适合的介电材料形成的介电层。第二钝化层208覆盖第二导电接垫206且具有多个接触开口，其中第二钝化层208的接触开口部分地暴露出第二导电接垫206。在一些实施例中，第二导电杆210通过镀覆形成在第二导电接垫206上。在一些实施例中，第二保护层212形成在第二钝化层208上，且覆盖第二导电杆210以保护第二导电杆210。在某些实施例中，可沿着分割线DL分割半导体晶片WF2以将所述多个第二半导体管芯200彼此分离开。尽管对第二半导体管芯200的说明类似于对第一半导体管芯100的说明，但应注意，基于设计要求，其中所使用的材料可相同或有所不同。
参考图1C，在将第二半导体管芯200分离开之后，将第二半导体管芯200中的至少一者堆叠在第一半导体管芯100上。举例来说，在由所述多个第一导电杆110(穿孔)环绕的区域中将第二半导体管芯200的背面侧固定或接合到第一半导体管芯100中的每一者的第一钝化层108上。在示例性实施例中，通过熔融接合将第二半导体管芯200固定到第一钝化层108上。在一些实施例中，在100℃到300℃的温度范围下执行熔融接合以产生将第二半导体管芯200接合到第一半导体管芯100中的每一者的第一钝化层108上的化学键。在某些实施例中，化学键形成在第一钝化层108的表面与第二半导体衬底202的表面(第二半导体管芯200的背面侧)之间。在一些示例性实施例中，所形成的化学键是共价键。在一些替代实施例中，通过管芯贴合膜(未示出)将第二半导体管芯200固定或接合到第一半导体管芯100中的每一者的第一钝化层108上。
参考图1D，在接合第二半导体管芯200之后，在第一钝化层108的表面之上形成保护性材料112以覆盖所述多个第一导电杆110(穿孔)及第二半导体管芯200。在一些实施例中，保护性材料112还覆盖第二半导体管芯200的第二保护层212。在某些实施例中，保护性材料112填充到邻近的第一导电杆110的间隙中，且填充第二半导体管芯200与第一导电杆110之间的间隙。换句话说，第一导电杆110与第二半导体管芯200之间嵌入保护性材料112且受到保护性材料112的良好保护。在一些实施例中，保护性材料112包含聚合物、介电材料、模塑化合物、树脂材料等。然而，本揭露并不仅限于此，且可使用其他适合的保护性材料。在一个实施例中，保护性材料112(用于形成第一保护性层)与第二保护层212的材料不同。在另一实施例中，保护性材料112与第二保护层212包含相同的材料。本揭露并不仅限于此。
参考图1E，在下一步骤中，通过机械研磨工艺及/或化学机械抛光(chemicalmechanical polishing，CMP)工艺研磨或抛光第二半导体管芯200的保护性材料112及第二保护层212，直到显露出第一导电杆110(穿孔)的顶部110-TS及第二导电杆210的顶部210-TS为止。在一些实施例中，将第一导电杆110(穿孔)及第二导电杆210部分地抛光，以使得第一导电杆110(穿孔)的顶部110-TS及第二导电杆210的顶部210-TS与第二保护层212的顶表面212-TS齐平。在一些实施例中，对保护性材料112进行抛光以形成保护层112’(第一保护层)。在抛光工艺之后，保护层112’的顶表面112-TS与第一导电杆110(穿孔)的顶部110-TS、第二导电杆210的顶部210-TS及第二保护层212的顶表面212-TS共面。此外，由于是在不同的步骤中形成保护层112’及第二保护层212，因此应注意，不论是使用相同的材料还是不同的材料，保护层112’的表面与第二保护层212的表面之间皆将会存在界面。
参考图1F，在抛光工艺之后，可沿着分割线DL(图1E中示出)分割半导体晶片WF1以将所述多个第一半导体管芯100彼此分离开，从而形成堆叠管芯单元SU1。在示例性实施例中，堆叠管芯单元SU1包括堆叠在第一半导体管芯100上的至少一个第二半导体管芯200。在某些实施例中，第二半导体管芯200嵌入在第一半导体管芯100的保护层112’内且被所述多个第一导电杆110(穿孔)横向环绕。尽管仅示出一个第二半导体管芯200堆叠在第一半导体管芯100上，但本揭露并不仅限于此。在一些其他实施例中，可基于设计要求来调整堆叠在第一半导体管芯100上的半导体管芯的数目。至此，实现根据本揭露的一些示例性实施例的堆叠管芯单元SU1。
图2A到图2G是根据本揭露的一些示例性实施例的制作封装结构的方法的各个阶段的示意性剖视图。参考图2A，提供载体302。在一些实施例中，载体302可以是承载半导体晶片或重构的晶片以供进行封装结构制造方法的玻璃载体或任何适合的载体。在一些实施例中，载体302涂布有剥离层304。剥离层304的材料可以是适合于接合载体302及从设置在载体302上的上方层或任何晶片剥离载体302的任何材料。
在一些实施例中，剥离层304可包含由介电材料制成的介电材料层，所述介电材料包括任何适合的聚合物系介电材料(例如，苯环丁烷(“BCB”)、聚苯并恶唑(“PBO”))。在替代实施例中，剥离层304可包括由在受热时会失去粘著性的环氧树脂系热释放材料制成的介电材料层，例如光热转换(light-to-heat-conversion，LTHC)释放涂布膜。在另一实施例中，剥离层304可包括由在暴露于UV光下时会失去粘著性的紫外线(ultra-violet，UV)胶制成的介电材料层。在某些实施例中，剥离层304可以液体的形式被施配并被固化，或可以是层压到载体302上的层压膜，或可以是诸如此类的材料。剥离层304的顶表面与接触载体302的底表面相对，可以是齐平的且可具有高共面程度。在某些实施例中，剥离层304是例如具有良好的耐化学性的LTHC层，且此层使得能够通过施加激光辐照来从载体302进行室温剥离，然而本揭露并不仅限于此。
在替代实施例中，可在剥离层304上涂布缓冲层(未示出)，其中剥离层304夹在缓冲层与载体302之间，且缓冲层的顶表面也可具备高共面程度。在一些实施例中，缓冲层可以是介电材料层。在一些实施例中，缓冲层可以是由聚酰亚胺、PBO、BCB或任何其他适合的聚合物系介电材料制成的聚合物层。在一些实施例中，缓冲层可以是味之素构成膜(Ajinomoto Buildup Film，ABF)、阻焊膜(Solder Resist，SR)等。换句话说，缓冲层是选用性的且可基于需求省略，因此本揭露并不仅限于此。
如图2A中进一步说明，在载体302之上形成重布线层RDL1。举例来说，在剥离层304上形成重布线层RDL1，且重布线层RDL1的形成包括依序地交替形成一个或多个介电层DI1以及一个或多个导电层CD1。在一些实施例中，重布线层RDL1包括两个介电层DI1及一个导电层CD1，如图2A中所示，其中导电层CD1夹在介电层DI1之间。然而，本揭露并不仅限于此。重布线层RDL1中所包括的介电层DI1及导电层CD1的数目并不仅限于此，且可基于需求来决定并选择。举例来说，介电层DI1及导电层CD1的数目可以是一个或一个以上。
在某些实施例中，介电层DI1的材料可以是聚酰亚胺、聚苯并恶唑(PBO)、苯环丁烷(BCB)、氮化物(例如氮化硅)、氧化物(例如氧化硅)、磷硅酸盐玻璃(phosphosilicateglass，PSG)、硼硅酸盐玻璃(borosilicate glass，BSG)、掺杂硼的磷硅酸盐玻璃(boron-doped phosphosilicate glass，BPSG)、其组合等，可使用光刻及/或刻蚀工艺将介电层DI1的材料图案化。在一些实施例中，介电层DI1的材料可通过适合的制作技术形成，例如旋转涂布、化学气相沉积(chemical vapor deposition，CVD)、等离子加强化学气相沉积(plasma-enhanced chemical vapor deposition，PECVD)等。本揭露并不仅限于此。
在一些实施例中，导电层CD1的材料可由通过电镀或沉积形成的导电材料(例如，铝、钛、铜、镍、钨及/或其合金)制成，可使用光刻及刻蚀工艺将所述导电层的材料图案化。在一些实施例中，导电层CD1可以是图案化的铜层或其他适合的图案化的金属层。在本说明通篇，用语“铜”旨在包括实质上纯元素铜、含有不可避免的杂质的铜及含有微量元素(例如，钽、铟、锡、锌、锰、铬、钛、锗、锶、铂、镁、铝或锆等)的铜合金。
参考图2B，在形成重布线层RDL1之后，在重布线层RDL1上且在载体302之上安置图1F中所获得的至少一个堆叠管芯单元SU1、及多个绝缘体穿孔306。在一些实施例中，绝缘体穿孔306是集成扇出型(integrated fan-out，“InFO”)穿孔。在一个实施例中，绝缘体穿孔306的形成包括：形成具有开口的掩模图案(未示出)，然后通过电镀或沉积形成金属材料(未示出)来填充所述开口，并移除所述掩模图案以在重布线层RDL1上形成绝缘体穿孔306。在某些实施例中，绝缘体穿孔306填充到显露出重布线层RDL1的导电层CD1的通孔开口中，以使得绝缘体穿孔306可电连接到重布线层RDL1。在一些实施例中，所述掩模图案的材料可包括正性光刻胶或负性光刻胶。在一个实施例中，绝缘体穿孔306的材料可包括金属材料，例如铜或铜合金等。然而，本揭露并不仅限于此。
在替代实施例中，绝缘体穿孔306可通过以下步骤形成：在重布线层RDL1上形成晶种层(未示出)；形成具有开口的掩模图案，所述开口暴露出晶种层的一些部分；通过镀覆在晶种层的暴露出部分上形成金属材料以形成绝缘体穿孔306；移除掩模图案；且然后移除晶种层的被绝缘体穿孔306暴露出的部分。举例来说，晶种层可以是钛/铜复合层。为简明起见，图2B中仅示出了两个绝缘体穿孔306。然而应注意，绝缘体穿孔306的数目并不仅限于此，且可基于要求来选择。
此外，在一些实施例中，至少一个堆叠管芯单元SU1被拾放在重布线层RDL1上。在某些实施例中，通过将第一半导体管芯100的第一半导体衬底102贴合到重布线层RDL1的介电层DI1来将堆叠管芯单元SU1放置在重布线层RDL1上。举例来说，通过管芯贴合膜(未示出)将第一半导体衬底102贴合到重布线层RDL1。通过使用管芯贴合膜来确保堆叠管芯单元SU1与重布线层RDL1之间较好地粘著。在示例性实施例中，仅示出一个堆叠管芯单元SU1。然而应注意，放置在重布线层RDL1上的堆叠管芯单元SU1的数目并不仅限于此，且此可基于设计要求来调整。
在一些实施例中，当一个以上堆叠管芯单元SU1放置在重布线层RDL1上时，可将堆叠管芯单元SU1排列成阵列，且当堆叠管芯单元SU1排列成阵列时，可将绝缘体穿孔306分类成群组。堆叠管芯单元SU1的数目可与绝缘体穿孔306的群组的数目对应。在示例性实施例中，可在形成绝缘体穿孔306之后，将堆叠管芯单元SU1拾放在重布线层RDL1上。然而，本揭露并不仅限于此。在一些替代实施例中，可在形成绝缘体穿孔306之前将堆叠管芯单元SU1拾放在重布线层RDL1上。
此外，在示例性实施例中，堆叠管芯单元SU1至少包括堆叠在第一半导体管芯100上的第二半导体管芯200。举例来说，第一半导体管芯100及第二半导体管芯200可从以下选择：专用集成电路(application-specific integrated circuit，ASIC)芯片、模拟芯片(例如，无线射频芯片)、数字芯片(例如，基带芯片)、集成无源器件(integrated passivedevice，IPD)、电压调节器芯片、传感器芯片、存储器芯片等。本揭露并不仅限于此。
参考图2C，在下一步骤中，在重布线层RDL1上且在堆叠管芯单元SU1之上形成绝缘材料308。在一些实施例中，绝缘材料308是通过例如模压成型工艺形成，所述模压成型工艺填充堆叠管芯单元SU1与绝缘穿孔306之间的间隙以包封堆叠管芯单元SU1。绝缘材料308也填充邻近的绝缘体穿孔306之间的间隙以包封绝缘体穿孔306。在此阶段，第一导电杆110(穿孔)、保护层112’、第二导电杆210及第二保护层212被绝缘材料308包封且受到绝缘材料308的良好保护。换句话说，第一导电杆110(穿孔)、第一半导体管芯100的保护层112’、以及第二导电杆210、第二半导体管芯200的第二保护层212未显露出且未受到绝缘材料308的良好保护。
在一些实施例中，绝缘材料308包括聚合物(例如，环氧树脂、酚醛树脂、含硅树脂或其他适合的树脂)、具有低电容率(Dk)及低损耗角正切(Df)性质的介电材料或其他适合的材料。在替代实施例中，绝缘材料308可包括可接受的绝缘包封材料。在一些实施例中，绝缘材料308还可包括无机填充物或无机化合物(例如，二氧化硅、粘土等)，所述无机填充物或无机化合物可添加在绝缘材料308中以优化绝缘材料308的热膨胀系数(CTE)。本揭露并不仅限于此。
参考图2D，在一些实施例中，部分地移除绝缘材料308以暴露出绝缘体穿孔306、第一导电杆110(穿孔)及第二导电杆210。在一些实施例中，通过平面化步骤来研磨或抛光绝缘材料308。举例来说，通过机械研磨工艺及/或化学机械抛光(CMP)工艺执行平面化步骤，直到显露出第一导电杆110(穿孔)的顶部110-TS及第二导电杆210的顶部210-TS为止。在一些实施例中，可部分地抛光绝缘体穿孔306，以使得绝缘体穿孔306的顶表面306-TS与第一导电杆110(穿孔)的顶部110-TS及第二导电杆210的顶部210-TS齐平。换句话说，还可轻微研磨/抛光绝缘体穿孔306、第一导电杆110(穿孔)及第二导电杆210。
在所示的实施例中，对绝缘材料308进行抛光以形成绝缘包封体308’。在一些实施例中，绝缘包封体308’的顶表面308-TS、绝缘体穿孔306的顶表面306-TS、第一导电杆110(穿孔)的顶部110-TS、保护层112’的顶表面112-TS、第二导电杆210的顶部210-TS、第二保护层212的顶表面212-TS彼此共面且齐平。在一些实施例中，在进行机械研磨或化学机械抛光(CMP)步骤之后，可视情况执行清洁步骤。举例来说，执行清洁步骤来清洁并移除平面化步骤所产生的残余物。然而，本揭露并不仅限于此，且可通过任何其他适合的方法执行平面化步骤。
参考图2E，在进行研磨/抛光步骤之后，在绝缘包封体308’、绝缘体穿孔306及堆叠管芯单元SU1上形成重布线层RDL2。举例来说，绝缘包封体308’具有第一表面S1及与第一表面S1相对的第二表面S2，其中重布线层RDL2形成在绝缘包封体308’的第一表面S1上，且重布线层RDL1形成在第二表面S2上。在一些实施例中，重布线层RDL2通过第一导电杆110及第二导电杆210分别电连接到绝缘体穿孔306且电连接到第一半导体管芯100及第二半导体管芯200。在某些实施例中，重布线层RDL2将第一半导体管芯100的第一导电杆110电连接到第二半导体管芯200的第二导电杆210。换句话说，第一半导体管芯100与第二半导体管芯200通过第一导电杆110、重布线层RDL2及第二导电杆210电连接。在一些实施例中，堆叠管芯单元SU1通过重布线层RDL2电连接到绝缘体穿孔306。
此外，在一些实施例中，重布线层RDL2的形成包括依序地交替形成一个或多个介电层DI2以及一个或多个导电层CD2。在某些实施例中，导电层CD2夹在介电层DI2之间。尽管本文中仅示出了三层导电层CD2及四层介电层DI2，然而本揭露的范围并不受实施例限制。在其他实施例中，可基于产品要求来调整导电层CD2及介电层DI2的数目。在一些实施例中，导电层CD2电连接到第一半导体管芯100的第一导电杆110(穿孔)，且电连接到第二半导体管芯200的第二导电杆210。此外，导电层CD2电连接到绝缘体穿孔306。在一些实施例中，重布线层RDL2的介电层DI2及导电层CD2的材料与关于重布线层RDL1所述的介电层DI1及导电层CD1的材料类似。因此，本文中将不再对介电层DI2及导电层CD2加以赘述。
在形成重布线层RDL2之后，可在导电层CD2的最顶层的暴露出顶表面上设置多个导电接垫310以用于与导电球电连接。在某些实施例中，导电接垫310例如是用于球安装的球下金属(under-ball metallurgy，UBM)图案。如图2E中所示，导电接垫310形成在重布线层RDL2上且电连接到重布线层RDL2。在一些实施例中，导电接垫310的材料可包括铜、镍、钛、钨或其合金等，且可例如通过电镀工艺形成。导电接垫310的数目并不限于本揭露，且可基于设计布局来做出选择。在一些替代实施例中，可省略导电接垫310。换句话说，在后续步骤中形成的导电球312可直接设置在重布线层RDL2上。
在形成导电接垫310之后，在导电接垫310上且在重布线层RDL2之上设置多个导电球312。在一些实施例中，可通过植球工艺或回焊工艺在导电接垫310上设置导电球312。在一些实施例中，导电球312是例如焊球或球栅阵列(ball grid array，BGA)球。在一些实施例中，导电球312通过导电接垫310连接到重布线层RDL2。在某些实施例中，导电球312中的一些可通过重布线层RDL2电连接到堆叠管芯单元SU1。此外，导电球312中的一些可通过重布线层RDL2电连接到绝缘体穿孔306。导电球312的数目并不限于本揭露，且可基于导电接垫310的数目决定并选择。
参考图2F，在形成重布线层RDL2且放置导电球312之后，可将图2E中所示的结构倒置并将其贴合到框架402所支撑的条带401(例如，分割条带)。如图2F中所说明，将载体302与重布线层RDL1剥离并分离开。在一些实施例中，剥离工艺包括将光(例如，激光或UV光)投射在剥离层304(例如，LTHC释放层)上，以使得可容易地将载体302与剥离层304一起移除。在剥离步骤期间，使用条带401先稳固封装结构，再剥离载体302及剥离层304。在剥离工艺之后，会显露出或暴露出重布线层RDL1的背面侧表面。在某些实施例中，会显露出或暴露出重布线层RDL1的介电层DI1。
参考图2G，在剥离工艺之后，沿着分割线DL(图2F中示出)执行分割工艺以将整个晶片结构(切割穿过绝缘包封体308’及重布线层RDL1及重布线层RDL2)切割成多个封装结构PK1A。在示例性实施例中，分割工艺是包括机械刀锯割或激光切割在内的晶片分割工艺。在后续工艺中，可基于要求将分离开的封装结构PK1A例如设置到电路衬底上或安置到其他组件上。
图3是根据本揭露的一些其他示例性实施例的封装结构的示意性剖视图。图3中所示的封装结构PK1B与图2G中所示的封装结构PK1A类似，因此使用相同的参考编号来指代相同或相似的部件，且本文中将不再对其加以详细说明。实施例之间的差异在于，在封装结构PK1B中将第二半导体管芯200固定到堆叠管芯单元SU1中的第一半导体管芯100。在先前实施例中，通过熔融接合将第二半导体管芯200固定到第一钝化层108上。然而，本揭露并不仅限于此。参考图3，在一些实施例中，可使用管芯贴合膜DAF将第二半导体管芯200固定到第一半导体管芯100的第一钝化层108上。换句话说，管芯贴合膜DAF位于第二半导体管芯200的第二半导体衬底202与第一半导体管芯100的第一钝化层108之间。
图4是根据本揭露的一些其他示例性实施例的封装结构的示意性剖视图。图4中所示的封装结构PK1C与图2G中所示的封装结构PK1A类似，因此使用相同的参考编号来指代相同或相似的部件，且本文中将不再对其加以详细说明。实施例之间的差异在于封装结构PK1C的第二半导体管芯200省略了第二保护层212。参考图4，第二半导体管芯200具有暴露出或显露出的第二导电杆210。因此，在将第二半导体管芯200固定到第一半导体管芯100上且形成保护层112’之后，保护层112’将覆盖且实体接触第二半导体管芯200的第二导电杆210。换句话说，保护层112’足以保护第一导电杆110(穿孔)及第二导电杆210两者。此外，由于省略了第二保护层212，因此封装结构PK1C中也将不存在保护层112’的表面与第二保护层212的表面之间的界面。
图5是根据本揭露的一些其他示例性实施例的封装结构的示意性剖视图。图5中所示的封装结构PK1D与图2G中所示的封装结构PK1A类似，因此使用相同的参考编号来指代相同或相似的部件，且本文中将不再对其加以详细说明。所述实施例之间的差异在于固定到第一半导体管芯100上的第二半导体管芯200的数目。参考图5，两个第二半导体管芯200固定在第一半导体管芯100的第一钝化层108上。在一些实施例中，两个第二半导体管芯200嵌入在第一半导体管芯100的保护层112’中。此外，第二半导体管芯200中的每一者被所述多个第一导电杆110(穿孔)环绕。在某些实施例中，由于第一导电杆110位于第二半导体管芯200之间，因此第二半导体管芯200中的一者与第二半导体管芯200中的另一者是分离开的。此外，所述两个第二半导体管芯200位于同一平面上且位于第一半导体管芯100的同一表面上，且彼此实质上共面。
图6是根据本揭露的一些其他示例性实施例的封装结构的示意性剖视图。图6中所示的封装结构PK1E与图2G中所示的封装结构PK1A类似，因此使用相同的参考编号来指代相同或相似的部件，且本文中将不再对其加以详细说明。所述实施例之间的差异在于封装结构PK1E还包括第三半导体管芯30。参考图6，在一些实施例中，第三半导体管芯30邻近于第二半导体管芯200而设置在第一半导体管芯100的第一钝化层108上。在一些实施例中，第三半导体管芯30的尺寸小于第二半导体管芯200及第一半导体管芯100的尺寸。然而，本揭露并不仅限于此，且可基于要求选择第三半导体管芯30的尺寸。在某些实施例中，第三半导体管芯30、第二半导体管芯200及第一半导体管芯100是不同类型的半导体管芯。然而，本揭露并不仅限于此。在替代实施例中，第三半导体管芯30可以是与第一半导体管芯100或第二半导体管芯200中的任一者相同类型的半导体管芯，仅尺寸或大小有所不同。
在示例性实施例中，第三半导体管芯30包括第三半导体衬底32、内连线层34、多个第三导电接垫36、第三钝化层38、多个第三导电杆31及第三保护层33。第三半导体衬底32可以是块状硅衬底或绝缘体上硅(SOI)衬底，且第三半导体衬底32中还形成有有源组件(例如，晶体管等)且视情况包括无源组件(例如，电阻器、电容器、电感器等)。内连线层34设置在第三半导体衬底32上且可例如包括交替堆叠的多个金属化层及层间电介质。第三导电接垫36可以是铝接垫、铜接垫或其他适合的金属接垫。第三导电接垫36例如电连接到内连线层34。第三钝化层38可以是氧化硅层、氮化硅层、氮氧化硅层或由任何适合的介电材料形成的介电层。第三钝化层38覆盖第三导电接垫36且具有多个接触开口，其中第三钝化层38的接触开口部分地暴露出第三导电接垫36。在一些实施例中，通过镀覆在第三导电接垫36上形成第三导电杆31。在一些实施例中，第三保护层33形成在第三钝化层38上，且覆盖第三导电杆31以保护第三导电杆31。此外，如图6中所说明，第三半导体管芯30嵌入在第一半导体管芯100的保护层112’中，且被所述多个第一导电杆110(穿孔)环绕。另外，重布线层RDL2电连接到第三半导体管芯30的第三导电杆31。在某些实施例中，第三半导体管芯30通过重布线层RDL2电连接到第一半导体管芯100及/或第二半导体管芯。
图7是根据本揭露的一些其他示例性实施例的封装结构的示意性剖视图。图7中所示的封装结构PK1F与图6中所示的封装结构PK1E类似，因此使用相同的参考编号来指代相同或相似的部件，且本文中将不再对其加以详细说明。所述实施例之间的差异在于第三半导体管芯30的位置。参考图7，在堆叠管芯单元SU1中，第三半导体管芯30设置在第二半导体管芯200上。第三半导体管芯30的尺寸小于第二半导体管芯200及第一半导体管芯100的尺寸。此外，在某些实施例中，第三半导体管芯30设置在第二半导体管芯200的第二钝化层208上，且被第二导电杆210环绕。另一方面，第二半导体管芯200还设置在第一半导体管芯100的第一钝化层108上，且被第一导电杆110(穿孔)环绕。
图8是根据本揭露的一些其他示例性实施例的封装结构的示意性剖视图。图8中所示的封装结构PK1G与图7中所示的封装结构PK1F类似，因此使用相同的参考编号来指代相同或相似的部件，且本文中将不再对其加以详细说明。所述实施例之间的差异在于，在封装结构PK1G中两个堆叠管芯单元(SU1/SU2)包括在封装结构PK1G中。参考图8，在示例性实施例中，包括堆叠管芯单元SU1及堆叠管芯单元SU2。堆叠管芯单元SU1中的堆叠半导体管芯的数目与堆叠管芯单元SU2中的堆叠半导体管芯的数目不同。举例来说，堆叠管芯单元SU1包括堆叠在一起的第一半导体管芯100、第二半导体管芯200及第三半导体管芯30，而堆叠管芯单元SU2包括第一半导体管芯100及第二半导体管芯200。尽管本文中仅说明了两个堆叠管芯单元(SU1/SU2)，然而应注意，封装结构中的每一者的堆叠管芯单元的数目并不仅限于此。举例来说，在替代实施例中，封装结构可包括两个或更多个堆叠管芯单元。此外，堆叠管芯单元中的每一者中的半导体管芯的数目及排列可基于设计要求而相同或有所不同。
图9是根据本揭露的一些其他示例性实施例的封装结构的示意性剖视图。图9中所示的封装结构PK1H与图2G中所示的封装结构PK1A类似，因此使用相同的参考编号来指代相同或相似的部件，且本文中将不再对其加以详细说明。所述实施例之间的差异在于，封装结构PK1H中还包括集成无源器件IPD。参考图9，在一些实施例中，集成无源器件IPD可设置在第一半导体管芯100的第一钝化层108上且嵌入在保护层112’内。集成无源器件IPD可与第二半导体管芯200设置在第一半导体管芯100的同一表面上且位于同一平面上，且可电连接到重布线层RDL2。此外，第一导电杆110环绕第二半导体管芯200及集成无源器件IPD两者。
图10是根据本揭露的一些其他示例性实施例的封装结构的示意性剖视图。图10中所示的封装结构PK1I与图2G中所示的封装结构PK1A类似，因此使用相同的参考编号来指代相同或相似的部件，且本文中将不再对其加以详细说明。所述实施例之间的差异在于封装结构PK1I省略了重布线层RDL1。参考图10，在一些实施例中，介电层DL代替重布线层RDL1设置在绝缘包封体308’的第二表面S2上。在某些实施例中，介电层DL具有显露出绝缘体穿孔306的开口，而介电层DL的开口中还设置有导电端子120，且导电端子120连接到绝缘体穿孔306。换句话说，实现无重布线层RDL1而具有双侧端子的封装结构PK1I。在替代实施例中，可省略导电端子120，且介电层DL可覆盖绝缘包封体308’的背面侧(第二表面S2)及堆叠管芯单元SU1的背面侧。
图11是根据本揭露的一些示例性实施例的叠层封装(PoP)结构的示意性剖视图。参考图11，在制作第一封装(例如，图2G中所说明的封装结构PK1A)之后，可将第二封装PK2堆叠在封装结构PK1A(第一封装)上以形成叠层封装(PoP)结构。如图11中所示，第二封装PK2电连接到封装结构PK1A(第一封装)的导电层CD1。在一些实施例中，第二封装PK2具有衬底510、多个半导体芯片520，所述多个半导体芯片520安装在衬底510的一个表面(例如，顶表面)上且彼此堆叠。在一些实施例中，使用接合打线530来使得半导体芯片520与接垫540(例如，接合接垫)之间电连接。在一些实施例中，绝缘包封体560形成为包封半导体芯片520及接合打线530以保护这些组件。在一些实施例中，可使用绝缘体穿孔(未示出)来使得接垫540与位于衬底510的另一表面(例如底表面)上的导电接垫550(例如，接合接垫)电连接。在某些实施例中，导电接垫550通过这些绝缘体穿孔(未示出)电连接到半导体芯片520。在一些实施例中，封装结构PK2的导电接垫550电连接到导电球570。此外，导电球570电连接到封装结构PK1A(第一封装)中的重布线层RDL1(背面侧重布线层)的导电层CD1。在一些实施例中，还提供填充底胶580来填充导电球570之间的空间以保护导电球570。在将第二封装PK2堆叠在封装结构PK1A(第一封装)上且提供其之间的电连接之后，可制作出叠层封装结构POP1。
图12是根据本揭露的一些其他示例性实施例的叠层封装(PoP)结构的示意性剖视图。图12中所示的叠层封装结构POP2与图11中所示的叠层封装结构POP1类似，因此使用相同的参考编号来指代相同或相似的部件，且本文中将不再对其加以详细说明。所述实施例之间的差异在于叠层封装结构POP2省略了重布线层RDL1。参考图12，在一些实施例中，由于省略了重布线层RDL1，因此第二封装PK2的导电球570可直接连接到封装结构PK1A(第一封装)的绝缘体穿孔306以形成叠层封装结构POP2。
在上述实施例中，封装结构或叠层封装结构中包括至少一个堆叠管芯单元。堆叠管芯单元包括嵌入在第一半导体管芯的保护层内的至少一个第二半导体管芯，其中第一导电杆环绕第二半导体管芯。此外，重布线层分别电连接到第一半导体管芯的第一导电杆及第二半导体管芯的第二导电杆。由于第二半导体管芯堆叠在第一半导体管芯上且嵌入在第一半导体管芯中，因此可缩短半导体管芯之间的通信路径(通过重布线层)。总的来说，封装结构的性能及效率可得到提高。
根据本揭露的一些实施例，提供一种封装结构，所述封装结构包括：第一半导体管芯、至少一个第二半导体管芯、绝缘包封体及重布线层。所述第一半导体管芯具有多个第一导电杆及横向环绕所述多个第一导电杆的第一保护层。所述至少一个第二半导体管芯嵌入在所述第一半导体管芯的所述第一保护层中且被所述多个第一导电杆环绕，其中所述至少一个第二半导体管芯包括多个第二导电杆。所述绝缘包封体包封所述第一半导体管芯及所述至少一个第二半导体管芯。所述重布线层设置在所述绝缘包封体上且与所述多个第一导电杆及所述多个第二导电杆连接，其中所述第一半导体管芯与所述至少一个第二半导体管芯通过所述多个第一导电杆、所述重布线层及所述多个第二导电杆电连接。
在一些实施例中，所述多个第一导电杆的顶部与所述多个第二导电杆的顶部齐平。在一些实施例中，所述的封装结构还包括穿透过所述绝缘包封体的多个绝缘体穿孔，且背面侧重布线层设置在所述绝缘包封体上且与所述多个绝缘体穿孔连接。
根据本揭露的一些其他实施例，提供一种叠层封装结构，所述叠层封装结构包括第一封装及第二封装。所述第二封装包括电连接到所述第一封装的多个导电球。所述第一封装包括至少一个堆叠管芯单元、绝缘包封体及重布线层。所述至少一个堆叠管芯单元包括第一半导体管芯及至少一个第二半导体管芯。所述第一半导体管芯具有：多个第一导电接垫；第一钝化层，覆盖所述多个第一导电接垫的一些部分；多个穿孔，设置在所述第一钝化层上且电连接到所述多个第一导电接垫；及保护层，设置在所述第一钝化层上且覆盖所述多个穿孔。所述至少一个第二半导体管芯堆叠在所述第一半导体管芯上，其中所述至少一个第二半导体管芯包括：多个第二导电接垫；第二钝化层，覆盖所述多个第二导电接垫的一些部分；及多个导电杆，设置在所述第二钝化层上且电连接到所述多个第二导电接垫，其中所述第一半导体管芯的所述保护层覆盖所述至少一个第二半导体管芯。所述绝缘包封体具有第一表面及与所述第一表面相对的第二表面，其中所述绝缘包封体包封所述至少一个堆叠管芯单元。所述重布线层设置在所述绝缘包封体的所述第一表面上且电连接到所述多个穿孔及所述多个导电杆。
在一些实施例中，两个所述第二半导体管芯设置在所述第一钝化层上，且所述多个穿孔环绕两个所述第二半导体管芯。在一些实施例中，所述的叠层封装结构还包括无源器件，所述无源器件设置在所述第一半导体管芯的所述第一钝化层上且嵌入在所述保护层中。在一些实施例中，所述至少一个第二半导体管芯的背面侧通过熔融接合贴合到所述第一半导体管芯的所述第一钝化层。在一些实施例中，所述第一封装包括至少两个堆叠管芯单元，且所述堆叠管芯单元中的一者中的堆叠半导体管芯的数目不同于所述堆叠管芯单元中的另一者中的堆叠半导体管芯的数目。
在本揭露的又一实施例中，阐述一种制作封装结构的方法。所述方法包括以下步骤。形成堆叠管芯单元。所述形成所述堆叠管芯单元的步骤包括以下步骤。提供具有多个第一半导体管芯的半导体晶片，其中所述多个第一半导体管芯中的每一者包括第一钝化层及形成在所述第一钝化层上的多个第一导电杆。在由所述多个第一导电杆环绕的区域中将第二半导体管芯固定到所述多个第一半导体管芯中的每一者的所述第一钝化层上，其中所述第二半导体管芯包括多个第二导电杆。在所述多个第一半导体管芯中的每一者的所述第一钝化层的表面上形成第一保护层，以覆盖所述多个第一导电杆及所述第二半导体管芯。分割所述半导体晶片以分离开所述多个第一半导体管芯来形成所述堆叠管芯单元。将所述堆叠管芯单元接合到载体上。形成绝缘包封体以包封所述堆叠管芯单元。在所述绝缘包封体及所述堆叠管芯单元上形成重布线层，其中所述重布线层电连接到所述多个第一导电杆及所述多个第二导电杆。
在一些实施例中，将所述第二半导体管芯固定到所述多个第一半导体管芯中的每一者的所述第一钝化层上包括：在100℃到300℃的温度范围下将所述第二半导体管芯熔融接合到所述第一钝化层上，以在所述第二半导体管芯的背面侧与所述第一钝化层之间产生化学键。在一些实施例中，是通过管芯贴合膜将所述第二半导体管芯固定到所述多个第一半导体管芯中的每一者的所述第一钝化层上。在一些实施例中，所述的制作封装结构的方法还包括对所述堆叠管芯单元执行研磨工艺，以使得所述第一保护层的顶表面、所述多个第一导电杆的顶表面及所述多个第二导电杆的顶表面彼此齐平。在一些实施例中，所述的制作封装结构的方法还包括在所述第二半导体管芯的第二钝化层上形成第二保护层以覆盖所述多个第二导电杆，其中所述第一保护层覆盖所述第二保护层。
上述内容概述了数个实施例的特征，以使所属领域的技术人员可更好地理解本揭露的各方面。所属领域的技术人员应了解，其可容易地使用本揭露作为设计或修改其他工艺及结构以实现与本文中所介绍的实施例相同的目的及/或达成相同的优势的基础。所属领域的技术人员还应意识到这些等效构造并不背离本揭露的精神及范围，且其可在不背离本揭露的精神及范围的情况下在本文中做出各种变化、代替及更改。

Claims (10)

1.一种封装结构，包括：
第一半导体管芯，具有多个第一导电杆及横向环绕所述多个第一导电杆的第一保护层；
至少一个第二半导体管芯，嵌入在所述第一半导体管芯的所述第一保护层中且被所述多个第一导电杆环绕，其中所述至少一个第二半导体管芯包括多个第二导电杆；
绝缘包封体，包封所述第一半导体管芯及所述至少一个第二半导体管芯；以及
重布线层，设置在所述绝缘包封体上且与所述多个第一导电杆及所述多个第二导电杆连接，其中所述第一半导体管芯与所述至少一个第二半导体管芯通过所述多个第一导电杆、所述重布线层及所述多个第二导电杆电连接。
2.根据权利要求1所述的封装结构，其中所述至少一个第二半导体管芯包括嵌入在所述第一半导体管芯的所述第一保护层中的两个或更多个第二半导体管芯，且所述多个第一导电杆环绕所述两个或更多个第二半导体管芯。
3.根据权利要求1所述的封装结构，还包括管芯贴合膜，所述管芯贴合膜位于所述至少一个第二半导体管芯的背面侧与所述第一半导体管芯的钝化层之间，且所述至少一个第二半导体管芯通过所述管芯贴合膜贴合到所述第一半导体管芯的所述钝化层。
4.根据权利要求1所述的封装结构，其中所述至少一个第二半导体管芯的背面侧通过熔融接合贴合到所述第一半导体管芯的钝化层。
5.根据权利要求1所述的封装结构，其中所述至少一个第二半导体管芯还包括横向环绕所述多个第二导电杆的第二保护层，且所述至少一个第二半导体管芯的所述第二保护层位于所述多个第二导电杆与所述第一半导体管芯的所述第一保护层之间。
6.一种叠层封装结构，包括：
第一封装及堆叠在所述第一封装上的第二封装，其中所述第二封装包括电连接到所述第一封装的多个导电球，
其中所述第一封装包括：
至少一个堆叠管芯单元，包括：
第一半导体管芯，具有：多个第一导电接垫；第一钝化层，覆盖所述多个第一导电接垫的一些部分；多个穿孔，设置在所述第一钝化层上且电连接到所述多个第一导电接垫；及保护层，设置在所述第一钝化层上且覆盖所述多个穿孔；及
至少一个第二半导体管芯，堆叠在所述第一半导体管芯上，其中
所述至少一个第二半导体管芯包括多个第二导电接垫；第二钝化层，覆盖所述多个第二导电接垫的一些部分；及多个导电杆，设置在所述第二钝化层上且电连接到所述多个第二导电接垫，其中所述第一半导体管芯的所述保护层覆盖所述至少一个第二半导体管芯；
绝缘包封体，具有第一表面及与所述第一表面相对的第二表面，其中所述绝缘包封体包封所述至少一个堆叠管芯单元；以及
重布线层，设置在所述绝缘包封体的所述第一表面上且电连接到所述多个穿孔及所述多个导电杆。
7.根据权利要求6所述的叠层封装结构，其中所述第一封装还包括：
多个绝缘体穿孔，嵌入在所述绝缘包封体内；以及
背面侧重布线层，设置在所述绝缘包封体的所述第二表面上，且所述第二封装的所述多个导电球通过所述多个绝缘体穿孔电连接到所述第一封装的所述背面侧重布线层。
8.根据权利要求6所述的叠层封装结构，还包括：
第三半导体管芯，堆叠在所述至少一个第二半导体管芯上，其中所述第三半导体管芯包括多个第三导电接垫、覆盖所述多个第三导电接垫的一些部分的第三钝化层，且所述至少一个第二半导体管芯的所述多个导电杆环绕所述第三半导体管芯。
9.根据权利要求6所述的叠层封装结构，还包括：
第三半导体管芯，邻近于所述至少一个第二半导体管芯而设置在所述第一半导体管芯上，其中所述第三半导体管芯包括多个第三导电接垫、覆盖所述多个第三导电接垫的一些部分的第三钝化层，且其中所述第一半导体管芯的所述多个穿孔环绕所述第三半导体管芯。
10.一种制作封装结构的方法，包括：
形成堆叠管芯单元，包括：
提供具有多个第一半导体管芯的半导体晶片，其中所述多个第一半导体管芯中的每一者包括第一钝化层及形成在所述第一钝化层上的多个第一导电杆；
在由所述多个第一导电杆环绕的区域中将第二半导体管芯固定到所述多个第一半导体管芯中的每一者的所述第一钝化层上，其中所述第二半导体管芯包括多个第二导电杆；
在所述多个第一半导体管芯中的每一者的所述第一钝化层的表面上形成第一保护层，以覆盖所述多个第一导电杆及所述第二半导体管芯；及
分割所述半导体晶片以分离开所述多个第一半导体管芯来形成所述堆叠管芯单元；
将所述堆叠管芯单元接合到载体上；
形成绝缘包封体以包封所述堆叠管芯单元；以及
在所述绝缘包封体及所述堆叠管芯单元上形成重布线层，其中所述重布线层电连接到所述多个第一导电杆及所述多个第二导电杆。
CN201910560561.XA 2019-04-29 2019-06-26 封装结构、叠层封装结构及其制作方法 Pending CN111863766A (zh)

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