CN108122861B - 具有虚设管芯的封装结构、半导体装置及其形成方法 - Google Patents

具有虚设管芯的封装结构、半导体装置及其形成方法 Download PDF

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CN108122861B
CN108122861B CN201710478033.0A CN201710478033A CN108122861B CN 108122861 B CN108122861 B CN 108122861B CN 201710478033 A CN201710478033 A CN 201710478033A CN 108122861 B CN108122861 B CN 108122861B
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dies
main
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CN108122861A (zh
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林彦甫
余振华
陈宪伟
李孟灿
吴伟诚
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明实施例提供一种形成封装结构的方法及一种封装结构。所述方法包括将主管芯与虚设管芯并排地放置在载体衬底上。所述方法还包括沿所述主管芯的侧壁及所述虚设管芯的侧壁形成模塑料。所述方法还包括在所述主管芯及所述虚设管芯之上形成包括多个通孔及多个导电线的重布线层，其中所述多个通孔及所述导电线电连接到所述主管芯的连接件。所述方法还包括移除所述载体衬底。

Description

具有虚设管芯的封装结构、半导体装置及其形成方法
技术领域
本发明实施例涉及一种结构，且更具体来说涉及例如具有虚设管芯的扇出型封装的结构及其形成方法。
背景技术
随着半导体技术的演变，半导体芯片/管芯变得越来越小。与此同时，需要将更多的功能集成至半导体管芯中。因此，半导体管芯需要将越来越大数目的输入/输出(I/O)焊盘充填至更小的面积中，且输入/输出焊盘的密度随着时间迅速上升。因此，对半导体管芯的封装变得更困难，此会不利地影响封装的产率(yield)。
传统的封装技术可分为两个类别。在第一类别中，晶片上的管芯先被封装、之后被锯切。此种封装技术具有某些有利特征，例如生产量(throughput)更大及成本更低。此外，需要使用更少的底部填充剂或模制化合物。然而，此种封装技术也具有缺点。如上所述，管芯的尺寸正变得越来越小，且相应封装仅可为扇入型封装(fan-in type package)，其中每一管芯的输入/输出焊盘被限于相应管芯的表面正上方的区。由于管芯的面积有限，输入/输出焊盘的数目会因对输入/输出焊盘的间距的限制而受限。假如焊盘的间距减小，则可能会出现焊料桥(solderbridge)。另外，在固定球尺寸要求下，焊料球必须具有某一尺寸，而此又会限制可被充填在管芯的表面上的焊料球的数目。
在另一种封装类别中，管芯先被从晶片锯切出、之后被封装，且仅对“已知合格管芯(known-good-die)”进行封装。此种封装技术的有利特征是可形成扇出型封装，这意味着，管芯上的输入/输出焊盘可被重布至比管芯大的面积，且因此充填在管芯的表面上的输入/输出焊盘的数目可增加。
发明内容
本发明实施例提供一种结构，包括一个或多个主管芯，一个或多个虚设管芯、模塑料、多个重布线层以及多个外部连接件。所述一个或多个虚设管芯中的虚设管芯被定位在所述一个或多个主管芯中的主管芯旁边。所述模塑料沿所述一个或多个主管芯的侧壁及所述一个或多个虚设管芯的侧壁延伸。所述多个重布线层包括多个通孔及多个导电线，所述一个或多个主管芯接触所述多个重布线层的第一表面。所述多个外部连接件设置在所述多个重布线层的第二表面上，所述第一表面与所述第二表面是所述多个重布线层的相对表面。
附图说明
结合附图阅读以下详细说明，会最佳地理解本发明实施例的各方面。应注意，根据本行业中的标准惯例，各种特征并非按比例绘制。事实上，为使论述清晰起见，可任意增大或减小各种特征的尺寸。
图1是根据某些实施例的晶片的平面图。
图2A、图2B及图2C是根据某些实施例的装置的剖视图。
图3是根据某些实施例的晶片的平面图。
图4至图9是根据某些实施例在制造扇出型封装时的中间阶段的剖视图。
图10A、图10B及图10C是根据某些实施例在制造扇出型封装时的中间阶段的剖视图。
图11A、图11B及图11C是根据某些实施例在制造扇出型封装时的中间阶段的剖视图。
图12A、图12B及图12C是根据某些实施例在制造扇出型封装时的中间阶段的剖视图。
图13A、图13B、图13C及图13D是根据某些实施例在制造扇出型封装时的中间阶段的剖视图。
图14A、图14B、图14C及图14D是根据某些实施例在制造扇出型封装时的中间阶段的剖视图。
图15A、图15B、图15C及图15D是根据某些实施例在制造扇出型封装时的中间阶段的剖视图。
图16A、图16B、图16C及图16D是根据某些实施例在制造扇出型封装时的中间阶段的剖视图。
具体实施方式
以下公开内容提供用于实作本发明实施例的不同特征的许多不同的实施例或实例。下文阐述组件及构造的具体实例以简化本发明实施例。当然，这些仅为实例且不旨在进行限制。例如，以下说明中将第一特征形成在第二特征“之上”或第二特征“上”可包括其中第一特征与第二特征被形成为直接接触的实施例，且也可包括其中第一特征与第二特征之间可形成有额外特征、进而使得所述第一特征与所述第二特征可能不直接接触的实施例。另外，本发明实施例可能在各种实例中重复使用参考编号及/或字母。这种重复使用是出于简洁及清晰的目的，而不是自身表示所论述的各种实施例及/或配置之间的关系。
此外，为易于说明，本文中可能使用例如“在...下方(beneath)”、“在...下面(below)”、“下部的(lower)”、“上方(above)”、“上部的(upper)”等空间相对性用语来阐述图中所说明的一个元件或特征与另一(些)元件或特征的关系。所述空间相对性用语旨在除图中所绘示的取向外还囊括装置在使用或操作中的不同取向。设备可具有其他取向(旋转90度或其他取向)，且本文中所用的空间相对性描述语可同样相应地进行解释。
根据各种示例性实施例，提供一种包括一个或多个虚设管芯的集成扇出型(Integrated Fan-Out，“InFO”)封装及形成所述集成扇出型封装的方法。所述集成扇出型封装在平面图中的面积对所述封装被主管芯及虚设管芯覆盖的面积的比率可小于约2.5。包含所述虚设管芯及/或将所述比率降低至小于或等于约2.5可改进所述集成扇出型封装的翘曲特性。在某些实施例中，当将一个或多个虚设管芯包含在集成扇出型封装中及/或所述比率是约2.5或小于2.5时，所述集成扇出型封装可经历更少的翘曲及/或更对称的翘曲。说明形成所述集成扇出型封装的中间阶段并论述实施例的变化形式。
参照图1，其绘示晶片100的平面图。晶片100在晶片100的表面上包括多个集成扇出型封装102。在某些实施例中，集成扇出型封装102可覆盖晶片100的全部或实质上全部的表面。每一集成扇出型封装102包括一个或多个主管芯104。虽然在图1所示每一集成扇出型封装102中绘示了一个主管芯104，然而，在某些实施例中，每一集成扇出型封装102中可存在多于一个主管芯104。集成扇出型封装102可与相邻集成扇出型封装102具有相同数目的主管芯104，或者集成扇出型封装102可与相邻集成扇出型封装102具有不同数目的主管芯104。在各相邻集成扇出型封装102中，主管芯104可具有相同尺寸，或者在各相邻集成扇出型封装102中，主管芯104可具有不同尺寸。主管芯104可为包括电路及/或有源装置或无源装置的功能性管芯。可包括任何适合的主管芯104。举例来说，主管芯104可包括静态随机存取存储器(static random access memory，SRAM)芯片或动态随机存取存储器(dynamicrandom access memory，DRAM)芯片、处理器芯片、存储器芯片、逻辑芯片、模拟芯片、数字芯片、中央处理器(central processing unit，CPU)、图形处理器(graphics processingunit，GPU)或其组合等。
可确定集成扇出型封装102在平面图中的面积对集成扇出型封装102在平面图中被一个或多个主管芯104覆盖的面积的比率。在图1中，根据以下关系式来确定集成扇出型封装102被主管芯104覆盖的面积：管芯面积＝B×D，其中B及D是矩形主管芯104的侧壁在平面图中的长度。如果主管芯104在平面图中具有不同于矩形的形状，则可使用任何适合的关系式来确定主管芯104在集成扇出型封装102的平面图中的面积。根据关系式封装面积＝A×C来确定集成扇出型封装102的面积，其中A及C是矩形集成扇出型封装102的侧壁在平面图中的尺寸。如果集成扇出型封装102在平面图中具有不同于矩形的形状，则可使用任何适合的关系式来确定集成扇出型封装102在集成扇出型封装102的平面图中的面积。
在某些实施例中，当集成扇出型封装102在平面图中的面积对集成扇出型封装102在平面图中被一个或多个主管芯104覆盖的面积的比率大于约2.5时，则晶片100及/或相应集成扇出型封装102可经历难以接受的翘曲。举例来说，主管芯104可因此类管芯104中存在的半导体材料(例如，硅)而具有大约3.0的有效热膨胀系数(effective CTE)。所述集成扇出型封装可进一步包括可具有更高有效热膨胀系数的各种其他材料(例如，模制化合物42及/或绝缘层穿孔(TIV)33(参见图12A至图12C))。当所述比率是约2.5或大于2.5时，主管芯104与集成扇出型封装102的其他材料之间的热膨胀系数失配可能会在晶片100及集成扇出型封装102处于室温(例如，大约25摄氏度)时以及在晶片100及集成扇出型封装102被暴露至高温(例如，大约260摄氏度或高于260摄氏度)时引起难以接受的翘曲。举例来说，晶片100可具有大得难以接受的“哭泣状”轮廓，如图2A中所说明，其中晶片100的中间部分高于晶片100的边缘部分。在某些实施例中，如图2A中所说明，晶片100的中间部分与晶片100的边缘部分之间的距离T1可为约100μm至约1300μm。晶片100也可具有大得难以接受的微笑状轮廓，如图2C中所说明。在某些实施例中，如图2C中所说明，晶片100的中间部分与晶片100的边缘部分之间的距离T2可为约100μm至约1300μm。晶片100所经历的翘曲可为非对称的。晶片100的难以接受的翘曲可降低晶片100的性能及可靠性。
晶片100的难以接受的翘曲可至少部分地归因于晶片100的表面上的相应集成扇出型封装102发生难以接受的翘曲。举例来说，相应集成扇出型封装102可具有大得难以接受的“哭泣状”轮廓，如图2A中所说明，其中集成扇出型封装102的中间部分高于集成扇出型封装102的边缘部分。在某些实施例中，如图2A中所说明，集成扇出型封装102的中间部分与集成扇出型封装102的边缘部分之间的距离T1可为约60μm至约120μm。集成扇出型封装102也可具有大得难以接受的微笑状轮廓，如图2C中所说明。在某些实施例中，如图2C中所说明，集成扇出型封装102的中间部分与集成扇出型封装102的边缘部分之间的距离T2可为约60μm至约120μm。相应集成扇出型封装102所经历的翘曲可为非对称的。相应集成扇出型封装102的难以接受的翘曲可降低集成扇出型封装102的性能及可靠性。
参照图3，在某些实施例中，可在集成扇出型封装102中插入一个或多个虚设管芯(例如，虚设管芯106)，以降低所得集成扇出型封装102与晶片100的热膨胀系数失配并改进所得集成扇出型封装102与晶片100的翘曲轮廓。虚设管芯106的数目及虚设管芯106的尺寸可被确定成使得每一集成扇出型封装102在集成扇出型封装102的平面图中的面积对集成扇出型封装102在集成扇出型封装102的平面图中被一个或多个主管芯104及被虚设管芯106覆盖的面积的比率是约2.5或小于2.5。尽管主管芯104可为含有装置、电路等的功能性管芯，然而，虚设管芯106可为非功能性管芯且在某些实施例中可能不含有任何装置及/或功能性电路。
在某些实施例中，可根据关系式虚设面积＝F×E来确定虚设管芯106中的一者的尺寸，其中F及E是矩形虚设管芯106的侧壁在集成扇出型封装102的平面图中的尺寸。当虚设管芯106的形状并非是矩形时，可使用任何适合的关系式来确定虚设管芯在集成扇出型封装102的平面图中的面积。如果集成扇出型封装102包括多于一个虚设管芯106，则可确定集成扇出型封装102中被每一虚设管芯覆盖的面积，且可通过将被每一虚设管芯覆盖的面积相加来确定集成扇出型封装中被所有虚设管芯覆盖的总面积(总虚设面积)。
根据关系式管芯面积＝B×D来确定集成扇出型封装被主管芯104覆盖的面积，其中B及D是矩形主管芯104的侧壁在平面图中的长度。如果主管芯104在平面图中具有不同于矩形的形状，则可使用任何适合的关系式来确定主管芯104在集成扇出型封装102的平面图中的面积。如果集成扇出型封装102包括多于一个主管芯104，则可确定集成扇出型封装102中被每一主管芯104覆盖的面积，且可通过将被每一主管芯104覆盖的面积相加来确定集成扇出型封装102中被所有主管芯104覆盖的总面积(总管芯面积)。
根据关系式封装面积＝A×C来确定集成扇出型封装102的面积，其中A及C是矩形集成扇出型封装102的侧壁在平面图中的尺寸。如果集成扇出型封装102在平面图中具有不同于矩形的形状，则可使用任何适合的关系式来确定集成扇出型封装102在集成扇出型封装102的平面图中的面积。
接着，可根据关系式比率＝封装面积/(总管芯面积+总虚设面积)来确定集成扇出型封装102在平面图中的面积对集成扇出型封装102在平面图中被一个或多个主管芯104及被虚设管芯106覆盖的面积的比率。当所述比率是约2.5或小于2.5时，相应集成扇出型封装102及晶片100所经历的翘曲可得以减弱及/或可更对称。在某些实施例中，当晶片100包括比率为约2.5或小于2.5的集成扇出型封装102时，晶片100可如图2B所说明具有实质上平整的横向表面。通过包含虚设管芯106并将所述比率降低至2.5或小于2.5，具有哭泣状轮廓的晶片100的最高点与最低点之差(图2A中的尺寸T1)可得以减小。在某些实施例中，中间部分与边缘部分之间的距离T1可为约50μm至约1100μm。通过包含虚设管芯106并将所述比率降低至2.5或小于2.5，具有微笑状轮廓的晶片100的最高点与最低点之差(图2C中的尺寸T2)可得以减小。在某些实施例中，中间部分与边缘部分之间的距离T2可为约50μm至约1100μm。
在某些实施例中，相应集成扇出型封装102具有约2.5或小于2.5的比率也可使得集成扇出型封装102如图2B所说明具有实质上平整的横向表面。通过包含虚设管芯106并将所述比率降低至2.5或小于2.5，具有哭泣状轮廓的相应集成扇出型封装102的最高点与最低点之差(图2A中的尺寸T1)可得以减小。在某些实施例中，中间部分与边缘部分之间的距离T1可为约0μm至约55μm。通过包含虚设管芯106并将所述比率降低至2.5或小于2.5，具有微笑状轮廓的相应集成扇出型封装102的最高点与最低点之差(图2C中的尺寸T2)可得以减小。在某些实施例中，中间部分与边缘部分之间的距离T2可为约0μm至约55μm。
虚设管芯106可包含任何适用于将集成扇出型封装102的有效热膨胀系数调整至所需水平的材料。虚设管芯106可包含用于使集成扇出型封装102的有效热膨胀系数降低的材料，例如硅、玻璃、或陶瓷。在其他实施例中，虚设管芯106可包含用于提高有效热膨胀系数的材料，例如铜或聚合物。在某些实施例中，虚设管芯106由主管芯104中所包含的相同材料构成或包含主管芯104中所包含的相同材料。举例来说，在某些实施例中，虚设管芯106可被选择成使虚设管芯106的有效热膨胀系数相同于或相似于主管芯104的有效热膨胀系数。
图4到图16A至图16D说明根据某些实施例在形成半导体封装时的中间步骤的剖视图。首先参照图4，其示出上面形成有释放层22的载体衬底20。通常，载体衬底20在后续处理步骤期间提供临时机械与结构支撑。载体衬底20可包含任何适合材料，例如硅系材料(例如硅晶片、玻璃、或氧化硅)、或其他材料(例如氧化铝、陶瓷材料)、这些材料中任何者的组合等。在某些实施例中，载体衬底20是平坦的，以适应其他处理。
释放层22是在载体衬底20之上形成的可选层，其可容许载体衬底20被更容易地移除。如下文更详细地解释，将在载体衬底20之上放置各种层及装置，此后可移除载体衬底20。可选释放层22帮助将载体衬底20移除，从而减少对在载体衬底20之上形成的结构的损坏。释放层22可由聚合物系材料形成。在某些实施例中，释放层22是在受热时会丧失其粘着性的环氧树脂系热释放材料(epoxy-based thermal release material)，例如光/热转换(Light-to-Heat-Conversion，LTHC)释放涂层。在其他实施例中，释放层22可为紫外(ultra-violet，UV)胶，其在被暴露至紫外光时会丧失其粘着性。释放层22可以液体形式施用配置并进行固化。在其他实施例中，释放层22可为被积层至载体衬底20上的积层膜。也可利用其他释放层。
参照图4，在释放层22之上形成缓冲层24。缓冲层24是介电层，其可为聚合物(例如聚苯并恶唑(polybenzoxazole，PBO)、聚酰亚胺、苯环丁烷(benzocyclobutene，BCB)等)、氮化物(例如氮化硅等)、氧化物(例如氧化硅、磷硅酸盐玻璃(PhosphoSilicate Glass，PSG)、硼硅酸盐玻璃(BoroSilicate Glass，BSG)、掺硼磷硅酸盐玻璃(Boron-dopedPhosphoSilicate Glass，BPSG)、或其组合等)等且可例如通过旋转涂布(spin coating)、积层(lamination)、化学气相沉积(Chemical Vapor Deposition，CVD)等来形成。在某些实施例中，缓冲层24是具有均匀厚度的平坦层，其中所述厚度可介于约2μm与约6μm之间。缓冲层24的顶表面及底表面也是平坦的。
现在参照图5至图9，其示出根据某些实施例视需要来形成穿孔(through vias，“TV”)33(参见图9)。穿孔33提供从集成扇出型封装102的一侧至集成扇出型封装102的另一侧的电连接。举例来说，如下文将更详细地解释，将向缓冲层24安装主管芯104及虚设管芯106，且将围绕穿孔及管芯形成模制化合物。随后，可将另一装置(例如另一管芯、封装、衬底等)贴合至管芯及模制化合物。穿孔33提供所述另一装置与所述封装的背侧之间的电连接，而不必使电信号穿过安装至缓冲层24的主管芯104。
可例如通过如图5中所示在缓冲层24之上形成导电晶种层26来形成穿孔33。在某些实施例中，晶种层26是金属层，其可为单个层或可为包括由不同材料形成的多个子层的复合层。晶种层26可由铜、钛、镍、金或其组合等制成。在某些实施例中，晶种层26包括钛层及位于所述钛层之上的铜层。可例如利用物理气相沉积(physical vapor deposition，PVD)、化学气相沉积、原子层沉积(atomic layer deposition，ALD)、其组合等来形成晶种层26。在某些实施例中，晶种层26包括钛层及位于所述钛层之上的铜层。在替代实施例中，晶种层26是铜层。
转至图6，可沉积并图案化掩模层(例如经图案化光刻胶层28)，其中所述掩模层中的开口30暴露出晶种层26。参照图7，可例如利用无电镀敷工艺(electroless platingprocess)或电化学镀敷工艺(electrochemical plating process)来用导电材料填充开口30，从而形成金属特征32。所述镀敷工艺可单向地(例如，从晶种层26向上)填充经图案化光刻胶层28中的开口。单向填充可容许对此类开口进行更均匀的填充。作为另一选择，可在经图案化光刻胶层28中的开口30的侧壁上形成另一晶种层，且可多向地填充此类开口。金属特征32可包含铜、铝、钨、镍、焊料、或其合金。金属特征32的俯视图形状可为矩形、正方形、圆形等。金属特征32的高度由随后放置的主管芯104及/或虚设管芯106(图10A至图10C中所示)的厚度决定，其中在某些实施例中，金属特征32的高度大于主管芯104及/或虚设管芯106的厚度。
接下来，可例如以灰化(ashing)工艺及/或湿式剥除(wet strip)工艺来移除掩模层，如图8中所示。参照图9，执行蚀刻步骤，以移除晶种层26的暴露出的部分，其中所述蚀刻可为各向异性蚀刻。另一方面，晶种层26的与金属特征32交叠的部分保持不被蚀刻。金属特征32与晶种层26的剩余下伏部分形成穿孔33。虽然晶种层26被示出为与金属特征32分开的层，然而，当晶种层26是由与相应上覆金属特征32相似或相同的材料形成时，晶种层26可与金属特征32合并且其之间无可区分开的界面。在某些实施例中，晶种层26与上覆金属特征32之间存在可区分开的界面。也可用通过丝焊(wire bonding)工艺(例如铜丝焊工艺)放置的金属线接线柱(metal wire stud)来实现穿孔33。使用丝焊工艺可消除对沉积晶种层26、沉积及图案化掩模层28、以及进行镀敷以形成穿孔33的需要。
图10A至图10C说明根据某些实施例将主管芯104及虚设管芯106贴合至缓冲层24的背侧。通过粘着层36(例如管芯贴合膜(die-attach film，DAF))将主管芯104及虚设管芯106中的每一者粘附至缓冲层24。粘着层36的厚度可处于从约5μm至约50μm的范围中，例如约10μm。可如图10A至图10C中所说明使用一个主管芯104及一个虚设管芯106，或在某些实施例中，可使用多于一个主管芯104及/或多于一个虚设管芯106。对于图10A至图10C所示实施例中的每一者，集成扇出型封装102在平面图中的面积对集成扇出型封装102被主管芯104及虚设管芯106覆盖的面积的比率是约2.5或小于2.5。因此，图10A至图10C中的每一者所示的集成扇出型封装102可经历减弱的翘曲及/或更对称的翘曲，此可提高集成扇出型封装102的可靠性且提高集成扇出型封装102的性能。
可针对特定设计或应用将主管芯104及虚设管芯106贴合至适合的位置。举例来说，图10A至图10C说明其中主管芯104及虚设管芯106被安装在中心区中的实施例，其中穿孔33是围绕周边而定位。在其他实施例中，主管芯104及/或虚设管芯106可相对于中心偏移。
在贴合至缓冲层24之前，可根据适用制造工艺来处理主管芯104，以在主管芯104中形成集成电路。主管芯104可包括半导体衬底35，其中所述半导体衬底的背侧贴合至粘着层36。在某些示例性实施例中，主管芯104包括金属柱40(例如铜支柱)，金属柱40电耦合到主管芯104中例如晶体管(图中未示出)等的装置。在某些实施例中，在主管芯104的顶表面处形成有介电层38，其中金属柱40的至少下部部分位于介电层38中。在某些实施例中，金属柱40的顶表面还可与介电层38的顶表面齐平。作为另一选择，不形成介电层38，且金属柱40突出至相应主管芯104的顶部层上方。
图10A至图10C绘示可被包含在集成扇出型封装102中的虚设管芯106的各种实施例。在图10A至图10C到图15A至图15D中，以“A”结尾的图绘示第一实施例，以“B”结尾的图绘示第二实施例，以“C”结尾的图绘示第三实施例，且以“D”结尾的图绘示第四实施例。
参照图10A，虚设管芯106可包括半导体衬底35，其中半导体衬底35的背侧贴合至粘着层36。在某些实施例中，半导体衬底35可包含与主管芯104的半导体衬底35相同的材料。视需要，在虚设管芯106的半导体衬底35的与接触所述粘着层的表面相对的表面上包含介电层38。虚设管芯106的介电层38可包含与主管芯104的介电层38相同的材料。在图10A所示实施例中，在虚设管芯106中未包含电触点(例如金属柱40)。作为另一选择，在虚设管芯106的介电层38中包含金属柱40，如图10B中所示。在某些实施例中，金属柱40包含铜等。
在图10A及图10B所示实施例中，虚设管芯106具有与主管芯104相同的厚度，其中所述厚度是在与穿孔33平行的方向上测量。作为另一选择，如图10C中所示，虚设管芯106可具有比主管芯104的厚度小的厚度。在某些实施例中，主管芯104可具有40μm至300μm的厚度T3，而虚设管芯106可具有40μm至300μm的厚度T4。在某些实施例中，虚设管芯106的厚度T4对主管芯104的厚度T3的比率可为约40％至约100％。
参照图11A至图11C，在主管芯104、虚设管芯106、及穿孔33上模制出模塑料42。模塑料42填充主管芯104与虚设管芯106之间、主管芯104与穿孔33之间、以及虚设管芯106与穿孔33之间的间隙，且可接触缓冲层24。此外，当金属柱40是突出的金属柱时，模塑料42被填充至金属柱40中。可例如利用压缩模制(compression molding)在主管芯104、虚设管芯106、及穿孔33上模制出模塑料42。在某些实施例中，模塑料42是模制化合物、聚合物、环氧树脂、氧化硅填充材料等、或其组合。可执行固化步骤，以使模塑料42固化，其中所述固化可为热固化(thermal curing)、紫外固化等、或其组合。模塑料42的顶表面高于主管芯104上的金属柱40的顶端及穿孔33的顶端。
接下来，执行研磨步骤以将模塑料42薄化，直至主管芯104上的金属柱40、及穿孔33被暴露出为止。图12A至图12C中示出所得结构。由于所述研磨，金属特征32的顶端与主管芯104上的金属柱40的顶端实质上齐平(共面)，且与模塑料42的顶表面实质上齐平(共面)。在其中虚设管芯106具有与主管芯104相同的厚度的实施例中，所述研磨步骤会暴露出虚设管芯106的顶表面。举例来说，研磨工艺可暴露出虚设管芯106的介电层38及/或虚设管芯106的金属柱40。
在其中虚设管芯106具有比主管芯104的厚度小的厚度的实施例中，所述研磨步骤不会暴露出虚设管芯106，如图12C中所示。在研磨步骤之后，模塑料覆盖虚设管芯106的距载体衬底20最远的表面。
作为所述研磨的结果，可能会产生金属残渣(例如金属颗粒)，且其留在模塑料42的顶表面及主管芯104的顶表面上。因此，在研磨之后，可例如通过湿式蚀刻来执行清洁，以使金属残渣被移除。
接下来，参照图13A至图13C，形成一个或多个重布线层(redistribution layer，RDL)43。通常，重布线层会提供导电图案，以容许成品封装的引脚输出接触图案(pin-outcontact pattern)不同于穿孔33及/或金属柱40的图案，从而容许对穿孔33及主管芯104的放置具有更大灵活性。重布线层可用于提供与主管芯104及/或穿孔33的外部电连接。重布线层可进一步用于将主管芯104电耦合到穿孔33，穿孔33可电耦合到一个或多个其他封装、封装衬底、组件等、或其组合。重布线层包括导电线44及通孔接点48，其中通孔接点48将上覆线(例如，上覆导电线44)连接到下伏导电特征(例如，穿孔33、金属柱40及/或导电线44)。导电线44可沿任一方向延伸。图13A至图13C说明三层重布线层，但可存在一层、两层、或多于三层的重布线层43，这视相应集成扇出型封装102的布线要求而定。
可利用任何适合的工艺来形成重布线层43。举例来说，在某些实施例中，在模塑料42上以及在主管芯104及虚设管芯106之上形成介电层50。在某些实施例中，介电层50是由聚合物形成，所述聚合物可为可利用光刻进行图案化的感光性材料，例如聚苯并恶唑(PBO)、聚酰亚胺、苯环丁烷(BCB)等。在其他实施例中，介电层50是由氮化物(例如氮化硅)、氧化物(例如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、掺硼磷硅酸盐玻璃(BPSG))等形成。可通过旋转涂布、积层、化学气相沉积等、或其组合来形成介电层50。接着，将介电层50图案化以形成开口，从而暴露出主管芯104的金属柱40并暴露出穿孔33。在其中导电线44电连接到虚设管芯106(参见图13D)的实施例中，虚设管芯106上的电连接件也会被暴露出。在其中介电层50是由感光性材料形成的实施例中，可通过根据所需图案将介电层50曝光并显影以移除不需要的材料来执行所述图案化。也可使用其他方法(例如使用经图案化掩模并进行蚀刻)来将介电层50图案化。
在介电层50之上以及在形成于介电层50中的开口中形成晶种层(图中未示出)。在某些实施例中，所述晶种层是金属层，其可为单个层或为包括由不同材料形成的多个子层的复合层。在某些实施例中，所述晶种层包括钛层及位于所述钛层之上的铜层。可例如利用物理气相沉积等来形成所述晶种层。接着，在所述晶种层上形成掩模，并根据所需重布线图案(例如，图13A至图13D中所说明的图案)将所述掩模图案化。在某些实施例中，所述掩模是通过旋转涂布等形成并被暴露至光以进行图案化的光刻胶。所述图案化会穿过掩模而形成开口，以暴露出晶种层。在掩模的开口中以及在晶种层的暴露出的部分上形成导电材料。可通过镀敷(例如电镀或无电镀敷)等来形成所述导电材料。所述导电材料可包括金属，如铜、钛、钨、铝等。接着，移除光刻胶以及移除晶种层的上面未形成导电材料的部分。可例如利用氧等离子等通过可接受的灰化工艺或剥除工艺来移除光刻胶。一旦光刻胶被移除，便例如利用可接受的蚀刻工艺(例如通过湿式蚀刻或干式蚀刻)来移除晶种层的暴露出的部分。所述晶种层的剩余部分与所述导电材料形成导电线44及通孔接点48。在介电层50之上形成介电层52，以为后续各层提供更平坦的表面，且可利用与用于形成介电层50的材料及工艺相似的材料及工艺来形成介电层52。在某些实施例中，介电层52是由聚合物、氮化物、氧化物等形成。在某些实施例中，介电层52是聚苯并恶唑并通过旋转涂布工艺而形成。
以上过程阐述了对一层重布线层43的形成。可视需要重复以上过程，以在需要时形成额外的重布线层43。
如上所述，在某些实施例中，虚设管芯106不形成有任何用于将虚设管芯106电连接到外部组件的电连接件。因此，不需要将重布线层43的任何通孔连接件48或导电线44连接到虚设管芯106。图13A及图13C中示出其中虚设管芯106不具有金属柱40的实施例的实例。在其他实施例中，虚设管芯106可在虚设管芯106的距载体衬底20最远的表面上形成有金属柱40。图13B及图13D中示出其中虚设管芯106包括金属柱40的实施例的实例。如图13B中所示，在某些实施例中，重布线层43的导通孔48或导电线44均不被形成为连接到虚设管芯106中的金属柱40。因此，金属柱40可接触重布线层43的介电层且与重布线层43的任何导通孔48或导电线44电隔离。参照图13D，在某些实施例中，可在重布线层43中形成与虚设管芯106中的金属柱40电连接的导通孔48及导电线。在某些实施例中，可将虚设管芯106的金属柱40电连接到集成扇出型封装102的接地节点。
图14A至图14D说明根据某些实施例在图13A至图13D所示结构的最上部金属化图案之上形成并图案化从而与最上部金属化层形成电连接的凸块下金属化层(under bumpmetallization，UBM)70。凸块下金属化层70提供上面可放置电连接件(例如，焊料球/凸块、导电柱等)的电接点。在实施例中，凸块下金属化层70包括扩散障壁层、晶种层或其组合。所述扩散障壁层可包含Ti、TiN、Ta、TaN、或其组合。所述晶种层可包含铜或铜合金。然而，也可包含其他金属，例如镍、钯、银、金、铝、其组合及其多层。在实施例中，利用溅镀来形成凸块下金属化层70。在其他实施例中，可使用电镀。
根据某些实施例，在凸块下金属化层70之上形成连接件68。连接件68可为焊料球、金属柱、受控塌陷芯片连接(controlled collapse chip connection，C4)凸块、微凸块、由无电镀镍钯浸金技术(electroless nickel-electroless palladium-immersion goldtechnique，ENEPIG)形成的凸块、其组合(例如，贴合有焊料球的金属柱)等。连接件68可包含导电材料，例如焊料、铜、铝、金、镍、银、钯、锡等或其组合。在某些实施例中，连接件68包含共熔材料(eutectic material)，且作为实例可包括焊料凸块或焊料球。焊料材料可例如是铅系焊料及无铅焊料，例如，用于铅系焊料的Pb-Sn组合物；无铅焊料包含：InSb；锡、银及铜(tin,silver,and copper，SAC)组合物；以及电应用中具有共同熔点且形成导电焊料接点的其他共熔材料。对于无铅焊料，可使用组成各异的SAC焊料，例如，作为实例：SAC 105(Sn 98.5％、Ag 1.0％、Cu 0.5％)、SAC 305及SAC 405。例如焊料球等的无铅连接件也可由SnCu化合物形成，而不使用银(Ag)。作为另一选择，无铅焊料连接件可包含锡及银(Sn-Ag)，而不使用铜。连接件68可形成栅格，例如球栅阵列封装(ball grid array，BGA)。在某些实施例中，可执行回焊工艺(reflow process)，从而在某些实施例中对连接件68赋予局部球体的形状。作为另一选择，连接件68可包括其他形状。例如，连接件68也可包括非球形导电连接件。
在某些实施例中，连接件68包括通过溅镀、印刷、电镀、无电镀敷、化学气相沉积等形成的上面具有或不具有焊料材料的金属柱(例如铜柱)。所述金属柱可为无焊料的且具有实质上垂直侧壁或锥形侧壁。
接下来，从封装剥离载体衬底20。也从封装清除释放层22。图15A至图15D中示出所得结构。作为移除释放层22的结果，缓冲层24被暴露出。
在后续处理(图中未示出)中，如果同时形成多个集成扇出型封装，则可将所述集成扇出型封装单体化(singulate)成多个集成扇出型封装102。
参照图16A至图16C，可将顶部封装300接合至集成扇出型封装102。顶部封装300包括衬底302及耦合到衬底302的一个或多个堆叠管芯308(308A及308B)。衬底302可由例如硅、锗、金刚石等的半导体材料制成。在某些实施例中，也可使用化合物材料，例如硅锗、碳化硅、镓砷、砷化铟、磷化铟、碳化硅锗、磷化镓砷、磷化镓铟这些的组合等。另外，衬底302可为绝缘体上半导体(semiconductor on insulator，SOI)衬底。通常，绝缘体上半导体衬底包括一层半导体材料，例如外延硅、锗、硅锗、绝缘体上硅(silicon on insulator，SOI)、绝缘体上硅锗(silicon germanium on insulator，SGOI)或其组合。在一个替代实施例中，衬底302是基于绝缘芯，例如玻璃纤维强化树脂芯(fiberglass reinforced resin core)。一种示例性芯材料是玻璃纤维树脂，例如FR4。所述芯材料的替代方案包括双马来酰亚胺-三嗪(bismaleimide-triazine，BT)树脂，或作为另一选择，包括其他印刷电路板(printedcircuit board，PCB)材料或膜。可将例如味之素增层膜(Ajinomoto build-up film，ABF)等的增层膜或其他积层体用于衬底302。
衬底302可包括有源装置及无源装置(图中未示出)。所属领域中的普通技术人员应认识到，可使用各种各样的装置(例如晶体管、电容器、电阻器这些的组合等)来满足用于半导体封装300的设计的结构性及功能性要求。可利用任何适合的方法来形成所述装置。
衬底302还可包括金属化层(图中未示出)及穿孔306。所述金属化层可形成在有源装置及无源装置之上且被设计成连接各种装置以形成功能性电路。所述金属化层可由介电材料(例如，低介电常数介电材料)与导电材料(例如，铜)的交替层形成(其中通孔对各层导电材料进行内连)且可通过任何适合的工艺(例如沉积、镶嵌(damascene)、双重镶嵌(dualdamascene)等)来形成。在某些实施例中，衬底302实质上不具有有源装置及无源装置。
衬底302可具有位于衬底302的第一侧上以耦合到堆叠管芯308的接合焊盘303以及位于衬底302的第二侧上以耦合到导电连接件314的接合焊盘304，所述第二侧与衬底302的第一侧相对。在某些实施例中，接合焊盘303及304是通过向衬底302的第一侧及第二侧上的介电层(图中未示出)中形成凹槽(图中未示出)而形成。所述凹槽可被形成为容许接合焊盘303及304被嵌入至所述介电层中。在其他实施例中，由于接合焊盘303及304可形成在所述介电层上，因而所述凹槽被省却。在某些实施例中，接合焊盘303及304包括由铜、钛、镍、金、钯等或其组合制成的薄晶种层(图中未示出)。可在所述薄晶种层之上沉积接合焊盘303及304的导电材料。可通过电化学镀敷工艺、无电镀敷工艺、化学气相沉积、原子层沉积、物理气相沉积等、或其组合来形成导电材料。在实施例中，接合焊盘303及304的导电材料是铜、钨、铝、银、金等或其组合。在实施例中，接合焊盘303及304是利用与前面结合凸块下金属化层70所述工艺相同或相似的工艺而形成的凸块下金属化层。
在所说明实施例中，堆叠管芯308是通过丝焊310耦合到衬底302，然而，可使用其他接点，例如导电凸块。在实施例中，堆叠管芯308是堆叠存储器管芯。举例来说，堆叠存储器管芯308可包括低功率(low-power，LP)双倍数据速率(double data rate，DDR)存储器模块，例如低功率双倍数据速率1存储器模块、低功率双倍数据速率2存储器模块、低功率双倍数据速率3存储器模块、低功率双倍数据速率4存储器模块等。
在某些实施例中，可通过模塑料312来包封堆叠管芯308及丝焊310。可例如利用压缩模制在堆叠管芯308及丝焊310上模制出模塑料312。在某些实施例中，模塑料312是模制化合物、聚合物、环氧树脂、氧化硅填充材料等或其组合。可执行固化步骤，以使模塑料312固化，其中所述固化可为热固化、紫外固化等或其组合。
在某些实施例中，堆叠管芯308及丝焊310被埋入模塑料312中，且在使模塑料312固化之后，执行平坦化步骤(例如研磨)，以移除模塑料312的多余部分并为第二封装300提供实质上平坦的表面。
在形成顶部封装300之后，顶部封装300通过导电连接件314及接合焊盘304而接合至集成扇出型封装102。在某些实施例中，堆叠存储器管芯308可经由丝焊310、接合焊盘303及304、穿孔306、导电连接件314及穿孔33而耦合到主管芯104。
导电连接件314可与上文所述连接件68相似，且本文中不再对其予以赘述，然而，导电连接件314与68不必是相同的。在某些实施例中，在对导电连接件314进行接合之前，用免清洗助焊剂(no-clean flux)等的助焊剂(图中未示出)来涂布导电连接件314。可将导电连接件314浸入助焊剂中，或可将助焊剂喷射至导电连接件314上。
在某些实施例中，导电连接件314上可在其被回焊之前先形成有环氧树脂助焊剂(图中未示出)，其中所述环氧树脂助焊剂的环氧树脂部分中的至少某些在顶部封装300贴合至集成扇出型封装102之后被保留。此所保留的环氧树脂部分可充当底部填充剂，以减小因对导电连接件314进行回焊而产生的应力并保护因对导电连接件314进行回焊而产生的接缝。在某些实施例中，可在顶部封装300与集成扇出型封装102之间以及在导电连接件314周围形成底部填充剂(图中未示出)。所述底部填充剂可在顶部封装300被贴合之后通过毛细管流动工艺(capillary flow process)而形成，或可在顶部封装300被贴合之前通过适合的沉积方法而形成。
顶部封装300与集成扇出型封装102之间的接合可为焊料接合或直接金属间接合(a direct metal-to-metal bonding)(例如铜-铜间或锡-锡间接合)。在实施例中，通过回焊工艺将顶部封装300接合至集成扇出型封装102。在此回焊工艺期间，导电连接件314接触接合焊盘304及穿孔33，以将顶部封装300物理耦合及电耦合到集成扇出型封装102。
根据某些实施例，一种集成扇出型封装包括一个或多个主管芯及一个或多个虚设管芯。所述集成扇出型封装在平面图中的面积对所述封装被主管芯及虚设管芯覆盖的面积的比率小于约2.5。包含所述虚设管芯及/或将所述比率降低至小于或等于约2.5可改进所述集成扇出型封装的翘曲特性。在某些实施例中，当所述比率是约2.5或小于2.5时，所述集成扇出型封装可经历更少的翘曲及/或更对称的翘曲。
根据某些实施例，提供一种结构。所述结构包括一个或多个主管芯及一个或多个虚设管芯，所述一个或多个虚设管芯中的虚设管芯被定位在所述一个或多个主管芯中的主管芯旁边。所述结构还包括模塑料，所述模塑料沿所述一个或多个主管芯的侧壁及所述一个或多个虚设管芯的侧壁延伸。所述结构还包括多个重布线层，所述多个重布线层包括多个通孔及多个导电线，所述一个或多个主管芯沿所述多个重布线层的第一表面延伸。所述结构还包括多个外部连接件，所述多个外部连接件沿所述多个重布线层的第二表面延伸，所述第一表面与所述第二表面是所述多个重布线层的相对表面。
在某些实施例中，所述结构在所述结构的平面图中的面积是第一面积，所述结构在所述结构的所述平面图中被所述一个或多个主管芯及所述一个或多个虚设管芯覆盖的面积是第二面积，且所述第一面积对所述第二面积的比率是2.5或小于2.5。在某些实施例中，所述一个或多个虚设管芯在所述相应虚设管芯的最靠近所述多个重布线层的表面处包括聚合物层。在某些实施例中，所述一个或多个虚设管芯包括设置在所述一个或多个虚设管芯的所述聚合物层中的多个金属柱。在某些实施例中，所述一个或多个虚设管芯在所述一个或多个虚设管芯的所述聚合物层中不包括电连接件。在某些实施例中，所述一个或多个主管芯的衬底包含与所述一个或多个虚设管芯的衬底相同的材料。在某些实施例中，所述一个或多个主管芯的有效热膨胀系数实质上相同于所述一个或多个虚设管芯的有效热膨胀系数。在某些实施例中，所述一个或多个虚设管芯中的虚设管芯的厚度小于所述一个或多个主管芯中的主管芯的厚度，其中所述一个或多个主管芯中的所述主管芯的所述厚度与所述一个或多个虚设管芯中的所述虚设管芯的所述厚度是在与所述一个或多个主管芯中的所述主管芯的主表面垂直的方向上测量。在某些实施例中，所述一个或多个虚设管芯中的虚设管芯包括沿所述虚设管芯的与所述多个重布线层最靠近的表面暴露出的多个电连接件。在某些实施例中，所述多个通孔中的通孔电连接到所述一个或多个虚设管芯中的所述虚设管芯的所述多个电连接件中的一个电连接件。在某些实施例中，所述多个通孔中的所述通孔将所述一个或多个虚设管芯中的所述虚设管芯的所述多个电连接件中的所述一个电连接件电连接到接地节点。在某些实施例中，所述一个或多个虚设管芯中的所述多个电连接件与所述多个重布线层的所述多个通孔及所述多个导电线电隔离。在某些实施例中，所述模塑料覆盖所述一个或多个虚设管芯的最靠近所述多个重布线层的表面。
根据某些实施例，提供一种结构。所述结构包括一个或多个主管芯。所述结构还包括一个或多个虚设管芯，所述一个或多个虚设管芯中的第一虚设管芯被定位在所述一个或多个主管芯中的主管芯旁边。所述结构还包括多个穿孔，其中所述多个穿孔中的穿孔被定位在所述一个或多个虚设管芯中的第二虚设管芯旁边。所述结构还包括模塑料，所述模塑料沿所述一个或多个主管芯的侧壁、所述一个或多个虚设管芯的侧壁及所述多个穿孔的侧壁延伸。所述结构还包括重布线层，所述重布线层位于所述一个或多个主管芯及所述一个或多个虚设管芯之上，其中所述重布线层包括多个导电线及多个通孔，且其中所述多个导电线电连接到所述一个或多个主管芯。
在某些实施例中，所述结构在所述结构的平面图中的面积是第一面积，所述结构在所述结构的所述平面图中被所述一个或多个主管芯及所述一个或多个虚设管芯覆盖的面积是第二面积，且所述第一面积对所述第二面积的比率是2.5或小于2.5。在某些实施例中，所述一个或多个虚设管芯的厚度小于所述一个或多个主管芯的厚度，所述一个或多个虚设管芯的所述厚度与所述一个或多个主管芯的所述厚度是在与所述一个或多个虚设管芯的主表面垂直的方向上测量。在某些实施例中，所述多个导电线中的导电线将所述一个或多个虚设管芯中的虚设管芯电连接到接地节点。
根据某些实施例，提供另一种结构。所述结构包括一个或多个主管芯及一个或多个虚设管芯。所述结构还包括模塑料，所述模塑料沿所述一个或多个主管芯的侧壁、所述一个或多个虚设管芯的侧壁及多个穿孔的侧壁延伸。所述结构还包括重布线层，所述重布线层位于所述一个或多个主管芯及所述一个或多个虚设管芯之上，其中所述重布线层包括多个导电线及多个通孔。所述结构在所述结构的平面图中的面积是第一面积，所述结构在所述结构的所述平面图中被所述一个或多个主管芯及所述一个或多个虚设管芯覆盖的面积是第二面积，且所述第一面积对所述第二面积的比率是2.5或小于2.5。
在某些实施例中，所述一个或多个虚设管芯中的虚设管芯在所述虚设管芯的最靠近所述重布线层的表面处包括聚合物层，其中电连接件不延伸穿过所述聚合物层。在某些实施例中，所述聚合物层接触介电层，所述重布线层设置在所述介电层中。以上内容概述了若干实施例的特征以使所属领域中的技术人员可更好地理解本发明实施例的各方面。所属领域中的技术人员应了解，他们可易于使用本发明实施例作为基础来设计或修改其他工艺及结构以施行本文所介绍实施例的相同目的及/或实现本文所介绍实施例的相同优点。所属领域中的技术人员还应认识到，此种等效构造并不背离本发明实施例的精神及范围，且在不背离本发明实施例的精神及范围的条件下，他们可对本文做出各种改变、替代及变更。

Claims (40)

1.一种封装结构，其特征在于，包括：
一个或多个主管芯；
一个或多个虚设管芯，所述一个或多个虚设管芯中的虚设管芯被定位在所述一个或多个主管芯中的主管芯旁边，且所述一个或多个虚设管芯中的所述虚设管芯包括设置在衬底上方的聚合物层，所述聚合物层限定所述一个或多个虚设管芯中的所述虚设管芯的表面；
模塑料，沿所述一个或多个主管芯的侧壁及所述一个或多个虚设管芯的侧壁延伸；以及
多个重布线层，包括多个通孔及多个导电线，其中每一个所述多个重布线层都设置在所述封装结构的相同水平处，所述一个或多个主管芯接触所述多个重布线层的第一表面，且所述一个或多个虚设管芯中的所述虚设管芯的设置方式是使由所述聚合物层限定的所述虚设管芯的所述表面最靠近所述多个重布线层的所述第一表面，且所述聚合物层在所述衬底与所述多个重布线层的所述第一表面之间延伸；以及
多个外部连接件，设置在所述多个重布线层的第二表面上，所述第一表面与所述第二表面是所述多个重布线层的相对表面。
2.根据权利要求1所述的封装结构，其特征在于，所述封装结构在所述封装结构的平面图中的面积是第一面积，所述封装结构在所述封装结构的所述平面图中被所述一个或多个主管芯及所述一个或多个虚设管芯覆盖的面积是第二面积，且所述第一面积对所述第二面积的比率是2.5或小于2.5。
3.根据权利要求1所述的封装结构，其特征在于，所述一个或多个虚设管芯中的所述虚设管芯包括设置在所述聚合物层中的多个金属柱。
4.根据权利要求3所述的封装结构，其特征在于，在所述一个或多个虚设管芯的所述虚设管芯的所述聚合物层中不包括电连接件。
5.根据权利要求1所述的封装结构，其特征在于，所述一个或多个主管芯的衬底包含与所述一个或多个虚设管芯的所述衬底相同的材料。
6.根据权利要求5所述的封装结构，其特征在于，所述一个或多个主管芯的有效热膨胀系数相同于所述一个或多个虚设管芯的有效热膨胀系数。
7.根据权利要求6所述的封装结构，其特征在于，所述一个或多个虚设管芯中的所述虚设管芯的厚度小于所述一个或多个主管芯中的主管芯的厚度，其中所述一个或多个主管芯中的所述主管芯的所述厚度与所述一个或多个虚设管芯中的所述虚设管芯的所述厚度是在与所述一个或多个主管芯中的所述主管芯的主表面垂直的方向上测量。
8.根据权利要求1所述的封装结构，其特征在于，所述一个或多个虚设管芯中的所述虚设管芯包括沿所述虚设管芯的与所述多个重布线层的所述第一表面最靠近的所述表面暴露出的电连接件。
9.根据权利要求8所述的封装结构，其特征在于，所述多个通孔中的通孔电连接到所述一个或多个虚设管芯中的所述虚设管芯的所述电连接件。
10.根据权利要求9所述的封装结构，其特征在于，所述多个通孔中的所述通孔将所述一个或多个虚设管芯中的所述虚设管芯的所述电连接件电连接到接地节点。
11.根据权利要求8所述的封装结构，其特征在于，所述一个或多个虚设管芯中的所述电连接件与所述多个重布线层的所述多个通孔及所述多个导电线电隔离。
12.根据权利要求1所述的封装结构，其特征在于，所述模塑料覆盖所述一个或多个虚设管芯的最靠近所述多个重布线层的所述第一表面的所述表面。
13.一种封装结构，其特征在于，包括：
一个或多个主管芯；
一个或多个虚设管芯，所述一个或多个虚设管芯中的第一虚设管芯被定位在所述一个或多个主管芯中的主管芯旁边；
多个穿孔，其中所述多个穿孔中的穿孔被定位在所述一个或多个虚设管芯中的第二虚设管芯旁边；
模塑料，沿所述一个或多个主管芯的侧壁、所述一个或多个虚设管芯的侧壁、及所述多个穿孔的侧壁延伸；以及
重布线层，位于所述一个或多个主管芯及所述一个或多个虚设管芯之上，其中所述重布线层包括多个导电线及多个通孔，且其中所述多个导电线电连接到所述一个或多个主管芯。
14.根据权利要求13所述的封装结构，其特征在于，所述结构在所述结构的平面图中的面积是第一面积，所述结构在所述结构的所述平面图中被所述一个或多个主管芯及所述一个或多个虚设管芯覆盖的面积是第二面积，且所述第一面积对所述第二面积的比率是2.5或小于2.5。
15.根据权利要求13所述的封装结构，其特征在于，所述一个或多个虚设管芯的厚度小于所述一个或多个主管芯的厚度，所述一个或多个虚设管芯的所述厚度与所述一个或多个主管芯的所述厚度是在与所述一个或多个虚设管芯的主表面垂直的方向上测量。
16.根据权利要求13所述的封装结构，其特征在于，所述多个导电线中的导电线将所述一个或多个虚设管芯中的虚设管芯电连接到接地节点。
17.一种封装结构，其特征在于，包括：
一个或多个主管芯；
一个或多个虚设管芯，所述一个或多个虚设管芯中的虚设管芯被定位在所述一个或多个主管芯中的主管芯旁边；
模塑料，沿所述一个或多个主管芯的侧壁及所述一个或多个虚设管芯的侧壁延伸；以及
重布线层，位于所述一个或多个主管芯及所述一个或多个虚设管芯之上，其中所述重布线层包括多个导电线及多个通孔；且
其中所述结构在所述结构的平面图中的面积是第一面积，所述结构在所述结构的所述平面图中被所述一个或多个主管芯及所述一个或多个虚设管芯覆盖的面积是第二面积，且所述第一面积对所述第二面积的比率是2.5或小于2.5。
18.根据权利要求17所述的封装结构，其特征在于，所述一个或多个虚设管芯中的所述虚设管芯在所述虚设管芯的最靠近所述重布线层的表面处包括聚合物层，其中电连接件不延伸穿过所述聚合物层。
19.根据权利要求18所述的封装结构，其特征在于，所述聚合物层接触介电层，所述重布线层设置在所述介电层中。
20.根据权利要求18所述的封装结构，其特征在于，所述的封装结构更包括延伸穿过模塑料的多个穿孔，其中所述多个穿孔中的穿孔设置在所述一个或多个虚设管芯的所述虚设管芯的旁边。
21.一种形成封装结构的方法，其特征在于，包括：
将功能性管芯和第一虚设管芯放置在第一衬底上，其中所述第一虚设管芯包括设置在第二衬底上方的聚合物层；
用模塑料包封所述功能性管芯和所述第一虚设管芯的侧壁；
在所述功能性管芯和所述第一虚设管芯上形成重布线结构，所述重布线结构包括多个导电线及多个介电层，其中，所述功能性管芯电连接到所述多个导电线中的第一导电线，且所述第一虚设管芯的所述聚合物层是面对所述重布线结构；以及
在所述重布线结构上形成多个外部连接件。
22.根据权利要求21所述的方法，其特征在于，所述第一虚设管芯的所述聚合物层与所述重布线结构物理上分离，并且所述模塑料在所述第一虚设管芯和所述重布线结构之间延伸。
23.根据权利要求21所述的方法，其特征在于，所述第一虚设管芯的所述聚合物层与所述重布线结构接触。
24.根据权利要求23所述的方法，其特征在于，多个第一连接件延伸穿过所述第一虚设管芯的所述聚合物层。
25.根据权利要求24所述的方法，其特征在于，所述多个第一连接件与所述多个导电线电隔离。
26.根据权利要求24所述的方法，其特征在于，所述多个第一连接件通过所述多个导电线电连接到接地节点。
27.根据权利要求21所述的方法，其特征在于，更包括：
将第二虚设管芯放置在所述第一衬底上；以及
在与所述第二虚设管芯相邻的所述第一衬底上形成多个穿孔。
28.一种形成半导体装置的方法，其特征在于，包括：
形成第一穿孔与第二穿孔；
在所述第一穿孔与所述第二穿孔之间设置主管芯和多个虚设管芯；
用模塑料包封所述主管芯和所述多个虚设管芯的侧壁和顶表面；
平坦化所述模塑料以暴露出所述主管芯；
在所述主管芯和所述多个虚设管芯上形成重布线结构，其中所述主管芯与所述重布线结构接触；以及
在所述重布线结构上形成多个连接件。
29.根据权利要求28所述的方法，其特征在于，所述主管芯和所述多个虚设管芯在平面图中的面积是第一面积，所述半导体装置在所述平面图中的面积为第二面积，且所述第二面积对所述第一面积的比率是2.5或小于2.5。
30.根据权利要求28所述的方法，其特征在于，所述主管芯的有效热膨胀系数相同于所述多个虚设管芯中的第一虚设管芯的有效热膨胀系数。
31.根据权利要求28所述的方法，其特征在于，所述多个虚设管芯中的第一虚设管芯的厚度小于所述主管芯的厚度。
32.根据权利要求28所述的方法，其特征在于，所述多个虚设管芯中的第一虚设管芯包括设置在衬底上方的聚合物层，所述聚合物层限定所述第一虚设管芯的表面，其中由所述聚合物层限定的所述第一虚设管芯的所述表面是面向所述重布线结构。
33.根据权利要求32所述的方法，其特征在于，多个金属柱设置在所述第一虚设管芯的所述聚合物层中，并且所述多个金属柱电连接到所述重布线结构。
34.根据权利要求32所述的方法，其特征在于，所述第一虚设管芯的所述聚合物层中不包括电连接件。
35.一种形成封装结构的方法，其特征在于，包括：
形成第一封装，形成所述第一封装包括：
对掩模进行图案化以形成多个开口；
在所述多个开口中镀敷导电材料以形成多个穿孔；
移除所述掩模；
在所述多个穿孔中的两个相邻的穿孔之间放置至少一个主管芯和至少一个虚设管芯；
用模塑料包封所述至少一个主管芯、所述至少一个虚设管芯和所述多个穿孔的侧壁；以及
在所述至少一个主管芯和所述至少一个虚设管芯上形成重布线结构，其中所述至少一个主管芯与所述重布线结构接触、且所述多个穿孔与所述重布线结构接触；以及
使用多个连接件将所述第一封装连接到第二封装，其中，所述多个穿孔中的第一穿孔与所述多个连接件中的第一连接件接触。
36.根据权利要求35所述的方法，其特征在于，所述至少一个主管芯和所述至少一个虚设管芯在平面图中的面积是第一面积，所述第一封装在所述平面图中的面积为第二面积，且所述第二面积对所述第一面积的比率是2.5或小于2.5。
37.根据权利要求35所述的方法，其特征在于，所述至少一个虚设管芯不含有任何功能性电路。
38.根据权利要求35所述的方法，其特征在于，所述至少一个虚设管芯包括第一衬底，所述至少一个主管芯包括第二衬底，其中所述第一衬底包括与所述第二衬底相同的材料。
39.根据权利要求35所述的方法，其特征在于，更包括：
平坦化所述模塑料以通过所述模塑料暴露出所述至少一个主管芯和所述至少一个虚设管芯。
40.根据权利要求35所述的方法，其特征在于，所述一个主管芯的有效热膨胀系数相同于所述一个虚设管芯的有效热膨胀系数。
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