TWI718314B - 具有虛設晶粒的封裝結構、半導體裝置及其形成方法 - Google Patents

具有虛設晶粒的封裝結構、半導體裝置及其形成方法 Download PDF

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TWI718314B
TWI718314B TW106120767A TW106120767A TWI718314B TW I718314 B TWI718314 B TW I718314B TW 106120767 A TW106120767 A TW 106120767A TW 106120767 A TW106120767 A TW 106120767A TW I718314 B TWI718314 B TW I718314B
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main
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TW106120767A
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TW201820571A (zh
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林彥甫
余振華
陳憲偉
李孟燦
吳偉誠
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台灣積體電路製造股份有限公司
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Abstract

本發明實施例提供一種形成封裝結構的方法及一種封裝 結構。所述方法包括將主晶粒與虛設晶粒並排地放置在承載基底上。所述方法還包括沿所述主晶粒的側壁及所述虛設晶粒的側壁形成模封材料。所述方法還包括在所述主晶粒及所述虛設晶粒之上形成包括多個通孔及多個導線的重佈線層，其中所述多個通孔及所述導線電性連接至所述主晶粒的連接件。所述方法還包括移除所述承載基底。

Description

具有虛設晶粒的封裝結構、半導體裝置及其形 成方法
本發明實施例是有關於一種結構，且特別是有關於一種具有虛設晶粒的扇出型封裝的結構及其形成方法。
隨著半導體技術的演變，半導體晶片/晶粒正變得越來越小。與此同時，需要將更多的功能集成至半導體晶粒中。因此，半導體晶粒需要將越來越大數目的輸入/輸出(I/O)銲墊充填至更小的面積中，且輸入/輸出銲墊的密度是隨著時間而迅速上升。因此，半導體晶粒的封裝將變得更為困難，此會不利地影響封裝的產率(yield)。
傳統的封裝技術可分為兩個類別。在第一類別中，晶片上的晶粒先被封裝、之後被鋸切。此種封裝技術具有某些有利特徵，例如生產量(throughput)更大及成本更低。此外，所需要使用的底部填充劑或模封化合物更少。然而，此種封裝技術也具有缺點。如上所述，晶粒的尺寸正變得越來越小，且相應封裝僅可 為扇入型封裝(fan-in type package)，其中每一晶粒的輸入/輸出銲墊被限於相應晶粒的表面正上方的區域。由於晶粒的面積有限，輸入/輸出銲墊的數目會因對應輸入/輸出銲墊的間距的限制而受限。假如銲墊的間距減小，則可能會出現焊料橋(solder bridge)。另外，在固定的球尺寸之要求下，焊料球必須具有某一尺寸，而此又會限制可被充填在晶粒的表面上的焊料球的數目。
在另一種封裝類別中，晶粒先被從晶片鋸切出、之後被封裝，且僅對“已知合格晶粒(known-good-die)”進行封裝。此種封裝技術的有利特徵是可形成扇出型封裝(fan-out type package)，這意味著，晶粒上的輸入/輸出銲墊可被重佈至比晶粒大的面積，且因此充填在晶粒的表面上的輸入/輸出銲墊的數目可增加。
本發明實施例提供一種結構，包括一個或多個主晶粒，一個或多個虛設晶粒、模封材料、多個重佈線層以及多個外部連接件。所述一個或多個虛設晶粒中的虛設晶粒被定位在所述一個或多個主晶粒中的主晶粒旁邊。所述模封材料沿所述一個或多個主晶粒的側壁及所述一個或多個虛設晶粒的側壁延伸。所述多個重佈線層包括多個通孔及多個導線，所述一個或多個主晶粒接觸所述多個重佈線層的第一表面。所述多個外部連接件設置在所述多個重佈線層的第二表面上，所述第一表面與所述第二表面是所 述多個重佈線層的相對表面。
20:承載基底
22:釋放層
24:緩衝層
26:導電晶種層
28:罩幕層
30:開口
32:金屬特徵
33:絕緣層穿孔
35:半導體基底
36:黏著層
38、50、52:介電層
40:金屬柱
42、312:模封材料
43:重佈線層
44:導線
48:通孔接點
68:連接件
70:凸塊下金屬化層
100:晶片
102:積體扇出型封裝
104:主晶粒
106:虛設晶粒
300:頂部封裝
302:基底
303、304:接合銲墊
306:穿孔
308A、308B:堆疊晶粒
310:打線
314:導電連接件
結合附圖閱讀以下詳細說明，會最佳地理解本發明實施例的各方面。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為使論述清晰起見，可任意增大或減小各種特徵的尺寸。
圖1是根據某些實施例的晶片的平面圖。
圖2A、圖2B及圖2C是根據某些實施例的裝置的剖視圖。
圖3是根據某些實施例的晶片的平面圖。
圖4至圖9是根據某些實施例在製造扇出型封裝時的中間階段的剖視圖。
圖10A、圖10B及圖10C是根據某些實施例在製造扇出型封裝時的中間階段的剖視圖。
圖11A、圖11B及圖11C是根據某些實施例在製造扇出型封裝時的中間階段的剖視圖。
圖12A、圖12B及圖12C是根據某些實施例在製造扇出型封裝時的中間階段的剖視圖。
圖13A、圖13B、圖13C及圖13D是根據某些實施例在製造扇出型封裝時的中間階段的剖視圖。
圖14A、圖14B、圖14C及圖14D是根據某些實施例在製造扇出型封裝時的中間階段的剖視圖。
圖15A、圖15B、圖15C及圖15D是根據某些實施例在製造 扇出型封裝時的中間階段的剖視圖。
圖16A、圖16B、圖16C及圖16D是根據某些實施例在製造扇出型封裝時的中間階段的剖視圖。
以下公開內容提供用於實作本發明實施例的不同特徵的許多不同的實施例或實例。下文闡述元件及構造的具體實例以簡化本發明實施例。當然，這些僅為實例而非用以限制。例如，以下說明中將第一特徵形成在第二特徵“之上”或第二特徵“上”可包括其中第一特徵與第二特徵被形成為直接接觸的實施例，且也可包括其中第一特徵與第二特徵之間可形成有額外特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本發明實施例可能在各種實例中重複使用參考編號及/或字母。這種重複使用是出於簡潔及清晰的目的，而不是自身表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如“在...下方(beneath)”、“在...下面(below)”、“下部的(lower)”、“上方(above)”、“上部的(upper)”等空間相對性用語來闡述圖中所說明的一個元件或特徵與另一(些)元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外還囊括裝置在使用或操作中的不同取向。設備可具有其他取向(旋轉90度或其他取向)，且本文中所用的空間相對性描述語可同樣相應地進行解 釋。
根據各種示例性實施例，提供一種包括一個或多個虛設晶粒的積體扇出型(Integrated Fan-Out，“InFO”)封裝及形成所述積體扇出型封裝的方法。所述積體扇出型封裝在平面圖中的面積對所述封裝被主晶粒及虛設晶粒覆蓋的面積的比率可小於約2.5。包含所述虛設晶粒及/或將所述比率降低至小於或等於約2.5可改進所述積體扇出型封裝的翹曲特性。在某些實施例中，當將一個或多個虛設晶粒包含在積體扇出型封裝中及/或所述比率是約2.5或小於2.5時，所述積體扇出型封裝可經歷更少的翹曲及/或更對稱的翹曲。以下將說明形成所述積體扇出型封裝的中間階段並論述實施例的變化形式。
參照圖1，其繪示晶片100的平面圖。晶片100在晶片100的表面上包括多個積體扇出型封裝102。在某些實施例中，積體扇出型封裝102可覆蓋晶片100的全部或實質上全部的表面。每一積體扇出型封裝102包括一個或多個主晶粒104。雖然在圖1所示每一積體扇出型封裝102中僅繪示了一個主晶粒104，然而，在某些實施例中，每一積體扇出型封裝102中可存在多於一個主晶粒104。積體扇出型封裝102可與相鄰積體扇出型封裝102具有相同數目的主晶粒104，或者積體扇出型封裝102可與相鄰積體扇出型封裝102具有不同數目的主晶粒104。在各相鄰積體扇出型封裝102中，主晶粒104可具有相同尺寸，或者在各相鄰積體扇出型封裝102中，主晶粒104可具有不同尺寸。主晶粒104可為包 括電路及/或主動元件或被動元件的功能性晶粒。可包括任何適合的主晶粒104。舉例來說，主晶粒104可包括靜態隨機存取記憶體(static random access memory，SRAM)晶片或動態隨機存取記憶體(dynamic random access memory，DRAM)晶片、處理器晶片、記憶體晶片、邏輯晶片、類比晶片、數位晶片、中央處理器(central processing unit，CPU)、圖形處理器(graphics processing unit，GPU)或其組合等。
積體扇出型封裝102在平面圖中的面積對積體扇出型封裝102在平面圖中被一個或多個主晶粒104覆蓋的面積的比率是可被判斷的。在圖1中，根據以下關係式來確定積體扇出型封裝102被主晶粒104覆蓋的面積：晶粒面積=B×D，其中B及D是矩形主晶粒104的側壁在平面圖中的長度。如果主晶粒104在平面圖中具有不同於矩形的形狀，則可使用任何適合的關係式來確定主晶粒104在積體扇出型封裝102的平面圖中的面積。根據關係式封裝面積=A×C來確定積體扇出型封裝102的面積，其中A及C是矩形積體扇出型封裝102的側壁在平面圖中的尺寸。如果積體扇出型封裝102在平面圖中具有不同於矩形的形狀，則可使用任何適合的關係式來確定積體扇出型封裝102在積體扇出型封裝102的平面圖中的面積。
在某些實施例中，當積體扇出型封裝102在平面圖中的面積對積體扇出型封裝102在平面圖中被一個或多個主晶粒104覆蓋的面積的比率大於約2.5時，則晶片100及/或相應積體扇出 型封裝102可經歷難以接受的翹曲。舉例來說，主晶粒104可因此類晶粒104中存在的半導體材料(例如，矽)而具有大約3.0的有效熱膨脹係數(effective CTE)。所述積體扇出型封裝可進一步包括可具有更高有效熱膨脹係數的各種其他材料(例如，模封材料42及/或絕緣層穿孔(TIV)33(參見圖12A至圖12C))。當所述比率是約2.5或大於2.5時，主晶粒104與積體扇出型封裝102的其他材料之間的熱膨脹係數失配可能會在晶片100及積體扇出型封裝102處於室溫(例如，大約25攝氏度)時以及在晶片100及積體扇出型封裝102被暴露至高溫(例如，大約260攝氏度或高於260攝氏度)時引起難以接受的翹曲。舉例來說，晶片100可具有大得難以接受的“哭泣狀”輪廓，如圖2A中所說明，其中晶片100的中間部分高於晶片100的邊緣部分。在某些實施例中，如圖2A中所說明，晶片100的中間部分與晶片100的邊緣部分之間的距離T1可為約100μm至約1300μm。晶片100也可具有大得難以接受的微笑狀輪廓，如圖2C中所說明。在某些實施例中，如圖2C中所說明，晶片100的中間部分與晶片100的邊緣部分之間的距離T2可為約100μm至約1300μm。晶片100所經歷的翹曲可為非對稱的。晶片100的難以接受的翹曲可降低晶片100的性能及可靠性。
晶片100的難以接受的翹曲可至少部分地歸因於晶片100的表面上的相應積體扇出型封裝102所發生的難以接受的翹曲。舉例來說，相應積體扇出型封裝102可具有大得難以接受的 “哭泣狀”輪廓，如圖2A中所說明，其中積體扇出型封裝102的中間部分高於積體扇出型封裝102的邊緣部分。在某些實施例中，如圖2A中所說明，積體扇出型封裝102的中間部分與積體扇出型封裝102的邊緣部分之間的距離T1可為約60μm至約120μm。積體扇出型封裝102也可具有大得難以接受的微笑狀輪廓，如圖2C中所說明。在某些實施例中，如圖2C中所說明，積體扇出型封裝102的中間部分與積體扇出型封裝102的邊緣部分之間的距離T2可為約60μm至約120μm。相應積體扇出型封裝102所經歷的翹曲可為非對稱的。相應積體扇出型封裝102的難以接受的翹曲可降低積體扇出型封裝102的性能及可靠性。
參照圖3，在某些實施例中，可在積體扇出型封裝102中插入一個或多個虛設晶粒(例如，虛設晶粒106)，以降低所得積體扇出型封裝102與晶片100的熱膨脹係數失配，並改進所得積體扇出型封裝102與晶片100的翹曲輪廓。虛設晶粒106的數目及虛設晶粒106的尺寸可被確定成使得每一積體扇出型封裝102在積體扇出型封裝102的平面圖中的面積對積體扇出型封裝102在積體扇出型封裝102的平面圖中被一個或多個主晶粒104及被虛設晶粒106覆蓋的面積的比率是約2.5或小於2.5。儘管主晶粒104可為含有裝置、電路等的功能性晶粒，然而，虛設晶粒106可為非功能性晶粒且在某些實施例中可能不含有任何裝置及/或功能性電路。
在某些實施例中，可根據關係式虛設面積=F×E來確定虛 設晶粒106中的一者的尺寸，其中F及E是矩形虛設晶粒106的側壁在積體扇出型封裝102的平面圖中的尺寸。當虛設晶粒106的形狀並非是矩形時，可使用任何適合的關係式來確定虛設晶粒在積體扇出型封裝102的平面圖中的面積。如果積體扇出型封裝102包括多於一個虛設晶粒106，則可確定積體扇出型封裝102中被每一虛設晶粒覆蓋的面積，且可通過將被每一虛設晶粒覆蓋的面積相加來確定積體扇出型封裝中被所有虛設晶粒覆蓋的總面積(總虛設面積)。
根據關係式晶粒面積=B×D來確定積體扇出型封裝被主晶粒104覆蓋的面積，其中B及D是矩形主晶粒104的側壁在平面圖中的長度。如果主晶粒104在平面圖中具有不同於矩形的形狀，則可使用任何適合的關係式來確定主晶粒104在積體扇出型封裝102的平面圖中的面積。如果積體扇出型封裝102包括多於一個主晶粒104，則可確定積體扇出型封裝102中被每一主晶粒104覆蓋的面積，且可通過將被每一主晶粒104覆蓋的面積相加來確定積體扇出型封裝102中被所有主晶粒104覆蓋的總面積(總晶粒面積)。
根據關係式封裝面積=A×C來確定積體扇出型封裝102的面積，其中A及C是矩形積體扇出型封裝102的側壁在平面圖中的尺寸。如果積體扇出型封裝102在平面圖中具有不同於矩形的形狀，則可使用任何適合的關係式來確定積體扇出型封裝102在積體扇出型封裝102的平面圖中的面積。
接著，可根據關係式比率=封裝面積/(總晶粒面積+總虛設面積)來確定積體扇出型封裝102在平面圖中的面積對積體扇出型封裝102在平面圖中被一個或多個主晶粒104及被虛設晶粒106覆蓋的面積的比率。當所述比率是約2.5或小於2.5時，相應積體扇出型封裝102及晶片100所經歷的翹曲可得以減弱及/或可更對稱。在某些實施例中，當晶片100包括比率為約2.5或小於2.5的積體扇出型封裝102時，晶片100可如圖2B所說明具有實質上平整的橫向表面。通過包含虛設晶粒106並將所述比率降低至2.5或小於2.5，具有哭泣狀輪廓的晶片100的最高點與最低點之差(圖2A中的尺寸T1)可得以減小。在某些實施例中，中間部分與邊緣部分之間的距離T1可為約50μm至約1100μm。通過包含虛設晶粒106並將所述比率降低至2.5或小於2.5，具有微笑狀輪廓的晶片100的最高點與最低點之差(圖2C中的尺寸T2)可得以減小。在某些實施例中，中間部分與邊緣部分之間的距離T2可為約50μm至約1100μm。
在某些實施例中，相應積體扇出型封裝102具有約2.5或小於2.5的比率也可使得積體扇出型封裝102如圖2B所說明具有實質上平整的橫向表面。通過包含虛設晶粒106並將所述比率降低至2.5或小於2.5，具有哭泣狀輪廓的相應積體扇出型封裝102的最高點與最低點之差(圖2A中的尺寸T1)可得以減小。在某些實施例中，中間部分與邊緣部分之間的距離T1可為約0μm至約55μm。通過包含虛設晶粒106並將所述比率降低至2.5或小於 2.5，具有微笑狀輪廓的相應積體扇出型封裝102的最高點與最低點之差(圖2C中的尺寸T2)可得以減小。在某些實施例中，中間部分與邊緣部分之間的距離T2可為約0μm至約55μm。
虛設晶粒106可包含任何適用於將積體扇出型封裝102的有效熱膨脹係數調整至所需水準的材料。虛設晶粒106可包含用於使積體扇出型封裝102的有效熱膨脹係數降低的材料，例如矽、玻璃、或陶瓷。在其他實施例中，虛設晶粒106可包含用於提高有效熱膨脹係數的材料，例如銅或聚合物。在某些實施例中，虛設晶粒106由主晶粒104中所包含的相同材料構成或包含主晶粒104中所包含的相同材料。舉例來說，在某些實施例中，虛設晶粒106可被選擇成使虛設晶粒106的有效熱膨脹係數相同於或相似於主晶粒104的有效熱膨脹係數。
圖4到圖16A至圖16D說明根據某些實施例在形成半導體封裝時的中間步驟的剖視圖。首先參照圖4，其示出上面形成有釋放層22的承載基底20。通常，承載基底20在後續處理步驟期間提供臨時機械與結構支撐。承載基底20可包含任何適合材料，例如矽系材料(例如矽晶片、玻璃、或氧化矽)、或其他材料(例如氧化鋁、陶瓷材料)、這些材料中任何者的組合等。在某些實施例中，承載基底20是平坦的，以適應其他處理。
釋放層22是在承載基底20之上形成的可選層，其可容許承載基底20被更容易地移除。如下文更詳細地解釋，將在承載基底20之上放置各種層及裝置，此後可移除承載基底20。可選的 釋放層22幫助將承載基底20移除，從而減少對在承載基底20之上形成的結構的損壞。釋放層22可由聚合物系材料形成。在某些實施例中，釋放層22是在受熱時會喪失其黏著性的環氧樹脂系熱釋放材料(epoxy-based thermal release material)，例如光/熱轉換(Light-to-Heat-Conversion，LTHC)釋放塗層。在其他實施例中，釋放層22可為紫外(ultra-violet，UV)膠，其在被暴露至紫外光時會喪失其黏著性。釋放層22可以液體形式施用配置並進行固化。在其他實施例中，釋放層22可為疊置於承載基底20上的疊層膜。也可利用其他釋放層。
參照圖4，在釋放層22之上形成緩衝層24。緩衝層24是介電層，其可為聚合物(例如聚苯並惡唑(polybenzoxazole，PBO)、聚醯亞胺、苯環丁烷(benzocyclobutene，BCB)等)、氮化物(例如氮化矽等)、氧化物(例如氧化矽、磷矽酸鹽玻璃(PhosphoSilicate Glass，PSG)、硼矽酸鹽玻璃(BoroSilicate Glass，BSG)、摻硼磷矽酸鹽玻璃(Boron-doped PhosphoSilicate Glass，BPSG)、或其組合等)等且可例如通過旋轉塗布(spin coating)、積層(lamination)、化學氣相沉積(Chemical Vapor Deposition，CVD)等來形成。在某些實施例中，緩衝層24是具有均勻厚度的平坦層，其中所述厚度可介於約2μm與約6μm之間。緩衝層24的頂表面及底表面也是平坦的。
現在參照圖5至圖9，其示出根據某些實施例視需要來形成穿孔(through vias，“TV”)33(參見圖9)。穿孔33提供從 積體扇出型封裝102的一側至積體扇出型封裝102的另一側的電性連接。舉例來說，如下文將更詳細地解釋，將向緩衝層24安裝主晶粒104及虛設晶粒106，且將圍繞穿孔及晶粒形成模封材料。隨後，可將另一裝置(例如另一晶粒、封裝、基底等)貼合至晶粒及模封材料。穿孔33提供所述另一裝置與所述封裝的背側之間的電性連接，而不必使電訊號穿過安裝至緩衝層24的主晶粒104。
穿孔33可例如通過如圖5中所示在緩衝層24之上形成導電晶種層26而形成。在某些實施例中，晶種層26是金屬層，其可為單一層或可為包括由不同材料形成的多個子層的複合層。晶種層26可由銅、鈦、鎳、金或其組合等製成。在某些實施例中，晶種層26包括鈦層及位於所述鈦層之上的銅層。可例如利用物理氣相沉積(physical vapor deposition，PVD)、化學氣相沉積、原子層沉積(atomic layer deposition，ALD)、其組合等來形成晶種層26。在某些實施例中，晶種層26包括鈦層及位於所述鈦層之上的銅層。在替代實施例中，晶種層26是銅層。
接著參照圖6，可沉積並圖案化罩幕層(例如經圖案化光阻層28)，其中所述罩幕層中的開口30暴露出晶種層26。參照圖7，可例如利用無電鍍敷步驟(electroless plating process)或電化學鍍敷步驟(electrochemical plating process)來用導電材料填充開口30，從而形成金屬特徵32。所述鍍敷步驟可單向地(例如，從晶種層26向上)填充經圖案化光阻層28中的開口。單向填充可容許對此類開口進行更均勻的填充。作為另一選擇，可在經圖 案化光阻層28中的開口30的側壁上形成另一晶種層，且可多向地填充此類開口。金屬特徵32可包含銅、鋁、鎢、鎳、焊料或其合金。金屬特徵32的俯視圖形狀可為矩形、正方形、圓形等。金屬特徵32的高度由隨後放置的主晶粒104及/或虛設晶粒106(圖10A至圖10C中所示)的厚度決定，其中在某些實施例中，金屬特徵32的高度大於主晶粒104及/或虛設晶粒106的厚度。
接下來，可例如以灰化(ashing)步驟及/或濕式剝除(wet strip)步驟來移除罩幕層，如圖8中所示。參照圖9，執行蝕刻步驟，以移除晶種層26的暴露出的部分，其中所述蝕刻可為非等向性蝕刻。另一方面，晶種層26的與金屬特徵32交疊的部分保持不被蝕刻。金屬特徵32與晶種層26的剩餘下伏部分形成穿孔33。雖然晶種層26被示出為與金屬特徵32分開的層，然而，當晶種層26是由與相應上覆金屬特徵32相似或相同的材料形成時，晶種層26可與金屬特徵32合並且其之間無可區分開的介面。在某些實施例中，晶種層26與上覆金屬特徵32之間存在可區分開的介面。也可用通過打線(wire bonding)步驟(例如銅打線步驟)放置的金屬線接線柱(metal wire stud)來實現穿孔33。使用打線步驟可消除對沉積晶種層26、沉積及圖案化罩幕層28、以及進行鍍敷以形成穿孔33的需要。
圖10A至圖10C說明根據某些實施例將主晶粒104及虛設晶粒106貼合至緩衝層24的背側。通過黏著層36(例如晶粒貼合膜(die-attach film，DAF))將主晶粒104及虛設晶粒106中的 每一者黏附至緩衝層24。黏著層36的厚度可處於從約5μm至約50μm的範圍中，例如約10μm。可如圖10A至圖10C中所說明使用一個主晶粒104及一個虛設晶粒106，或在某些實施例中，可使用多於一個主晶粒104及/或多於一個虛設晶粒106。對於圖10A至圖10C所示實施例中的每一者，積體扇出型封裝102在平面圖中的面積對積體扇出型封裝102被主晶粒104及虛設晶粒106覆蓋的面積的比率是約2.5或小於2.5。因此，圖10A至圖10C中的每一者所示的積體扇出型封裝102可經歷減弱的翹曲及/或更對稱的翹曲，此可提高積體扇出型封裝102的可靠性且提高積體扇出型封裝102的性能。
可針對特定設計或應用將主晶粒104及虛設晶粒106貼合至適合的位置。舉例來說，圖10A至圖10C說明其中主晶粒104及虛設晶粒106被安裝在中心區中的實施例，其中穿孔33是圍繞周邊而定位。在其他實施例中，主晶粒104及/或虛設晶粒106可相對於中心偏移。
在貼合至緩衝層24之前，可根據適用製造步驟來處理主晶粒104，以在主晶粒104中形成積體電路。主晶粒104可包括半導體基底35，其中所述半導體基底的背側貼合至黏著層36。在某些示例性實施例中，主晶粒104包括金屬柱40(例如銅支柱)，金屬柱40電耦合到主晶粒104中例如電晶體(圖中未示出)等的裝置。在某些實施例中，在主晶粒104的頂表面處形成有介電層38，其中金屬柱40的至少下部部分位於介電層38中。在某些實施例 中，金屬柱40的頂表面還可與介電層38的頂表面齊平。作為另一選擇，不形成介電層38，且金屬柱40突出至相應主晶粒104的頂部層上方。
圖10A至圖10C繪示可被包含在積體扇出型封裝102中的虛設晶粒106的各種實施例。在圖10A至圖10C到圖15A至圖15D中，以“A”結尾的圖繪示第一實施例，以“B”結尾的圖繪示第二實施例，以“C”結尾的圖繪示第三實施例，且以“D”結尾的圖繪示第四實施例。
參照圖10A，虛設晶粒106可包括半導體基底35，其中半導體基底35的背側貼合至黏著層36。在某些實施例中，半導體基底35可包含與主晶粒104的半導體基底35相同的材料。視需要，在虛設晶粒106的半導體基底35的與接觸所述黏著層的表面相對的表面上包含介電層38。虛設晶粒106的介電層38可包含與主晶粒104的介電層38相同的材料。在圖10A所示實施例中，在虛設晶粒106中未包含電觸點(例如金屬柱40)。作為另一選擇，在虛設晶粒106的介電層38中包含金屬柱40，如圖10B中所示。在某些實施例中，金屬柱40包含銅等。
在圖10A及圖10B所示實施例中，虛設晶粒106具有與主晶粒104相同的厚度，其中所述厚度是在與穿孔33平行的方向上測量。作為另一選擇，如圖10C中所示，虛設晶粒106可具有比主晶粒104的厚度小的厚度。在某些實施例中，主晶粒104可具有40μm至300μm的厚度T3，而虛設晶粒106可具有40μm 至300μm的厚度T4。在某些實施例中，虛設晶粒106的厚度T4對主晶粒104的厚度T3的比率可為約40%至約100%。
參照圖11A至圖11C，在主晶粒104、虛設晶粒106、及穿孔33上模制出模封材料42。模封材料42填充主晶粒104與虛設晶粒106之間、主晶粒104與穿孔33之間、以及虛設晶粒106與穿孔33之間的間隙，且可接觸緩衝層24。此外，當金屬柱40是突出的金屬柱時，模封材料42被填充至金屬柱40中。可例如利用壓縮模制(compression molding)在主晶粒104、虛設晶粒106、及穿孔33上模制出模封材料42。在某些實施例中，模封材料42是封裝膠體、聚合物、環氧樹脂、氧化矽填充材料等、或其組合。可執行固化步驟，以使模封材料42固化，其中所述固化可為熱固化(thermal curing)、紫外固化等、或其組合。模封材料42的頂表面高於主晶粒104上的金屬柱40的頂端及穿孔33的頂端。
接下來，執行研磨步驟以將模封材料42薄化，直至主晶粒104上的金屬柱40、及穿孔33被暴露出為止。圖12A至圖12C中示出所得結構。由於所述研磨，金屬特徵32的頂端與主晶粒104上的金屬柱40的頂端實質上齊平(共面)，且與模封材料42的頂表面實質上齊平(共面)。在其中虛設晶粒106具有與主晶粒104相同的厚度的實施例中，所述研磨步驟會暴露出虛設晶粒106的頂表面。舉例來說，研磨步驟可暴露出虛設晶粒106的介電層38及/或虛設晶粒106的金屬柱40。
在其中虛設晶粒106具有比主晶粒104的厚度小的厚度 的實施例中，所述研磨步驟不會暴露出虛設晶粒106，如圖12C中所示。在研磨步驟之後，模封材料覆蓋虛設晶粒106的距承載基底20最遠的表面。
作為所述研磨的結果，可能會產生金屬殘渣(例如金屬顆粒)，且其留在模封材料42的頂表面及主晶粒104的頂表面上。因此，在研磨之後，可例如通過濕式蝕刻來執行清潔，以使金屬殘渣被移除。
接下來，參照圖13A至圖13C，形成一個或多個重佈線層(redistribution layer，RDL)43。通常，重佈線層會提供導電圖案，以容許成品封裝的引腳輸出接觸圖案(pin-out contact pattern)不同於穿孔33及/或金屬柱40的圖案，從而容許對穿孔33及主晶粒104的放置具有更大靈活性。重佈線層可用於提供與主晶粒104及/或穿孔33的外部電性連接。重佈線層可進一步用於將主晶粒104電耦合到穿孔33，穿孔33可電耦合到一個或多個其他封裝、封裝基底、元件等、或其組合。重佈線層包括導線44及通孔接點48，其中通孔接點48將上覆線(例如，上覆導線44)連接到下伏導電特徵(例如，穿孔33、金屬柱40及/或導線44)。導線44可沿任一方向延伸。圖13A至圖13C說明三層重佈線層，但可存在一層、兩層、或多於三層的重佈線層43，這視相應積體扇出型封裝102的佈線要求而定。
可利用任何適合的步驟來形成重佈線層43。舉例來說，在某些實施例中，在模封材料42上以及在主晶粒104及虛設晶粒 106之上形成介電層50。在某些實施例中，介電層50是由聚合物形成，所述聚合物可為可利用微影進行圖案化的感光性材料，例如聚苯並惡唑(PBO)、聚醯亞胺、苯環丁烷(BCB)等。在其他實施例中，介電層50是由氮化物(例如氮化矽)、氧化物(例如氧化矽、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、摻硼磷矽酸鹽玻璃(BPSG))等形成。可通過旋轉塗布、積層、化學氣相沉積等、或其組合來形成介電層50。接著，將介電層50圖案化以形成開口，從而暴露出主晶粒104的金屬柱40並暴露出穿孔33。在其中導線44電性連接到虛設晶粒106(參見圖13D)的實施例中，虛設晶粒106上的電連接件也會被暴露出。在其仲介電層50是由感光性材料形成的實施例中，可通過根據所需圖案將介電層50曝光並顯影以移除不需要的材料來執行所述圖案化。也可使用其他方法(例如使用經圖案化罩幕並進行蝕刻)來將介電層50圖案化。
在介電層50之上以及在形成於介電層50中的開口中形成晶種層(圖中未示出)。在某些實施例中，所述晶種層是金屬層，其可為單個層或為包括由不同材料形成的多個子層的複合層。在某些實施例中，所述晶種層包括鈦層及位於所述鈦層之上的銅層。可例如利用物理氣相沉積等來形成所述晶種層。接著，在所述晶種層上形成罩幕，並根據所需重佈線圖案(例如，圖13A至圖13D中所說明的圖案)將所述罩幕圖案化。在某些實施例中，所述罩幕是通過旋轉塗布等形成並被暴露至光以進行圖案化的光 阻。所述圖案化會穿過罩幕而形成開口，以暴露出晶種層。在罩幕的開口中以及在晶種層的暴露出的部分上形成導電材料。可通過鍍敷(例如電鍍或無電鍍敷)等來形成所述導電材料。所述導電材料可包括金屬，如銅、鈦、鎢、鋁等。接著，移除光阻以及移除晶種層的上面未形成導電材料的部分。可例如利用氧等離子等通過可接受的灰化步驟或剝除步驟來移除光阻。一旦光阻被移除，便例如利用可接受的蝕刻步驟(例如通過濕式蝕刻或乾式蝕刻)來移除晶種層的暴露出的部分。所述晶種層的剩餘部分與所述導電材料形成導線44及通孔接點48。在介電層50之上形成介電層52，以為後續各層提供更平坦的表面，且可利用與用於形成介電層50的材料及步驟相似的材料及步驟來形成介電層52。在某些實施例中，介電層52是由聚合物、氮化物、氧化物等形成。在某些實施例中，介電層52是聚苯並惡唑並通過旋轉塗布步驟而形成。
以上過程闡述了對一層重佈線層43的形成。可視需要重複以上過程，以在需要時形成額外的重佈線層43。
如上所述，在某些實施例中，虛設晶粒106不形成有任何用於將虛設晶粒106電性連接到外部元件的電連接件。因此，不需要將重佈線層43的任何通孔連接件48或導線44連接到虛設晶粒106。圖13A及圖13C中示出其中虛設晶粒106不具有金屬柱40的實施例的實例。在其他實施例中，虛設晶粒106可在虛設晶粒106的距承載基底20最遠的表面上形成有金屬柱40。圖13B 及圖13D中示出其中虛設晶粒106包括金屬柱40的實施例的實例。如圖13B中所示，在某些實施例中，重佈線層43的導通孔48或導線44均不被形成為連接到虛設晶粒106中的金屬柱40。因此，金屬柱40可接觸重佈線層43的介電層且與重佈線層43的任何導通孔48或導線44電隔離。參照圖13D，在某些實施例中，可在重佈線層43中形成與虛設晶粒106中的金屬柱40電性連接的導通孔48及導線。在某些實施例中，可將虛設晶粒106的金屬柱40電性連接到積體扇出型封裝102的接地節點。
圖14A至圖14D說明根據某些實施例在圖13A至圖13D所示結構的最上部金屬化圖案之上形成並圖案化從而與最上部金屬化層形成電性連接的凸塊下金屬化層(under bump metallization，UBM)70。凸塊下金屬化層70提供上面可放置電連接件(例如，焊料球/凸塊、導電柱等)的電接點。在實施例中，凸塊下金屬化層70包括擴散障壁層、晶種層、或其組合。所述擴散障壁層可包含Ti、TiN、Ta、TaN、或其組合。所述晶種層可包含銅或銅合金。然而，也可包含其他金屬，例如鎳、鈀、銀、金、鋁、其組合、及其多層。在實施例中，利用濺鍍來形成凸塊下金屬化層70。在其他實施例中，可使用電鍍。
根據某些實施例，在凸塊下金屬化層70之上形成連接件68。連接件68可為焊料球、金屬柱、受控塌陷晶片連接(controlled collapse chip connection，C4)凸塊、微凸塊、由無電鍍鎳鈀浸金技術(electroless nickel-electroless palladium-immersion gold technique，ENEPIG)形成的凸塊、其組合(例如，貼合有焊料球的金屬柱)等。連接件68可包含導電材料，例如焊料、銅、鋁、金、鎳、銀、鈀、錫等、或其組合。在某些實施例中，連接件68包含共熔材料(eutectic material)，且作為實例可包括焊料凸塊或焊料球。焊料材料可例如是鉛系焊料及無鉛焊料，例如，用於鉛系焊料的Pb-Sn組合物；無鉛焊料包含：InSb；錫、銀及銅(tin,silver,and copper，SAC)組合物；以及電應用中具有共同熔點且形成導電焊料接點的其他共熔材料。對於無鉛焊料，可使用組成各異的SAC焊料，例如，作為實例：SAC 105(Sn 98.5%、Ag 1.0%、Cu 0.5%)、SAC 305、及SAC 405。例如焊料球等的無鉛連接件也可由SnCu化合物形成，而不使用銀(Ag)。作為另一選擇，無鉛焊料連接件可包含錫及銀(Sn-Ag)，而不使用銅。連接件68可形成柵格，例如球柵陣列封裝(ball grid array，BGA)。在某些實施例中，可執行回焊步驟(reflow process)，從而在某些實施例中對連接件68賦予局部球體的形狀。作為另一選擇，連接件68可包括其他形狀。例如，連接件68也可包括非球形導電連接件。
在某些實施例中，連接件68包括通過濺鍍、印刷、電鍍、無電鍍敷、化學氣相沉積等形成的上面具有或不具有焊料材料的金屬柱(例如銅柱)。所述金屬柱可為無焊料的且具有實質上垂直側壁或錐形側壁。
接下來，從封裝剝離承載基底20。也從封裝清除釋放層22。圖15A至圖15D中示出所得結構。作為移除釋放層22的結 果，緩衝層24被暴露出。
在後續處理(圖中未示出)中，如果同時形成多個積體扇出型封裝，則可將所述積體扇出型封裝單體化(singulate)成多個積體扇出型封裝102。
參照圖16A至圖16C，可將頂部封裝300接合至積體扇出型封裝102。頂部封裝300包括基底302及耦合到基底302的一個或多個堆疊晶粒308(308A及308B)。基底302可由例如矽、鍺、金剛石等的半導體材料製成。在某些實施例中，也可使用化合物材料，例如矽鍺、碳化矽、鎵砷、砷化銦、磷化銦、碳化矽鍺、磷化鎵砷、磷化鎵銦、這些的組合等。另外，基底302可為絕緣體上半導體(semiconductor on insulator，SOI)基底。通常，絕緣體上半導體基底包括一層半導體材料，例如磊晶矽、鍺、矽鍺、絕緣體上矽(silicon on insulator，SOI)、絕緣體上矽鍺(silicon germanium on insulator，SGOI)、或其組合。在一個替代實施例中，基底302是基於絕緣芯，例如玻璃纖維強化樹脂芯(fiberglass reinforced resin core)。一種示例性芯材料是玻璃纖維樹脂，例如FR4。所述芯材料的替代方案包括雙馬來醯亞胺-三嗪(bismaleimide-triazine，BT)樹脂，或作為另一選擇，包括其他印刷電路板(printed circuit board，PCB)材料或膜。可將例如味之素增層膜(Ajinomoto build-up film，ABF)等的增層膜或其他積層體用於基底302。
基底302可包括主動元件及被動元件(圖中未示出)。所 屬領域中的一般技術人員應認識到，可使用各種各樣的裝置(例如電晶體、電容器、電阻器、這些的組合等)來滿足用於半導體封裝300的設計的結構性及功能性要求。可利用任何適合的方法來形成所述裝置。
基底302還可包括金屬化層(圖中未示出)及穿孔306。所述金屬化層可形成在主動元件及被動元件之上且被設計成連接各種裝置以形成功能性電路。所述金屬化層可由介電材料(例如，低介電常數介電材料)與導電材料(例如，銅)的交替層形成(其中通孔對各層導電材料進行內連)且可通過任何適合的步驟(例如沉積、鑲嵌(damascene)、雙重鑲嵌(dual damascene)等)來形成。在某些實施例中，基底302實質上不具有主動元件及被動元件。
基底302可具有位於基底302的第一側上以耦合到堆疊晶粒308的接合銲墊303以及位於基底302的第二側上以耦合到導電連接件314的接合銲墊304，所述第二側與基底302的第一側相對。在某些實施例中，接合銲墊303及304是通過向基底302的第一側及第二側上的介電層(圖中未示出)中形成凹槽(圖中未示出)而形成。所述凹槽可被形成為容許接合銲墊303及304被嵌入至所述介電層中。在其他實施例中，由於接合銲墊303及304可形成在所述介電層上，因而所述凹槽被省卻。在某些實施例中，接合銲墊303及304包括由銅、鈦、鎳、金、鈀等、或其組合製成的薄晶種層(圖中未示出)。可在所述薄晶種層之上沉積接 合銲墊303及304的導電材料。可通過電化學鍍敷步驟、無電鍍敷步驟、化學氣相沉積、原子層沉積、物理氣相沉積等或其組合來形成導電材料。在實施例中，接合銲墊303及304的導電材料是銅、鎢、鋁、銀、金等或其組合。在實施例中，接合銲墊303及304是利用與前面結合凸塊下金屬化層70所述步驟相同或相似的步驟而形成的凸塊下金屬化層。
在所說明實施例中，堆疊晶粒308是通過打線310耦合到基底302，然而，可使用其他接點，例如導電凸塊。在實施例中，堆疊晶粒308是堆疊記憶體晶粒。舉例來說，堆疊記憶體晶粒308可包括低功率(low-power，LP)雙倍數據速率(double data rate，DDR)記憶體模組，例如低功率雙倍數據速率1記憶體模組、低功率雙倍數據速率2記憶體模組、低功率雙倍數據速率3記憶體模組、低功率雙倍數據速率4記憶體模組等。
在某些實施例中，可通過模封材料312來包封堆疊晶粒308及打線310。可例如利用壓縮模制在堆疊晶粒308及打線310上模制出模封材料312。在某些實施例中，模封材料312是模封材料、聚合物、環氧樹脂、氧化矽填充材料等或其組合。可執行固化步驟，以使模封材料312固化，其中所述固化可為熱固化、紫外固化等或其組合。
在某些實施例中，堆疊晶粒308及打線310被埋入模封材料312中，且在使模封材料312固化之後，執行平坦化步驟(例如研磨)，以移除模封材料312的多餘部分並為第二封裝300提供 實質上平坦的表面。
在形成頂部封裝300之後，頂部封裝300通過導電連接件314及接合銲墊304而接合至積體扇出型封裝102。在某些實施例中，堆疊記憶體晶粒308可經由打線310、接合銲墊303及304、穿孔306、導電連接件314及穿孔33而耦合到主晶粒104。
導電連接件314可與上文所述連接件68相似，且本文中不再對其予以贅述，然而，導電連接件314與68不必是相同的。在某些實施例中，在對導電連接件314進行接合之前，用免清洗助焊劑(no-clean flux)等的助焊劑(圖中未示出)來塗布導電連接件314。可將導電連接件314浸入助焊劑中，或可將助焊劑噴射至導電連接件314上。
在某些實施例中，導電連接件314上可在其被回焊之前先形成有環氧樹脂助焊劑(圖中未示出)，其中所述環氧樹脂助焊劑的環氧樹脂部分中的至少某些在頂部封裝300貼合至積體扇出型封裝102之後被保留。此所保留的環氧樹脂部分可充當底部填充劑，以減小因對導電連接件314進行回焊而產生的應力並保護因對導電連接件314進行回焊而產生的接縫。在某些實施例中，可在頂部封裝300與積體扇出型封裝102之間以及在導電連接件314周圍形成底部填充劑(圖中未示出)。所述底部填充劑可在頂部封裝300被貼合之後通過毛細管流動步驟(capillary flow process)而形成，或可在頂部封裝300被貼合之前通過適合的沉積方法而形成。
頂部封裝300與積體扇出型封裝102之間的接合可為焊料接合或直接金屬間接合(例如銅-銅間或錫-錫間接合)。在實施例中，通過回焊步驟將頂部封裝300接合至積體扇出型封裝102。在此回焊步驟期間，導電連接件314接觸接合銲墊304及穿孔33，以將頂部封裝300物理耦合及電耦合到積體扇出型封裝102。
根據某些實施例，一種積體扇出型封裝包括一個或多個主晶粒及一個或多個虛設晶粒。所述積體扇出型封裝在平面圖中的面積對所述封裝被主晶粒及虛設晶粒覆蓋的面積的比率小於約2.5。包含所述虛設晶粒及/或將所述比率降低至小於或等於約2.5可改進所述積體扇出型封裝的翹曲特性。在某些實施例中，當所述比率是約2.5或小於2.5時，所述積體扇出型封裝可經歷更少的翹曲及/或更對稱的翹曲。
根據某些實施例，提供一種結構。所述結構包括一個或多個主晶粒及一個或多個虛設晶粒，所述一個或多個虛設晶粒中的虛設晶粒被定位在所述一個或多個主晶粒中的主晶粒旁邊。所述結構還包括模封材料，所述模封材料沿所述一個或多個主晶粒的側壁及所述一個或多個虛設晶粒的側壁延伸。所述結構還包括多個重佈線層，所述多個重佈線層包括多個通孔及多個導線，所述一個或多個主晶粒沿所述多個重佈線層的第一表面延伸。所述結構還包括多個外部連接件，所述多個外部連接件沿所述多個重佈線層的第二表面延伸，所述第一表面與所述第二表面是所述多個重佈線層的相對表面。
在某些實施例中，所述結構在所述結構的平面圖中的面積是第一面積，所述結構在所述結構的所述平面圖中被所述一個或多個主晶粒及所述一個或多個虛設晶粒覆蓋的面積是第二面積，且所述第一面積對所述第二面積的比率是2.5或小於2.5。在某些實施例中，所述一個或多個虛設晶粒在所述相應虛設晶粒的最靠近所述多個重佈線層的表面處包括聚合物層。在某些實施例中，所述一個或多個虛設晶粒包括設置在所述一個或多個虛設晶粒的所述聚合物層中的多個金屬柱。在某些實施例中，所述一個或多個虛設晶粒在所述一個或多個虛設晶粒的所述聚合物層中不包括電連接件。在某些實施例中，所述一個或多個主晶粒的基底包含與所述一個或多個虛設晶粒的基底相同的材料。在某些實施例中，所述一個或多個主晶粒的有效熱膨脹係數實質上相同於所述一個或多個虛設晶粒的有效熱膨脹係數。在某些實施例中，所述一個或多個虛設晶粒中的虛設晶粒的厚度小於所述一個或多個主晶粒中的主晶粒的厚度，其中所述一個或多個主晶粒中的所述主晶粒的所述厚度與所述一個或多個虛設晶粒中的所述虛設晶粒的所述厚度是在與所述一個或多個主晶粒中的所述主晶粒的主表面垂直的方向上測量。在某些實施例中，所述一個或多個虛設晶粒中的虛設晶粒包括沿所述虛設晶粒的與所述多個重佈線層最靠近的表面暴露出的多個電連接件。在某些實施例中，所述多個通孔中的通孔電性連接到所述一個或多個虛設晶粒中的所述虛設晶粒的所述多個電連接件中的一個電連接件。在某些實施例中，所 述多個通孔中的所述通孔將所述一個或多個虛設晶粒中的所述虛設晶粒的所述多個電連接件中的所述一個電連接件電性連接到接地節點。在某些實施例中，所述一個或多個虛設晶粒中的所述多個電連接件與所述多個重佈線層的所述多個通孔及所述多個導線電隔離。在某些實施例中，所述模封材料覆蓋所述一個或多個虛設晶粒的最靠近所述多個重佈線層的表面。
根據某些實施例，提供一種結構。所述結構包括一個或多個主晶粒。所述結構還包括一個或多個虛設晶粒，所述一個或多個虛設晶粒中的第一虛設晶粒被定位在所述一個或多個主晶粒中的主晶粒旁邊。所述結構還包括多個穿孔，其中所述多個穿孔中的穿孔被定位在所述一個或多個虛設晶粒中的第二虛設晶粒旁邊。所述結構還包括模封材料，所述模封材料沿所述一個或多個主晶粒的側壁、所述一個或多個虛設晶粒的側壁、及所述多個穿孔的側壁延伸。所述結構還包括重佈線層，所述重佈線層位於所述一個或多個主晶粒及所述一個或多個虛設晶粒之上，其中所述重佈線層包括多個導線及多個通孔，且其中所述多個導線電性連接到所述一個或多個主晶粒。
在某些實施例中，所述結構在所述結構的平面圖中的面積是第一面積，所述結構在所述結構的所述平面圖中被所述一個或多個主晶粒及所述一個或多個虛設晶粒覆蓋的面積是第二面積，且所述第一面積對所述第二面積的比率是2.5或小於2.5。在某些實施例中，所述一個或多個虛設晶粒的厚度小於所述一個或 多個主晶粒的厚度，所述一個或多個虛設晶粒的所述厚度與所述一個或多個主晶粒的所述厚度是在與所述一個或多個虛設晶粒的主表面垂直的方向上測量。在某些實施例中，所述多個導線中的導線將所述一個或多個虛設晶粒中的虛設晶粒電性連接到接地節點。
根據某些實施例，提供另一種結構。所述結構包括一個或多個主晶粒及一個或多個虛設晶粒。所述結構還包括模封材料，所述模封材料沿所述一個或多個主晶粒的側壁、所述一個或多個虛設晶粒的側壁、及多個穿孔的側壁延伸。所述結構還包括重佈線層，所述重佈線層位於所述一個或多個主晶粒及所述一個或多個虛設晶粒之上，其中所述重佈線層包括多個導線及多個通孔。所述結構在所述結構的平面圖中的面積是第一面積，所述結構在所述結構的所述平面圖中被所述一個或多個主晶粒及所述一個或多個虛設晶粒覆蓋的面積是第二面積，且所述第一面積對所述第二面積的比率是2.5或小於2.5。
在某些實施例中，所述一個或多個虛設晶粒中的虛設晶粒在所述虛設晶粒的最靠近所述重佈線層的表面處包括聚合物層，其中電連接件不延伸穿過所述聚合物層。在某些實施例中，所述聚合物層接觸介電層，所述重佈線層設置在所述介電層中。以上內容概述了若干實施例的特徵以使所屬領域中的技術人員可更好地理解本發明實施例的各方面。所屬領域中的技術人員應瞭解，他們可易於使用本發明實施例作為基礎來設計或修改其他步 驟及結構以施行本文所介紹實施例的相同目的及/或實現本文所介紹實施例的相同優點。所屬領域中的技術人員還應認識到，此種等效構造並不背離本發明實施例的精神及範圍，且在不背離本發明實施例的精神及範圍的條件下，他們可對本文做出各種改變、替代、及變更。
24:緩衝層
33:穿孔/絕緣層穿孔
35:半導體基底
42、312:模封材料
43:重佈線層
44:導線
48:通孔接點
50、52:介電層
68:連接件
70:凸塊下金屬化層
102:積體扇出型封裝
104:主晶粒/晶粒
106:虛設晶粒
300:頂部封裝
302:基底
303、304:接合銲墊
306:穿孔
308A、308B:堆疊晶粒
310:打線
314:導電連接件

Claims (10)

  1. 一種封裝結構，包括：一或多個主晶粒；一或多個虛設晶粒，所述一或多個虛設晶粒中的虛設晶粒被定位在所述一或多個主晶粒中的主晶粒旁邊，且所述一或多個虛設晶粒中的所述虛設晶粒包括設置在基底上方的介電層，所述介電層限定所述一或多個虛設晶粒中的所述虛設晶粒的表面；模封材料，沿所述一或多個主晶粒的側壁及所述一或多個虛設晶粒的側壁延伸；以及多個重佈線層，包括多個通孔及多個導線，其中每一個所述多個重佈線層都設置在所述封裝結構的相同水平處，所述一個或多個主晶粒接觸所述多個重佈線層的第一表面，且所述一或多個虛設晶粒中的所述虛設晶粒的設置方式是使由所述介電層限定的所述虛設晶粒的所述表面最靠近所述多個重佈線層的第一表面，且所述介電層在所述基底與所述多個重佈線層的所述第一表面之間延伸；以及多個外部連接件，設置在所述多個重佈線層的第二表面上，所述第一表面與所述第二表面是所述多個重佈線層的相對表面。
  2. 如申請專利範圍第1項所述的封裝結構，其中，所述封裝結構在所述封裝結構的平面圖中的面積是第一面積，所述封裝結構在所述封裝結構的所述平面圖中被所述一個或多個主晶粒及 所述一個或多個虛設晶粒覆蓋的面積是第二面積，且所述第一面積對所述第二面積的比率是2.5或小於2.5。
  3. 如申請專利範圍第1項所述的封裝結構，其中，所述一個或多個虛設晶粒包括設置在所述一個或多個虛設晶粒的所述介電層中的多個金屬柱。
  4. 一種封裝結構，包括：一個或多個主晶粒；一個或多個虛設晶粒，所述一個或多個虛設晶粒中的第一虛設晶粒被定位在所述一個或多個主晶粒中的主晶粒旁邊；多個穿孔，其中所述多個穿孔中的穿孔被定位在所述一個或多個虛設晶粒中的第二虛設晶粒旁邊；模封材料，所述模封材料沿所述一個或多個主晶粒的側壁、所述一個或多個虛設晶粒的側壁、及所述多個穿孔的側壁延伸；以及重佈線層，所述重佈線層位於所述一個或多個主晶粒及所述一個或多個虛設晶粒之上，其中所述重佈線層包括多個導線及多個通孔，且其中所述多個導線電性連接到所述一個或多個主晶粒。
  5. 如申請專利範圍第4項所述的封裝結構，所述一個或多個虛設晶粒的厚度小於所述一個或多個主晶粒的厚度，所述一個或多個虛設晶粒的所述厚度與所述一個或多個主晶粒的所述厚度是在與所述一個或多個虛設晶粒的主表面垂直的方向上測量。
  6. 一種封裝結構，包括： 一個或多個主晶粒及一個或多個虛設晶粒；模封材料，所述模封材料沿所述一個或多個主晶粒的側壁、所述一個或多個虛設晶粒的側壁、及多個穿孔的側壁延伸；以及重佈線層，所述重佈線層位於所述一個或多個主晶粒及所述一個或多個虛設晶粒之上，其中所述重佈線層包括多個導線及多個通孔，其中所述封裝結構在所述封裝結構的平面圖中的面積是第一面積，所述封裝結構在所述封裝結構的所述平面圖中被所述一個或多個主晶粒及所述一個或多個虛設晶粒覆蓋的面積是第二面積，且所述第一面積對所述第二面積的比率是2.5或小於2.5。
  7. 一種形成封裝結構的方法，包括：將功能性晶粒及第一虛設晶粒放置在第一基底上，其中所述第一虛設晶粒包括設置在第二基底上的介電層；用模封材料包封所述功能性晶粒及所述第一虛設晶粒的側壁；在所述功能性晶粒及所述第一虛設晶粒上方形成重佈線結構，所述重佈線結構包括多個導線及多個介電層，其中所述功能性晶粒是電性連接到所述多個導線中的第一導線，且所述第一虛設晶粒的所述介電層是面對所述重佈線結構；以及在所述重佈線結構上形成多個外部連接件。
  8. 如申請專利範圍第7項所述的方法，更包括：將第二虛設晶粒放置在所述第一基底上；以及在與所述第二虛設晶粒相鄰的第一基底上形成多個穿孔。
  9. 一種形成半導體裝置的方法，包括：形成第一穿孔與第二穿孔；在所述第一穿孔與所述第二穿孔之間設置主晶粒及多個虛設晶粒；用模封材料包封所述主晶粒及所述多個虛設晶粒的側壁及頂表面；平坦化所述模封材料以暴露出所述主晶粒；在所述主晶粒及所述多個虛設晶粒上方形成重佈線結構，其中所述主晶粒與所述重佈線結構接觸；以及在所述重佈線結構上形成多個連接件。
  10. 一種形成封裝結構的方法，包括：形成第一封裝，形成所述第一封裝包括：對罩幕進行圖案化以形成多個開口；在所述多個開口中鍍敷導電材料以形成多個穿孔；移除所述罩幕；在所述多個穿孔中的兩個相鄰的穿孔之間放置至少一個主晶粒及至少一個虛設晶粒；用模封材料包封所述至少一個主晶粒及所述至少一個虛設晶粒的側壁；以及在所述至少一個主晶粒及所述至少一個虛設晶粒上方形成重佈線結構，其中所述至少一個主晶粒與所述重佈線結構接觸，且所述多個穿孔與所述重佈線結構接觸；以及 使用多個連接件將所述第一封裝連接到第二封裝，其中，所述多個穿孔中的第一穿孔與所述多個連接件中的第一連接件接觸。
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