TW201608651A - 半導體封裝及其形成方法 - Google Patents

半導體封裝及其形成方法 Download PDF

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TW201608651A
TW201608651A TW103142547A TW103142547A TW201608651A TW 201608651 A TW201608651 A TW 201608651A TW 103142547 A TW103142547 A TW 103142547A TW 103142547 A TW103142547 A TW 103142547A TW 201608651 A TW201608651 A TW 201608651A
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Taiwan
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package
die
electrical connector
forming
layer
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TW103142547A
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TWI620254B (zh
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余振華
林俊成
蔡柏豪
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台灣積體電路製造股份有限公司
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Abstract

本申請案揭示內容之實施例係包含半導體封裝及其形成方法。該方法係包含形成第一晶粒封裝，該第一晶粒封裝包含第一晶粒、第一電連接體以及第一重佈層，該第一重佈層係耦合至該第一晶粒與該第一電連接體，於該第一晶粒封裝上方形成底膠填充，圖案化該底膠填充而具有開口以暴露部分的該第一電連接體，以及用接合結構將第二晶粒封裝接合至該第一晶粒封裝，該接合結構係耦合至該底膠填充的該開口中的該第一電連接體。

Description

半導體封裝及其形成方法
本發明係關於半導體封裝及其形成方法。
半導體裝置用於許多電子應用中，例如個人電腦、手機、數位相機以及其他電子設備。半導體裝置的典型製造方式係在半導體基板上連續沉積絕緣或介電層、傳導層以及半導體層，並且使用微影製程將不同的材料層圖案化以於其上形成電路組件與元件。
由於各種電子元件(例如，電晶體、二極體、電阻器、電容器等)之整合密度持續改良，半導體產業已經快速成長。整體而言，此整合密度改良係來自於縮小半導體製程節點(例如，將半導體製程節點縮小至次20奈米節點)。為因應最近微小化、更高速度、更大頻寬、以及較低功率消耗與遲延的需求增加，因此需要用於半導體晶粒之較小且更具創造力的封裝技術。
本申請案揭示內容的一些實施例係提供一種方法，其包括：形成第一封裝，其包括：在載體基板上方，形成第一介電層；在該第一 介電層上方，形成第一電連接體；將第一晶粒附接相鄰該第一電連接體且於該第一介電層上方；在該第一晶粒與該第一電連接體上方，形成重佈層；在該重佈層上方，形成第二電連接體，該第二電連接體係耦合至該第一晶粒與該第一電連接體至少其一；移除該載體基板，以暴露該第一介電層；以及移除該第一介電層，以暴露部分的該第一晶粒與該第一電連接體；以接合結構，將第二封裝接合至該第一封裝，該接合結構係耦合至該第一電連接體；以及在該第一封裝與該第二封裝之間，形成底膠填充。
在一實施例中，其中在該第一封裝與該第二封裝之間形成底膠填充係包括：以該接合結構將該第二封裝接合至該第一封裝後，在該第一封裝與該第二封裝之間，注入該底膠填充，該底膠填充係環繞該接合結構。
在一實施例中，其中在該第一封裝與該第二封裝之間注入該底膠填充之後，經由該底膠填充暴露部分的該第一晶粒。
在一實施例中，其中在該第一封裝與該第二封裝之間形成底膠填充係包括：以該接合結構將該第二封裝接合至該第一封裝之前，在該第一封裝上方，形成該底膠填充；以及圖案化該底膠填充，以暴露至少該第一電連接體的部分。
在一實施例中，其中圖案化該底膠填充係進一步包括圖案化該底膠填充，以暴露該第一晶粒的部分。
在一實施例中，其中在該第一封裝與該第二封裝之間形成底膠填充係包括形成液體環氧化合物、變形膠、矽橡膠、非傳導膜、聚合物、聚苯并噁唑、聚亞醯胺、抗焊劑、或其組合。
在一實施例中，其中移除該第一介電層進一步包括蝕刻該第一介電層以暴露部分的該第一晶粒與該第一電連接體。
在一實施例中，其中移除該第一介電層進一步包括研磨該第一 介電層以暴露部分的該第一晶粒與該第一電連接體。
在一實施例中，其中形成該第一封裝進一步包括用成形材料封裝該第一晶粒與該第一電連接體，該第一電連接體延伸通過該成形材料，其中該第二電連接體係金屬凸塊。
本申請案揭示內容的一些實施例係提供一種方法，其包括：形成第一晶粒封裝，該第一晶粒封裝包括第一晶粒、第一電連接體以及第一重佈層，該第一重佈層係耦合至該第一晶粒與該第一電連接體；在該第一晶粒封裝上方，形成底膠填充；圖案化該底膠填充而具有開口以暴露部分的該第一電連接體；以及以接合結構，將第二晶粒封裝接合至該第一晶粒封裝，該接合結構係耦合至該底膠填充的該開口中的該第一電連接體。
在一實施例中，所述之方法進一步包括將該第一晶粒封裝與該第二晶粒封裝從相鄰的晶粒封裝切單，以形成半導體封裝，該半導體封裝係包括該第一晶粒封裝與該第二晶粒封裝。
在一實施例中，其中形成該第一晶粒封裝進一步包括：在第一載體基板上方，形成第一介電層；在該第一介電層上方，形成該第一電連接體，該第一電連接體自該第一介電層的第一側延伸；附接該第一晶粒至該第一介電層的該第一側；用成形材料封裝該第一晶粒與該第一電連接體，該第一電連接體，該第一電連接體延伸穿過該成形材料；在該第一晶粒、該第一電連接體以及該成形材料上方，形成該第一重佈層；移除該第一載體基板以暴露該第一介電層的第二側，該第二側係與該第一側對立；以及移除該第一介電層以暴露該第一晶粒的背側表面與該第一電連接體，該底膠填充係形成於所暴露的該第一晶粒的該背側表面與該第一電連接體。
在一實施例中，其中該第一晶粒的該背側表面進一步包括晶粒附接膜。
在一實施例中，其中圖案化的該底膠填充具有側壁，該側壁實質上垂直於該第一晶粒的背側表面。
在一實施例中，其中在該第一晶粒封裝上方形成該底膠填充係包括形成液體環氧化合物、變形膠、矽橡膠、非傳導膜、聚合物、聚苯并噁唑、聚亞醯胺、抗焊劑、或其組合。
在一實施例中，所述之方法進一步包括圖案化該底膠填充以形成開口於該第一晶粒上方且與該第一晶粒對準，該開口之寬度小於該第一晶粒之寬度。
本申請案揭示內容的一些實施例係提供一種半導體封裝，其包括：第一封裝，其包括：第一晶粒；封裝體，其係環繞該第一晶粒；以及貫穿封裝通路，其延伸穿過該封裝體；第二封裝，其包括第二晶粒，該第二封裝係藉由一組連接體而接合至該第一封裝；以及底膠填充，其係位於該第一封裝與該第二封裝之間且環繞該組連接體，該底膠填充具有側壁，該側壁實質上垂直於該第一晶粒的背側表面。
在一實施例中，其中該底膠填充係包括液體環氧化合物、變形膠、矽橡膠、非傳導膜、聚合物、聚苯并噁唑、聚亞醯胺、抗焊劑、或其組合。
在一實施例中，其中該底膠填充具有第一開口於該第一晶粒上方，該第一開口的寬度小於該第一晶粒的寬度。
在一實施例中，其中該第一封裝具有第一寬度以及該第二封裝具有第二寬度，該第二寬度小於該第一寬度。前文已頗為廣泛地概述本發明之特徵及技術優勢以便可更好地理解隨後的本發明之詳細描述。本發明之額外特徵及優勢將在下文中加以描述，且形成本發明之申請專利範圍的主題。熟習此項技術者應瞭解，所揭示之概念及特定實施例可易於用作修改或設計其他結構或程序以用於進行本發明之同樣目的之基礎。熟習此項技術者亦應認識到，此等等效構造並不脫離 如隨附申請專利範圍中所闡明之本發明之精神及範疇。
100‧‧‧第一封裝
102‧‧‧載體基板
104‧‧‧黏著層
106‧‧‧介電層
108‧‧‧晶種層
110‧‧‧電連接體
110A‧‧‧表面
110B‧‧‧表面
112‧‧‧光阻
120‧‧‧晶粒
120A‧‧‧表面
120B‧‧‧背側表面
124‧‧‧接點區
126‧‧‧黏著層
130‧‧‧成形材料
130A‧‧‧表面
131‧‧‧重佈層
132‧‧‧金屬層
134‧‧‧鈍化層
136‧‧‧連接體
138‧‧‧框架
140‧‧‧第二載體基板
142‧‧‧可剝黏膠
200‧‧‧第二封裝
202‧‧‧基板
204‧‧‧接墊
206‧‧‧接墊
208‧‧‧貫穿通路
210‧‧‧傳導連接體
212‧‧‧堆疊晶粒
214‧‧‧線接合
216‧‧‧成形材料
218‧‧‧介金屬化合物
220‧‧‧底膠填充
220A‧‧‧側壁
224‧‧‧開口
222‧‧‧開口
232‧‧‧結構
230‧‧‧緩衝層
300‧‧‧半導體封裝
234‧‧‧切割工具
402‧‧‧封裝基板
400‧‧‧半導體封裝
406‧‧‧底膠填充
404‧‧‧通路
由以下詳細說明與附隨圖式得以最佳了解本申請案揭示內容之各方面。注意，根據產業之標準實施方式，各種特徵並非依比例繪示。實際上，為了清楚討論，可任意增大或縮小各種特徵的尺寸。
圖1A至圖1J係根據一些實施例說明形成第一封裝的中間步驟之橫切面圖式。
圖2A至圖2C係根據一些實施例說明將第二封裝附接至圖1A至圖1J所形成之第一封裝以及將該封裝切單為半導體封裝的中間步驟之橫切面圖式。
圖3A至圖3C係根據一些實施例說明半導體封裝的橫切面圖式。
圖4A與圖4B係根據一些實施例說明形成半導體封裝之中間步驟的橫切面圖式。
圖5A至圖5C係根據一些其他實施例說明半導體封裝的橫切面圖式。
圖6、7A與7B係根據一些其他實施例說明形成半導體封裝之中間步驟的橫切面圖式。
圖8係根據一些實施例說明半導體封裝的橫切面圖式。
上文已經概略地敍述本揭露之圖式，俾使下文之本揭露詳細描述得以獲得較佳瞭解。構成本揭露之申請專利範圍標的之其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應可瞭解，下文揭示之概念與特定實施例可作為基礎而相當輕易地予以修改或設計其它結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域中具有通常知識者亦應可瞭解，這類等效的建構並無法脫離後附之申請專利範圍所提出之本揭露的精神和範圍。
以下揭示內容提供許多不同的實施方式或範例，用於實施本申請案之不同特徵。元件與配置的特定範例之描述如下，以簡化本申請案之揭示內容。當然，這些僅為範例，並非用於限制本申請案。例如，以下描述在第二特徵上或上方形成第一特徵可包含形成直接接觸的第一與第二特徵之實施方式，亦可包含在該第一與第二特徵之間形成其他特徵的實施方式，因而該第一與第二特徵可並非直接接觸。此外，本申請案可在不同範例中重複元件符號與/或字母。此重複係為了簡化與清楚之目的，而非支配不同實施方式與/或所討論架構之間的關係。
再者，本申請案可使用空間對應語詞，例如「之下」、「低於」、「較低」、「高於」、「較高」等類似語詞之簡單說明，以描述圖式中一元件或特徵與另一元件或特徵的關係。空間對應語詞係用以包括除了圖式中描述的位向之外，裝置於使用或操作中之不同位向。裝置或可被定位(旋轉90度或是其他位向)，並且可相應解釋本申請案使用的空間對應描述。
所描述關於特定內容的實施例係稱為三維(3D)整合扇出(InFO)封裝堆疊封裝(PoP)裝置。然而，其他實施例亦可用於其他電連接元件，其包含但不限於封裝堆疊封裝組合、晶粒堆疊晶粒組合、晶圓堆疊晶圓組合、晶粒堆疊基板組合、組合封裝、處理基板、中介層(interposer)、基板、或類似物、或是安裝輸入元件、板、晶粒或其他元件、或是用於連接封裝、安裝任何形式的積體電路或電路元件之結合。
圖1A至圖1J係根據一些實施例說明形成兩個第一封裝100之中間步驟的橫切面圖式。圖1A中的第一半導體封裝係包含在載體基板102 上方的黏著層104、在該黏著層104上方的介電層106，以及在該介電層106上方的晶種層108。載體基板102可為任何合適的基板，其對於該載體基板102上方的層，提供(在製程的中間操作過程中)機械支撐。該載體基板102可為晶圓，其包含玻璃、矽(例如，矽晶圓)、氧化矽、金屬板、陶瓷材料或類似物。
該黏著層104可位於該載體基板102上，例如可層壓(laminated)至該載體基板102上。該黏著層104可由黏膠(glue)形成，例如紫外線(UV)黏膠、光熱轉換(LTHC)材料、或是可為箔形成的疊層(lamination layer formed of a foil)。
該介電層106係形成於該黏著層104上方。該介電層106可為氮化矽、碳化矽、氧化矽、例如碳摻雜的氧化物之低k介電質、例如多孔碳摻雜的二氧化矽之超低k介電質、聚合物，例如環氧化合物、聚亞醯胺、苯并環丁烯(benzocyclobutene，BCB)、聚苯并噁唑(polybenzoxazole，PBO)、類似物、或其組合物，然而亦可使用其他相對軟的、通常為有機的介電材料。可藉由化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)、旋塗介電製程、類似方法或其組合，沉積該介電層106。
在該介電層106上方，形成該晶種層108。該晶種層108可由銅、鈦、鎳、金、類似物、或其組合形成。可藉由PVD、CVD、ALD、類似方法或其組合而沉積晶種層108。
圖1B係說明圖案化晶種層108以及電連接體110的形成。可藉由蝕刻製程或是任何合適的圖案化製程，將晶種層108圖案化。
電連接體110可形成於晶種層108上方，並且從該晶種層108以實質垂直於介電層106之表面的方向延伸。在一些實施例中，經由電鍍形成該電連接體110。在這些實施例中，該電連接體110係由銅、鋁、鎳、金、銀、鈀、錫、類似物、或其組合而形成，並且可具有包含複 數層的複合結構。在這些實施例中，在載體基板上方，形成光阻112或犧牲層。在一些實施例中，在晶種層108上形成且圖案化光阻112，而後在該圖案化的光阻112中形成電連接體110。可藉由例如旋塗製程之濕式製程，或是藉由例如使用乾膜的乾式製程，形成該光阻112。在光阻112中形成複數個開口，以暴露下方的晶種層108。而後，進行電鍍步驟，以電鍍該電連接體110。
在其他實施例中，該電連接體110可為焊接凸塊(stud bump)，其係在介電層106上方藉由線接合並且切割接合線而留下部分接合線附接至個別接合球而形成。例如，電連接體110可包含下部與上部，其中該下部可為形成於線接合中的接合球(未繪示)，以及該下部可為剩餘的接合線(未繪示)。電連接體110的上部具有均勻寬度與均勻形狀，從上部的頂部、中間部至底部皆為均勻。該電連接體110可為非焊料金屬材料，其可由打線機(wire bonder)接合。在一些實施例中，電連接體110係由銅線、金線、類似物或其組合而形成，並且可具有包含複數層的複合結構。在打線(wire bonding)實施例中，可省略晶種層108與光阻112。
電連接體110可形成第一封裝的背側重佈層(backside redistribution layer)。此背側重佈層可用以將另一封裝或元件(參閱圖2)耦合至第一封裝。
圖1C係說明移除光阻112。可經由合適的移除製程，例如灰化或蝕刻製程，移除該光阻112。
圖1D係說明附接晶粒120至介電層106。可用黏著層126，將晶粒120的第一側附接至介電層106。黏著層126可為任何合適的黏著劑，例如晶粒附接膜或類似物。晶粒120可為單一晶粒或是可為超過兩個晶粒。該晶粒120可包含邏輯晶粒，例如中央處理單元(CPU)、圖形處理單元(GPU)、類似物或是其組合。在一些實施例中，晶粒120係包 含晶粒堆疊(未繪示)，其可包含邏輯晶粒與記憶體晶粒。晶粒120可包含輸入/輸出(I/O)晶粒，例如寬I/O晶粒，其提供第一封裝100與後續附接之第二封裝200之間的連接(參閱圖2A)。
晶粒120包含接點區(contact area)124於晶粒120的第二側上。在一些實施例中，接點區124為接墊。接點區124可形成於晶粒120的第二側上方。在一些實施例中，在晶粒120第二側上的介電層(未繪示)中形成凹處(未繪示)而形成接點區124。所形成的該凹處使得接點區124嵌埋在介電層中。在一些實施例中，接點區124可形成於介電層上，因而省略凹處。接點區124電性與/或物理耦合晶粒120至後續接合的第二封裝200(參閱圖2A)，以及/或電連接體110。在一些實施例中，接點區124包含薄晶種層(未繪示)，其係由銅、鈦、鎳、金、錫、類似物或其組合而形成。可在該薄晶種層上方，沉積接點區124的傳導材料。可藉由電化學電鍍製程、CVD、ALD、PVD、類似方法或其組合，形成該傳導材料。在一些實施例中，接點區124的傳導材料係銅、鎢、鋁、銀、金、錫、類似物或其組合。
在一些實施例中，接點區124係凸塊下金屬層(underbump metallization，UBM)，其包含三層傳導材料，例如鈦層、銅層以及鎳層。然而，該技藝中具有通常技術者理解有許多合適的材料與層配置，例如鉻/鉻-銅合金/銅/金之配置、鈦/鈦鎢/銅之配置或是銅/鎳/金之配置，適合形成凸塊下金屬層。可用於凸塊下金屬層的任何適合的材料或材料層完全包含於本申請案的範圍內。
圖1E係說明晶粒120與電連接體110之封裝。在一些實施例中，使用成形材料130而將晶粒120與電連接體110封裝。例如，使用壓縮成形，可將成形材料130成形在晶粒120與電連接體110上。在一些實施例中，成形材料130係由模塑料(molding compound)、聚合物、環氧化合物、氧化矽填充材料、類似物或其組合而製成。可進行硬化步 驟，將成形材料130硬化，其中該硬化可為熱硬化、UV硬化、類似方法或其組合。
在一些實施例中，晶粒120、接點區124以及電連接體110係包埋在成形材料130中，並且在硬化該成形材料130之後，在該成形材料130上進行平面化步驟，例如研磨，如圖1E所示。該平面化步驟係用以移除成形材料130的過多部分，過多部分係位於接點區124與電連接體110的頂部表面上方。在一些實施例中，接點區124的表面與電連接體110的表面110A暴露，並且與成形材料130的表面130A及晶粒120的表面120A齊平。電連接體110可為貫穿成形通路(through molding via，TMV)、貫穿封裝通路(through package vias，TPV)以及/或貫穿InFO通路(through InFO via，TIV)。
在其他實施例中，接點區124為從晶粒120第二側部分延伸至晶粒120中的通路，或是在一些實施例中，該接點區124完全延伸穿過晶粒120。可由蝕刻製程形成接點區124，以於晶粒120中形成孔洞(未繪示)，並且可用傳導材料填充該孔洞，該傳導材料例如銅、鋁、鎳、金、銀、鈀、錫、類似物或其組合，該接點區124可具有包含複數層的複合結構。晶粒120亦可包含晶種層、阻障層、襯墊(liner)、類似物或其組合。
圖1F係說明在晶粒120、電連接體110以及成形材料130上方形成重佈層131。重佈層131可包含一或多金屬層132，金屬層132有時稱為頂部金屬層。在所有描述說明中，「金屬層132」一詞係指在相同層中的金屬線之統稱。重佈層131可包含一或多鈍化層134，其中該一或多金屬層132係位於一或多鈍化層134中。
鈍化層134可為氮化矽、碳化矽、氧化矽、例如碳摻雜的氧化物之低k介電質、例如多孔碳摻雜的二氧化矽之超低k介電質、聚合物，例如環氧化合物、聚亞醯胺、BCB、PBO、抗焊劑(solder resist， SR)、類似物或是其組合，然而亦可使用其他相對軟的、通常為有機的介電材料，並且藉由CVD、PVD、ALD、在介電質上旋塗的製程、壓層製程、類似方法或其組合而沉積該鈍化層134。該鈍化層134可進行硬化步驟，而硬化鈍化層134，其中該硬化可為熱硬化、UV硬化、類似方法或其組合。
可使用單一與/或雙鑲嵌製程、通路優先製程(via-first process)或是金屬優先製程(metal-first process)而形成金屬層132。該金屬層132與接點區124可由傳導材料形成，例如銅、鋁、鈦、類似物或其組合，可使用或不用阻障成形成該金屬層132與接點區124。
鑲嵌製程係形成包埋在另一層內的圖案化層，使得兩層的頂部表面為共平面。已知僅產生渠道(trench)或通路的鑲嵌製程係單鑲嵌製程(single damascene process。產生渠道與通路的鑲嵌製程係雙鑲嵌製程(dual damascene process)。
在實施例中，使用雙鑲嵌製程形成金屬層132。在此範例中，在最低鈍化層134上的形成蝕刻停止層(未繪示)，並且在該蝕刻停止層上形成下一鈍化層134，開始一部分金屬層的形成。一旦沉積該下一鈍化層134，蝕刻移除部分的該下一鈍化層134，以形成凹陷特徵，例如渠道與通路，其可用傳導材料填充以連接重佈層的不同區域並且容納金屬層132與接點區124。可對於下一部分金屬層，重複此製程。
重佈層131可指第一封裝100的前側重佈層。此前側重佈層131可用以耦合第一封裝100經由傳導連接體136而至一或多個封裝、封裝基板、元件、類似物、或其組合(參閱圖1G)。
金屬層132的數量與鈍化層134的數量係僅作為說明而不具限制性。可所述一金屬層更多或更少之其他層數。可為其他數量的鈍化層以及不同於圖1F所述之金屬層數量。
圖1G係說明形成一組傳導連接體136於重佈層131上方並且電性 耦合至該重佈層131。該傳導連接體136可為焊球、金屬柱、受控塌陷晶片連接(controlled collapse chip connection，C4)凸塊、微凸塊、無電式電鍍鎳-無電鈀浸金技術(electroless nickel-electroless palladium-immersion gold technique，ENEPIG)形成的凸塊、或類似物。該傳導連接體136可包含傳導材料，例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似物、或其組合。在傳導連接體136為焊料凸塊的實施例中，經由通常使用的方法，例如蒸鍍、電鍍、焊料轉移、植球或類似方法，初始形成焊料層而形成傳導連接體136。一旦在結構上形成焊料層，可進行回銲(reflow)，以將材料成形為所欲之凸塊形狀。在另一實施例中，傳導連接體136為金屬柱(例如銅柱)，其係由濺鍍、印刷、電鍍、無電式電鍍、CVD、或類似方法而形成。該金屬柱可為無焊料，並且具有實質垂直的側壁。在一些實施例中，在傳導連接體136的頂部上，形成金屬蓋層(未繪示)。該金屬蓋層可包含鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金、類似物、或其組合，以及可由電鍍製程形成。
雖未繪示，但可有凸塊下金屬層(UBM)耦合至重佈層131，該傳導連接體136耦合至凸塊下金屬層(未繪示)。藉由先形成一組開口(未繪示)而形成凸塊下金屬層，該組開口的形成係穿過最頂部鈍化層134，以暴露金屬層132之表面。凸塊下金屬層可延伸通過鈍化層134中的這些開口，並且亦沿著鈍化層134的表面延伸。凸塊下金屬層可包含三層傳導材料，例如鈦層、銅層以及鎳層。然而，該技藝中具有通常技術者理解有許多合適的材料與層配置，例如鉻/鉻-銅合金/銅/金的配置、鈦/鈦鎢/銅的配置、或是銅/鎳/金的配置，其適合用於形成凸塊下金屬層。可用於凸塊下金屬層之任何合適的材料或材料層完全包含在本申請案的範圍內。
圖1H係根據實施例說明移除載體基板102與黏著層104以暴露介 電層106。在此實施例中，該第一封裝係置放於框架138上，傳導連接體136鄰接框架138，而移除載體基板102與黏著層104。
圖1I係根據另一實施例說明移除載體基板102與黏著層104以暴露介電層106。在此實施例中，該第一封裝係置放於第二載體基板140上，傳導連接體136係鄰接第二載體基板140，而移除載體基板102與黏著層104。此實施例可包含在第二載體基板140上的可剝黏膠(peelable glue)142，該傳導連接體136係包埋在該可剝黏膠142中。可剝黏膠142可助於第一封裝100固定至第二載體基板140。在移除載體基板103之後，可藉由剝除方法移除可剝黏膠142，該剝除方法包含熱製程、化學剝離製程、雷射移除、UV處理、類似方法或其組合。
圖1J係說明介電層106的移除。可經由合適的移除製程，例如蝕刻製程，移除介電層106。在移除介電層106之後，暴露部分的晶粒120與電連接體110。曝光電連接體110的表面110B，其可包含晶種層108。此外，曝光晶粒120的背側表面120B，其可包含黏著層126。例如，在一些實施例中，在移除介電層106之後，可藉由蝕刻製程，使得電連接體110凹陷。在一些實施例中，移除黏著層126以暴露晶粒120之表面。在其他實施例中，當附接晶粒120至載體基板102時，不使用黏著層126(參閱圖1C)。在一些實施例中，表面130B與背側表面120B係實質共平面，並且高於表面110B。換言之，電連接體110凹陷於成形材料130中。
圖2A至圖2C係根據一些實施例說明將第二封裝附接至圖1A至圖1J所形成之第一封裝以及將該封裝切單為半導體封裝的中間步驟之橫切面圖式。參閱圖2A，第二封裝200係以一組傳導連接體210而接合至第一封裝100，形成半導體封裝300。
第二封裝200各自包含基板202以及耦合至基板202的一或多個堆疊晶粒212(212A與212B)。基板202可由半導體材料製成，例如矽、 鍺、鑽石、或類似物。或者，亦可使用化合物材料，例如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、鎵砷磷化物、鎵銦磷化物、其組合以及類似物。此外，基板202可為絕緣體上矽(SOI)基板。通常，SOI基板包含半導體材料層，例如磊晶矽、鍺、矽鍺、SOI、絕緣體上矽鍺(SGOI)、或其組合。在另一實施例中，基板202係以絕緣核心為基礎，該絕緣核心例如纖維玻璃強化的樹脂核心。核心材料的一範例係纖維玻璃樹脂，例如FR4。該核心材料的替代物包含雙馬來醯亞胺三嗪(bismaleimide-triazine，BT)樹脂，或是其他印刷電路板(PCB)材料或膜。例如Ajinomoto建立膜(Ajinomoto build-up film，ABF)或是其他壓層可作為基板202。基板202可稱為封裝基板202。
基板202可包含主動與被動裝置(未繪示於圖2A)。該技藝中具有通常技術者理解可使用許多裝置，例如電晶體、電容器、電阻器、其組合以及類似物，用以產生半導體封裝300之設計的結構與功能需求。可使用任何合適的方法形成該裝置。
基板202可包含金屬化層(未繪示)以及貫穿通路208。該金屬化層可形成於主動與被動裝置上方，並且設計為連接各種裝置以形成功能性電路。可用任何合適的製程(例如沉積、鑲嵌、雙鑲嵌、或類似方法)，由介電材料(例如，低k介電材料)與傳導材料(例如，銅)的交替層形成該金屬化層，以通路互連傳導材料層。在一些實施例中，基板202實質上無主動與被動裝置。
基板202可具有接墊204於基板202的第一側上，以耦合至堆疊晶粒212，以及具有接墊206於基板202的第二側上，以耦合至傳導連接體210，基板202的該第二側係與該第一側對立。在一些實施例中，在基板202的第一與第二側上的介電層(未繪示)中形成凹槽(未繪示)而形成接墊204與206。凹槽的形成使得接墊204與206包埋在介電層中。在其他實施例中，由於接墊204與206可形成在介電層上，因而可省略凹 槽。在一些實施例中，接墊204與206包含薄晶種層(未繪示)，其係由銅、鈦、鎳、金、鈀、類似物或其組合而製成。可在薄晶種層上方，沉積接墊204與206之傳導材料。可藉由電化學鍍製程、無電式電鍍製程、CVD、ALD、PVD、類似方法或其組合，形成該傳導材料。在實施例中，接墊204與206的傳導材料係銅、鎢、鋁、銀、金、類似物、或其組合。
在實施例中，接墊204與206係為凸塊下金屬層，其包含三層傳導材料，例如鈦層、銅層以及鎳層。然而，該技藝中具有通常技術者理解有許多合適的材料與層配置，例如鉻/鉻-銅合金/銅/金之配置、鈦/鈦鎢/銅之配置或是銅/鎳/金之配置，適合形成接墊204與206。可用於接墊204與206的任何適合的材料或材料層完全包含於本申請案的範圍內。在一些實施例中，貫穿通路208係沿伸穿過基板202並且耦合至少一接墊204到至少一接墊206。
在所述之實施例中，藉由線接合214，堆疊晶粒212係耦合至基板202，然而可使用其他連接，例如傳導凸塊。在實施例中，堆疊晶粒212係堆疊的記憶體晶粒。例如，該記憶體堆疊晶粒212可包含低功率(low-power,LP)雙倍數據率(double data rate，DDR)記憶體模組，例如LPDDR1、LPDDR2、LPDDR3或類似的記憶體模組。
在一些實施例中，堆疊晶粒212與線接合214可被成形材料216封裝。例如，使用壓縮成形，該成形材料216可成形於堆疊晶粒212與線接合214上。在一些實施例中，成形材料216係模塑料、聚合物、環氧化合物、氧化矽填充材料、類似物或其組合。可進行硬化步驟，以硬化該成形材料216，其中該硬化可為熱硬化、UV硬化、類似方法或其組合。
在一些實施例中，堆疊晶粒212與線接合214係包埋在成形材料216中，並且在硬化該成形材料216之後，進行平面化步驟，例如研 磨，以移除成形材料216的過多部分，並且對於第二封裝200提供實質平坦的表面。
在形成第二封裝200之後，藉由傳導連接體210、接墊206與電連接體110，將第二封裝200接合至第一封裝100。在一些實施例中，記憶體堆疊晶粒212可經由線接合214、接墊204與206、貫穿通路208、傳導連接體210以及電連接體110而耦合至晶粒120。
傳導連接體210可類似於上述的傳導連接體136，不再重複說明，然而傳導連接體210與136不需要相同。在一些實施例中，在接合傳導連接體210之前，傳導連接體210係塗覆助焊劑(flux)(未繪示)，例如免清洗助焊劑。該傳導連接體210可浸入助焊劑，或是該助焊劑可噴在該傳導連接體210上。在另一實施例中，該助焊劑可施用於電連接體110之表面。
第二封裝200與第一封裝100之間的接合可為焊料接合或是直接金屬對金屬(例如銅對銅或錫對錫)接合。在實施例中，第二封裝200係藉由回銲製程而接合至第一封裝100。在此回銲製程過程中，傳導連接體210係與該接墊206及電連接體110接觸，因而將第二封裝200物理性以及電性耦合至第一封裝100。在接合製程之後，介金屬化合物(intermetallic compound，IMC)218可形成在電連接體110與傳導連接體210的介面，亦形成於傳導連接體210與接墊206的介面。
圖2B係說明在第一封裝100與第二封裝200之間以及在傳導連接體210之間形成底膠填充(underfill)220。該底膠填充220可由液體環氧化合物、變形膠、矽橡膠、非傳導膜、聚合物、PBO、聚亞醯胺、抗焊劑、或其組合所形成。該底膠填充220對於傳導連接體210提供結構性支撐，並且在傳導連接體210接合在第一封裝100與第二封裝200之間之後，使用毛細作用力分配該底膠填充220。在這些實施例中，底膠填充220包含填角(fillet)，其中側壁220A對角線相交於晶粒120的背 側表面120B。在一些實施例中，形成底膠填充220，以於晶粒120上方留下開口222。
圖2C係說明將半導體封裝300切單。可從框架138移除半導體封裝300，該半導體封裝300可置放於結構232上方，該結構232例如切割膠帶(dicing tape)。可藉由切割工具234，將半導體封裝300切單，該切割工具234例如晶粒鋸、雷射、類似物或其組合。
圖1A至圖1J以及圖2A至圖2C中的第一封裝100與第二封裝200的數量僅係作為說明，並非用於限制本申請案。可為超過或少於所樹脂兩個封裝的其他封裝數量。
圖3A至圖3C係根據一些實施例說明半導體封裝300的橫切面圖式。參閱圖3A，此實施例具有底膠填充220，其含有填角(fillet)。該第一封裝100的寬度為W100，該第二封裝的寬度為W200，以及在第一與第二封裝100與200之間的該底膠填充220的外部寬度為W220。底膠填充220的開口222之寬度為W222，以及晶粒120的寬度為W120。在實施例中，寬度W220係小於或等於寬度W100，寬度W200係小於或等於W220，以及寬度W222係小於或等於寬度W120。在另一實施例中，寬度W220係小於寬度W100，寬度W200係小於寬度W220，以及寬度W222係小於寬度W120。第一與第二封裝100與200之間的底膠填充220高度為H220(有時稱為間距高度)。在實施例中，高度H220係約1微米至約200微米。
圖3B係說明半導體封裝300的另一實施例。此實施例係類似於圖3A之實施例，除了底膠填充220中無開口(請參閱圖3A中的222)。開口222的形成係僅於半導體封裝300外緣附近形成底膠填充220而不在半導體封裝300的中心區域形成底膠填充220。關於此實施例的詳細說明，其係與先前描述的實施例類似，因而不再重複說明。
圖3C係說明半導體封裝300的另一實施例。此實施例係類似於圖 3B的實施例，除了有緩衝層230插在第一封裝100與底膠填充220之間。關於此實施例的詳細說明，其係與先前描述的實施例類似，因而不再重複說明。
緩衝層230係形成於晶粒120(以及黏著層236)、電連接體110以及成形材料130的上方。緩衝層230可由聚合物形成，例如聚亞醯胺、PBO或類似物。緩衝層230亦可為LTHC材料。在實施例中，所形成的緩衝層230之厚度係從約0.1微米至約20微米。
藉由從第一封裝100移除介電層106，可減少第一封裝100的翹曲(warpage)，因而可改良第一封裝100與第二封裝200之間的共面性(coplanarity)與間距高度(standoff height)控制。此外，使用免清洗助焊劑排除第一封裝100與第二封裝200之間殘留助焊劑的問題。再者，在切單製程之前，藉由形成底膠填充220，保護傳導連接體210免於遭受切單製程殘留物造成的電性故障(例如，傳導連接體之間的短路)。再者，藉由使第二封裝200與第一封裝100寬度相似，這使得底膠填充220與半導體封裝300之間具有更大的間隔，以防止兩個半導體封裝300之間的底膠填充汙染以及底膠填充延伸至相鄰第二封裝200之間的問題。
圖4A與4B係根據一些其他實施例說明形成半導體封裝300之中間步驟的橫切面圖式。此實施例係類似於圖1A至圖1J與圖2A至圖2C之實施例，除了在第一封裝100接合至第二封裝200之前，形成且圖案化底膠填充220。關於此實施例的詳細說明，其係與先前描述的實施例類似，因而不再重複說明。
圖4A係說明已經完成圖1A至圖1J所述之步驟後的中間製程步驟。在圖1J的步驟之後，在晶粒120、成形材料130以及電連接體110上方，形成底膠填充220。可藉由CVD、PVD或ALD沉積底膠填充220、可藉由例如旋塗製程、網印製程之濕式製程形成底膠填充220， 或是藉由例如在乾膜上滾動之乾式製程而形成底膠填充220。在形成底膠填充220之後，將底膠填充220圖案化，以於電連接體110上方形成開口，以暴露部分的電連接體110(以及晶種層108)。在一些實施例中，將底膠填充220圖案化，以於晶粒120(以及黏著層126)上方形成開口222。使用可接受的光微影技術與蝕刻，例如雷射蝕刻製程，將底膠填充220圖案化。所形成的開口222之寬度為W222，以及所形成的開口224之寬度為W224。在實施例中，寬度W222係小於或等於寬度W120，以及寬度W224係小於或等於電連接體110之寬度W110。在另一實施例中，寬度W222係小於寬度W120，以及寬度W224係小於寬度W110。在含有緩衝層230的實施例(參閱圖3C)中，開口224中的緩衝層230之開口的寬度係小於或等於寬度W224。所形成的底膠填充220之高度H220係約1微米至約200微米。在此實施例中，底膠填充220之側壁220A係實質垂直於晶粒120的背側表面120B。在一些實施例中，將底膠填充220圖案化，使得在相鄰第一封裝100之間的切割道(scribe line)中無底膠填充220。
圖4B係說明將第二封裝200附接至圖4A的第一封裝100。此類似於圖2A所述之製程，除了在接合製程過程中有底膠填充220。關於此實施例的詳細說明，其係與先前描述的實施例類似，因而不再重複說明。而後將第一、二封裝100與200切成多個半導體晶粒，如圖2C所述。
圖5A至圖5C係根據一些實施例說明半導體封裝300的橫切面圖式。這些實施例係類似於圖3A至圖3C所述之實施例，除了這些實施例在將封裝接合在一起之前具有底膠填充220，以及底膠填充220的側壁220A係實質垂直於晶粒120的背側表面並且不具有填角(fillet)。關於此實施例的詳細說明，其係與先前描述的實施例類似，因而不再重複說明。
參閱圖5A，底膠填充220具有開口於晶粒120上方。圖5B係說明底膠填充220無開口於晶粒120上方。圖5C係說明半導體封裝300具有緩衝層230於第一封裝100上方。
在接合封裝之前，藉由從第一封裝100移除介電層106以及形成底膠填充220，可減少第一封裝100的翹曲，因而可改良第一封裝100與第二封裝200之間的共面性(coplanarity)與間距高度(standoff height)控制。此外，在切單製程之前，藉由形成底膠填充220，保護傳導連接體210免於遭受切單製程殘留物造成的電性故障(例如，傳導連接體之間的短路)。再者，藉由使第二封裝200與第一封裝100寬度相似，這使得底膠填充220與半導體封裝300之間具有更大的間隔，以防止兩個半導體封裝300之間的底膠填充汙染以及底膠填充延伸至相鄰第二封裝200之間的問題。
圖6、7A與7B根據一些其他實施例說明形成半導體封裝之中間步驟的橫切面圖式。此實施例係類似於圖1J所述之實施例，除了係用研磨製程而非蝕刻製程移除介電層106。關於此實施例的詳細說明，其係與先前描述的實施例類似，因而不再重複說明。
在此實施例中，該研磨製程可為化學機械拋光(CMP)製程。該研磨製程可移除晶種層108與黏著層126。在一些實施例中，表面130B、背側表面120B以及表面110B係實質上共平面。在一些其他實施例中，表面130B與背側表面120B係實質上共平面，以及表面110B係凹陷於成形材料130中。
此實施例的製程可繼續圖2A至圖2C所述之附接第二封裝200與切單。此實施例可使用如圖2A至圖3C以及圖4A與圖5C所述之底膠填充。
圖7A係說明來自圖6之第一封裝100與圖2A至圖3C之具填角的底膠填充之半導體封裝300之橫切面圖式。雖然所示之底膠填充220具有 開口222，然而可省略開口222。圖7B係說明來自圖6之第一封裝100與圖4A至圖5C之無填角的底膠填充之半導體封裝300之橫切面圖式。
圖8係根據一些實施例說明半導體封裝400的橫切面圖式。該半導體封裝400包含半導體封裝300安裝至封裝基板402。半導體封裝300可為上述任何實施例的半導體封裝300。使用傳導連接體136，將半導體封裝300安裝至封裝基板402。
封裝基板402可由半導體材料製成，例如矽、鍺、鑽石、或類似物。或者，亦可使用化合物材料，例如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、鎵砷磷化物、鎵銦磷化物、其組合以及類似物。此外，封裝基板402可為SOI基板。通常，SOI基板包含半導體材料層，例如磊晶矽、鍺、矽鍺、SOI、SGOI、或其組合。在另一實施例中，封裝基板402係以絕緣核心為基礎，該絕緣核心例如纖維玻璃強化的樹脂核心。核心材料的一範例係纖維玻璃樹脂，例如FR4。該核心材料的替代物包含雙馬來醯亞胺三嗪(bismaleimide-triazine，BT)樹脂，或是其他PCB材料或膜。例如ABF或是其他壓層可作為封裝基板402。
該封裝基板402可包含主動與被動裝置(未繪示於圖8)。該技藝中具有通常技術者理解可使用許多裝置，例如電晶體、電容器、電阻器、其組合以及類似物，用以產生半導體封裝400之設計的結構與功能需求。可使用任何合適的方法形成該裝置。
封裝基板402亦可包含通路404或金屬化層。通路404可形成於主動與被動裝置上方，並且設計為連接各種裝置以形成功能性電路。可用任何合適的製程(例如沉積、鑲嵌、雙鑲嵌、或類似方法)，由介電材料(例如，低k介電材料)與傳導材料(例如，銅)的交替層形成該通路404，以通路互連傳導材料層。在一些實施例中，封裝基板402實質上無主動與被動裝置。
半導體封裝400係包含半導體封裝300與封裝基板402之間以及傳導連接體136之間的底膠填充406。該底膠填充406可由液體環氧化合物、變形膠、矽橡膠、非傳導膜、聚合物、PBO、聚亞醯胺、抗焊劑、或其組合所形成。該底膠填充406對於傳導連接體136提供結構性支撐，並且在傳導連接體136接合在半導體封裝300與封裝基板402之間之後，使用毛細作用力分配該底膠填充406。在這些實施例中，底膠填充406包含填角(fillet)，並且可向上延伸該半導體封裝以鄰接該第一封裝100、底膠填充220與第二封裝200的側壁。
在接合封裝之前，藉由從第一封裝移除介電層以及形成底膠填充，可減少第一封裝的翹曲，因而可改良第一封裝與第二封裝之間的共面性(coplanarity)與間距高度(standoff height)控制。此外，在切單製程之前，藉由形成底膠填充，保護傳導連接體免於遭受切單製程殘留物造成的電性故障(例如，傳導連接體之間的短路)。再者，藉由使第二封裝與第一封裝100度相似，這使得底膠填充與半導體封裝之間具有更大的間隔，以防止兩個半導體封裝之間的底膠填充汙染以及底膠填充延伸至相鄰第二封裝之間的問題。
提供包含形成第一封裝之方法的實施例。形成第一封裝包含形成第一介電層於載體基板上方，形成第一電連接體於該第一介電層上方，將第一晶粒附接相鄰該第一電連接體且於該第一介電層上方，形成重佈層於該第一晶粒與該第一電連接體上方，形成第二電連接體於該重佈層上方，該第二電連接體係耦合至該第一晶粒與該第一電連接體至少其一，移除該載體基板以暴露該第一介電層，以及移除該第一介電層以暴露部分的該第一晶粒與該第一電連接體。該方法進一步包含以接合結構，將第二封裝接合至該第一封裝，該接合結構係耦合至該第一電連接體，以及形成該第一封裝與該第二封裝之間的底膠填充。
另一方法實施例係包含形成第一晶粒封裝，該第一晶粒封裝包含第一晶粒、第一電連接體以及第一重佈層，該第一重佈層係耦合至該第一晶粒與該第一電性連接器，形成底膠填充於該第一晶粒封裝上方，將該底膠填充圖案化而具有開口以暴露部分的該第一電連接體，以及用接合結構將第二晶粒封裝接合至該第一晶粒封裝，該接合結構係耦合至該底膠填充的開口中之該第一電連接體。
另一實施例係包含第一封裝的半導體封裝。該第一封裝包含第一晶粒、在該第一晶粒周圍的封裝體，以及貫穿封裝通路，其延伸穿過該封裝體。該半導體封裝進一步包含第二封裝，其包括第二晶粒，該第二封裝係藉由一組連接體而接合至該第一封裝，以及在該第一封裝與該第二封裝之間且環繞該組連接體的底膠填充，該底膠填充具有側壁，其係實質上垂直於該第一晶粒的背側表面。
前述內容概述一些實施方式的特徵，因而熟知此技藝之人士可更加理解本申請案揭示內容之各方面。熟知此技藝之人士應理解可輕易使用本申請案揭示內容作為基礎，用於設計或修飾其他製程與結構而實現與本申請案所述之實施方式具有相同目的與/或達到相同優點。熟知此技藝之人士亦應理解此均等架構並不脫離本申請案揭示內容的精神與範圍，以及熟知此技藝之人士可進行各種變化、取代與替換，而不脫離本申請案揭示內容之精神與範圍。
100‧‧‧第一封裝
200‧‧‧第二封裝
300‧‧‧半導體封裝
210‧‧‧傳導連接體
220A‧‧‧側壁
222‧‧‧開口

Claims (10)

  1. 一種方法，其包括：形成第一封裝，其包括：在載體基板上方，形成第一介電層；在該第一介電層上方，形成第一電連接體；將第一晶粒附接相鄰該第一電連接體且於該第一介電層上方；在該第一晶粒與該第一電連接體上方，形成重佈層；在該重佈層上方，形成第二電連接體，該第二電連接體係耦合至該第一晶粒與該第一電連接體至少其一；移除該載體基板，以暴露該第一介電層；以及移除該第一介電層，以暴露部分的該第一晶粒與該第一電連接體；以接合結構，將第二封裝接合至該第一封裝，該接合結構係耦合至該第一電連接體；以及在該第一封裝與該第二封裝之間，形成底膠填充。
  2. 如請求項1所述之方法，其中在該第一封裝與該第二封裝之間注入該底膠填充之後，經由該底膠填充暴露部分的該第一晶粒。
  3. 如請求項1所述之方法，其中在該第一封裝與該第二封裝之間形成底膠填充係包括：以該接合結構將該第二封裝接合至該第一封裝之前，在該第一封裝上方，形成該底膠填充；以及圖案化該底膠填充，以暴露至少該第一電連接體的部分。
  4. 如請求項3所述之方法，其中圖案化該底膠填充係進一步包括圖案化該底膠填充，以暴露該第一晶粒的部分。
  5. 如請求項1所述之方法，其中形成該第一封裝進一步包括用成形材料封裝該第一晶粒與該第一電連接體，該第一電連接體延伸通過該成形材料，其中該第二電連接體係金屬凸塊。
  6. 一種方法，其包括：形成第一晶粒封裝，該第一晶粒封裝包括第一晶粒、第一電連接體以及第一重佈層，該第一重佈層係耦合至該第一晶粒與該第一電連接體；在該第一晶粒封裝上方，形成底膠填充；圖案化該底膠填充而具有開口以暴露部分的該第一電連接體；以及以接合結構，將第二晶粒封裝接合至該第一晶粒封裝，該接合結構係耦合至該底膠填充的該開口中的該第一電連接體。
  7. 如請求項6所述之方法，其中形成該第一晶粒封裝進一步包括：在第一載體基板上方，形成第一介電層；在該第一介電層上方，形成該第一電連接體，該第一電連接體自該第一介電層的第一側延伸；附接該第一晶粒至該第一介電層的該第一側；用成形材料封裝該第一晶粒與該第一電連接體，該第一電連接體，該第一電連接體延伸穿過該成形材料；在該第一晶粒、該第一電連接體以及該成形材料上方，形成該第一重佈層；移除該第一載體基板以暴露該第一介電層的第二側，該第二側係與該第一側對立；以及移除該第一介電層以暴露該第一晶粒的背側表面與該第一電連接體，該底膠填充係形成於所暴露的該第一晶粒的該背側表 面與該第一電連接體。
  8. 一種半導體封裝，其包括：第一封裝，其包括：第一晶粒；封裝體，其係環繞該第一晶粒；以及貫穿封裝通路，其延伸穿過該封裝體；第二封裝，其包括第二晶粒，該第二封裝係藉由一組連接體而接合至該第一封裝；以及底膠填充，其係位於該第一封裝與該第二封裝之間且環繞該組連接體，該底膠填充具有側壁，該側壁實質上垂直於該第一晶粒的背側表面。
  9. 如請求項8所述之半導體封裝，其中該底膠填充具有第一開口於該第一晶粒上方，該第一開口的寬度小於該第一晶粒的寬度。
  10. 如請求項8所述之半導體封裝，其中該第一封裝具有第一寬度以及該第二封裝具有第二寬度，該第二寬度小於該第一寬度。
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