TWI712115B - 封裝件及其製造方法 - Google Patents
封裝件及其製造方法 Download PDFInfo
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- TWI712115B TWI712115B TW108104409A TW108104409A TWI712115B TW I712115 B TWI712115 B TW I712115B TW 108104409 A TW108104409 A TW 108104409A TW 108104409 A TW108104409 A TW 108104409A TW I712115 B TWI712115 B TW I712115B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 238000004806 packaging method and process Methods 0.000 claims description 105
- 238000000034 method Methods 0.000 claims description 90
- 239000004020 conductor Substances 0.000 claims description 36
- 229910000765 intermetallic Inorganic materials 0.000 claims description 33
- 239000010410 layer Substances 0.000 description 178
- 230000008569 process Effects 0.000 description 62
- 238000001465 metallisation Methods 0.000 description 60
- 239000000463 material Substances 0.000 description 42
- 229920002120 photoresistant polymer Polymers 0.000 description 41
- 239000000758 substrate Substances 0.000 description 40
- 229910052751 metal Inorganic materials 0.000 description 29
- 239000002184 metal Substances 0.000 description 29
- 238000010438 heat treatment Methods 0.000 description 18
- 239000004065 semiconductor Substances 0.000 description 17
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 13
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 13
- 229910052802 copper Inorganic materials 0.000 description 13
- 239000010949 copper Substances 0.000 description 13
- 238000005538 encapsulation Methods 0.000 description 13
- 238000000059 patterning Methods 0.000 description 13
- 239000010936 titanium Substances 0.000 description 13
- 229910052719 titanium Inorganic materials 0.000 description 13
- 238000005530 etching Methods 0.000 description 11
- 229910000679 solder Inorganic materials 0.000 description 11
- 230000001070 adhesive effect Effects 0.000 description 9
- 239000003989 dielectric material Substances 0.000 description 8
- 238000004528 spin coating Methods 0.000 description 8
- 239000000853 adhesive Substances 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 230000002829 reductive effect Effects 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 238000009713 electroplating Methods 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- 239000005360 phosphosilicate glass Substances 0.000 description 6
- 238000007747 plating Methods 0.000 description 6
- 229920000642 polymer Polymers 0.000 description 6
- 235000012431 wafers Nutrition 0.000 description 6
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 5
- 238000004140 cleaning Methods 0.000 description 5
- 150000001875 compounds Chemical class 0.000 description 5
- 238000007772 electroless plating Methods 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 5
- 229920002577 polybenzoxazole Polymers 0.000 description 5
- 229920000647 polyepoxide Polymers 0.000 description 5
- 230000001681 protective effect Effects 0.000 description 5
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 4
- 238000004380 ashing Methods 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 239000005388 borosilicate glass Substances 0.000 description 4
- 239000002131 composite material Substances 0.000 description 4
- 238000001816 cooling Methods 0.000 description 4
- 239000011162 core material Substances 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 230000004907 flux Effects 0.000 description 4
- 238000003475 lamination Methods 0.000 description 4
- 150000002739 metals Chemical class 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000002356 single layer Substances 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 229910052763 palladium Inorganic materials 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 238000007639 printing Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000011152 fibreglass Substances 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 230000036961 partial effect Effects 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 239000004952 Polyamide Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000000748 compression moulding Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000011010 flushing procedure Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 150000002466 imines Chemical class 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 239000005001 laminate film Substances 0.000 description 1
- 238000004093 laser heating Methods 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- BSIDXUHWUKTRQL-UHFFFAOYSA-N nickel palladium Chemical compound [Ni].[Pd] BSIDXUHWUKTRQL-UHFFFAOYSA-N 0.000 description 1
- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 150000003839 salts Chemical class 0.000 description 1
- -1 silicon nitride Chemical class 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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Abstract
一種製造封裝件的方法包括如下步驟。將第一封裝組件
對準第二封裝組件,第一封裝組件具有第一區及第二區,第一區包括第一導電連接件,第二區包括第二導電連接件。對第一封裝組件的頂表面的第一部分執行第一雷射照射,第一雷射照射使第一區的第一導電連接件回焊,第一封裝組件的頂表面的第一部分與第一區完全交疊。以及,在執行第一雷射照射後,對第一封裝組件的頂表面的第二部分執行第二雷射照射。第二雷射照射使第二區的第二導電連接件回焊,第一封裝組件的頂表面的第二部分與第二區完全交疊。
Description
本發明實施例是有關於一種封裝件及其製造方法。
由於各種電子組件(例如,電晶體、二極體、電阻器、電容器等)積體密度持續提高,半導體行業經歷了快速發展。在很大程度上,積體密度提高起因於最小特徵大小(minimum feature size)的交互減小,此使得更多組件能夠被整合於給定區域中。隨著縮小電子裝置需求的增長,更小且更具創造性的半導體晶粒封裝技術的需求浮現。此種封裝系統的實例是疊層封裝(Package-on-Package;PoP)技術。在疊層封裝裝置中,頂部半導體封裝疊置於底部半導體封裝的頂部上,以提供高積體程度及組件密度。疊層封裝技術一般而言能夠生產功能得到增強且在印刷電路板(printed circuit board;PCB)上佔用面積小的半導體裝置。
一種製造封裝件的方法包括下列步驟。將第一封裝組件對準第二封裝組件,所述第一封裝組件具有第一區及第二區,所述第一區包括第一導電連接件,所述第二區包括第二導電連接件。對所述第一封裝組件的頂表面的第一部分執行第一雷射照射,所述第一雷射照射使所述第一區的所述第一導電連接件回焊,所述第一封裝組件的所述頂表面的所述第一部分與所述第一區完全交疊。在執行所述第一雷射照射後,對所述第一封裝組件的所述頂表面的第二部分執行第二雷射照射,所述第二雷射照射使所述第二區的所述第二導電連接件回焊,所述第一封裝組件的所述頂表面的所述第二部分與所述第二區完全交疊。
一種製造封裝件的方法包括下列步驟。提供第一封裝組件及第二封裝組件,所述第一封裝組件包括多個第一區,所述第二封裝組件包括多個第二區。將所述第一封裝組件的所述多個第一區對準所述第二封裝組件的所述多個第二區。對所述第一封裝組件的頂表面執行多次雷射照射,所述雷射照射中的每一者是依序地執行,所述雷射照射中的每一相應的雷射照射與所述多個第一區中的相應的第一區及所述多個第二區中的相應的第二區交疊,所述相應的第一區與所述相應的第二區之間的導電材料由所述相應的雷射照射回焊。在執行所述雷射照射後,將所述第一封裝組件的所述多個第一區及所述第二封裝組件的所述多個第二區單體化。
一種封裝件包括第一封裝件、第二封裝件、第一導電連
接件、第一金屬間化合物(inter-metallic compound;IMC)、第二導電連接件以及第二金屬間化合。第一封裝件包括第一導電特徵及第二導電特徵。第二封裝件包括第三導電特徵及第四導電特徵。第一導電連接件將所述第三導電特徵接合至所述第一導電特徵。第一金屬間化合物位於所述第一導電連接件與所述第一導電特徵之間,所述第一金屬間化合物具有第一厚度。第二導電連接件將所述第四導電特徵接合至所述第二導電特徵。第二金屬間化合物位於所述第二導電連接件與所述第二導電特徵之間,所述第二金屬間化合物具有小於所述第一厚度的第二厚度。
1、2、3、4、5、6、7、8、9、40、48、A、B、C、D、E、F、G、H、I、J、K、L:區
40A:第一區
40AB:交疊區
40B:第二區
42:中心點
44:箭頭
46:所選擇區
52:雷射光束
52A:第一雷射照射
52B:第二雷射照射
52C:第三雷射照射
52D:第四雷射照射
52E:第五雷射照射
52F:第六雷射照射
54:雷射光束產生器
100:第一封裝組件
100A、200A:第一封裝區
100B、200B:第二封裝區
101:第一封裝件
102:載體基底
104:釋放層
106:背面重佈線結構
108、112、146、150、154、158:介電層
110、148、152、156:金屬化圖案
114:開口
116:穿孔
126:積體電路晶粒
128:黏合劑
130:半導體基底
132:內連結構
134:接墊
136:保護膜
138:晶粒連接件
140:介電材料
142:包封體
144:正面重佈線結構
160:凸塊下金屬
162、164、166、168、168A、168B:導電連接件
170A、170B:金屬間化合物區
200:第二封裝組件
201:第二封裝件
300:封裝結構
302:封裝基底
304:結合墊
D1:距離
T1、T2、T3、T4:厚度
W1:寬度
圖1至圖19是根據一些實施例的在形成裝置封裝件的過程期間的中間步驟的剖視圖。
以下揭露內容提供用於實作本發明的不同特徵的諸多不同的實施例或實例。以下闡述組件及排列的具體實例以簡化本揭露內容。當然,該些僅為實例且不旨在進行限制。舉例而言,以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其中第一特徵與第二特徵被形成為直接接觸的實施例,且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而
使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外,本揭露內容可能在各種實例中重複使用參考編號及/或字母。此種重複使用是出於簡潔及清晰的目的,但自身並不表示所論述的各種實施例及/或配置之間的關係。
此外,為易於說明,本文中可能使用例如「位於...之下(beneath)」、「位於...下面(below)」、「下部的(lower)」、「位於...上方(above)」、「上部的(upper)」等空間相對性用語來闡述圖中所示一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的定向外亦囊括裝置在使用或操作中的不同定向。設備可具有其他定向(旋轉90度或處於其他定向)且本文中所用的空間相對性描述語可同樣相應地進行解釋。
根據一些實施例,藉由多照射回焊製程(multi-shot reflow process)將第一封裝組件結合至第二封裝組件。第一封裝組件及第二封裝組件可為例如晶圓,且分別包含多個封裝區。在多照射回焊製程中,藉由雷射光束依序地加熱封裝組件的封裝區。每一雷射照射與至少一個封裝區完全交疊,且每一雷射照射可與其他鄰近的封裝區部分地交疊。多照射回焊製程藉由僅直接加熱頂部封裝組件來使得第一封裝組件與第二封裝組件能夠結合在一起。可減少對底部封裝組件的間接加熱,此可幫助減少晶圓翹曲(warpage)。此外,可改變不同的雷射照射的參數以進一步幫助減少晶圓翹曲。
圖1至圖10示出根據一些實施例的在形成第一封裝組件
100的過程期間的中間步驟的剖視圖。圖中示出第一封裝區100A及第二封裝區100B,且在第一封裝區100A及第一封裝區100B中的每一者中形成有第一封裝件101(參見圖19)。第一封裝件101亦可被稱為積體扇出型(integrated fan-out;InFO)封裝。
在圖1中,提供載體基底102,且在載體基底102上形成釋放層104。載體基底102可為玻璃載體基底、陶瓷載體基底等。載體基底102可為晶圓,進而使得可同時在載體基底102上形成多個封裝。釋放層104可由聚合物系材料形成,可將聚合物系材料與載體基底102一起自將在後續步驟中形成的上覆結構移除。在一些實施例中,釋放層104是當受熱時會失去其黏合性質的環氧樹脂系熱釋放材料,例如光熱轉換(light-to-heat-conversion;LTHC)釋放塗層。在其他實施例中,釋放層104可為當暴露至紫外(ultra-violet;UV)光時會失去其黏合性質的紫外線膠(ultra-violet glue)。釋放層104可以液體形態被分配並被固化,可為疊層至載體基底102上的疊層膜(laminate film)或可為類似材料。釋放層104的頂表面可被整平且可具有高的平坦程度。
在圖2中,在釋放層104上形成背面重佈線結構106。在所示出的實施例中,背面重佈線結構106包括介電層108、金屬化圖案110(有時被稱為重佈線層或重佈線)及介電層112。背面重佈線結構106是可選的,且在一些實施例中,僅形成介電層108。
介電層108形成於釋放層104上。介電層108的底表面可接觸釋放層104的頂表面。在一些實施例中,介電層108是由
例如聚苯並噁唑(polybenzoxazole;PBO)、聚醯亞胺、苯並環丁烯(benzocyclobutene;BCB)等聚合物形成。在其他實施例中,介電層108是由以下材料形成:氮化物,例如氮化矽;氧化物,例如氧化矽、磷矽酸鹽玻璃(phosphosilicate glass;PSG)、硼矽酸鹽玻璃(borosilicate glass;BSG)、摻雜硼的磷矽酸鹽玻璃(boron-doped phosphosilicate glass;BPSG)等;或類似材料。介電層108可藉由例如以下任何可接受的沈積製程來形成:旋轉塗佈(spin coating)、化學氣相沈積(chemical vapor deposition;CVD)、疊層、類似製程或其組合。
金屬化圖案110形成於介電層108上。作為形成金屬化圖案110的實例,在介電層108上形成晶種層。在一些實施例中,晶種層是金屬層,可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中,晶種層包括鈦層及位於所述鈦層上的銅層。可使用例如物理氣相沈積(physical vapor deposition;PVD)等來形成晶種層。接著在晶種層上形成光阻並將所述光阻圖案化。可藉由旋轉塗佈等來形成光阻且可將所述光阻暴露至光以進行圖案化。光阻的圖案對應於金屬化圖案110。所述圖案化會形成穿過光阻的開口以暴露出晶種層。在光阻的開口中及在晶種層暴露出的部分上形成導電材料。導電材料可藉由鍍覆(例如,電鍍或無電鍍覆等)形成。導電材料可包括金屬,例如銅、鈦、鎢、鋁等。接著,移除光阻以及晶種層的上面未形成有導電材料的部分。可藉由例如使用氧電漿等可接受的灰化製程或剝除製程來移
除光阻。一旦光阻被移除,則例如使用可接受的蝕刻製程(例如藉由濕式蝕刻或乾式蝕刻)來移除晶種層暴露出的部分。晶種層的剩餘部分與導電材料形成金屬化圖案110。
介電層112形成於金屬化圖案110及介電層108上。在一些實施例中,介電層112是由聚合物形成,所述聚合物可為可使用微影罩幕(lithography mask)進行圖案化的感光性材料(例如,聚苯並噁唑、聚醯亞胺、苯並環丁烯或類似材料)。在其他實施例中,介電層112是由以下材料形成:氮化物,例如氮化矽;氧化物,例如氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃;或類似材料。介電層112可藉由旋轉塗佈、疊層、化學氣相沈積、類似製程或其組合來形成。接著將介電層112圖案化以形成開口114,暴露出金屬化圖案110的一些部分。所述圖案化可藉由可接受的製程來進行,例如藉由在介電層112是感光性材料時將介電層112暴露至光或者藉由使用例如非等向性蝕刻(anisotropic etch)的蝕刻來進行。
應理解,背面重佈線結構106可包括任何數目的介電層及金屬化圖案。可藉由重複進行形成金屬化圖案110及介電層112的製程來形成附加的介電層及金屬化圖案。金屬化圖案可包括導電線及導通孔。導通孔可在形成金屬化圖案期間藉由在下方介電層的開口中形成金屬化圖案的晶種層及導電材料來形成。導通孔可因此對各種導電線進行內連及電性耦合。
在圖3中,在開口114中形成穿孔116,且穿孔116遠離
背面重佈線結構106的最頂部介電層(例如,所示實施例中的介電層112)延伸。作為形成穿孔116的實例,在背面重佈線結構106上(例如,在介電層112以及金屬化圖案110的被開口114暴露出的部分上)形成晶種層。在一些實施例中,晶種層是金屬層,可為單層或包括由不同材料形成的多個子層的複合層。在特定實施例中,晶種層包括鈦層及位於所述鈦層上的銅層。可使用例如物理氣相沈積等來形成晶種層。在晶種層上形成光阻並將所述光阻圖案化。可藉由旋轉塗佈等來形成光阻且可將所述光阻暴露至光以進行圖案化。光阻的圖案對應於導通孔。所述圖案化會形成穿過光阻的開口以暴露出晶種層。在光阻的開口中及在晶種層暴露出的部分上形成導電材料。導電材料可藉由鍍覆(例如,電鍍或無電鍍覆等)形成。導電材料可包括金屬,例如銅、鈦、鎢、鋁等。移除光阻以及晶種層的上面未形成有導電材料的部分。可藉由例如使用氧電漿等可接受的灰化製程或剝除製程來移除光阻。一旦光阻被移除,則例如使用可接受的蝕刻製程(例如藉由濕式蝕刻或乾式蝕刻)來移除晶種層暴露出的部分。晶種層的剩餘部分與導電材料形成穿孔116。
在圖4中,藉由黏合劑128將積體電路晶粒126黏附至介電層112。積體電路晶粒126可為邏輯晶粒(例如,中央處理單元、微控制器等)、記憶體晶粒(例如,動態隨機存取記憶體(dynamic random access memory;DRAM)晶粒、靜態隨機存取記憶體(static random access memory;SRAM)晶粒等)、電源管
理晶粒(例如,電源管理積體電路(power management integrated circuit;PMIC)晶粒)、射頻(radio frequency;RF)晶粒、感測器晶粒、微機電系統(micro-electro-mechanical-system;MEMS)晶粒、訊號處理晶粒(例如,數位訊號處理(digital signal processing;DSP)晶粒)、前端晶粒(例如,類比前端(analog front-end;AFE)晶粒)、類似晶粒或其組合。此外,在一些實施例中,積體電路晶粒126可為不同大小(例如,不同高度及/或表面積),且在其他實施例中,積體電路晶粒126可為相同大小(例如,相同高度及/或表面積)。
在將積體電路晶粒126黏附至介電層112之前,可根據適用於在積體電路晶粒126中形成積體電路的製造流程來加工積體電路晶粒126。舉例而言,積體電路晶粒126各自包括半導體基底130(例如摻雜或未摻雜的矽)或絕緣層上半導體(semiconductor-on-insulator;SOI)基底的主動層。半導體基底可包含例如以下其他半導體材料:鍺;化合物半導體,包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦;合金半導體,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP;或其組合。亦可使用例如多層式基底或梯度基底(gradient substrate)等其他基底。可在半導體基底130中及/或半導體基底130上形成例如電晶體、二極體、電容器、電阻器等裝置,且可藉由通過例如位於半導體基底130上的一或多個介電層中的金屬化圖案所形成的內連結構132而使各所述裝置內連以形
成積體電路。
積體電路晶粒126更包括與外部連接的接墊134(例如,鋁墊)。接墊134位於可被稱為積體電路晶粒126的相應主動側的位置上。在積體電路晶粒126上及接墊134的一些部分上具有保護膜136。開口延伸穿過保護膜136至接墊134。晶粒連接件138(例如,導電柱(例如,包含例如銅等金屬))延伸穿過保護膜136中的開口並且機械地(mechanically)且電性地耦合至相應的接墊134。晶粒連接件138可藉由例如鍍覆等來形成。晶粒連接件138電性耦合積體電路晶粒126的相應的積體電路。
在積體電路晶粒126的主動側上,例如在保護膜136及晶粒連接件138上具有介電材料140。介電材料140橫向地包封晶粒連接件138,且介電材料140橫向地鄰接(coterminous)相應的積體電路晶粒126。介電材料140可為:聚合物,例如聚苯並噁唑、聚醯亞胺、苯並環丁烯等;氮化物,例如氮化矽等;氧化物,例如氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃等;類似材料或其組合,且可例如藉由旋轉塗佈、疊層、化學氣相沈積等來形成。
黏合劑128位於積體電路晶粒126的背面上且將積體電路晶粒126黏附至背面重佈線結構106(例如,介電層112)。黏合劑128可為任何適合的黏合劑、環氧樹脂、晶粒貼合膜(die attach film;DAF)等。黏合劑128可被施加至積體電路晶粒126的背面或者可被施加於背面重佈線結構106的表面上。舉例而言,可在
進行單體化以將積體電路晶粒126分開之前將黏合劑128施加至積體電路晶粒126的背面。
儘管圖中示出在第一封裝區100A及第二封裝區100B中的每一者中黏附有一個積體電路晶粒126,然而應理解,在每一封裝區中可黏附有更多的積體電路晶粒126。舉例而言,在每一區中可黏附有多個積體電路晶粒126。另外,積體電路晶粒126的大小可變化。在一些實施例中,積體電路晶粒126可為具有大的佔用面積(footprint)的晶粒(例如,系統晶片(system-on-chip;SoC)裝置)。在其中積體電路晶粒126具有大的佔用面積的實施例中,封裝區中可供用於穿孔116的空間可為有限的。當封裝區具有有限的可用於穿孔116的空間時,使用背面重佈線結構106能夠實現改善的內連排列。
在圖5中,在各個組件上形成包封體142。在形成之後,包封體142橫向地包封穿孔116及積體電路晶粒126。包封體142可為模塑化合物、環氧樹脂等。包封體142可藉由壓縮模塑(compression molding)、轉移模塑(transfer molding)等施加,且可形成於載體基底102上以使得穿孔116及/或積體電路晶粒126被掩埋或被覆蓋。接著將包封體142固化。
在圖6中,對包封體142執行平坦化製程以暴露出穿孔116及晶粒連接件138。平坦化製程亦可對介電材料140進行磨削。在平坦化製程後,穿孔116的頂表面、晶粒連接件138的頂表面、介電材料140的頂表面及包封體142的頂表面是共面的。
平坦化製程可為例如化學機械研磨(chemical-mechanical polish;CMP)、磨削製程等。在一些實施例中,舉例而言,若已暴露出穿孔116及晶粒連接件138,則可省略平坦化。
在圖7中,在穿孔116、包封體142及積體電路晶粒126上形成正面重佈線結構144。正面重佈線結構144包括:介電層146、介電層150、介電層154及介電層158;金屬化圖案148、金屬化圖案152及金屬化圖案156;以及凸塊下金屬(under bump metallurgies;UBM)160。金屬化圖案亦可被稱為重佈線層或重佈線。所示出的正面重佈線結構144僅為實例。可在正面重佈線結構144中形成更多或更少的介電層及金屬化圖案。若欲形成更少的介電層及金屬化圖案,則可省略以下論述的步驟及製程。若欲形成更多的介電層及金屬化圖案,則可重複以下論述的步驟及製程。
作為形成正面重佈線結構144的實例,在包封體142、穿孔116及晶粒連接件138上沈積介電層146。在一些實施例中,介電層146是由可使用微影罩幕進行圖案化的感光性材料(例如,聚苯並噁唑、聚醯亞胺、苯並環丁烯等)形成。可藉由旋轉塗佈、疊層、化學氣相沈積、類似製程或其組合來形成介電層146。接著將介電層146圖案化。所述圖案化會形成開口,開口暴露出穿孔116的一些部分及晶粒連接件138的一些部分。所述圖案化可藉由可接受的製程來進行,例如藉由在介電層146是感光性材料時將介電層146暴露至光或者藉由使用例如非等向性蝕刻的蝕刻來進
行。若介電層146是感光性材料,則可在所述曝光後將介電層146顯影。
接著形成金屬化圖案148。金屬化圖案148包括導電線(conductive line),所述導電線位於介電層146的主表面(major surface)上且沿介電層146的主表面延伸。金屬化圖案148更包括導通孔,所述導通孔延伸穿過介電層146以實體地及電性地連接至穿孔116及積體電路晶粒126。為形成金屬化圖案148,在介電層146上以及在延伸穿過介電層146的開口中形成晶種層。在一些實施例中,晶種層是金屬層,可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中,晶種層包括鈦層及位於所述鈦層上的銅層。可使用例如物理氣相沈積等來形成晶種層。接著在晶種層上形成光阻並將所述光阻圖案化。可藉由旋轉塗佈等來形成光阻且可將所述光阻暴露至光以進行圖案化。光阻的圖案對應於金屬化圖案148。所述圖案化會形成穿過光阻的開口以暴露出晶種層。接著在光阻的開口中及在晶種層暴露出的部分上形成導電材料。導電材料可藉由鍍覆(例如,電鍍或無電鍍覆等)形成。所述導電材料可包括金屬,比如銅、鈦、鎢、鋁等。導電材料與下方晶種層的一些部分的組合形成金屬化圖案148。移除光阻以及晶種層的上面未形成有導電材料的部分。可藉由例如使用氧電漿等可接受的灰化製程或剝除製程來移除光阻。一旦光阻被移除,則例如使用可接受的蝕刻製程(例如藉由濕式蝕刻或乾式蝕刻)來移除晶種層暴露出的部分。
在金屬化圖案148及介電層146上沈積介電層150。介電層150可採用與介電層146相似的方式來形成,且可由與介電層146相同的材料形成。
接著形成金屬化圖案152。金屬化圖案152包括導電線,所述導電線位於介電層150的主表面上且沿介電層150的主表面延伸。金屬化圖案152更包括導通孔,所述導通孔延伸穿過介電層150以實體地及電性地連接至金屬化圖案148。金屬化圖案152可採用與金屬化圖案148相似的方式來形成,且可由與金屬化圖案148相同的材料形成。
在金屬化圖案152及介電層150上沈積介電層154。介電層154可採用與介電層146相似的方式來形成,且可由與介電層146相同的材料形成。
接著形成金屬化圖案156。金屬化圖案156包括導電線,所述導電線位於介電層154的主表面上且沿介電層154的主表面延伸。金屬化圖案156更包括導通孔,所述導通孔延伸穿過介電層154以實體地及電性地連接至金屬化圖案152。金屬化圖案156可採用與金屬化圖案148相似的方式來形成,且可由與金屬化圖案148相同的材料形成。
在金屬化圖案156及介電層154上沈積介電層158。介電層158可採用與介電層146相似的方式來形成,且可由與介電層146相同的材料形成。
在介電層158上可選地形成凸塊下金屬160且凸塊下金
屬160延伸穿過介電層158。作為形成凸塊下金屬160的實例,可將介電層158圖案化以形成開口,暴露出金屬化圖案156的一些部分。所述圖案化可藉由可接受的製程來進行,例如藉由在介電層158是感光性材料時將介電層158暴露至光或者藉由使用例如非等向性蝕刻的蝕刻來進行。若介電層158是感光性材料,則可在所述曝光後將介電層158顯影。凸塊下金屬160的開口可較金屬化圖案148、152及156的導通孔部分的開口寬。在介電層158上以及在開口中形成晶種層。在一些實施例中,晶種層是金屬層,可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中,晶種層包括鈦層及位於所述鈦層上的銅層。可使用例如物理氣相沈積等來形成晶種層。接著在晶種層上形成光阻並將所述光阻圖案化。可藉由旋轉塗佈等來形成光阻且可將所述光阻暴露至光以進行圖案化。光阻的圖案對應於凸塊下金屬160。所述圖案化會形成穿過光阻的開口以暴露出晶種層。在光阻的開口中及在晶種層暴露出的部分上形成導電材料。導電材料可藉由鍍覆(例如,電鍍或無電鍍覆等)形成。所述導電材料可包括金屬,例如銅、鈦、鎢、鋁等。接著,移除光阻以及晶種層的上面未形成有導電材料的部分。可藉由例如使用氧電漿等可接受的灰化製程或剝除製程來移除光阻。一旦光阻被移除,則例如使用可接受的蝕刻製程(例如藉由濕式蝕刻或乾式蝕刻)來移除晶種層暴露出的部分。晶種層的剩餘部分與導電材料形成凸塊下金屬160。在其中凸塊下金屬160以不同方式形成的實施例中,可利用更多的光阻
及圖案化步驟。
在圖8中,在凸塊下金屬160上形成導電連接件162。導電連接件162可為球柵陣列(ball grid array;BGA)連接件、焊料球、金屬柱、受控塌陷晶粒連接(controlled collapse chip connection;C4)凸塊、微凸塊、無電鍍鎳鈀浸金技術(electroless nickel-electroless palladium-immersion gold technique;ENEPIG)形成的凸塊等。導電連接件162可包含導電材料,例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似材料或其組合。在一些實施例中,導電連接件162藉由以下方式來形成:在開始時藉由例如蒸鍍、電鍍、印刷、焊料轉移(solder transfer)、植球(ball placement)等常用方法形成焊料層。一旦已在所述結構上形成焊料層,則可執行回焊(reflow)以將材料塑形成所期望的凸塊形狀。在另一個實施例中,導電連接件162包括藉由濺鍍、印刷、電鍍、無電鍍覆、化學氣相沈積等形成的金屬柱(例如銅柱)。金屬柱可為無焊料的(solder free)且具有實質上垂直的側壁。在一些實施例中,在金屬柱的頂部上形成金屬頂蓋層。金屬頂蓋層可包含鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金、類似材料或其組合,且可藉由鍍覆製程來形成。
在圖9中,執行載體基底剝離(carrier substrate de-bonding)以將載體基底102自背面重佈線結構106(例如,介電層108)分離(或「剝離」)。根據一些實施例,所述剝離包括在釋放層104上投射例如雷射光或紫外光等光,以使得釋放層104
在光的熱量作用下分解,且可移除載體基底102。接著將所述結構翻轉並放置於膠帶上。
在圖10中,延伸穿過介電層108形成導電連接件164以使導電連接件164接觸金屬化圖案110。穿過介電層108形成開口以暴露出金屬化圖案110的一些部分。可例如使用雷射鑽孔(laser drilling)、蝕刻等來形成開口。在開口中形成導電連接件164。在一些實施例中,導電連接件164包含焊劑(flux)且是採用焊劑浸漬製程形成。在一些實施例中,導電連接件164包括導電膏(例如,焊料膏、銀膏等),且採用印刷製程分配。在一些實施例中,導電連接件164採用與導電連接件162相似的方式來形成,且可由與導電連接件162相同的材料形成。
圖11至圖18示出根據一些實施例的在將第一封裝組件100結合至第二封裝組件200的過程期間的中間步驟的剖視圖。圖中示出第一封裝區200A及第二封裝區200B,且在封裝區(第一封裝區200A及第二封裝區200B)中的每一者中形成有第二封裝件201(參見圖19)。
在圖11中,提供或製造第二封裝組件200。在圖中所示實施例中,在第一封裝組件100與第二封裝組件200中形成相同類型的封裝件。在一些實施例中,在第一封裝組件100與第二封裝組件200中形成不同類型的封裝件。在圖中所示實施例中,第一封裝組件100與第二封裝組件200均為積體扇出型(InFO)封裝。第二封裝組件200具有導電連接件166,導電連接件166與第
一封裝組件100的導電連接件162相似。
在圖12中,將第二封裝組件200對準第一封裝組件100。對第一封裝組件100及第二封裝組件200中的每一者中的相應的封裝區進行對準。舉例而言,將第一封裝區100A與第一封裝區200A對準,且將第二封裝區100B與第二封裝區200B對準。將第一封裝組件100與第二封裝組件200按壓在一起以使得第二封裝組件200的導電連接件166接觸第一封裝組件100的導電連接件164。
圖13至圖18示出一種回焊製程,所述回焊製程包括多次雷射照射以及對應多次雷射照射的多個回焊製程。圖13至圖18所示回焊製程因此被稱為多照射回焊製程。所述多次雷射照射是使用由雷射光束產生器54產生的雷射光束52執行。在所述多次雷射照射中的每一次雷射照射中,將雷射光束52投射於第二封裝組件200的頂表面的一個區上,以使得熱量被第二封裝組件200吸收且經由第二封裝組件200被導通至導電連接件164及166,進而使導電連接件164及166回焊以形成導電連接件168。雷射光束產生器54被配置成產生雷射光束52,且雷射光束52是自雷射光束產生器54的射極(emitter)發出。雷射光束52大於典型的雷射光束。舉例而言,雷射光束52可具有處於自約0.03×0.03平方毫米至約100×100平方毫米範圍內的大小。舉例而言,雷射光束產生器54被配置成將小的雷射光束放大至期望的較大的尺寸。另外,如圖15、圖16、圖17A、圖17B及圖17C中所示,雷射光束
52可覆蓋矩形區。雷射光束52的不同部分的能量實質上為均勻的,例如,在整個矩形區中具有小於約百分之十的變化。在所述多次雷射照射中的每一次雷射照射中,被雷射光束52覆蓋的導電連接件164與導電連接件166實質上同時回焊。
在圖13中,在第二封裝組件200的第一區40A處執行第一雷射照射52A。第一區40A包括第一封裝組件100及第二封裝組件200的直接位於第一雷射照射52A的投射路徑中的組件。根據一些實施例,第一區40A與第一封裝區200A(參見圖12)完全交疊,且較第一封裝區200A大。舉例而言,第一區40A亦與第二封裝區200B部分地交疊。當雷射光束52投射於第二封裝組件200的第一區40A上時,第一區40A被加熱,且熱量被傳遞至直接位於第一區40A下方的導電連接件164及166。第一雷射照射52A執行直至第一區40A中的導電連接件164及166熔化且回焊以形成導電連接件168。位於第一區40A外(例如,不位於雷射光束52的投射路徑中)的導電連接件164及166被加熱的程度較位於第一區40A內的導電連接件164及166小,且不會回焊。第一雷射照射52A的持續時間及單位功率(例如,每單位面積的功率)被控制成使得第一區40A外的大部分導電連接件164及166不熔化且因此不會回焊。因此,第一雷射照射52A的持續時間足夠長以將第一區40A內的導電連接件164及166熔化,且足夠短以使第一區40A外的至少大部分(或所有的)導電連接件164及166不會熔化。位於第一區40A外且靠近第一區40A的少數導電
連接件164及166亦可例如因製程變化或製程裕度(margin)增大而熔化。雷射光束52的單位功率亦被選擇成足夠高以使第一區40A內的導電連接件164及166熔化,且足夠低以使第一區40A外的導電連接件164及166不會熔化。在一些實施例中,雷射照射的持續時間處於自約2秒至約30秒的範圍內。單位功率可處於自約0.1瓦特/平方毫米至約0.7瓦特/平方毫米的範圍內。應理解,使導電連接件164及166熔化所需的時間長度及單位功率受多種因素影響,所述因素可包括單位功率、照射持續時間、第二封裝組件200的厚度、第二封裝組件200的材料及導熱性等。在一些實施例中,導電連接件164及166具有高於約200℃的熔化溫度,且可處於自約215℃至約230℃的範圍內。可對雷射照射的單位功率進行調整以獲得特定的加熱速率及峰值溫度。在實施例中,峰值溫度處於自約240℃至約250℃的範圍內,且加熱速率處於自約0.5℃/秒至約50℃/秒的範圍內。在第一區40A內的導電連接件164及166熔化後且在第一區40A外的導電連接件164及166熔化之前,結束第一雷射照射。
在第一雷射照射52A後,關閉雷射光束52,且雷射光束52停止投射於第二封裝組件200上。在第一雷射照射52A的結束時間與第二雷射照射52B(參見圖14)的開始時間之間,可採用延遲時間。在延遲期間,不執行雷射照射。延遲足夠長以使得經回焊的導電連接件168冷卻下來且固化。舉例而言,在延遲時間後,導電連接件168的溫度可降至自約100℃至約150℃的範圍
中。延遲時間可處於自約5秒至約30秒的範圍內。在一些實施例中,執行導電連接件168的冷卻,例如空氣冷卻。在該些實施例中,可對延遲時間進行調整以獲得特定的冷卻速率。在一些實施例中,延遲時間是預定時間段。在實施例中,冷卻速率大於約1℃/秒。
在圖14中,在第二封裝組件200的第二區40B處執行第二雷射照射52B。第二區40B包括第一封裝組件100及第二封裝組件200的直接位於第二雷射照射52B的投射路徑中的組件。因此,第二區40B中的導電連接件164及166被回焊。第二區40B外的大部分及所有的導電連接件164及166不會接受足夠的熱量,且不會熔化及不會回焊。位於第二區40B外且靠近第二區40B的少數導電連接件164及166亦可例如因製程變化或製程裕度增大而熔化。在一些實施例中,第一區40A與第二區40B在交疊區40AB中交疊。所得導電連接件168中的一些導電連接件168設置於交疊區40AB中。交疊區40AB中的導電連接件168回焊兩次:一次在第一雷射照射52A期間,且一次在第二雷射照射52B期間。交疊區40AB外的其他導電連接件168回焊一次。第一區40A與區40B交疊會確保即使當存在製程變化(例如,多次雷射照射中的一次雷射照射中的未對準)時,第一封裝區200A及第二封裝區200B(參見圖12)的全部仍被多次雷射照射覆蓋。由此,所有導電連接件164及166將會被回焊。
圖15示出多照射回焊製程的俯視圖。如圖中所示,第一
雷射照射52A及第二雷射照射52B各自覆蓋矩形區。被第一雷射照射52A及第二雷射照射52B覆蓋的矩形區可具有相同的大小及形狀。第一雷射照射52A與第二雷射照射52B的組合區充分覆蓋第一封裝區200A及第二封裝區200B。組合區可延伸超出第一封裝區200A的邊緣及第二封裝區200B的邊緣以提供足夠的製程裕度,以使得所有封裝區(第一封裝區200A及第二封裝區200B)皆被雷射照射覆蓋。如前文所述,交疊區40AB接受兩次雷射照射。交疊區40AB中的導電連接件168被回焊兩次。在一些實施例中,交疊區40AB具有處於自約1毫米至約5毫米範圍內的寬度W1。在此寬度W1內,可端視導電連接件168的節距及交疊的寬度W1而存在多行導電連接件168(例如,多於十行)。
多照射回焊製程在多次照射中的每一次照射中引起對第二封裝組件200的部分加熱,而非同時對第一封裝組件100及第二封裝組件200二者全部進行全域加熱。當之前的照射結束後執行雷射照射時,由之前的雷射照射造成的升高的溫度已降低。對第一封裝組件100及第二封裝組件200進行加熱會使晶圓翹曲,且翹曲的量值與加熱溫度有關。藉由執行更多的部分加熱,總體加熱溫度可降低,且第一封裝組件100及第二封裝組件200的翹曲可減小。另外,第一雷射照射52A及第二雷射照射52B投射於第二封裝組件200上,且第一封裝組件100直接接受極少量(若會接受的話)的雷射光束。因此,第一封裝組件100不會被顯著加熱,且對應的翹曲得到減小。
在圖13及圖14所示的實例中,第一區40A及第二區40B具有細長的俯視形狀。在一些實施例中,第二區40A及第二區40B具有其他形狀。舉例而言,圖16A示出具有形狀不那麼細長(例如,正方形)的多個區40的第二封裝組件200。區40可具有任何大小或形狀。在一些實施例中,區40是20毫米乘以20毫米的正方形。圖16B是圖16A的區的放大圖。圖16B所示區域可由包括六次雷射照射(第一雷射照射52A、第二雷射照射52B、第三雷射照射52C、第四雷射照射52D、第五雷射照射52E以及第六雷射照射52F)的多照射回焊製程加熱。第一雷射照射52A至第六雷射照射52F中的每一次雷射照射可交疊。因此,中心點42接受四次雷射照射。第一雷射照射52A至第六雷射照射52F的交疊區可呈組合形式交叉形狀。可根據需要將第一雷射照射52A至第六雷射照射52F的次序調整成任何次序。
圖17A、圖17B及圖17C示出根據一些實施例的各種雷射照射圖案。在圖17A中,在整個第二封裝組件200內以來回掃描的方式對第二封裝組件200的區40進行加熱。依序地對第二封裝組件200的每一列進行加熱,其中每一列是藉由沿所述行依序地加熱每一區40來進行加熱的。舉例而言,可沿圖17A中的箭頭44來對區40進行加熱。
在圖17B中,區40被劃分成若干群組。依序地對每一群組進行加熱,其中每一群組是藉由依序地加熱群組中的每一個區40來進行加熱的。舉例而言,在圖中所示實施例中,區40被劃分
成兩個群組:第一群組(包括區1至區9)以及第二群組(包括區A至區K)。依序地對第一群組中的區中的每一個區進行加熱。在對第一群組中的區進行加熱後,依序地對第二群組中的區中的每一個區進行加熱。在一些實施例中,在相同的加熱條件(例如,雷射光束52的相同的持續時間、單位功率等)下對第一群組與第二群組進行加熱。在一些實施例中,在不同的加熱條件(例如,雷射光束52的不同的持續時間、單位功率等)下對第一群組與第二群組進行加熱。
在圖17C中,僅對區40的子集進行加熱。舉例而言,可預先決定區40的自訂的形狀或圖案。僅對預先決定形狀的所選擇區46進行加熱,而不對其餘的區48進行加熱。未被加熱的區48可為其中未封裝有裝置的區,或者可為因雷射光束52的製程變化而被間接加熱的區。
圖18示出形成後的導電連接件168的剖視圖。導電連接件168包括導電連接件168A及168B。導電連接件168A是被回焊兩次(例如,位於交疊區40AB中)的連接件,且導電連接件168B是被回焊一次(例如,位於第一區40A或第二區40B中的一個區中)的連接件。在多照射回焊製程期間,形成金屬間化合物(inter-metallic compound;IMC)區170A及170B。金屬間化合物區170A及170B是由導電連接件168的材料以及分別為凸塊下金屬160的表面層的材料及金屬化圖案110的表面層的材料所形成的化合物。端視各種導電材料的結構及材料而定,金屬間化合
物區170A及170B可為焊料與鎳、銅、鈦、鈀、金、鋁或相似者所形成的化合物。對應的金屬間化合物區170A及170B藉由對應的導電連接件168沒有和金屬化圖案110及凸塊下金屬160化合的部分而彼此分開,且對應的金屬間化合物區170A及170B接觸對應的導電連接件168沒有和金屬化圖案110及凸塊下金屬160化合的部分。由於對導電連接件168A執行了兩次(或更多次)回焊製程,因此導電連接件168A的金屬間化合物區170A的厚度T1大於導電連接件168B的金屬間化合物區170A的厚度T2。T1:T2的比率大於1.0,且可處於自約1.2至約2.0的範圍內。根據本揭露的一些實施例,厚度T1處於自約7.2微米至約8微米的範圍內,且厚度T2處於自約4微米至約6微米的範圍內。相似地,導電連接件168A的金屬間化合物區170B的厚度T3大於導電連接件168B的金屬間化合物區170B的厚度T4。T3:T4的比率大於1.0,且可處於自約1.2至約2.0的範圍內。根據本揭露的一些實施例,厚度T3處於自約7.2微米至約8微米的範圍內,且厚度T4處於自約4微米至約6微米的範圍內。儘管論述了具體的厚度,然而應理解,金屬間化合物(例如,金屬間化合物區170A及170B)可具有變化的或不均勻的厚度。因此,此處所論述的金屬間化合物厚度可為平均厚度。
儘管在圖中將導電連接件168示出為連接金屬化圖案110與凸塊下金屬160,然而應理解,導電連接件168可用於連接至第一封裝組件100及第二封裝組件200的任何導電特徵。舉例而言,
在其中省略背面重佈線結構106的實施例中,導電連接件168亦可實體地連接至穿孔116。同樣地,例如在其中省略凸塊下金屬160的實施例中,導電連接件168可實體地連接至金屬化圖案156。
由於多照射回焊製程減少或避免了晶圓翹曲,因此第一封裝組件100與第二封裝組件200之間總體的距離D1在不同的封裝區中可更加一致。舉例而言,第一封裝組件100與第二封裝組件200的邊緣處的距離D1可能小於第一封裝組件100的中心與第二封裝組件200的中心處的距離D1。此外,距離D1可在第一封裝組件100及第二封裝組件200的直徑上變化小於5%。
具有較厚的金屬間化合物區170A及170B的導電連接件168A可被分配成在每一相應的封裝區(例如,第一封裝區200A及第二封裝區200B)中沿裝置封裝的邊緣延伸的條帶(strip)。在所得封裝中,可存在單一個交疊的條帶或彼此平行的多個交疊的條帶,且該些條帶受到多於一次(例如兩次或四次)雷射照射。
在完成多照射回焊製程後,可在清潔製程中對第一封裝組件100及第二封裝組件200進行清潔。清潔製程可為例如焊劑清潔,其幫助移除殘留材料。可使用熱水或清潔溶劑藉由沖刷、沖洗或浸泡來執行焊劑清潔。此外,可在第一封裝組件100與第二封裝組件200之間可選地注入底部填充物或包封體以環繞導電連接件168。
圖19示出根據一些實施例的在形成封裝結構300的過程期間的中間步驟的剖視圖。封裝結構300可被指代為疊層封裝
(PoP)結構。
藉由沿切割道區(例如,在第一封裝組件100的封裝區與第二封裝組件200的封裝區之間)進行鋸切來執行單體化製程。所述鋸切將相鄰的第一封裝區100A、第二封裝區100B、第一封裝區200A及第二封裝區200B自第一封裝組件100及第二封裝組件200單體化。所得的被單體化的第一封裝件101來自第一封裝區100A或第二封裝區100B中的一個封裝區,且所得的被單體化的第二封裝件201來自第一封裝區200A或第二封裝區200B中的一個封裝區。
接著使用導電連接件162將第一封裝件101及第二封裝件201安裝至封裝基底302。封裝基底302可由例如矽、鍺、金剛石等半導體材料製成。作為另外一種選擇,亦可使用例如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、磷化砷化鎵、磷化鎵銦、其組合等化合物材料。另外,封裝基底302可為絕緣層上半導體基底(SOI)。一般而言,絕緣層上半導體基底包括例如磊晶矽、鍺、矽鍺、絕緣層上矽(SOI)、絕緣層上矽鍺(SGOI)或其組合等半導體材料的層。在一個替代實施例中,封裝基底302是基於例如被纖維玻璃強化的樹脂芯體等絕緣芯體。一種示例性芯體材料是纖維玻璃樹脂(例如,FR4)。所述芯體材料的替代物包括雙馬來醯亞胺三嗪BT樹脂,或者作為另外一種選擇,為其他印刷電路板材料或膜。可對封裝基底302使用例如味之素構成膜(Ajinomoto Build up Film;ABF)等構成膜或其他疊層。
封裝基底302可包括主動裝置及被動裝置(圖中未示出)。如本領域中具有通常知識者將理解,可使用例如電晶體、電容器、電阻器、其組合等各種各樣的裝置來產生封裝結構300的設計的結構性要求及功能性要求。可使用任何適合的方法來形成所述裝置。
封裝基底302亦可包括金屬化層及通孔(圖中未示出)以及位於金屬化層及通孔上的結合墊304。金屬化層可形成於主動裝置及被動裝置上並被設計成連接各種裝置以形成功能性電路系統。金屬化層可由交替的介電層(例如,低介電常數(low-k)介電材料)與導電材料層(例如銅)形成且可藉由任何適合的製程(例如,沈積、鑲嵌、雙鑲嵌等)來形成,其中通孔對導電材料層進行內連。在一些實施例中,封裝基底302實質上不具有主動裝置及被動裝置。
在一些實施例中,使導電連接件162被回焊以將第一封裝件101貼合至結合墊304。導電連接件162將封裝基底302(包括封裝基底302中的金屬化層)電性地及/或實體地耦合至第一封裝件101。在一些實施例中,可將被動裝置(例如,表面安裝裝置(surface mount device;SMD),圖中未示出)在安裝於封裝基底302之前貼合至第一封裝件101(例如,結合至結合墊304)。在該些實施例中,可將被動裝置結合至第一封裝件101的與導電連接件162相同的表面。
在導電連接件162被回焊之前,導電連接件162上可能
形成有環氧樹脂焊劑(圖中未示出),其中環氧樹脂焊劑的至少一些環氧樹脂部分在第一封裝件101貼合至封裝基底302之後餘留下來。此一餘留的環氧樹脂部分可充當底部填充物以減小應力並保護因使導電連接件162被回焊而形成的接頭(joint)。在一些實施例中,可在第一封裝件101與封裝基底302之間且環繞導電連接件162形成底部填充物(圖中未示出)。底部填充物可在貼合第一封裝件101之後藉由毛細流動製程(capillary flow process)來形成或者可在貼合第一封裝件101之前藉由適合的沈積方法來形成。
本揭露的實施例可達成許多優點。藉由執行多照射回焊製程,第一封裝組件100及第二封裝組件200的翹曲可減少,且例如冷接頭(cold joint)及焊料橋接等缺陷可被消除。藉由選擇性地加熱第一封裝組件100及第二封裝組件200的一些區域,可在製造期間提供更多靈活性。藉由雷射加熱提供的較快的加熱亦可增大製造產出量。
一種製造封裝件的方法包括下列步驟。將第一封裝組件對準第二封裝組件,所述第一封裝組件具有第一區及第二區,所述第一區包括第一導電連接件,所述第二區包括第二導電連接件。對所述第一封裝組件的頂表面的第一部分執行第一雷射照射,所述第一雷射照射使所述第一區的所述第一導電連接件回焊,所述第一封裝組件的所述頂表面的所述第一部分與所述第一區完全交疊。在執行所述第一雷射照射後,對所述第一封裝組件
的所述頂表面的第二部分執行第二雷射照射,所述第二雷射照射使所述第二區的所述第二導電連接件回焊,所述第一封裝組件的所述頂表面的所述第二部分與所述第二區完全交疊。
在所述方法的一些實施例中,所述第一封裝組件的所述頂表面的所述第一部分與所述第二部分部分地交疊。在所述方法的一些實施例中,所述第一導電連接件被所述第二雷射照射加熱但不被所述第二雷射照射回焊。在所述方法的一些實施例中,執行所述第一雷射照射包括下列步驟。將雷射光束引導於所述第一封裝組件的所述頂表面的所述第一部分處,直至所述第一導電連接件回焊。以及在所述第一導電連接件回焊後,關閉所述雷射光束直至所述第一導電連接件固化。在所述方法的一些實施例中,執行所述第二雷射照射包括下述步驟。在所述第一導電連接件固化後,將所述雷射光束引導於所述第一封裝組件的所述頂表面的所述第二部分處,直至所述第二導電連接件回焊。在所述方法的一些實施例中,關閉所述雷射光束直至所述第一導電連接件固化包括關閉所述雷射光束達預定時間段,其中所述第一導電連接件在所述預定時間段期間固化。在所述方法的一些實施例中,所述第一導電連接件及所述第二導電連接件鄰近所述第一封裝組件的底表面設置,且其中在所述第一雷射照射及所述第二雷射照射期間熱量經由所述第一封裝組件傳遞至所述第一導電連接件及所述第二導電連接件。在所述方法的一些實施例中,使所述第一導電連接件及所述第二導電連接件回焊會將所述第一封裝組件結合至
所述第二封裝組件。在一些實施例中,所述方法更包括下述步驟。在所述第一封裝組件結合至所述第二封裝組件後,將所述第一區自所述第二區單體化以形成第一裝置封裝。在所述方法的一些實施例中,所述第一封裝組件的所述頂表面的所述第一部分與所述第二部分在第三區中交疊,所述第三區包括第三導電連接件,所述第一雷射照射及所述第二雷射照射二者使所述第三導電連接件回焊。
一種製造封裝件的方法包括下列步驟。提供第一封裝組件及第二封裝組件,所述第一封裝組件包括多個第一區,所述第二封裝組件包括多個第二區。將所述第一封裝組件的所述多個第一區對準所述第二封裝組件的所述多個第二區。對所述第一封裝組件的頂表面執行多次雷射照射,所述雷射照射中的每一者是依序地執行,所述雷射照射中的每一相應的雷射照射與所述多個第一區中的相應的第一區及所述多個第二區中的相應的第二區交疊,所述相應的第一區與所述相應的第二區之間的導電材料由所述相應的雷射照射回焊。在執行所述雷射照射後,將所述第一封裝組件的所述多個第一區及所述第二封裝組件的所述多個第二區單體化。
在所述方法的一些實施例中,執行所述多次雷射照射中的每一相應的雷射照射包括下列步驟。將雷射光束引導於所述第一封裝組件的所述相應的第一區處直至所述導電材料回焊,所述雷射光束產生的熱量經由所述第一封裝組件傳遞至所述導電材
料。在所述導電材料回焊後,關閉所述雷射光束直至所述導電材料冷卻。在所述方法的一些實施例中,所述多次雷射照射是以相同的單位功率(unit power)執行的。在所述方法的一些實施例中,所述多次雷射照射被執行相同的時間段。在所述方法的一些實施例中,所述多次雷射照射的第一子集是以第一單位功率執行且所述多次雷射照射的第二子集是以第二單位功率執行,所述第二單位功率不同於所述第一單位功率。在所述方法的一些實施例中,所述多次雷射照射的第一子集被執行第一時間段且所述多次雷射照射的第二子集被執行第二時間段,所述第二時間段不同於所述第一時間段。在所述方法的一些實施例中,所述多次雷射照射是對所述第一封裝組件的所有區依序地執行。在所述方法的一些實施例中,所述多次雷射照射是對所述第一封裝組件的多個區的子集執行。
一種封裝件包括第一封裝件、第二封裝件、第一導電連接件、第一金屬間化合物(inter-metallic compound;IMC)、第二導電連接件以及第二金屬間化合。第一封裝件包括第一導電特徵及第二導電特徵。第二封裝件包括第三導電特徵及第四導電特徵。第一導電連接件將所述第三導電特徵接合至所述第一導電特徵。第一金屬間化合物位於所述第一導電連接件與所述第一導電特徵之間,所述第一金屬間化合物具有第一厚度。第二導電連接件將所述第四導電特徵接合至所述第二導電特徵。第二金屬間化合物位於所述第二導電連接件與所述第二導電特徵之間,所述第
二金屬間化合物具有小於所述第一厚度的第二厚度。
在所述封裝件的一些實施例中,所述第一封裝件更包括重佈線結構、積體電路晶粒、包封體以及導通孔。重佈線結構包括所述第一導電特徵及所述第二導電特徵,所述第一導電特徵及所述第二導電特徵是重佈線(redistribution line)。積體電路晶粒位於所述重佈線結構上。包封體環繞所述積體電路晶粒。導通孔延伸穿過所述包封體,所述導通孔電性連接至所述積體電路晶粒及所述重佈線結構。
以上概述了若干實施例的特徵,以使熟習此項技術者可更佳地理解本揭露的各個態樣。熟習此項技術者應知,他們可容易地使用本揭露作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應認識到,該些等效構造並不背離本揭露的精神及範圍,而且他們可在不背離本揭露的精神及範圍的條件下對其作出各種改變、代替、及變更。
101:第一封裝件
162、168:導電連接件
201:第二封裝件
300:封裝結構
302:封裝基底
304:結合墊
Claims (10)
- 一種製造封裝件的方法,包括:將第一封裝組件對準第二封裝組件,所述第一封裝組件具有第一區及第二區,所述第一區包括第一導電連接件,所述第二區包括第二導電連接件;對所述第一封裝組件的頂表面的第一部分執行第一雷射照射,所述第一雷射照射使所述第一區的所述第一導電連接件回焊,所述第一封裝組件的所述頂表面的所述第一部分與所述第一區完全交疊;以及在執行所述第一雷射照射後,對所述第一封裝組件的所述頂表面的第二部分執行第二雷射照射,所述第二雷射照射使所述第二區的所述第二導電連接件回焊,所述第一封裝組件的所述頂表面的所述第二部分與所述第二區完全交疊,且所述第一封裝組件的頂表面的所述第一部分與所述第二部分彼此僅部分交疊。
- 如申請專利範圍第1項所述的方法,其中執行所述第一雷射照射包括:將雷射光束引導於所述第一封裝組件的所述頂表面的所述第一部分處,直至所述第一導電連接件回焊;以及在所述第一導電連接件回焊後,關閉所述雷射光束直至所述第一導電連接件固化。
- 如申請專利範圍第2項所述的方法,其中執行所述第二 雷射照射包括:在所述第一導電連接件固化後,將所述雷射光束引導於所述第一封裝組件的所述頂表面的所述第二部分處,直至所述第二導電連接件回焊。
- 如申請專利範圍第1項所述的方法,其中所述第一封裝組件的所述頂表面的所述第一部分與所述第二部分在第三區中交疊,所述第三區包括第三導電連接件,所述第一雷射照射及所述第二雷射照射二者使所述第三導電連接件回焊。
- 一種製造封裝件的方法,包括:提供第一封裝組件及第二封裝組件,所述第一封裝組件包括多個第一區,所述第二封裝組件包括多個第二區;將所述第一封裝組件的所述多個第一區對準所述第二封裝組件的所述多個第二區;對所述第一封裝組件的頂表面執行多次雷射照射,所述多次雷射照射中的每一者是依序地執行,所述多次雷射照射中的每一相應的雷射照射與所述多個第一區中的相應的第一區及所述多個第二區中的相應的第二區交疊,所述相應的第一區與所述相應的第二區之間的導電材料由所述相應的雷射照射回焊;以及在執行所述雷射照射後,將所述第一封裝組件的所述多個第一區及所述第二封裝組件的所述多個第二區單體化。
- 如申請專利範圍第5項所述的方法,其中執行所述多次 雷射照射中的每一相應的雷射照射,包括:將雷射光束引導於所述第一封裝組件的所述相應的第一區直至所述導電材料回焊,所述雷射光束產生的熱量經由所述第一封裝組件傳遞至所述導電材料;以及在所述導電材料回焊後,關閉所述雷射光束直至所述導電材料冷卻。
- 如申請專利範圍第6項所述的方法,其中所述多次雷射照射是以相同的單位功率(unit power)執行的,且所述多次雷射照射被執行相同的時間段。
- 如申請專利範圍第6項所述的方法,其中所述多次雷射照射的第一子集是以第一單位功率執行且所述多次雷射照射的第二子集是以第二單位功率執行,所述第二單位功率不同於所述第一單位功率。
- 如申請專利範圍第6項所述的方法,其中所述多次雷射照射的第一子集被執行第一時間段且所述多次雷射照射的第二子集被執行第二時間段,所述第二時間段不同於所述第一時間段。
- 一種封裝件,包括:第一封裝件,包括第一導電特徵及第二導電特徵;第二封裝件,包括第三導電特徵及第四導電特徵;第一導電連接件,將所述第三導電特徵接合至所述第一導電特徵; 第一金屬間化合物(inter-metallic compound;IMC),位於所述第一導電連接件與所述第一導電特徵之間,所述第一金屬間化合物具有第一厚度;第二導電連接件,將所述第四導電特徵接合至所述第二導電特徵;以及第二金屬間化合物,位於所述第二導電連接件與所述第二導電特徵之間,所述第二金屬間化合物具有小於所述第一厚度的第二厚度,且所述第一厚度與所述第二厚度的比率處於自1.2至1.8的範圍內。
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US16/148,465 US11069671B2 (en) | 2018-03-23 | 2018-10-01 | Semiconductor package and method |
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- 2018-10-01 US US16/148,465 patent/US11069671B2/en active Active
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- 2019-01-07 KR KR1020190001626A patent/KR102257456B1/ko active IP Right Grant
- 2019-02-11 TW TW108104409A patent/TWI712115B/zh active
- 2019-02-27 CN CN202110275797.6A patent/CN113113318A/zh active Pending
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Also Published As
Publication number | Publication date |
---|---|
US11942464B2 (en) | 2024-03-26 |
CN110299326A (zh) | 2019-10-01 |
CN110299326B (zh) | 2021-03-09 |
KR20190111735A (ko) | 2019-10-02 |
KR102257456B1 (ko) | 2021-06-01 |
US20190296002A1 (en) | 2019-09-26 |
US11069671B2 (en) | 2021-07-20 |
US20210351172A1 (en) | 2021-11-11 |
TW201941376A (zh) | 2019-10-16 |
CN113113318A (zh) | 2021-07-13 |
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