TWI559829B - 封裝結構及其製法 - Google Patents

封裝結構及其製法 Download PDF

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TWI559829B
TWI559829B TW103136417A TW103136417A TWI559829B TW I559829 B TWI559829 B TW I559829B TW 103136417 A TW103136417 A TW 103136417A TW 103136417 A TW103136417 A TW 103136417A TW I559829 B TWI559829 B TW I559829B
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Taiwan
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protective layer
insulating protective
package structure
layer
dielectric body
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TW103136417A
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TW201616933A (zh
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白裕呈
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矽品精密工業股份有限公司
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Priority to TW103136417A priority Critical patent/TWI559829B/zh
Priority to CN201410603698.6A priority patent/CN105633052B/zh
Priority to US14/833,103 priority patent/US20160118323A1/en
Publication of TW201616933A publication Critical patent/TW201616933A/zh
Application granted granted Critical
Publication of TWI559829B publication Critical patent/TWI559829B/zh
Priority to US15/440,390 priority patent/US10147615B2/en

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Description

封裝結構及其製法
本發明係有關一種封裝結構及其製法，尤指一種供半導體封裝之線路封裝結構及其製法。
隨著電子產業的蓬勃發展，許多高階電子產品都逐漸朝往輕、薄、短、小等高集積度方向發展，且隨著封裝技術之演進，晶片的封裝技術也越來越多樣化，半導體封裝件之尺寸或體積亦隨之不斷縮小，藉以使該半導體封裝件達到輕薄短小之目的。
一般封裝結構的製法係如第1A至1F圖所示者係習知之封裝結構之製法的剖視圖。
如第1A圖所示，於一載板10上形成線路層11。
再於部分該線路層11上形成導電柱13，如第1B圖所示。
接著，形成具有相對之第一表面12a與第二表面12b之介電體12，使該導電柱13與線路層11嵌埋於其中，如第1C圖所示。
如第1D圖所示，移除部份該載板10，並保留部分該 載板10’以作為支撐之用，並於該介電體12之第一表面12a上設置並電性連接半導體元件40。
如第1E至1F圖所示，以模具90於由該介電體12之第一表面12a與該模具90所構成之容置空間900中灌注封裝膠體42，而得到如第1F圖之經封裝的習知封裝結構1。
上述封裝結構之製法中未避免在溫度較高的製程中，該封裝結構發生翹曲因而藉由所保留的部分該載板10’作為支撐。
然而，通常而言，該載板10’(如，鋼板)因加工方式的限制，厚度最低僅能達到200微米(μm)，即便將模具90的模穴拉成與該載板10’齊平，如第1E’圖所示，所形成之封裝膠體42之厚度h1仍無法突破200微米厚度的限制，遂使整體封裝結構的厚度難以降低。
隨著電子產業朝輕、薄、短、小的方向發展，此結構也無法。因此，需要予以改善。
但隨著電子產品微小化的需求增加，習知封裝結構顯然無法符合電子元件輕薄短小的發展趨勢，因此，如何在不增加製程的複雜度，即能得到厚度更薄的封裝結構，實為業界迫切待開發之方向。
鑒於上述習知技術之缺失，本發明提供一種封裝結構之製法，係包括：於一載板上形成第一絕緣保護層；於該第一絕緣保護層上形成具有相對之第一表面與第二表面之介電體，且該介電體以其第一表面形成於該第一絕緣保護 層上，該介電體中係嵌埋有線路層與形成於該線路層上之複數導電柱；於該介電體之第二表面形成第二絕緣保護層，其中，該第一絕緣保護層之玻璃轉移溫度及/或該第二絕緣保護層之玻璃轉移溫度係大於250℃；以及移除該載板。
本發明復提供一種封裝結構，係包括：介電體，係具有相對之第一表面與第二表面；線路層，係嵌埋於該介電體中；複數導電柱，係嵌埋於該介電體中並形成於該線路層上；第一絕緣保護層，係形成於該介電體之第一表面上；以及第二絕緣保護層，係形成於該介電體之第二表面上，其中，該第一絕緣保護層之玻璃轉移溫度及/或該第二絕緣保護層之玻璃轉移溫度係大於250℃。
於本發明之封裝結構及其製法中，該導電柱外露於該介電體之第二表面。其中，該第一絕緣保護層復包括複數外露出該線路層之第一開口；該第二絕緣保護層復包括複數外露出該導電柱端面之第二開口。復包括在外露於各該第一開口之部分該線路層上形成複數導電凸塊，該導電凸塊之高度係為50微米。
於本發明之封裝結構及其製法中，復包括於該第一絕緣保護層上設置半導體元件，該半導體元件係電性連接至該線路層。復包括於該第一絕緣保護層上形成封裝膠體，使該封裝膠體包覆該半導體元件。
於前述本發明之封裝結構及其製法中，該封裝膠體之厚度係介於20至180微米。
於本發明之封裝結構及其製法中，該第一絕緣保護層 之厚度及/或該第二絕緣保護層之厚度係介於1至20微米。
於本發明之封裝結構及其製法中，該第一絕緣保護層之玻璃轉移溫度及/或該第二絕緣保護層之玻璃轉移溫度係大於400℃。
於本發明之封裝結構及其製法中，形成該第一絕緣保護層及/或該第二絕緣保護層之材質係選自聚醯亞胺、聚醯胺醯亞胺、或聚苯咪唑。
由上可知，本發明藉由使用玻璃轉移溫度較高的第一絕緣保護層及/或第二絕緣保護層，得以在不需保留部分該載板作為支撐的情況下，即能防止封裝結構發生翹曲之問題。
此外，本案之第一絕緣保護層與第二絕緣保護層更可做為絕緣保護線路之用，亦不會額外增加整體封裝之厚度，得以使後續設置半導體元件時，用以嵌埋該半導體元件的封裝膠體之厚度低於200微米，因此得以降低整體封裝結構的厚度，進而應用於厚度較小之電子產品。
1、3、3’、4、4’、4”‧‧‧封裝結構
10、10’、20‧‧‧載板
11、31‧‧‧線路層
12、32‧‧‧介電體
12a、32a‧‧‧第一表面
12b、32b‧‧‧第二表面
13、33‧‧‧導電柱
21‧‧‧晶種層
30‧‧‧第一絕緣保護層
30a‧‧‧第一開口
33a‧‧‧端面
34‧‧‧第二絕緣保護層
34a‧‧‧第二開口
37、37’‧‧‧表面處理層
40‧‧‧半導體元件
41、41’‧‧‧導電凸塊
42‧‧‧封裝膠體
90‧‧‧模具
900‧‧‧容置空間
h1、h2‧‧‧厚度
t‧‧‧高度
第1A至1F圖係為習知封裝結構之製法的示意圖，其中，第1E’係為第1E圖之習知封裝結構的另一實施態樣；以及第2A至2E”圖係顯示本發明封裝結構之製法的示意圖，其中，第2A’係為第2A圖之另一實施態樣，第2B’圖係第2B圖之另一實施態樣，第2D’係為第2D圖之另一實施態樣，第2E’係為第2E圖之另一實施態樣，以及第2E” 係為第2E圖之再一實施態樣。
以下係藉由特定的具體實例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點與功效。本發明亦可藉由其他不同的具體實例加以施行或應用，本說明書中的各項細節亦可基於不同觀點與應用，在不悖離本發明之精神下進行各種修飾與變更。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本創作可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本創作所能產生之功效及所能達成之目的下，均應仍落在本創作所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「第一」、「第二」、「端面」等之用語，亦僅為便於敘述之明瞭，而非用以限定本創作可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本創作可實施之範疇。
請參閱第2A至2E圖係顯示本發明封裝結構之製法的剖視圖。
如第2A圖所示，於一載板20上形成第一絕緣保護層30。
於本實施例中，係以表面形成有金屬層(例如，銅)的承載板(如，鋼板、矽板、玻璃承載板)作為載板20。
再者，該第一絕緣保護層30之玻璃轉移溫度(glass transition temperature，簡稱TG)大於250℃，較佳係大於400℃。
又，形成該第一絕緣保護層30之材質係選自聚醯亞胺(polyimide，簡稱PI)、聚醯胺醯亞胺(polyamide-imide，簡稱PAI)或聚苯咪唑(polybenzimidazole，簡稱PBI)。
另外，於其它實施例中，該第一絕緣保護層30上復可形成有晶種層(seed layer)21，以用於後續電鍍線路之用，如第2A’圖所示，其中，對於該晶種層21之材質並未有特殊限制，僅需為可被蝕刻圖案化之金屬即可。
如第2B圖所示，於該第一絕緣保護層30上形成具有相對之第一表面32a與第二表面32b之介電體32，該介電體32係嵌埋有線路層31與形成於該線路層31上之複數導電柱33，且該導電柱33之端面33a係外露於該第二表面32b。
於本實施例中，對於該介電體32、線路層31與導電柱33之設置順序並未有特殊限制，於本實施例中係先於該第一絕緣保護層30上形成線路層31，並於部分該線路層31上形成導電柱33，再形成介電材料於該第一絕緣保護層30上使該等線路層31與導電柱33嵌埋於該介電體32中。
再者，對於形成該介電體32之材質並未有特殊限制，係包括模壓樹脂(molding compound)、預浸材(prepreg)或感光型介電層(photodielectric)。或者，形成該介電體32之材質亦可使用與該第一絕緣層30相同的材質形成。
又，對於該導電柱33的形狀並未有特殊限制，可為圓柱體、橢圓柱體或多邊形柱體皆可。
此外，倘若係延續如第2A’圖之製程，該線路層31係形成於該晶種層21上，如第2B’圖所示。
如第2C圖所示，於該介電體30之第二表面30b形成第二絕緣保護層34。
於本實施例中，該第二絕緣保護層34之玻璃轉移溫度係大於250℃，更佳係大於400℃。
再者，形成該第二絕緣保護層34之材質係選自聚醯亞胺(PI)、聚醯胺醯亞胺(PAI)或聚苯咪唑(PBI)。
如第2D圖所示，係接續第2C圖之製程，移除該載板20，以外露出整該第一絕緣保護層30。接著，於該第一絕緣保護層30與該第二絕緣保護層34上分別形成用以外露出該線路層31與導電柱33之複數第一開口30a與複數第二開口34a。之後並進行切單製程得到本發明之封裝結構3。
於本實施例中，可於該線路層31與該導電柱33上分別形成表面處理層37,37’。其中，形成該表面處理層37,37’之材質係為鎳、鈀、金所組群組之合金或有機保銲層(Organic Solderability Preservatives，簡稱OSP)。
再者，若接續第2B’圖之製程，該表面處理層37將形成於該線路層31之晶種層21之表面上，如第2D’圖所示的封裝結構3’。
於本發明之封裝結構3中，係藉由該第一絕緣保護層 30之玻璃轉移溫度及/或該第二絕緣保護層34之玻璃轉移溫度大於250℃，使後續製程中不需保留載板20作為支撐，即能藉由該第一絕緣保護層30及/或該第二絕緣保護層34提供本發明之封裝結構3不易脆裂、於高溫製程中不具有流動性之良好地結構剛性。
於後續製程中，如第2E圖所示，於該第一絕緣保護層30上可設置半導體元件40，該半導體元件40係電性連接至該線路層31，且於該第一絕緣保護層30上形成封裝膠體42，以包覆該半導體元件40。具體地，形成複數如銲錫材料之導電凸塊41於外露於各該第一開口30a之部分該線路層31上，使該半導體元件40藉由該些導電凸塊41電性連接至該線路層31。
於本實施例中，該封裝膠體42之玻璃轉移溫度係小於該第一絕緣保護層30之玻璃轉移溫度或該第二絕緣保護層34之玻璃轉移溫度。
再者，第2E’圖係接續第2D’圖之製程。
又，如第2E”圖所示，該導電凸塊41’係包含銅柱與銲錫材料。
另外，該封裝膠體42之厚度h2係介於20至180微米，且該導電凸塊41之高度t係為50微米。
於本發明之封裝結構4,4’,4”中，由於該第一絕緣保護層30之玻璃轉移溫度及/或該第二絕緣保護層34之玻璃轉移溫度大於250℃，故不需保留載板20作為支撐，因此該封裝膠體42的厚度h2能介於20至180微米。
本發明提供一種封裝結構3,3’,4,4’,4”，係包括：一介電體32、一線路層31、複數導電柱33、一第一絕緣保護層30以及一第二絕緣保護層34。
所述之介電體32係具有相對之第一表面32a與第二表面32b。
所述之線路層31係嵌埋於該介電體32中。
所述之複數導電柱33係嵌埋於該介電體32中並形成於該線路層31上。
所述之第一絕緣保護層30係形成於該介電體32之第一表面32a上，所述之第二絕緣保護層34係形成於該介電體32之第二表面32b上，該第一絕緣保護層30及/或該第二絕緣保護層34之厚度係介於1至20微米。其中，該第一絕緣保護層30之玻璃轉移溫度及/或該第二絕緣保護層34之玻璃轉移溫度係大於250℃。
於一實施例中，該導電柱33外露於該介電體32之第二表面32b。該第一絕緣保護層30復包括外露出該線路層31之第一開口30a，該第二絕緣保護層34復包括外露出該導電柱33之第二開口34a。復包括複數導電凸塊41,41’，係對應形成於各該第一開口30a中之該線路層31上。其中，該導電凸塊41,41’之高度t係為50微米。
於一實施例中，復包括於該第一絕緣保護層30上設置半導體元件40，該半導體元件40係電性連接至該線路層31。復包括於該第一絕緣保護層30上形成封裝膠體42，使該封裝膠體42包覆該半導體元件40，且該封裝膠體42 的厚度h2係介於20至180微米。
於一實施例中，該第一絕緣保護層30之玻璃轉移溫度及/或該第二絕緣保護層34之玻璃轉移溫度係大於400℃。
於一實施例中，形成該第一絕緣保護層30及/或該第二絕緣保護層34之材質係選自聚醯亞胺、聚醯胺醯亞胺、或聚苯咪唑。
由上可知，於本發明藉由使用玻璃轉移溫度較高的第一絕緣保護層及/或第二絕緣保護層，得以在不需保留部分該載板作為支撐的情況下，即能防止封裝結構發生翹曲之問題。
再者，由於本發明之第一絕緣保護層及/或第二絕緣保護層具有較高的玻璃轉移溫度，因此於進行高溫且時間較長的迴銲製程(如，紅外線迴銲製程(IR reflow))時，不會發生軟化的現象、變形量小、不易產生位移，相較於習知封裝結構本發明之封裝結構更具有對位精準度高之功效。
此外，本案之第一絕緣保護層與第二絕緣保護層更可做為絕緣保護線路之用，亦不會額外增加整體封裝結構之厚度，得以使後續設置半導體元件時，用以嵌埋該半導體元件的封裝膠體之厚度低於200微米(μm)，因此得以降低整體封裝結構的厚度，進而應用於厚度較小之電子產品。
上述實施例僅例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修飾與改變。因此，本發明之權利保護範圍，應如後述之申請專利 範圍所列。
3‧‧‧封裝結構
30‧‧‧第一絕緣保護層
30a‧‧‧第一開口
31‧‧‧線路層
32‧‧‧介電體
32a‧‧‧第一表面
32b‧‧‧第二表面
33‧‧‧導電柱
34‧‧‧第二絕緣保護層
34a‧‧‧第二開口
37、37’‧‧‧表面處理層

Claims (22)

  1. 一種封裝結構之製法，係包括：於一載板上形成第一絕緣保護層；於該第一絕緣保護層上形成具有相對之第一表面與第二表面之介電體，且該介電體以其第一表面形成於該第一絕緣保護層上，該介電體中係嵌埋有線路層與形成於該線路層上之複數導電柱；於該介電體之第二表面形成第二絕緣保護層，其中，該第一絕緣保護層之玻璃轉移溫度及/或該第二絕緣保護層之玻璃轉移溫度係大於250℃；以及移除該載板。
  2. 如申請專利範圍第1項所述之封裝結構之製法，其中，該導電柱外露於該介電體之第二表面。
  3. 如申請專利範圍第2項所述之封裝結構之製法，復包括於該第一絕緣保護層形成外露出該線路層之第一開口，於該第二絕緣保護層形成外露出該導電柱之第二開口。
  4. 如申請專利範圍第3項所述之封裝結構之製法，復包括在外露於各該第一開口之部分該線路層上形成複數導電凸塊。
  5. 如申請專利範圍第4項所述之封裝結構之製法，其中，該導電凸塊之高度係為50微米。
  6. 如申請專利範圍第1項所述之封裝結構之製法，復包括於該第一絕緣保護層上設置半導體元件，該半導體 元件係電性連接至該線路層。
  7. 如申請專利範圍第6項所述之封裝結構之製法，復包括於該第一絕緣保護層上形成封裝膠體，使該封裝膠體包覆該半導體元件。
  8. 如申請專利範圍第7項所述之封裝結構之製法，其中，該封裝膠體之厚度係為20至180微米。
  9. 如申請專利範圍第1項所述之封裝結構之製法，其中，該第一絕緣保護層之厚度或該第二絕緣保護層之厚度係介於1至20微米。
  10. 如申請專利範圍第1項所述之封裝結構之製法，其中，該第一絕緣保護層之玻璃轉移溫度及/或該第二絕緣保護層之玻璃轉移溫度係大於400℃。
  11. 如申請專利範圍第1項所述之封裝結構之製法，其中，形成該第一絕緣保護層及/或該第二絕緣保護層之材質係選自聚醯亞胺、聚醯胺醯亞胺、或聚苯咪唑。
  12. 一種封裝結構，係包括：介電體，係具有相對之第一表面與第二表面；線路層，係嵌埋於該介電體中；複數導電柱，係嵌埋於該介電體中並形成於該線路層上；第一絕緣保護層，係形成於該介電體之第一表面上且未嵌入該介電體中；以及第二絕緣保護層，係形成於該介電體之第二表面上，其中，該第一絕緣保護層之玻璃轉移溫度及/或該 第二絕緣保護層之玻璃轉移溫度係大於250℃。
  13. 如申請專利範圍第12項所述之封裝結構，其中，該導電柱外露於該介電體之第二表面。
  14. 如申請專利範圍第13項所述之封裝結構，其中，該第一絕緣保護層復包括複數外露出該線路層之第一開口；該第二絕緣保護層復包括複數外露出該導電柱之第二開口。
  15. 如申請專利範圍第14項所述之封裝結構，復包括複數導電凸塊，各該導電凸塊係對應形成於各該第一開口中之該線路層上。
  16. 如申請專利範圍第15項所述之封裝結構，其中，該導電凸塊之高度係為50微米。
  17. 如申請專利範圍第12項所述之封裝結構，復包括設於該第一絕緣保護層上之半導體元件，其電性連接至該線路層。
  18. 如申請專利範圍第17項所述之封裝結構，復包括形成於該第一絕緣保護層上之封裝膠體，其包覆該半導體元件。
  19. 如申請專利範圍第18項所述之封裝結構，其中，該封裝膠體之厚度係介於20至180微米。
  20. 如申請專利範圍第12項所述之封裝結構，其中，該第一絕緣保護層之厚度或該第二絕緣保護層之厚度係介於1至20微米。
  21. 如申請專利範圍第12項所述之封裝結構，其中，該第 一絕緣保護層之玻璃轉移溫度及/或該第二絕緣保護層之玻璃轉移溫度係大於400℃。
  22. 如申請專利範圍第12項所述之封裝結構，其中，形成該第一絕緣保護層及/或該第二絕緣保護層之材質係選自聚醯亞胺、聚醯胺醯亞胺、或聚苯咪唑。
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