CN105990268B - 电子封装结构及其制法 - Google Patents

电子封装结构及其制法 Download PDF

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CN105990268B
CN105990268B CN201510095684.2A CN201510095684A CN105990268B CN 105990268 B CN105990268 B CN 105990268B CN 201510095684 A CN201510095684 A CN 201510095684A CN 105990268 B CN105990268 B CN 105990268B
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insulating layer
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白裕呈
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Siliconware Precision Industries Co Ltd
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Abstract

一种电子封装结构及其制法，该制法先形成线路层于导体件上；设置电子元件于该线路层上；形成绝缘层于该导体件上以包覆该电子元件与该线路层；以及移除部分该导体件，使该导体件成为多个导电凸块，所以当该电子封装结构以表面粘着技术(SMT)设于电路板上时，该些导电凸块容易对位于该电路板上的接点，因而能有效降低SMT制程的不良率。

Description

电子封装结构及其制法
技术领域
本发明涉及一种封装技术，尤指一种电子封装结构的制法。
背景技术
随着电子产业的蓬勃发展，电子产品也逐渐迈向多功能、高性能的趋势。为了满足半导体封装件微型化(miniaturization)的封装需求，所以朝着降低承载晶片的封装基板的厚度发展。
图1A至图1D为现有无核心层(coreless)的半导体封装件1的制法的剖视示意图。
如图1A所示，形成一线路层11于一载板10上，其中，该线路层11包含一置晶垫111与多个电性连接垫112，该些该电性连接垫112围绕该置晶垫111。
如图1B所示，将一半导体晶片12接置于该线路层11的置晶垫111上，并利用多个焊线120电性连接该半导体晶片12与该线路层11的电性连接垫112。之后，形成用于包覆该半导体晶片12与该些焊线120的绝缘层13。
如图1C所示，移除该载板10，以外露出该线路层11与该绝缘层13底部。
如图1D所示，形成一表面处理层14于该线路层11的外露表面上，再形成一绝缘保护层15于该绝缘层11底部，且令该表面处理层14外露于该绝缘保护层15。之后，形成多个如焊球的导电元件16于该表面处理层14上，并进行切单作业。
惟，于现有半导体封装件1的制法中，该线路层11的外露表面齐平该该绝缘层13底部，所以当该半导体封装件1以表面粘着技术(Surface Mounting Technology，简称SMT)设于电路板上时，该些线路层11上的导电元件16不易对位于该电路板上的接点，导致SMT制程的不良率提高。
因此，如何克服上述现有技术的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺失，本发明提供一种电子封装结构及其制法，能有效降低SMT制程的不良率。
本发明的电子封装结构，包括：绝缘层，其具有相对的第一表面与第二表面；线路层，其自该第二表面嵌埋于该绝缘层中；至少一电子元件，其埋设于该绝缘层中并设于该线路层上，且该电子元件电性连接至该线路层；以及多个导电凸块，其设于该线路层上并外露出该绝缘层的第二表面。
本发明还提供一种电子封装结构的制法，其包括：形成线路层于一导体件上；设置至少一电子元件于该线路层上，且令该电子元件电性连接该线路层；形成绝缘层于该导体件上，以令该绝缘层包覆该电子元件与该线路层，其中，该绝缘层具有相对的第一表面与第二表面，且该绝缘层以其第二表面结合至该导体件上；以及移除部分该导体件，使该导体件的保留部分成为多个导电凸块，且外露出该绝缘层的第二表面。
前述的电子封装结构及其制法中，该导电凸块自该绝缘层的第二表面凸出。
前述的电子封装结构及其制法中，该导电凸块的位置未对齐该电性连接垫的位置。
前述的电子封装结构及其制法中，还包括于设置该电子元件前，形成表面处理层于该线路层上。
前述的电子封装结构及其制法中，还包括于设置该电子元件前，形成表面处理层于该导体件上，以于移除部分该导体件后，该表面处理层位于该导电凸块上。
前述的电子封装结构及其制法中，还包括于移除部分该导体件后，形成表面处理层于该导电凸块上。
前述的电子封装结构及其制法中，还包括于移除部分该导体件后，形成绝缘保护层于该绝缘层的第二表面上，且令该些导电凸块外露于该绝缘保护层。
另外，前述的电子封装结构及其制法中，还包括于形成该线路层前，将该导体件覆盖于一止蚀层上，以于移除部分该导体件后，该止蚀层位于该导电凸块上。
由上可知，本发明的电子封装结构及其制法中，主要藉由移除部分该导体件，使该导体件成为多个导电凸块，所以相较于现有技术，当该电子封装结构以表面粘着技术(SMT)设于电路板上时，该些导电凸块上的导电元件容易对位于该电路板上的接点，因而能有效降低SMT制程的不良率。
附图说明
图1A至图1D为现有无核心层的半导体封装件的制法的剖视示意图；
图2A至图2F为本发明的电子封装结构的第一实施例的制法的剖视示意图；其中，图2E’至图2F’为图2E至图2F的另一方式；
图3A至图3F为本发明的电子封装结构的第二实施例的制法的剖视示意图；以及
图4本发明的电子封装结构的线路层的上视图。
符号说明
1 半导体封装件
10 载板
11,21 线路层
111,210 置晶垫
112,211,412 电性连接垫
12 半导体晶片
120,220 焊线
13,23 绝缘层
14,24 表面处理层
15,25 绝缘保护层
16 导电元件
2,2’,3 电子封装结构
20 导体件
20’,20” 导电凸块
20a,30a 上侧
20b,30b 下侧
200 水平部
201 直立部
22 电子元件
23a 第一表面
23b 第二表面
30 承载件
36 止蚀层
410 导电迹线
S 切割路径。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用于配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用于限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“下”、“底”、“第一”、“第二”及“一”等用语，也仅为便于叙述的明了，而非用于限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2F为本发明的电子封装结构2的第一实施例的制法的剖视示意图。
如图2A所示，提供一具有上侧20a与下侧20b的导体件20。于本实施例中，该导体件20为铜箔，但不限于此。
如图2B所示，以电镀或沉积铜材方式形成一线路层21于该导体件20的上侧20a上。
于本实施例中，该线路层21具有至少一置晶垫210与多个电性连接垫211。
于其它实施例中，该线路层21的布设可如图4所示。具体地，该线路层21包含多个围绕该置晶垫210的导电迹线410、一置晶垫210与多个电性连接垫211,412，该导电迹线410可依需求蜿蜒而呈现出多变及复杂的图形，且部分该电性连接垫211围绕该置晶垫210，而部分该电性连接垫412位于该导电迹线410的外端。
如图2C所示，形成一表面处理层24于该线路层21的电性连接垫211与该导体件20的下侧20b的部分表面上。
于本实施例中，该表面处理层24为有机保焊膜(Organic SolderabilityPreservatives，简称OSP)、镍、钯、金或银层等。
此外，于形成该表面处理层24前，可先形成一阻障层(图略)于该线路层21上，以避免该表面处理层24的金材与线路层21的铜材之间产生迁移(Migration)或扩散(Diffusion)效应。
如图2D所示，设置至少一电子元件22于该线路层21的置晶垫210上，且令该电子元件22电性连接该线路层21的电性连接垫211。接着，形成一绝缘层23于该导体件20的上侧20a与该线路层21上，以令该绝缘层23包覆该电子元件22。
于本实施例中，该电子元件22藉由打线(即多个如金线的焊线220)电性连接该些电性连接垫211，且该绝缘层23包覆该些焊线220。
此外，该电子元件22为主动元件、被动元件或其组合者，且该主动元件为例如半导体晶片，而该被动元件为例如电阻、电容及电感。于此，该电子元件22为主动元件。
又，该绝缘层23为模压(molding)制程制作的封装胶体，且该绝缘层23具有相对的第一表面23a与第二表面23b，并以该第二表面23b结合至该导体件20的上侧20a上。
另外，于其它实施例中，该电子元件22也可藉由多个如焊球的导电凸块(图略)电性连接该些电性连接垫211，所以于形成该绝缘层23后，可透过研磨该绝缘层23，使该电子元件22的背面外露于该绝缘层23的第一表面23a，以供散热之用。
如图2E所示，移除部分该导体件20，使该导体件20的保留部分成为多个导电凸块20’，且令该绝缘层23的第二表面23b外露。
于本实施例中，该导电凸块20’自该绝缘层23的第二表面23b凸出。
此外，以蚀刻方式移除部分该导体件20，所以该绝缘层23的第二表面23b会呈凹状，且该表面处理层24可作为蚀刻用的阻层，即保留该表面处理层24所覆盖的导体件20材质，以作为该些导电凸块20’，使该表面处理层24位于该导电凸块20’的端面上。
又，于另一实施例中，也可于移除部分该导体件20后，再形成该表面处理层24于该导电凸块20’上，所以于移除部分该导体件20前，需先形成蚀刻用的阻层(图略)。
另外，如图2E’所示，也可以半蚀刻(half etch)方式移除该导体件20，使该导电凸块20”位于该线路层21的外端，即该导电凸块20”的位置未对齐该电性连接垫211的位置。
如图2F所示，接续图2E的制程，形成一绝缘保护层25于该绝缘层23的第二表面23b上，且令该些导电凸块20’凸出并外露于该绝缘保护层25。之后，沿如图2E所示的切割路径S进行切单作业。
于本实施例中，该绝缘保护层25为防焊层，所以于后续制程中，可形成多个如焊球的导电元件(图略)于各该导电凸块20’上。
此外，若接续图2E’的制程，将得到图2F’所示的电子封装结构2’。
本发明的制法藉由该些导电凸块20’,20”凸出该绝缘层23的第二表面23b，所以当该电子封装结构2,2’以表面粘着技术(SMT)设于电路板(图略)上时，该些导电凸块20’,20”上的导电元件(图略)容易对位于该电路板上的接点，因而能有效降低SMT制程的不良率。
图3A至图3F为本发明的电子封装结构3的第二实施例的制法的剖视示意图。本实施例与第一实施例的差异仅在于新增止蚀层的制程，其它制程大致相同，所以以下仅详细说明差异处，而不再赘述相同处。
如图3A所示，提供一具有上侧30a与下侧30b的承载件30，且该承载件30的上侧具有一止蚀层36。
如图3B所示，形成一导体件20于该承载件30上，以令该导体件20包覆该止蚀层36；再形成一线路层21于该导体件20上。
如图3C所示，形成一表面处理层24于该线路层21的电性连接垫211上。
如图3D所示，设置至少一电子元件22于该线路层21的置晶垫210上，且令该电子元件22电性连接该线路层21的电性连接垫211。接着，形成一绝缘层23于该导体件20与该线路层21上，以令该绝缘层23包覆该电子元件22，且该绝缘层23具有相对的第一表面23a与第二表面23b，并以该第二表面23b结合至该导体件20上。
如图3E所示，移除该承载件30与部分该导体件20，使该导体件20的保留部分成为多个导电凸块20’，且令该绝缘层23的第二表面23b外露。
于本实施例中，以蚀刻方式移除部分该导体件20，所以该止蚀层36作为蚀刻用的阻层，即保留该止蚀层36所覆盖的导体件20，以作为该些导电凸块20’，使该止蚀层36位于该导电凸块20’的端面上。
如图3F所示，形成一绝缘保护层25于该绝缘层23的第二表面23b上，且令该些导电凸块20’外露于该绝缘保护层25。之后，进行切单作业。
本发明提供一种电子封装结构2,2’,3，包括：一绝缘层23、一线路层21、一电子元件22以及多个导电凸块20’,20”。
所述的绝缘层23具有相对的第一表面23a与第二表面23b。
所述的线路层21自该第二表面23b嵌埋于该绝缘层23中。
所述的电子元件22埋设于该绝缘层23中并设于该线路层21上，且令该电子元件22电性连接该线路层21。
所述的导电凸块20’,20”设于该线路层21上并外露出该绝缘层23的第二表面23b。
于一实施例中，该导电凸块20’,20”自该绝缘层23的第二表面23b凸出。
于一实施例中，该电子封装结构2,2’,3还包括形成于该线路层21上的一表面处理层24。
于一实施例中，该电子封装结构2,2’还包括形成于该导电凸块20’,20”上的一表面处理层24。
于一实施例中，该电子封装结构2,2’,3还包括一绝缘保护层25，其形成于该绝缘层23的第二表面23b上，且令该些导电凸块20’外露于该绝缘保护层25。
于一实施例中，该电子封装结构3还包括形成于该导电凸块20’上的一止蚀层36。
综上所述，本发明的电子封装结构及其制法，藉由移除部分该导体件，使该导体件成为多个导电凸块，所以当该电子封装结构以表面粘着技术(SMT)设于电路板上时，该些导电凸块上的导电元件容易对位于该电路板上的接点，因而能有效降低SMT制程的不良率。
上述实施例仅用于例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (9)

1.一种电子封装结构，其特征在于，该电子封装结构包括：
绝缘层，其具有相对的第一表面与第二表面，该绝缘层的第二表面呈凹状；
线路层，其自该第二表面嵌埋于该绝缘层中；
阻障层，其形成于该线路层上；
表面处理层，其形成于该阻障层上；
至少一电子元件，其埋设于该绝缘层中并设于该线路层上，且该电子元件电性连接至该线路层；
多个导电凸块，其设于该线路层上并自该绝缘层的第二表面凸出以外露出该绝缘层的第二表面，其中该导电凸块的位置未对齐该线路层的位置，使部分该线路层外露于该绝缘层；以及
绝缘保护层，其形成于该绝缘层的第二表面上，并覆盖在外露于该绝缘层的部分线路层上，且令该多个导电凸块外露于该绝缘保护层。
2.根据权利要求1所述的电子封装结构，其特征为，该电子封装结构还包括形成于该导电凸块上的另一表面处理层。
3.根据权利要求1的所述的电子封装结构，其特征为，该电子封装结构还包括形成于该导电凸块上的一止蚀层。
4.一种电子封装结构的制法，其特征为，该制法包括：
形成线路层于一导体件上；
形成阻障层于该线路层上；
形成表面处理层于该阻障层上；
设置至少一电子元件于该线路层上，且令该电子元件电性连接该线路层；
形成绝缘层于该导体件上，以令该绝缘层包覆该电子元件与该线路层，其中，该绝缘层具有相对的第一表面与第二表面，且该绝缘层以其第二表面结合至该导体件上；以及
移除部分该导体件，使该导体件的保留部分成为多个导电凸块，且自该绝缘层的第二表面凸出以外露出该绝缘层的第二表面，其中，该绝缘层的第二表面呈凹状，该导电凸块的位置未对齐该线路层的位置，且使部分该线路层外露于该绝缘层；以及
形成绝缘保护层于该绝缘层的第二表面上，并覆盖在外露于该绝缘层的部分线路层上，且令该多个导电凸块外露于该绝缘保护层。
5.根据权利要求4所述的电子封装结构的制法，其特征为，该制法还包括于设置该电子元件前，形成另一表面处理层于该导体件上。
6.根据权利要求5所述的电子封装结构的制法，其特征为，于移除部分该导体件后，该另一表面处理层位于该导电凸块上。
7.根据权利要求4所述的电子封装结构的制法，其特征为，该制法还包括于移除部分该导体件后，形成另一表面处理层于该导电凸块上。
8.根据权利要求4所述的电子封装结构的制法，其特征为，该制法还包括于形成该线路层前，将该导体件覆盖于一止蚀层上。
9.根据权利要求8所述的电子封装结构的制法，其特征为，于移除部分该导体件后，该止蚀层位于该导电凸块上。
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