CN1315823A - 电路装置的制造方法及电路装置 - Google Patents
电路装置的制造方法及电路装置 Download PDFInfo
- Publication number
- CN1315823A CN1315823A CN01110969A CN01110969A CN1315823A CN 1315823 A CN1315823 A CN 1315823A CN 01110969 A CN01110969 A CN 01110969A CN 01110969 A CN01110969 A CN 01110969A CN 1315823 A CN1315823 A CN 1315823A
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- conductive path
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- circuit arrangement
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- H05K1/00—Printed circuits
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- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/188—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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Abstract
在第一导电箔60A上形成分离槽54后,安装电路元件,将该层叠导电箔60作为支撑基板被覆绝缘性树脂50,翻转后,此次将绝缘性树脂50作为支撑基板,对第二导电箔60B进行刻蚀,分离成导电路径。因此不使用支撑基板,就能实现导电路径51、电路元件52被支撑在绝缘性树脂50上的电路装置。而且电路中有必要的布线L1~L3,有弯曲结构59或遮挡层,所以能防止拉脱。
Description
本发明涉及电路装置的制造方法及电路装置,特别是涉及薄型的电路装置的制造方法。
迄今,安装在电子机器中的电路装置由于被用于携带电话、携带用的计算机等中,所以要求小型化、薄型化、轻量化。
例如,作为电路装置,以半导体装置为例进行说明,作为一般的半导体装置,迄今有采用通常的传递模塑法封装的组件型半导体装置。如图24所述,该半导体装置1印刷电路基板PS上。
另外该组件型半导体装置1用树脂层3被覆在半导体芯片2的周围,从该树脂层3的侧面导出外部连接用的引线端子4。
可是该组件型半导体装置1从树脂层3引出引线端子4,而其总体尺寸大,并不能满足小型化、薄型化及轻量化的要求。
因此,各公司竟相开发各种各样的结构,来实现小型化、薄型化及轻量化,最近开发出了一种称为CSP(芯片尺寸组件)的与芯片的尺寸等同的晶片级CSP、或比芯片尺寸大一些的CSP。
图25表示采用环氧玻璃基板作为支撑基板的比芯片尺寸大一些的CSP6。这里说明在环氧玻璃基板5上安装了晶体管芯片的例。
在该环氧玻璃基板5的表面上形成第一电极7、第二电极8及缓冲垫9,在背面上形成第一背面电极10和第二背面电极11。而且上升第一电极7通过通孔TH与第一背面电极10导电性连接,第二电极8通过通孔与第二背面电极11导电性连接。另外,上述裸晶体管芯片T固定在缓冲垫9上,通过金属裸线12连接晶体管的发射极和第一电极7,通过金属裸线12连接晶体管的基极和第二电极8。另外覆盖着晶体管芯片T,将树脂层13设置在环氧玻璃基板5上。
上述CSP6虽然采用环氧玻璃基板5,但与晶片级CSP不同,具有从芯片T至外部连接用的背面电极10、11的延伸结构简单、制造成本低的优点。
另外如图24所述,上述CSP6安装在印刷电路基板PS上。构成电路的电极、布线设置在印刷电路基板PS上,上述CSP6、组件型半导体装置1、片状电阻CR或片状电容器CC等导电性连接并固定。
而且在该印刷电路基板上构成的电路被安装在各种装置中。
其次,参照图26及图27说明该CSP的制造方法。另外,在图27中,参照以中央的ガラエポ/フレキ基板为题的流程图。
首先作为基体材料(支撑基板),准备环氧玻璃基板5,通过绝缘性黏合剂将Cu箔20、21加压粘接在其两面上。(以上参照图26A)
接着,将耐蚀性的抗蚀剂22被覆在第一电极7、第二电极8、缓冲垫9、第一背面电极10及第二背面电极11所对应的Cu箔20、21上,对Cu箔20、21进行图形刻蚀。另外,也可以在表面和背面分别进行图形刻蚀。(以上参照图26B)
接着,利用穿孔器或激光,在上述环氧玻璃基板上形成通孔TH用的孔,对该孔进行电镀,形成通孔TH。利用该通孔TH导电性地连接第一电极7和第一背面电极10、以及第二电极8和第二背面电极11。(以上参照图26C)
另外,图中虽然省略了,但对成为焊接区的第一电极7、第二电极8实施镀Ni,同时对成为小片焊接区的缓冲垫9实施镀Au,对晶体管芯片T进行小片焊接。
最后,通过金属细线12连接晶体管芯片T的发射极和第一电极7、以及晶体管芯片T的基极和第二电极8,用树脂层13覆盖。(以上参照图26D)
而且根据需要,进行切割,作为一个一个的电气元件分离开。在图26中,在环氧玻璃基板5上虽然只设置一个晶体管芯片T,但实际上呈矩阵状地设置着多个晶体管芯片T。因此,最后利用切割装置进行单个分离。
利用以上的制造方法,制成采用支撑基板5的CSP型电气元件。该制造方法即使采用挠性薄片作为支撑基板也一样。
另一方面,在图27左侧的流程中给出了采用陶瓷基板的制造方法。准备了作为支撑基板的陶瓷基板后,形成通孔,然后,使用导电膏剂,印刷表面和背面的电极,进行烧结。然后,直至前一制造方法中的被服树脂层为止,与图26中的制造方法相同,但陶瓷基板非常脆,与挠性薄片和环氧玻璃基板不同,由于会立刻破碎,所以存在不能使用金属模的模具的问题。因此,用封装树脂进行封装,硬化后进行使封装树脂平坦的研磨,最后使用切割装置单个地分开。
在图25中,晶体管芯片T、连接装置7~12及树脂层13与外部导电性地连接,虽然保护晶体管是必要的结构要素,但只是这样的结构要素,难以提供实现小型化、薄型化、轻量化的电路装置。
另外,如上所述,成为支撑基板的环氧玻璃基板5本来是不需要的。可是在制造方法上为了粘贴电极,采用它作为支撑基板,不能没有该环氧玻璃基板5。
因此,由于采用该环氧玻璃基板5,所以成本上升,另外由于环氧玻璃基板5厚,所以电路装置变厚,限制了小型化、薄型化、轻量化。
另外,在环氧玻璃基板和陶瓷基板上连接两面上的电极用的通孔形成工序是不可少的,还存在制造工序长的问题。
图28是表示环氧玻璃基板、陶瓷基板或金属基板等上形成的图形的图。该图形一般形成IC电路,安装着晶体管芯片21、IC芯片22、片状电容器23及/或片状电阻24。在该晶体管芯片21和IC芯片22的周围形成与布线25呈一体的焊接区26,通过金属细线28导电性地连接芯片21、22和焊接区。另外与外部引线焊接区30呈一体地形成布线29。这些布线25、29在基板中曲折地延伸,根据需要,在IC芯片中形成得更细。因此,该细的布线与基板的接触面积非常少,存在布线剥离、或翘曲的问题。另外焊接区26是电源用的焊接区和小信号用的焊接区,特别是小信号用的焊接区接触面积小,成为剥离的原因。
另外,虽然外部引线固定在外部引线焊接区上,但存在由于加在外部引线上的外力的作用,致使外部引线焊接区剥离的问题。
本发明就是鉴于上述多个问题而完成的,第一,这样解决上述问题,即本发明包括:将板状体的表面层的一部分刻蚀成规定的形状,形成导电路径的工序;
将所希望的电路元件导电性地连接在所希望的上述导电路径上的工序;
用绝缘性树脂被覆上述电路元件及上述导电路径的工序;以及
从相对于上述导电路径形成面的面除去上述板状体,使上述导电路径从上述绝缘性树脂露出来的工序。
如果采用这样的结构,则由于焊接时应连接电路元件的区域刚性高,能保持本来的位置,所以焊接的可靠性极高。另外,即使在树脂封装工序中应连接电路元件的区域刚性也高,能保持本来的位置,所以能大幅度地防止短路等的发生。
如果采用该方法,则不会发生位置偏移,能高精度地形成可靠性高的电路装置。
例如,在作为出发材料使用以铜为主要成分的导电体、例如铜箔的情况下,与电镀膜相比,薄片电阻小,能谋求降低布线电阻。另外,在使用铜箔等轧制板状材料的情况下,即使热账系数差,也不会产生裂纹,提高了焊接性能。与此不同,在镀膜的情况下,由于沿z轴方向生长,所以相对于面的延伸方向弱,容易产生裂纹,焊接性能也低。
本发明的第二方面这样解决问题,即用导电箔支撑被刻蚀成规定的形状的侧面弯曲的导电路径,
将所希望的电路元件导电性地连接并固定在所希望的上述导电路径上,
用绝缘性树脂被覆上述电路元件及上述导电路径,
至少除去对应于导电路径的部分以外的上述导电箔。
利用本制造方法可以不需要通孔,同时能灵活地使导电箔成为支撑基板及导电路径,使结构要素达到最小限度,而且不需要从上述绝缘性树脂去掉导电路径。
另外,由于充分地确保了焊接区域之后,使树脂进入间隙中,所以能抑制裂纹的发生。
例如,在作为出发材料使用以铜为主要成分的导电体、例如铜箔的情况下,虽然表面上均匀地形成Cu2O、CuO等薄氧化膜,但在弯曲面的情况下表面积特别大,由于该氧化物与环氧树脂等树脂的化学结合性高,所以大幅度地提高了与树脂的粘接性。
第三,这样解决,即包括:在第一导电箔的背面准备层叠了第二导电箔的层叠导电箔的工序;
至少在成为导电路径的区域以外的上述第一导电箔上形成分离槽,形成侧面呈弯曲结构的第一导电路径的工序;
将所希望的电路元件导电性地连接并固定在所希望的上述第一导电路径上的工序;
用绝缘性树脂被覆上述电路元件及上述第一导电路径,以便填充在上述分离槽中进行模制的工序;以及
将对应于上述分离槽的部分的上述第二导电箔除去,在上述第一导电路径的背面形成第二导电路径的工序。
能灵活地将第二导电箔作为形成第一导电路径时的刻蚀阻挡层使用,同时防止第一导电路径分散。而且最终作为第二导电路径使用。另外利用填充在分离槽中的绝缘性树脂,呈一体地支撑导电路径,防止导电路径拉脱。当然不需要通孔。
第四,这样解决,即包括:在第一导电箔的背面准备层叠了第二导电箔的层叠导电箔的工序;
在上述第一导电箔表面上的至少成为导电路径的区域形成耐蚀性的导电被覆膜的工序;
至少在成为导电路径以外的上述第一导电箔上形成分离槽,形成侧面呈弯曲结构的第一导电路径的工序;
将电路元件固定在所希望的上述第一导电路径上的工序;
形成导电性地连接上述电路元件的电极和所希望的上述第一导电路径的连接构件的工序;
用绝缘性树脂被覆上述电路元件、上述连接构件及第一导电路径,以便填充在上述分离槽中进行模制,嵌合上述导电路径和上述绝缘性树脂的工序;以及
将未设置上述分离槽的上述第二导电箔除去,在上述第一导电路径的背面形成第二导电路径的工序。
能灵活地将第二导电箔作为形成第一导电路径时的刻蚀阻挡层使用,同时防止第一导电路径分散。而且最终作为第二导电路径使用。另外通过采用导电被覆膜,在导电路径的表面上形成遮挡层,被覆该遮挡层并且利用填充在分离槽中的绝缘性树脂,防止导电路径拉脱。当然不需要通孔。
第五,这样解决,即包括:在第一导电箔的背面准备层叠了第二导电箔的层叠导电箔的工序;
至少在成为导电路径以外的上述第一导电箔上形成分离槽,形成侧面呈弯曲结构的导电路径的工序;
将电路元件固定在所希望的上述导电路径上的工序;
形成导电性地连接上述电路元件的电极和所希望的上述第一导电路径的连接构件的工序;
用绝缘性树脂被覆上述电路元件、上述连接构件及第一导电路径,以便填充在上述分离槽中进行模制,嵌合上述第一导电路径和上述绝缘性树脂的工序;
将未设置上述分离槽的上述第一导电箔除去,在上述第一导电路径的背面形成第二导电路径的工序;以及
切断上述绝缘性树脂,分离成个别的电路装置的工序。
第六,这样解决,即包括:在第一导电箔的背面准备层叠了第二导电箔的层叠导电箔的工序;
在上述第一导电箔表面上的至少成为导电路径的区域形成耐蚀性的导电被覆膜的工序;
至少在成为第一导电路径以外的上述第一导电箔上形成分离槽,形成侧面呈弯曲结构的导电路径的工序;
将电路元件固定在所希望的上述第一导电路径上的工序;
形成导电性地连接上述电路元件的电极和所希望的上述第一导电路径的连接构件的工序;
用绝缘性树脂被覆上述电路元件,以便填充在上述分离槽中进行模制,嵌合上述第一导电路径和上述绝缘性树脂的工序;
将未设置上述分离槽的上述第二导电箔除去,在上述第一导电路径的背面形成第二导电路径的工序;以及
切断上述绝缘性树脂,分离成个别的电路装置的工序。
附图的简单说明
图1是说明本发明的电路装置的图。
图2是说明本发明的电路装置的图。
图3是说明本发明的电路装置的制造方法的图。
图4是说明本发明的电路装置的制造方法的图。
图5是说明本发明的电路装置的制造方法的图。
图6是说明本发明的电路装置的制造方法的图。
图7是说明本发明的电路装置的制造方法的图。
图8是说明本发明的电路装置的图。
图9是说明本发明的电路装置的制造方法的图。
图10是说明本发明的电路装置的制造方法的图。
图11是说明本发明的电路装置的制造方法的图。
图12是说明本发明的电路装置的制造方法的图。
图13是说明本发明的电路装置的制造方法的图。
图14是说明本发明的电路装置的制造方法的图。
图15是说明本发明的电路装置的制造方法的图。
图16是说明本发明的电路装置的制造方法的图。
图17是说明本发明的电路装置的制造方法的图。
图18是说明本发明的电路装置的制造方法的图。
图19是说明本发明的电路装置的制造方法的图。
图20是说明本发明的电路装置的制造方法的图。
图21是说明本发明的电路装置的图。
图22是说明本发明的电路装置的图。
图23是说明本发明的电路装置的安装方法的图。
图24是说明现有的电路装置的安装结构的图。
图25是说明现有的电路装置的图。
图26是说明现有的电路装置的制造方法的图。
图27是说明现有的和本发明的电路装置的制造方法的图。
图28是现有的和本发明的电路装置中使用的IC电路的图形图。
图29是说明半导体制造和装置制造的位置评价的图。
说明电路装置的第一实施形态
首先,参照图1说明本发明的电路装置的结构。
在图1中,示出了这样构成的电路装置53,即它有被埋在绝缘性树脂50中的导电路径51,电路元件52被固定在上述导电路径51上,用上述绝缘性树脂50支撑导电路径51。而且导电路径51的侧面有弯曲结构59。
本结构主要由电路元件52A、52B、多个第一导电路径51A~51C、以及将该第一导电路径51~51C埋入的绝缘性树脂50这样三种材料构成,在第一导电路径51A~51C之间设有用该绝缘性树脂50填充的分离槽54。而且利用绝缘性树脂50支撑弯曲结构59的上述导电路径51。
更详细地说,上述导电路径51实际上基本上由叠层结构构成,第一导电路径51A和第二导电路径51S重叠,第一导电路径51B和第二导电路径51T重叠,以及第一导电路径51C和第二导电路径51U重叠。
作为绝缘性树脂可以使用环氧树脂等热硬化性树脂、聚酰亚胺树脂、硫化聚苯等热塑性树脂。另外,绝缘性树脂可以采用使用金属模进行硬化的树脂、能进行浸渍、涂敷而被覆的全部树脂。
另外层叠导电箔的结构作为一例举出:上层的第一导电路径以Cu(或Al)为主要材料,下层的第二导电路径以Al(或Cu)为主要材料。另外上述第一及第二导电路径也可以用同一种材料构成。
另外电路元件52的连接构件是金属细线55A、由焊料构成的球、扁平的导电球、焊锡等焊料55B、Ag膏等导电膏55C、导电被覆膜或各向异性导电性树脂等。这些连接构件根据电路元件52的种类、电路元件32的实施形态来选择。例如,如果是裸半导体元件,则表面电极和导电路径51的连接选择金属细线,如果是CSP、倒装片等,则选择焊锡球或焊锡凸点。另外片状电阻、片状电容器选择焊锡55B。另外,即使将组合的电路元件、例如BGA或组件型的半导体元件等安装在导电路径51上也没有问题,在采用它的情况下,连接构件能选择焊锡。
另外电路元件和导电路径51A的固定方法,如果不需要进行导电性连接,则选择绝缘性黏合剂,另外在需要进行导电性连接的情况下,采用导电被覆膜。这里该导电被覆膜至少一层即可。
可以作为该导电被覆膜考虑的材料,有Ni、Ag、Au、Pt或Pd等,采用蒸镀、溅射、CVD等低真空或高真空下的粘附、电镀或导电膏的烧结等方法进行被覆。
例如Ag与Au粘接,也与焊料粘接。因此如果Au被覆膜被覆在芯片背面,则通过将Ag被覆膜、Au被覆膜、焊锡被覆膜直接被覆在导电路径51A上,能对芯片进行热压接,另外还能通过焊锡等焊料固定芯片。这里,也可以在层叠了多层的导电被覆膜的最上层形成上述导电被覆膜。例如,在Cu导电路径51A上能形成依次被覆了Ni被覆膜、Au被覆膜这样的两层被覆膜,或依次被覆了Ni被覆膜、Cu被覆膜、焊锡被覆膜这样的三层被覆膜,或依次被覆了Ag被覆膜、Ni被覆膜这样的两层被覆膜。另外,这些导电被覆膜的种类、叠层结构除此以外还有许多,但这里将其省略。
本电路装置有被覆导电路径51、且填充在上述第一导电路径51A~51C之间的上述分离槽54中、呈一体进行支撑的绝缘性树脂50。
该导电路径51之间成为分离槽54,这里由于填充绝缘性树脂50,所以具有谋求互相绝缘的优点。
该呈弯曲结构59的导电路径51A~51C之间成为分离槽54,在这里填充绝缘性树脂50,所以能防止导电路径51A~51C拉脱,同时具有谋求互相绝缘的优点。
另外,还有被覆导电路径52、且填充在上述导电路径51A~51C之间的上述分离槽54中、使第二导电路径51S~51U露出、呈一体进行支撑的绝缘性树脂50。
由于使第二导电路径51S~51U露出,所以第二导电路径的背面能与外部连接,具有不需要图25所示的现有结构的通孔TH的特征。
而且在电路元件通过焊料、Au、Ag等导电被覆膜直接固定的情况下,从电路元件及导电路径52A发生的热能通过导电路径51A传递给安装基板。特别是由于放热,对于能改善驱动电流的上升等的特性的半导体芯片有效。
图1是用多个电路元件构成IC电路的图,特别是连接电路元件和电路元件的导电路径具有布线功能,但如图1B所示,实际上呈接触区的形状。可是如图2或图28所示,实际的形状更复杂。
说明电路装置的第二实施形态
其次说明图2所示的电路装置53。
本结构形成布线L1~L3作为导电路径51,除此以外,与图1中的结构实际上相同。因此说明该布线L1~L3。
如上所述,在IC电路中,是从规模小的电路到规模大的电路。可是这里还有附图的情况,将规模小的电路示于图2A。该电路多半用于音频放大电路,是差动放大电路和电流反射镜电路连接而成的。如图2A所示,上述差动放大电路由TR1和TR2构成,上述电流反射镜电路主要由TR3和TR4构成。
图28是在本电路装置中实现了图2A所示的电路时的平面图,图2C是图2B中的A-A线处的剖面图,图2D是D-D线处的剖面图。安装着TR1和TR3的缓冲垫51A设置在图2B的左侧,安装着TR2和TR4的缓冲垫51D设置在右侧。外部连接用的电极51B、51E~51G设置在该缓冲垫51A、51D的上侧,51C、51H~51J设置在下侧。另外,B、E分别表示基极、发射极。而且由于TR1的发射极和TR2的发射极相连接,所以布线2与电极51E、51G呈一体地形成。另外由于TR3的基极和TR4的基极相连接、TR3的发射极和TR4的发射极相连接,所以布线L1与电极51C、55J呈一体地设置,布线L3与电极55H、55I呈一体地设置。
该布线L1~L3有特征,用图28说明,布线25、布线29是与其相当的布线。该布线随着本电路装置的集成度的不同而不同,但宽度约为25微米,非常窄。另外,该25微米的宽度是采用湿法刻蚀时的数值,如果采用干法刻蚀,其宽度可以更窄。
从图2D可知,构成布线L1的第一导电路径51K被埋入绝缘性树脂50中,侧面有弯曲结构,同时用绝缘性树脂50进行支撑。如果进行另外的表现,则布线被埋入绝缘性树脂50中。因此,如图24~图28所示,与布线只粘贴的支撑基板上的情况不同,能防止布线拉脱、翘区。特别是从后面所述的制造方法可知,第一导电路径的侧面是粗糙面,而且呈弯曲结构,由于在第一导电路径的表面上形成遮挡层等,所以有固定效果,构成上述导电路径不能从绝缘性树脂拉脱的结构。另外,有遮挡层的结构将用图8说明。
另外,如上所述,由于外部连接用的电极51B、51C、55E~51J被绝缘性树脂埋入,所以即使施加外力,也不会从被固定的外部引线上剥离。这里电阻R1和电容器C1虽然被省略了,但也可以安装在第一导电路径上。另外在后面的安装结构的实施形态中虽然将进行说明,但也可以安装在本电路装置的背面,作为外部附设也可以安装在安装基板一侧。
说明电路装置的第三实施形态
其次说明图8所示的电路装置56。
本结构是在第一导电路径51A~51C的表面上形成导电被覆膜57,除此以外,与图1或图2所示的结构实际上相同。因此这里以该导电被覆膜为中心进行说明。
第一个特征在于:利用与构成第一导电路径51A~51C的材料(以下称第一种材料)不同的第二种材料而具有固定效果。利用第二种材料形成遮挡层58,而且由于第一导电路径51A~51C和被覆的遮挡层58被埋入绝缘性树脂50中,所以具有固定效果,能防止第一导电路径51拉脱。
本发明利用弯曲结构59和遮挡层58两者,具有双重的固定效果,抑制第一导电路径51A~51C拉脱。
以上三个实施形态虽然用安装多个电路元件、包括布线构成电路的电路装置进行了说明,但如图21、图22所示,也可以实施封装一个电路元件(半导体元件或无源元件)构成的电路装置。在图21中,作为一例示出了安装了CSP、倒装片等背面馈送型的元件80的电路装置,另外在图22中,示出了封装了片状电阻、片状电容器等无源元件82的电路装置。另外,也可以在两个导电路径之间连接金属细线,并封装它们。这样做能灵活地利用表面。
说明电路装置的制造方法的第一种实施形态
其次利用图3~图7及图1,说明电路装置53的制造方法。
首先如图3所示,准备薄片状的导电箔60。该导电箔60是层叠第一导电箔60A和第二导电箔60B构成的。
这里重要的是能有选择地刻蚀两个导电箔、以及电阻值低。另外为了提高集成度,刻蚀时能形成精细图形也是重要的。例如,通过刻蚀第一导电箔60A进行图形刻蚀时,第二导电箔60B停止刻蚀是重要的,另外反之,对第二导电箔60B进行图形刻蚀时,第一导电箔60A停止刻蚀也是重要的。
例如,作为电阻值低的材料,能举出Cu、Al、Au、Ag、Pt等,但如果考虑成本、可加工性等,Cu和Al是适当的。由于Cu电阻值低、成本也便宜,所以是采用得最多的材料,是能进行湿法刻蚀的材料。因此在要求低成本和低电阻值的情况下,也可以采用该Cu作为第一导电箔60A。可是不易进行干法刻蚀。另一方面,Al多半被用于半导体IC的布线,是能进行各向异性刻蚀的材料。由于能光滑地刻蚀侧壁,所以能以更高的密度形成布线。因此在要求更精细的图形的情况下,也可以采用Al作为第一导电箔60A。
例如在采用Cu作为第一导电箔60A的情况下,准备Al箔,如果在该Al箔的表面上电镀Cu,则能调整Cu的厚度,所以能形成更精细的图形。如果Cu的厚度薄,当然不能进行横向刻蚀,所以更能形成精细的图形。在采用Al作为第一导电箔60A的情况下,准备Cu箔,如果通过蒸镀或溅射在该Cu箔的表面上形成Al,则能调整Al的厚度。另外,由于能用C12气体或BC13气体进行各向异性刻蚀,所以能形成更精细的图形。
以下,说明采用10微米~300微米的Al箔作为第二导电箔60B,采用在它上面电镀了数微米~20微米的Cu作为第一导电箔60A,使用该层叠导电箔60。
另外,按照规定的宽度卷成圆筒状,准备薄片状的层叠导电箔60,把它送给后面所述的各工序即可,准备按规定的大小切好的导电箔,送给后面所述的各工序即可。
接着,有至少将成为第一导电路径51A~51C的区域除外的第一导电箔60A除去的工序、将电路元件52安装在上述第一导电箔60A上的工序、以及将绝缘性树脂50被覆在由上述除去工序形成的分离槽61及层叠导电箔60上,封装电路元件的工序。
首先,如图4所示,在Cu箔60的第一导电箔60A上形成光敏抗蚀剂PR(耐蚀掩模),对光敏抗蚀剂PR进行图形刻蚀,以便使成为第一导电路径51A~51C的区域除外的第一导电箔60A露出。然后,如图5A所示,通过上述光敏抗蚀剂PR进行刻蚀。
在本制造方法中,具有以下特征:利用温法刻蚀或干法刻蚀,各向异性地进行刻蚀,其侧面呈粗糙面,而且弯曲。
在湿法刻蚀的情况下,刻蚀剂采用氯化铁或氯化铜,上述导电箔浸渍在该刻蚀剂中,或在该刻蚀剂中喷淋。这里湿法刻蚀一般是进行非各向异性刻蚀,所以侧面呈弯曲结构。另外如果采用氧化铁作为刻蚀剂,则Al的刻蚀速度比Cu快,所以Al不能起阻止刻蚀的作用。因此,第一导电箔60A被刻蚀成第一导电路径51A~51C时,Al第二导电箔60B的厚度必须厚一些,以便能呈一体地支撑该第一导电路径51A~51C。在此情况下,如虚线所示,在第二导电箔60B上也形成分离槽。在此情况下能获得固定效果。
另外在干法刻蚀的情况下,能进行各向异性、非各向异性刻蚀。现在,可以说用反应性离子刻蚀将Cu除去是不可能的,而用溅射法能除去。另外能根据溅射条件,进行各向异性、非各向异性刻蚀。由于呈非各向异性,所以分离槽61的侧面呈弯曲结构。
这里,采用刻蚀Cu、而不刻蚀Al的刻蚀方法,最好是Al成为阻止刻蚀的刻蚀剂。
如图5B所示,在成为刻蚀掩模的光敏抗蚀剂PR的正下方进行横向刻蚀,沿横向刻蚀比它更深的部分。如图所示,如果从分离槽61的侧面的位置向上,与该位置对应的开口部的口径变小,则构成倒圆锥结构。另外通过采用喷射,沿纵深方向进行刻蚀,能抑制横向的刻蚀,所以明显地呈现出该固定结构。
另外,在图4中,也可以代替光敏抗蚀剂而有选择地被覆对刻蚀液具有耐蚀性的导电被覆膜。如果有选择地被覆在成为导电路径的部分上,则该导电被覆膜成为刻蚀保护膜,不采用抗蚀剂,也能刻蚀分离槽。能作为该导电被覆膜考虑的材料,有Ni、Ag、Au、Pt或Pd等。而且这些耐蚀性的导电被覆膜具有能直接作为缓冲垫、焊接区灵活使用的特征。
例如Ag被覆膜可以和Au粘接,也可以和焊料粘接。因此如果在芯片背面被覆Au被覆膜,则能直接将芯片热压接在导电路径51上的Ag被覆膜上,或者通过焊锡等焊料能固定芯片。另外,由于Au细线能粘接在Ag导电被覆膜上,所以也能进行导线焊接。因此具有能将这些导电被覆膜直接作为缓冲垫、焊接区灵活使用的优点。
接着,如图6所示,有将电路元件52A、52B导电性地连接在形成了分离槽61的第一导电路径51A~51C上的安装工序。
作为电路元件52,有晶体管、二极管、IC芯片等半导体元件52A、片状电容器、片状电阻等无源元件52B。另外这些元件即可以是裸芯片,也可以是封装的芯片。厚度虽然变厚,但也能安装CSP、BGA等背面馈送元件(也称为倒装片)。
这里,裸晶体管芯片52A被焊接在第一导电路径51A上。另外,利用热压接进行的球焊接法或利用超声波进行的湿焊接法等,通过固定的金属细线55A,连接发射极和第一导电路径51B、基极和第一导电路径51B。另外,片状电容器或无源元件通过焊锡等焊料或Ag膏等导电膏剂55B被安装固定在第一导电路径51B和51C之间。
另外在本实施形态中应用图28所示的图形的情况下,焊接区26的尺寸非常小,但如图5所示,与第二导电箔60B呈一体。因此能传导焊头的能量,有提高焊接性能的优点。另外焊接后切断金属细线时,有时将金属细线全切断。这时,由于焊接区与第二导电箔60B呈一体,所以没有焊接区露出的现象,提高了全切断性。
另外,如图7所示,还有将绝缘性树脂50附着在上述第一导电路径51A~51C上及弯曲的分离槽61中的工序。该工序能通过传递模塑法、注入模塑法、浸渍法或涂敷来实现。作为树脂材料,环氧树脂等热硬化性树脂能用传递模塑法实现,聚酰亚胺树脂、硫化聚苯等热塑性树脂能用注入模塑法实现。
在本实施形态中,导电箔60表面上被覆的绝缘性树脂50的厚度调整成从电路元件的最顶部(这里为金属细线55A的顶部)算起大约被覆100微米。考虑强度的大小,该厚度可以厚一些,也可以薄一些。
另外,由于第二导电箔60B维持薄片状态,所以作为第一导电路径51A~51C不会被分离成单个的。因此,作为薄片状的层叠导电箔60呈整体地处理,模制绝缘性树脂时,具有向金属模输送、往金属模中安装的作业非常容易的特征。
另外,由于绝缘性树脂50被填充在具有弯曲结构59的分离槽61中,所以该部分具有固定效果,能防止绝缘性树脂50剥离,反之能防止在后面的工序中分离的导电路径51的拉脱。
另外,在被覆这里的绝缘性树脂50之前,为了保护例如半导体芯片或金属细线的连接部分,也可以用硅树脂等进行封装。
接着,有用化学方法及/或物理方法除去第二导电箔60B的背面,分离成导电路径51的工序。
这里,采用氢氧化钠等碱性溶液进行刻蚀。由于上述氢氧化钠刻蚀Al,但不刻蚀Cu,所以不会腐蚀第一导电路径51A~51C。
其结果,成为在绝缘性树脂50中露出第二导电路径51S~51U的结构。然后露出分离槽61的底部,成为图1中的分离槽54。另外这里也可以将第二导电箔60B全部除去。(以上参照图7)
最后,根据需要,将焊锡等导电材料被覆在露出的第二导电路径51S~51U上,完成图1所示的电路装置。
另外,在将导电被覆膜被覆在导电路径51S~51U的背面的情况下,也可以在图3中的导电箔的背面先形成导电被覆膜。在此情况下,可以有选择地被覆与导电路径对应的部分。被覆方法例如是电镀。另外该导电被覆膜可以是耐刻蚀的材料。
另外,在本制造方法中,只是在导电路径上安装晶体管和片状电阻,但也可以将它作为一个单元配置成矩阵状,也可以将图2或图28所示的电路作为一个单元配置成矩阵状。在此情况下,如后面所述,用切割装置一个一个地分开。
采用上述的制造方法,能实现在绝缘性树脂50中埋入第一导电路径51A~51C,而第二导电路径51S~51U在绝缘性树脂50的背面露出的电路装置53。
绝缘性树脂50作为埋入导电路径51的材料是必要的材料,而不需要图26中的现有的制造方法所示的支撑基板5。因此,能用最小限度的材料制造,具有能实现降低成本的特征。(以上参照图1)
说明电路装置的制造方法的第二实施形态
再次利用图3~图7及图1,说明电路装置53的制造方法。
本实施形态采用Al作为第一导电箔60A,采用Cu作为第二导电箔,这一点与前面的实施形态不同,各制造工序实际上相同。因此,说明不同的地方,除此以外省略。
在前面的实施形态中已说明过,该层叠导电箔60既可以在Al箔上形成Cu薄膜,也可以在Cu上形成Al薄膜。该薄膜既可以用电镀、蒸镀、溅射等方法形成,也可以准备好呈箔的状态,进行层叠、压接。(以上参照图3)
接着,在层叠导电箔60上形成光敏抗蚀剂PR,在对应于导电路径的部分形成上述光敏抗蚀剂PR,以便残留下来。(以上参照图4)
接着,通过光敏抗蚀剂PR,对第一导电箔60A进行图形刻蚀。在该工序中,采用氢氧化钠等碱性溶液作为刻蚀剂。该氢氧化钠刻蚀Al,不刻蚀Cu,所以不需要象前一个实施形态那样考虑第二导电箔的厚度。因此由Cu构成的第二导电箔60B可以薄一些,也可以厚一些。另外由于是湿法刻蚀,所以其侧面弯曲。另外如果进行喷射,会更弯曲。另外,也可以使用C12气体或BC13+C12气体,进行非各向异性干法刻蚀。(以上参照图5)
接着有安装电路元件52的工序。这里,如果在第一导电路径51A~51C的表面上涂敷Ag膏后烧结,则能与在半导体芯片的背面形成的Au结合,另外还能进行Al、Au金属细线55A的焊接。另外Ag与焊锡等焊料的粘接性好,也能通过焊料55B固定。(以上参照图6)
接着有被覆绝缘性树脂50的工序。详细情况与前一个实施形态相同,故说明从略。
接着,有对第二导电箔60B进行图形刻蚀的工序。这里,对光敏抗蚀剂PR进行图形刻蚀,以便留下对应于第二导电路径的部分,用氯化铁、氯化铜或氢氧化钠等刻蚀剂进行刻蚀。最好是课时Cu而不刻蚀Al的选择性的刻蚀剂。(以上参照图7)
最后,根据需要,将焊锡等导电材料被覆在露出的第二导电路径51S~51U上,完成图1所示的电路装置。
这里也可以采用Ag作为导电材料。在此情况下,也可以在图3中的第二导电箔60B的全部背面上电镀Ag,也可以进行局部电镀。最终通过焊料将设置在第二导电路径51S~51U的背面上的Ag和安装基板上的布线固定。
在本制造方法中将由Al构成的第一导电箔60A刻蚀成第一导电路径51A~51C时,由于其侧面呈弯曲结构,所以具有固定效果。因此能防止导电路径拉脱。
说明电路装置的制造方法的第三实施形态
其次,利用图9~图13、图8说明有遮挡层58的电路装置56的制造方法。另外除了被覆成为遮挡层的导电被覆膜(以下称第二种材料)70以外,与第一实施形态(图1、图2)实际上相同,所以详细说明从略。
首先如图9所示,准备在成为第一种材料的第一导电箔60A上被覆了刻蚀速度小的第二种材料70的层叠导电箔60。
例如,如果将Ni被覆在Cu箔上,则氯化铁或氯化铜等能与Cu和Ni一起刻蚀,由于刻蚀速度慢,所以Ni适合于形成遮挡层58。粗的实线是由Ni构成的导电被覆膜70,其厚度最好为1~10微米左右。另外Ni的厚度越厚,越容易形成遮挡层58。
另外第二种材料也可以被覆能与第一种材料进行选择刻蚀的材料。在此情况下,首先对由第二种材料构成的被覆膜进行图形刻蚀,以便被覆在第一导电路径51A~51C的形成区域,将该被覆膜作为掩模,对由第一种材料构成的第一导电箔60A进行刻蚀,能形成遮挡层58。作为第二种材料可以考虑Al、Ag、Au等。(以上参照图9)
接着,有至少将除了成为第一导电路径51A~51C的区域以外的第一导电箔60A除去的工序。
如图10所示,在Ni70上形成光敏抗蚀剂PR,对光敏抗蚀剂PR进行图形刻蚀,以便使除了成为第一导电路径51A~51C的区域以外的Ni70露出,如图11所示,可以通过上述光敏抗蚀剂进行刻蚀。
如上所述,如果采用氯化铁、氯化铜的刻蚀剂等进行刻蚀,则由于Ni70的刻蚀速度比Cu60的刻蚀速度慢,所以随着刻蚀的进行而形成遮挡层58。
另外,将电路元件52安装在形成了上述分离槽61的第一导电路径51A~51C上的工序(图12);将绝缘性树脂50被覆在上述第一导电路径51A~51C上及分离槽61中,用化学方法及/或物理方法除去第二导电箔60B,分离成第二导电路径51S~51U的工序(图13);以及在导电路径背面形成导电被覆膜直至完成的工序(图8)与前面的制造方法相同,所以其说明从略。
以上,由于利用遮挡层58和弯曲结构59而具有双重固定效果,所以能防止导电路径的拉脱、翘曲等。
说明电路装置的制造方法的第四实施形态
接着,参照图14~图20,说明将由多种电路元件、布线、缓冲垫、焊接区等形成的导电路径构成的IC电路作为一个单元,配置成矩阵状,封装后一个个地分开,作为构成IC电路的电路装置的制造方法。另外本制造方法与第一实施形态、第二实施形态大致相同,所以只简单地说明相同的部分。
首先如图14所示,准备薄片状的层叠导电箔60。
另外,在图16所示的工序中形成分离槽61时,第二导电箔60B的厚度必须能支撑第一导电路径,以便不致使其零散。这里,一个是Al,另一个是Cu,在哪一个上面都可以。另外以规定的宽度卷成筒状,准备薄片状的层叠导电箔60,把它输送给后面所述的各工序即可,准备切成了规定大小的导电箔,输送给后面所述的各工序即可。
接着,有至少将除去成为第一导电路径51A~51C的区域以外的第一导电箔60A除去的工序。
首先,如图15所示,在第一导电箔60A上形成光敏抗蚀剂PR,对光敏抗蚀剂PR进行图形刻蚀,以便使除了成为第一导电路径51A~51C的区域以外的第一导电箔60A露出。如图16所示,通过上述光敏抗蚀剂PR进行刻蚀即可。
通过刻蚀形成的分离槽61的侧面呈粗糙面,所以能提高与绝缘性树脂50的粘接性。
另外该分离槽61的侧壁被进行非各向异性刻蚀,所以弯曲。该除去工序能采用湿法刻蚀、或干法刻蚀。而且利用该弯曲结构而呈具有固定效果的结构。(详细情况参照说明电路装置的制造方法的第一实施形态)
另外,在图15中,也可以代替光敏抗蚀剂PR而有选择地被覆对刻蚀液具有耐蚀性的导电被覆膜。如果有选择地被覆在成为第一导电路径的部分上,则该导电被覆膜成为刻蚀保护膜,不采用抗蚀剂,也能刻蚀分离槽。
接着,如图17所示,有将电路元件52A导电性地连接并安装在形成了分离槽61的第一导电箔60A上的工序。
作为电路元件52A,有晶体管、二极管、IC芯片等半导体元件、片状电容器、片状电阻等无源元件。另外厚度虽然变厚,但也能安装CSP、BGA等背面馈送元件(也称为倒装片)。
这里,裸晶体管芯片52A被焊接在导电路径51A上,通过金属细线55A,连接发射极和第一导电路径51B、基极和第一导电路径51B。
另外,如图18所示,还有将绝缘性树脂50附着在上述层叠导电箔60上及分离槽61中的工序。该工序能通过传递模塑法、注入模塑法、浸渍法或涂敷来实现。
在本实施形态中,层叠导电箔60表面上被覆的绝缘性树脂的厚度调整成从电路元件的最顶部算起大约被覆100微米。考虑强度的大小,该厚度可以厚一些,也可以薄一些。
另外,由于第二导电箔60B呈薄片状态残留,所以第一导电箔60A作为第一导电路径51A~51C,分离槽61不会被分离成单个的。因此,作为薄片状的层叠导电箔60呈整体地处理,模制绝缘性树脂时,具有向金属模输送、往金属模中安装的作业非常容易的特征。
接着,有用化学方法及/或物理方法除去第二导电箔60B的背面,分离成导电路径51的工序。这里,通过刻蚀实施上述除去工序。其结果,成为在绝缘性树脂50的背面露出第二导电路径51S~51U的结构。
另外,如图19所示,将焊锡等导电材料被覆在露出的第二导电路径51S~51U上。
最后,如图20所示,有将每个电路元件分开,作为电路装置完成的工序。
分离线是箭头所在位置,能采用切割、剪断、压截、分片等方法实现。另外,在采用分片法的情况下,被覆绝缘性树脂时,在金属模中形成突出部即可,以便使槽位于分离线上。
特别是在通常的半导体装置的制造方法中,切割是大多数情况下使用的一种方法,由于能分离尺寸非常小的物体,所以很适用。
在以上的第一~第三实施形态中说明的制造方法也能实施图28所示的复杂的图形。特别弯曲、与焊接区26呈一体、另一端导电性地与电路元件连接的布线的宽度窄,而且长度长。因此,由于受热而引起的翘曲非常大,在现有的结构中存在剥离的问题。可是在本发明中,布线被埋在绝缘性树脂中得以支撑,所以能防止布线本身的翘曲、剥离、拉脱。另外焊接区本身的平面面积小,在现有的结构中,会发生焊接区的剥离,但在本发明中,如上所述被埋在绝缘性树脂中,另外被具有弯曲结构的绝缘性树脂支撑着,该弯曲结构有固定效果,所以具有能防止拉脱的优点。
另外,还有能实现将电路埋在绝缘性树脂50中的电路装置的优点。如果用现有的结构说明的话,是将电路安装在印刷电路基板、陶瓷基板中。将在后面的安装方法中说明。
在图27的右侧,示出了简单地汇总了本发明的流程。通过层叠导电箔的准备、Ag或Ni等的电镀、第一导电箔的刻蚀、倒装、导线焊接、传递模塑、第二导电箔的刻蚀、导电路径的背面处理及切割等9道工序,能实现电路装置。而且不由厂商供给支撑基板,全部工序都能自行实施。
说明电路装置的种类及它们的安装方法的实施形态。
图21是表示安装了背面馈送型的电路元件80的电路装置81的图。作为电路元件80,裸半导体芯片、进行了表面封装的CSP或BGA(倒装片)等适合。另外图22是表示安装了片状电阻或片状电容器等无源元件82的电路装置83的图。它们由于是薄型的,而且用绝缘性树脂封装,所以对环境的适应性也好。
图23是说明安装结构的图。首先图23A是在印刷电路基板、陶瓷基板等安装基板84上形成的导电路径85上安装了至此说明的本发明的电路装置53、56、81、83的图。
特别是半导体芯片52的背面固定的导电路径51A由于与安装基板84的导电路径85进行热结合,所以通过上述导电路径85能使电路装置放热。另外作为安装基板84,如果采用金属基板,则金属基板有助于放热,更能降低半导体芯片52的温度。因此,能提高半导体芯片的激励能力。
例如功率MOS、IGBT、SIT、大电流激励用晶体管、大电流激励用的IC(MOS型、BIP型、Bi-CMOS型)存储元件等适合。
另外作为金属基板最好是Al基板、Cu基板、Fe基板,另外考虑到与导电路径85的短路,形成绝缘性树脂及/或氧化膜等。
另外图23B是将本电路装置90作为图23A中的基板84使用的图。这是本发明的最大的特征。就是说用现有的印刷电路基板、陶瓷基板,顶多在基板中形成通孔TH,但在本发明中,具有能实现内部安装了IC电路的基板模块的特征。例如,在印刷电路基板中至少安装了一个电路(内部甚至也可以安装系统)。
另外,以往作为支撑基板,必须是印刷电路基板、陶瓷基板,但在本发明中,能实现不需要该支撑基板的基板模块。它与印刷电路基板、陶瓷基板或用金属基板构成的混合基板相比,能使其厚度薄、重量轻。
另外由于将本电路装置90作为支撑基板用,能将电路元件安装在露出的导电路径上,所以能实现高功能的基板模块。特别是将本电路装置作为支撑基板,如果作为元件将本电路装置91安装在它上面,则能实现更轻更薄的基板模块。
因此,利用这些安装形态,安装了该模块的电子机器能实现小型化、轻量化。
另外,用符号93表示的划影线的部分是绝缘性的被覆膜。例如最好是焊锡抗蚀剂等高分子膜。由于它的形成,能防止基板90中埋入的导电路径和在电路元件91等上形成的电极短路。
另外,用图29说明本电路装置的优点。在现有的安装方法中,半导体厂商形成组件型半导体装置、倒装片,安装厂商将从半导体厂商供给的半导体装置和从零件厂商供给的无源元件等安装在印刷电路基板上,将它作为模块组装在装置中制成电子机器。可是在本电路装置中,由于能由于能采用本身作为安装基板,所以半导体厂商能利用后面的工序完成安装基板模块,供给安装厂商。因此,安装厂商能大幅度地节省往该基板上进行的元件安装。
从以上的说明可知,在本发明中,能以电路装置、导电路径及绝缘性树脂必要的最小限度构成,构成不浪费资源的电路装置。因此直至完工没有多余的结构要素,能实现能大幅度降低成本的电路装置。另外通过使绝缘性树脂的被覆膜厚度、导电箔的厚度为最佳值,能实现极其小型化、薄型化及轻量化的电路装置。另外由于翘曲或剥落现象显著的布线被埋入在绝缘性树脂中进行支撑,所以能解决这些问题。
另外由于只使导电路径的背面从绝缘性树脂露出,所以导电路径的背面能直接供与外部的连接用,具有能不需要图25所示的现有结构的背面电极及通孔的优点。
而且在电路元件通过焊料、Au、Ag等导电被覆膜直接固定的情况下,由于导电路径的背面露出,所以从电路元件发生的热能通过导电路径,将热直接传给安装基板。特别是利用该放热,还能安装功率元件。
另外由于导电路径的侧面呈弯曲结构、以及/或者在导电路径的表面上形成由第二种材料构成的被覆膜,能形成被覆在导电路径上的遮挡层,所以能具有固定效果,能防止导电路径的翘曲、拉脱。
另外在本发明的电路装置的制造方法中,使成为导电路径的材料的导电箔本身具有作为支撑基板的功能,形成分离槽时或安装电路元件、被覆绝缘性树脂时,用导电箔支撑全体,另外将导电箔作为各导电路径分离时,使绝缘性树脂具有作为支撑基板的功能。因此,能以电路元件、导电箔、绝缘性树脂必要的最小限度制造。不需要在现有例中说明的构成本来的电路装置的支撑基板,成本也能便宜。另外由于不需要支撑基板、导电路径被埋入绝缘性树脂中、还能调整绝缘性树脂和导电箔的厚度,所以还具有能形成非常薄的电路装置的优点。另外在形成分离槽的工序中还能形成弯曲结构,能同时实现具有固定效果的结构。
另外从图27可知,由于能省略通孔的形成工序、导体的印刷工序(陶瓷基板的情况下)等,所以与以往相比,能大幅度地缩短制造工序,具有能自行完成全部工序的优点。另外不需要一切结构金属模,是一种交货期极短的制造方法。
其次由于不将导电路径分成单个处理,所以在后面的绝缘性树脂的被覆工序中,具有提高工作效率的特征。
最后,由于将本电路装置作为支撑基板用,能将电路元件安装在露出的导电路径上,所以能实现高功能的基板模块。特别是将本电路装置作为支撑基板,如果在它上面作为元件安装本电路装置91,则更能实现轻量薄型的基板模块。
Claims (22)
1.一种电路装置的制造方法,其特征在于包括:
将板状体的表面层的一部分刻蚀成规定的形状,形成导电路径的工序;
将所希望的电路元件导电性地连接在所希望的上述导电路径上的工序;
用绝缘性树脂被覆上述电路元件及上述导电路径的工序;以及
从相对于上述导电路径形成面的面除去上述板状体,使上述导电路径从上述绝缘性树脂露出来的工序。
2.根据权利要求1所述的电路装置的制造方法,其特征在于:形成上述导电路径的工序包括进行图形刻蚀的工序。
3.根据权利要求1所述的电路装置的制造方法,其特征在于:上述板状体是铜箔。
4.根据权利要求1所述的电路装置的制造方法,其特征在于包括:在第一导电箔的背面准备层叠了第二导电箔的层叠导电箔的工序;
至少在成为导电路径以外的上述第一导电箔上形成分离槽,形成侧面呈弯曲结构的第一导电路径的工序;
将所希望的电路元件导电性地连接并固定在所希望的上述第一导电路径上的工序;
用绝缘性树脂被覆上述电路元件及上述第一导电路径,以便填充在上述分离槽中进行模制的工序;以及
有选择地将上述第二导电箔除去,在上述第一导电路径的背面形成第二导电路径的工序。
5.根据权利要求1所述的电路装置的制造方法,其特征在于包括:在第一导电箔的背面准备层叠了第二导电箔的层叠导电箔的工序;
在上述第一导电箔表面上的至少成为导电路径的区域形成耐蚀性的导电被覆膜的工序;
至少在成为导电路径以外的上述第一导电箔上形成分离槽,形成侧面呈弯曲结构的第一导电路径的工序;
将电路元件固定在所希望的上述第一导电路径上的工序;
形成导电性地连接上述电路元件的电极和所希望的上述第一导电路径的连接构件的工序;
用绝缘性树脂被覆上述电路元件、上述连接构件及第一导电路径,以便填充在上述分离槽中进行模制,嵌合上述导电路径和上述绝缘性树脂的工序;以及
将未设置上述分离槽的上述第二导电箔除去,在上述第一导电路径的背面形成第二导电路径的工序。
6.根据权利要求1所述的电路装置的制造方法,其特征在于包括:在第一导电箔的背面准备层叠了第二导电箔的层叠导电箔的工序;
至少在成为导电路径以外的上述第一导电箔上形成分离槽,形成侧面呈弯曲结构的导电路径的工序;
将电路元件固定在所希望的上述导电路径上的工序;
形成导电性地连接上述电路元件的电极和所希望的上述第一导电路径的连接构件的工序;
用绝缘性树脂被覆上述电路元件、上述连接构件及第一导电路径,以便填充在上述分离槽中进行模制,嵌合上述第一导电路径和上述绝缘性树脂的工序;
将未设置上述分离槽的上述第一导电箔除去,在上述第一导电路径的背面形成第二导电路径的工序;以及
切断上述绝缘性树脂,分离成个别的电路装置的工序。
7.根据权利要求1所述的电路装置的制造方法,其特征在于包括:在第一导电箔的背面准备层叠了第二导电箔的层叠导电箔的工序;
在上述第一导电箔表面上的至少成为导电路径的区域形成耐蚀性的导电被覆膜的工序;
至少在成为第一导电路径以外的上述第一导电箔上形成分离槽,形成侧面呈弯曲结构的导电路径的工序;
将电路元件固定在所希望的上述第一导电路径上的工序;
形成导电性地连接上述电路元件的电极和所希望的上述第一导电路径的连接构件的工序;
用绝缘性树脂被覆上述电路元件,以便填充在上述分离槽中进行模制,嵌合上述第一导电路径和上述绝缘性树脂的工序;
将未设置上述分离槽的上述第二导电箔除去,在上述第一导电路径的背面形成第二导电路径的工序;以及
切断上述绝缘性树脂,分离成个别的电路装置的工序。
8.根据权利要求4所述的电路装置的制造方法,其特征在于:上述第二导电箔用铜构成。
9.根据权利要求4所述的电路装置的制造方法,其特征在于:上述第二导电箔用铝、铁-镍中的任意一种构成。
10.根据权利要求4所述的电路装置的制造方法,其特征在于:上述第一导电箔通过电镀形成。
11.根据权利要求4所述的电路装置的制造方法,其特征在于:上述层叠导电箔是在由铝构成的导电箔上镀铜构成的。
12.根据权利要求4所述的电路装置的制造方法,其特征在于:上述第一导电箔是铝或铜。
13.根据权利要求5所述的电路装置的制造方法,其特征在于:上述导电被覆膜是镀镍或镀铜形成的。
14.根据权利要求5所述的电路装置的制造方法,其特征在于:有选择地形成上述第一导电箔的上述分离槽是通过化学刻蚀或物理刻蚀形成的。
15.根据权利要求5所述的电路装置的制造方法,其特征在于:将上述导电被覆膜作为上述分离槽形成时的掩模的一部分使用。
16。根据权利要求1所述的电路装置的制造方法,其特征在于:上述电路元件将半导体裸芯片、倒装片、片状电路零件、组件型半导体元件、CSP中的任意一种或两种固定。
17.根据权利要求4所述的电路装置的制造方法,其特征在于:上述连接构件由导线焊接或焊料形成。
18.根据权利要求1所述的电路装置的制造方法,其特征在于:上述绝缘性树脂用传递模塑法附着。
19.根据权利要求6所述的电路装置的制造方法,其特征在于:通过切割分离成个别的电路装置。
20.根据权利要求1所述的电路装置的制造方法,其特征在于:上述导电路径是布线图形。
21.一种电路装置,其特征在于:备有
被刻蚀成规定形状的导电路径;
导电性地连接在上述导电路径上的电路元件;以及
被覆上述电路元件及上述导电路径的绝缘性树脂,
上述导电路径的背面的至少一部分从上述绝缘性树脂露出。
22.根据权利要求21所述的电路装置,其特征在于:上述导电路径的侧面呈弯曲形状。
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CN1298203C (zh) * | 2002-12-03 | 2007-01-31 | 三洋电机株式会社 | 电路装置 |
CN1315185C (zh) * | 2002-04-11 | 2007-05-09 | 皇家飞利浦电子股份有限公司 | 包括载体的电子器件和制造该电子器件的方法 |
CN100338749C (zh) * | 2002-04-11 | 2007-09-19 | 皇家飞利浦电子股份有限公司 | 电子器件的制造方法以及电子器件 |
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-
2001
- 2001-01-18 KR KR10-2001-0002826A patent/KR100386520B1/ko not_active IP Right Cessation
- 2001-02-27 TW TW090104486A patent/TW567738B/zh not_active IP Right Cessation
- 2001-03-08 CN CNB011109696A patent/CN1227957C/zh not_active Expired - Fee Related
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CN105990268B (zh) * | 2015-01-30 | 2020-04-07 | 矽品精密工业股份有限公司 | 电子封装结构及其制法 |
CN112652544A (zh) * | 2020-12-22 | 2021-04-13 | 长电科技(滁州)有限公司 | 一种封装结构及其成型方法 |
Also Published As
Publication number | Publication date |
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EP1143509A3 (en) | 2004-04-07 |
EP1143509A2 (en) | 2001-10-10 |
TW567738B (en) | 2003-12-21 |
KR20010088323A (ko) | 2001-09-26 |
US6562660B1 (en) | 2003-05-13 |
CN1227957C (zh) | 2005-11-16 |
KR100386520B1 (ko) | 2003-06-02 |
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