JP2005077955A - エッチング方法およびそれを用いた回路装置の製造方法 - Google Patents
エッチング方法およびそれを用いた回路装置の製造方法 Download PDFInfo
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- JP2005077955A JP2005077955A JP2003310764A JP2003310764A JP2005077955A JP 2005077955 A JP2005077955 A JP 2005077955A JP 2003310764 A JP2003310764 A JP 2003310764A JP 2003310764 A JP2003310764 A JP 2003310764A JP 2005077955 A JP2005077955 A JP 2005077955A
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0369—Etching selective parts of a metal substrate through part of its thickness, e.g. using etch resist
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0502—Patterning and lithography
- H05K2203/0505—Double exposure of the same photosensitive layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0502—Patterning and lithography
- H05K2203/0508—Flood exposure
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0562—Details of resist
- H05K2203/0594—Insulating resist or coating with special shaped edges
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1184—Underetching, e.g. etching of substrate under conductors or etching of conductor under dielectrics; Means for allowing or controlling underetching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/202—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using self-supporting metal foil pattern
Abstract
【解決手段】被エッチング材としての導電箔11の表面にエッチングレジスト10を塗布する工程と、エッチングレジスト10を、露光マスク14を用いて選択的に露光させることにより、エッチングレジストを選択的に変質させて、断面の下部が上部よりも大きい残存領域としての非露光領域10Aを形成する工程と、溶液を用いて残存領域を除いたエッチングレジスト10を除去する工程と、残存領域をマスクとして導電箔をエッチングする工程とを有する。
【選択図】図2
Description
先ず、図1のフローチャートを参照して、本発明のエッチング方法の概要を説明する。
〈回路装置の製造方法を説明する第2の実施の形態〉
次に、図5を参照して、上述したエッチングの方法を用いて製造される回路装置を数種紹介する。図5を参照して、本発明に係る回路装置20の構成を説明する。図5(A)から図5(C)は各形態の回路装置の断面図である。
次に、図6以降を参照して、図5にて説明した構成の回路装置の製造方法を説明する。先ず、図6から図7を参照して、図5(A)に示す構成の回路装置20Aの製造方法を説明する。
10A 非露光領域
10B 露光領域
11 導電箔
12 基板
13 光線
14 露光マスク
15 露光パターン
16 導電パターン
Claims (8)
- 被エッチング材の表面にエッチングレジストを形成する工程と、
前記エッチングレジストを、露光マスクを用いて選択的に露光させることにより、前記エッチングレジストを選択的に変質させて、断面の下部が上部よりも大きい残存領域を形成する工程と、
溶液を用いて前記残存領域を除いた前記エッチングレジストを除去する工程と、
前記残存領域をマスクとして前記被エッチング材をエッチングする工程と、
を有することを特徴とするエッチング方法。 - 前記エッチングレジストはネガ型レジストであり、当該ネガ型レジストの前記残存領域に対応する領域に光線を照射させることで、前記ネガ型レジストを透過して前記被エッチング材の表面にて反射した前記光線により、前記残存領域の断面の下部が、その上部よりも大きくなることを特徴とする請求項1記載のエッチング方法。
- 前記エッチングレジストはポジ型レジストであり、当該ポジ型レジストの除去領域に光線を照射させ、前記除去領域の周辺部に照射される前記光線が前記エッチングレジストの途中で減衰することで、前記残存領域の断面の下部が、その上部よりも大きくなることを特徴とする請求項1記載のエッチング方法。
- 導電箔を用意する工程と、
前記導電箔の表面にエッチングレジストを形成する工程と、
前記エッチングレジストを、露光マスクを用いて選択的に露光させることにより、前記エッチングレジストを選択的に変質させて、断面の下部が上部よりも大きい残存領域を形成する工程と、
溶液を用いて前記残存領域を除いた前記エッチングレジストを除去する工程と、
前記残存領域をマスクとして前記導電箔をエッチングして導電パターンを形成する工程と、
前記導電パターン上に回路素子を配置する工程と、
前記回路素子が被覆されるように封止樹脂を形成する工程と、
を有することを特徴とする回路装置の製造方法。 - 前記エッチングにより、前記導電箔よりも浅い分離溝を前記導電パターン同士の間に形成し、
前記封止樹脂を形成する工程では前記分離溝に前記封止樹脂を充填し、
更に、前記分離溝に充填された前記封止樹脂が露出するまで前記導電箔の裏面を除去する工程を有することを特徴とする請求項4記載の回路装置の製造方法。 - 前記エッチングレジストはネガ型レジストであり、当該ネガ型レジストの前記残存領域に対応する領域に光線を照射させることで、前記ネガ型レジストを透過して前記被エッチング材の表面にて反射した前記光線により、前記残存領域の断面の下部が、その上部よりも大きくなることを特徴とする請求項4記載の回路装置の製造方法。
- 前記エッチングレジストはポジ型レジストであり、当該ポジ型レジストの除去領域に光線を照射させ、前記除去領域の周辺部に照射される前記光線が前記エッチングレジストの途中で減衰することで、前記残存領域の断面の下部が、その上部よりも大きくなることを特徴とする請求項4記載の回路装置の製造方法。
- 前記導電箔は、絶縁層を介して積層された複数層の導電箔を含み、複数層の前記導電パターンが形成されることを特徴とする請求項4記載の回路装置の製造方法。
Priority Applications (5)
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---|---|---|---|
JP2003310764A JP2005077955A (ja) | 2003-09-02 | 2003-09-02 | エッチング方法およびそれを用いた回路装置の製造方法 |
TW93124624A TWI301634B (en) | 2003-09-02 | 2004-08-17 | Etching method and method for making an electrical circuit device using such etching method |
CNB2004100575819A CN1312533C (zh) | 2003-09-02 | 2004-08-20 | 蚀刻方法及使用蚀刻方法的电路装置的制造方法 |
KR20040067381A KR100652099B1 (ko) | 2003-09-02 | 2004-08-26 | 에칭 방법 및 그것을 이용한 회로 장치의 제조 방법 |
US10/928,900 US20050101136A1 (en) | 2003-09-02 | 2004-08-27 | Etching method and method of manufacturing circuit device using the same |
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JP2003310764A JP2005077955A (ja) | 2003-09-02 | 2003-09-02 | エッチング方法およびそれを用いた回路装置の製造方法 |
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JP (1) | JP2005077955A (ja) |
KR (1) | KR100652099B1 (ja) |
CN (1) | CN1312533C (ja) |
TW (1) | TWI301634B (ja) |
Cited By (1)
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US7670949B2 (en) | 2006-03-27 | 2010-03-02 | Seiko Epson Corporation | Semiconductor device and method of manufacturing semiconductor device |
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US8641913B2 (en) * | 2003-10-06 | 2014-02-04 | Tessera, Inc. | Fine pitch microcontacts and method for forming thereof |
US8207604B2 (en) * | 2003-12-30 | 2012-06-26 | Tessera, Inc. | Microelectronic package comprising offset conductive posts on compliant layer |
KR101388538B1 (ko) | 2007-09-28 | 2014-04-23 | 테세라, 인코포레이티드 | 이중 포스트를 사용하여 플립칩 상호연결한 마이크로전자 어셈블리 |
US8330272B2 (en) | 2010-07-08 | 2012-12-11 | Tessera, Inc. | Microelectronic packages with dual or multiple-etched flip-chip connectors |
US8580607B2 (en) | 2010-07-27 | 2013-11-12 | Tessera, Inc. | Microelectronic packages with nanoparticle joining |
US8853558B2 (en) | 2010-12-10 | 2014-10-07 | Tessera, Inc. | Interconnect structure |
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US9633971B2 (en) | 2015-07-10 | 2017-04-25 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
US10886250B2 (en) | 2015-07-10 | 2021-01-05 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
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- 2004-08-17 TW TW93124624A patent/TWI301634B/zh not_active IP Right Cessation
- 2004-08-20 CN CNB2004100575819A patent/CN1312533C/zh not_active Expired - Fee Related
- 2004-08-26 KR KR20040067381A patent/KR100652099B1/ko not_active IP Right Cessation
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US7670949B2 (en) | 2006-03-27 | 2010-03-02 | Seiko Epson Corporation | Semiconductor device and method of manufacturing semiconductor device |
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US20050101136A1 (en) | 2005-05-12 |
KR20050025285A (ko) | 2005-03-14 |
KR100652099B1 (ko) | 2006-12-06 |
CN1312533C (zh) | 2007-04-25 |
CN1591191A (zh) | 2005-03-09 |
TW200511391A (en) | 2005-03-16 |
TWI301634B (en) | 2008-10-01 |
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