TWI301634B - Etching method and method for making an electrical circuit device using such etching method - Google Patents

Etching method and method for making an electrical circuit device using such etching method Download PDF

Info

Publication number
TWI301634B
TWI301634B TW93124624A TW93124624A TWI301634B TW I301634 B TWI301634 B TW I301634B TW 93124624 A TW93124624 A TW 93124624A TW 93124624 A TW93124624 A TW 93124624A TW I301634 B TWI301634 B TW I301634B
Authority
TW
Taiwan
Prior art keywords
photoresist
etching
region
conductive
layer
Prior art date
Application number
TW93124624A
Other languages
English (en)
Other versions
TW200511391A (en
Inventor
Shinya Mori
Original Assignee
Sanyo Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co filed Critical Sanyo Electric Co
Publication of TW200511391A publication Critical patent/TW200511391A/zh
Application granted granted Critical
Publication of TWI301634B publication Critical patent/TWI301634B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • H05K3/064—Photoresists
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68377—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0369—Etching selective parts of a metal substrate through part of its thickness, e.g. using etch resist
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0502—Patterning and lithography
    • H05K2203/0505—Double exposure of the same photosensitive layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0502—Patterning and lithography
    • H05K2203/0508—Flood exposure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0562—Details of resist
    • H05K2203/0594—Insulating resist or coating with special shaped edges
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1184—Underetching, e.g. etching of substrate under conductors or etching of conductor under dielectrics; Means for allowing or controlling underetching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/202—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using self-supporting metal foil pattern

Description

1301634 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種蝕刻方法，以及使用該方法之電路 裝£之製造方法，尤有關一種可提高蝕刻因數（etching factoi )的钱刻方法，以及一種使用該方法之電路裝置之製· 造方法。 , 【先前技術】 以下參照第11圖說明習知的蝕刻方法。 翏照第11圖（A)，於基板102的表面形成導電箔i 〇丨。鲁 然後’塗佈飿刻甩光阻劑100(photoresist，光敏抗蝕劑， 依一般通用稱法’簡稱為光阻劑）俾覆蓋導電箔1〇1表面。 γ參照第11圖（B) ’透過曝光遮罩（mask)(無圖示），將 光阻劑100予以選擇性曝光。於此，光阻劑1〇〇係為負型 光阻劑’亚係將光線！ 〇3選擇性地照射至對應於作為導電 圖樣之殘存區域的光阻劑1⑼。 二麥照第11圖（C) ’使用藥劑而進行溶融處理，從而將 前步驟中光線照射處以外的區域的光阻劑100予以選擇二# 剝離。健，參照第u圖⑼，將殘存下來的光阻劑_ 當作遮罩，而進行姓刻。結果，將導電落101予以選擇性 移除，而形成導電圖樣103。於此，由於蝕刻處理係採用 以大略等向性(isotropic)進行處理的濕式蚀刻，因 樣103的剖面即變成梯形。 導书圖 參照第11圖⑻說明蝕刻因數。於此，將導電圖樣⑽ 則面之被侵餘至最内側處和光阻劑上側端部間的距離當作 316161 5 1301634 al逖有，將導電箔101於縱方向被侵蝕的深度（於此亦 即為導電圖樣1G3的厚度）當作t。在此條件下，餘刻因 數Ef心以【Ef=t/al】來表示。亦即，該蝕刻因數的值較 大的洁，表示被蝕刻材的側蝕刻量較小，而可進行微細加 此外’此種敍刻方法係應用於印刷基板或 的製造方法。 寻 1日月欲.經^的問顳 /然而’上述之钱刻方法係具有蝕刻因數的值會變小的 問題。亦即，由兹刻造成之側方向的侵蝕較大，而使導带 =舞嶋 I田化。而且，會有導電圖樣的剖面變小 變小的問題。 优电机今里 【發明内容】 種使用该方法之電路裝置製造方法。 題的方法 本發明之姓刻方法的步驟係包括：在被蝕材 成钕刻光晴的步驟；使用曝光遮罩對前述烟光阻= 订選擇性曝光，而使前述蝕刻光 θ進 擇性變質’而形成 =下桃上部大的殘存區域的步驟；使用溶液 义 钱存區域以外之前述㈣光轉予以除去驟:了則 及，將前述殘存區域當作遮罩，而對^ ，以 刻的步驟。 +核_材進行姓 316161 6 1301634 本發明之電路裝置製造方法 落的步驟，·在前述導電箔表 “包括：準備導電 用曝光遮罩對前述钱刻光阻劑進行阻劑的步驟’·使 飯刻光阻劑選擇性變質，而彤、立、 曝光，而使前述 區域的步驟，'使甩溶液將除； 刻光阻劑予以徐去的步騾存&域以外之前述蝕 前述電路元件的步驟。 ’形成密封樹脂俾覆蓋 【實施方式】 1 首先’參照第1圖的流 概要。 口 h巩耘圖况明本發明的蝕刻方法之 入;^ ’步驟S1係進行被|刻村料（被飯刻材）的投 入於此，可採甩由金屬形、 層則祕積層板、或在緣層層疊（積 為投入材料。然後，步二2:上，塌 ^ ± ^ ^ ^ 知S2進仃則處理而將附著於被蝕 刻材表面塵i矢或油脂成分予以去除。 丄步驟S3係在被钱刻材表面形成光阻劑。可藉由液狀 光阻劑的塗佈、或是片狀光阻劑⑺，簡稱 DFR)的貼置來形成該光阻劑。於此所使用的光阻劑可為 負型光阻劑或是正型光阻劑中的任一種。步驟s4係進行 已塗佈之光阻劑的撰傳从 k擇丨生曝先。然後，步驟S 5係使用蝕 刻劑進行光阻劑的撰媒从 、擇拴蝕刻，其後，步驟S6係進行光 7 316161 1301634 阻剑的硬化。於此，本發明也可為將光阻劑之硬化步 予以省略而構成者。 1 2驟S7係使用蝕刻液’將殘存之光阻劑使用為蝕刻 遮罩來進行被蝕刻材的蝕刻。然後，步驟S8係使用溶液 來進行光阻劑的剝離。步驟S9係進行被蝕刻材的水洗乾 ^並結束飿刻步驟。於此’也可在進入步驟S8時同聍 進行步驟S9 〇 寸 該圖式之流程圖右側所示者係為顳示於上述步驟S5 使用之曝光遮罩之製造步驟的流程圖。步驟sl〇係取得使 用者的式樣和厨面，而進行電氣電路的設計。步驟s 11係 使用電腦输助設計（computer Aided Design，簡稱 而進行拫據電氣電路之導電圖樣的設計。步驟s i2係使用 描繪裳置來描翁導電圖樣。步驟S! 3係為使對應於導電圖 ^ ^ ^ ^ ϋ ^ , ^ Λ ^ ^ t ® # a ^ ^ H ^ it ^ ^ ^ ^ 形成曝光遮罩。 以上係為本發明之蝕刻步驟的概略說明。其次，表照 第2圖至第4圖詳細說明將蝕刻光阻劑予以圖樣化的步驟 (步驟S5至步驟S6)。首先參照第2圖及第3圖說明使蝕 刻光阻劑曝光的步驟。 /恥第2圖來說明進行負型光阻劑之光阻劑1 〇的曝光 之方法。負型-光阻劑原本係由可溶解於鹼性溶液中的材料 冓成並具有被光線知、射之部分會變成不溶性的性質。 翏舨第2圖（A)，做為被蝕刻材的導電箔丨丨係形成於 基板12的表面，而光阻劑1〇則塗佈於導電箔u的表面。 316161 8 1301634 阻劑1 〇。於此，也可使 於此’係採用負型光阻劑來做為光 用正型光阻劑來取代負型光阻劑。 =、弟2圖（B)，使用曝光遮罩14對光阻劑」〇進行選 ^:光。具體而言’係將對應於做料電圖樣之殘存區 或的光阻劑1G予以曝光，並將其他區域予以遮光。亦即， 將先阻劑10的曝光區域10]B予 κ Hϋ卞以邊存，而在顯像步驟時 粉非曝无區域i Q Α予以移除。非睛 夕丁、升曝先跑域10A的具體移除 万法係為，首先，將光阻劑丨〇浸 、、、、 /又，包於顯像液中，從而膨脹 潤'非曝光區域1 〇 A 〇然德，音田卜同 a, 、俊利用水壓將已膨賬潤濕的非 曝光區域10A予以移徐。 由本先遮罩14係具有：構成基材的破璃，以及形成於該 膜狀薄板來做為基材。亦即，對應於_性剝離區域來形 成爆光圖樣15。由此，將如此構成之曝光遮|14介置於 光阻劑ίο的上方’並從上方照射光線13，從而能夠將光 線13選擇牲地僅照射於形成導電圖樣之區域的光阻劑 10。於此’將諸曝光圖樣間的間隔距離當作L1。 第2圖(〇係為第2圖（3)的擴大圖，係顯示曝光區域 10B的具體剖面形狀。照射至光阻劑1〇之曝光區域ι〇β 的光線13的一部份會穿透光阻劑1〇而到達導電羯1丨的表 面。然後，光線13即被導電箔u的表面反射。特別是， 在曝光區域10B周邊部分的區域A1會以朝向外側的方式 在斜上方反射光線13。由於光線13的反射成分，使得區 域A1也會被曝光。從而，曝光區域1〇β的剖面會具有其 316161 9 1301634 下部較上部大的寬裙狀剖面。換言之，曝光區域刚 面的下方底部長度較上方頂部長度來得長。 使區域A1曝光的具體方法有：為了、使通過光阻劑10 多光線13的成分透過光阻劑1 〇，並被带 射，而使區域A1曝光。此外，藉由採用^於 、八面反 一 稭由抓用對於光線13且有 南透過性之材料當作光阻劑1G，能夠達到，的效果: 其次m 3 ®詳細彻正型級劑 劑1 〇時的曝光方法。正型光阻劑係具有原本不會溶 質’而麵 參照:第3圖（A)’在形成於基板12表面的導電m 的表面上，係塗佈有正型光阻劑1〇。 / ^參照第3圖(B)，使用曝光遮罩14進行光阻劑ι〇的 述之第2_及其朗中，係使先_1G之預 疋奴存的區域曝光’而於此係使光阻劑1〇之欲除去之區域 曝光。亦即沒有形成導電圖樣之區域的光阻们〇予以 曝光並使其產:生變質。因此，曝光遮罩14係形成有與預定 也成之導電圖樣為同一形狀的曝光圖樣Μ。 刀参照弟3圖（C)詳細說明非曝光區域1〇A。於此，沒 ，射光線13的非曝光區域1〇A係當作姓刻遮罩而殘存下 二。「因广，係將光線照射至光阻劑1G之部份欲除去區域（曝 ^域10B)。而在曝光區域應的周邊部，光線13並不 冒到達光阻劑10的下部。亦即，曝光區域_周邊部的 316161 1301634 下方不會曝光，而不會產生變質。因此，非曝光區域i〇a 的剖面形狀係形成與第2圖（C)所示之曝光區域應同樣的 形狀。亦即，非曝光區域10A的剖面的下部比其上部大。 具體而$ ’使區域A1曝光的方法有：減少光線13之 1〇β^ 部的先線13的照射減少，而能夠減少到達區域ai之光線 晴量。此外，其他的方法還有增加光阻劑Μ之遮光性 之方法’此種方法也能夠達成上述效 時間也能夠達成上述效果。縮且*光 面形狀之光阻劑的形成方法。麸
Kbmm + β …、，對/、他蝕刻條件加以 ^ ^ λ # ^ ^ ^ ^ ^ ^ ^ ^ 〇 ^ ^ ^ 法有·將顯像液濃度予以變化 種類予以變化的第2方法的弟1方法卜而 ^ ^^ ^11 ^^ ^ ^ ^ ^ ^ i, ^ tb ^ t =方广通常的顯像液係為， 的比率溶解於绝水中的溶液^而n是，將有機胺以1% 便能夠迅速地進行光11由將此濃度予以提高， 使殘存下來之先阻丄丨 的溶解或者膨潤。因此，能夠 狀。未之先阻刮10的剖面形狀形成寬祿狀的剖面形 將顯像液種類予以變化 鈉溶液而使用有機胺系溶 方法係為，不使用碳酸 的方法。有機胺系水溶液比碳 316161 11 1301634 酸鈉水溶歸更強的侵㈣。因此，能夠使綠 面形狀形成寬裙狀的剖面形狀。 的4 參照第4圖詳細說明顯影步驟以後的步驟。 參照第4圖㈧，藉由進行顯影而進行光 樣化。具體而言’係藉由將已曝光之光阻㈣= 而使對應於預定形叙導電圖制區域的光彳=， 下來，並將其他區域的光阻劑lc•予以移除j 存 劑1〇浸泡於驗性溶液中而進行此種處理。因此^ _)所示之絲劑心，曝光區域聰 在第3圖（B)所示之光阻劑 二存下來，而 下來。 巾_讀域魏會殘存 其次，參照第4圖（B)，將已殘存下來之阻齊卜 作㈣遮罩，而進行導電I關關，而形成圖=虽 於此等向性（i吻㈣所進行的 刻來。 圖樣16。從而將各圖樣16予以分離。 成 面彻說明業已於上述步驟形成之圖樣的剖 ^狀^由濕式細所形成之圖樣B的側面係形成梯形 面^此即，圖樣16係具有下底比上底長的矩形形 面。於此’將光阻劑1G之上部端部和圖樣16之上部^ ==广。_樣16從下端到上端為止的距^厚 度）“乍t。如此，便可用[晌/a2]來表示韻刻因數时。 於此，觀察光阻劑10的剖面時，可 有寬竭區域A1。亦即和第u圖⑻之習知例= 發現光阻劑則下側端部係朝外部擴張比寬讀區域^ 316161 12 1301634 ^出見度d。因此，光阻劑上側端部和圖樣16上側端部間 的距離32係縮短比區域^之寬度有d之距離之差距。因 此，於此之钮刻因數阶系能夠增加對應於d之寬度的數 值。亦即，圖樣16之側部可藉由等向性之㈣而形成 知例同程度的梯形形狀。然而，由於區域亂的擴張因 此光阻劑10上側端部和圖樣16上側端部間白 距離能夠更為接近。如 t、方向 細化的程度。 七棘…，而能夠提升微 通t補㈣韻樣14屬㈣罩 逸 的提升。具體而言，在光阻劑丨。係為負型 细：：因V讀由縮小曝光圖樣的寬度L2 ’而達成此種微 要^=此’若藉由此種方法提升微細化之方^ 之太i %、先遮罩16之描繪裝置而必須有巨額的成本。上述 10 T ,, L ^ ^ ^ ^ ^ ^ ® ^ 15 ^ ^ ^ ^ ^ m ^ t /品域A1 ’便旎夠縮小諸圖樣16的間隔。並且， 广於:夠增加圖樣16的截面積，能夠提高電流容量。 製造方法的第2 f施刑能 的電t w ^ ® μ _用上義刻方法所製造 的構成二7照弟5圖說明有關本發明之電路裝置20 剖視圖。 ㈧至第5圖(C)係為各型態的電路農置的 查》日刀楚 c 圖才/?1 圖（A)’本發明之電路裝置20A係具有導電 水、透過銲錫固著於導電圖樣21的電路元件、做 316161 1301634 為連接手段用而將導電圖樣21和 外部電極27。 卜°卩間予以電氣連接的 導電圖樣21係由銅等金屬所 埋藏於密封樹脂28中。此外 使，、内面路出而 α, 01 ^ 卜错由分離溝29將各導電圖 樣21予以電氣分離，並將密 、 29中。導雷円择y 了舳28充填於該等分離溝 .〇1 圖榼21的側面係形成彎曲狀，而提升導電圖 樣2 i和密封樹脂28間的結合姓。 ’ θ 能。=溝Μ:具有將各導電圖樣21予以電氣分離的功 匕 卜’该等分離溝係藉由上述之蝕 、/ 1 P由月請使諸導電圖樣21間的彼此間之 此月能1^大導電圖樣21的寬度而使截面積變大，因 此月匕夠棱南電流容量。 件22:::盖Ϊ路凡件22係由半導體元件22A以及晶片元 :::曰：(bare t_lstor chip )、，
电：。此外’亦能夠採用晶片電阻或晶片電容等被動 =北田作電路终。具體的組裝構造係將半導體元件22A 著於由導電圖樣21形成的銲接墊上。㈣，透過 至屬細線2 5將半導辦开| 0 0 λ叙t h ¥ 件22A表面的電極和導電圖樣21 曰】予以電氣連接。晶片开杜 著於導電圖樣21上件2B兩端的電極係透過薛錫固 “'密封樹脂28係由藉由射出成型形成的熱塑性樹脂，或 疋稭由轉移成型（transfermGlding)形成的熱硬化性樹脂 316161 14 1301634 而密封樹脂28除了具有將全體予以密封的作用 係由銲B:Z有將全體予以機械支持的功能。外部電極27 由杯=構成，而形成於導電圖樣21的背面。 成俜：:::圖⑻’於該圖所示之電路裝置_的基本構 係二異點係電路裝置廳 採周具有優異散熱性、絕佳機械強為持 :板:， ς==鱗，#採用^料導電性_構成的基板時， /、表面设置絕緣層以進行和導電圖樣21間的絕緣。 持美麵樣21Α以及第2導祕 土板1的表面以及背面。然後，將支持基板31予以貫 « 1 ^ f s # 21Α #σ f 2 ^ m 21B ^ ^ ^ ^ 爲連接。此外，於第2導電圖樣21B形成外部電極27。= =’由於第1以及第2導電圖樣21A、21B也 ^法所形成，因此能夠使圖樣間的寬度變窄.，而能夠促進 微細化。 參照第5圖（C)，在電路裝置2〇c巾，導電圖樣21係 具，多層線路結構。具體而言，由第」導電圖樣2ia和第 2導電圖樣21B所形成的2層導電圖樣係逸過由樹脂形成 之絕緣層32而疊層成形。於此，也可進—步構成3層以上 之線路構造。然後’將絕緣層32予以貫通，並將第丄導電 圖樣21A和第2導電圖樣21B間予以電氣連接。於此，由 於也藉由上述蝕刻方法形成第i以及第2導電圖樣21八、 316161 15 1301634 從而能夠促進微細 21β ’因此能夠使圖樣間的寬度變窄， 化0 二’參照第6圖以後的圖式，說明已藉由第5圖說 月叙構級f路裝置製造方法。首先，參 ^㈣第5圖⑷所示之構成之電路W的製造方 ^尿6圖(A)，最減製備击鋼等金屬構成的導 列^着’如第6圖⑻所示，在形成導電圖樣 後’藉由濕式_，將從刻光二 二：表面予以移除’從而形成分離溝2 9。 ：ΓΓ29^^ 於此’由於光阻劑叹係具有上述 成 此能夠提升__。 見裙狀韻形狀，因 心參照第6 _)，透過銲錫等接合材料將半 Α :及晶片元件删固著於預定之㈣ 電圖樣以間予以電氣2 件抓表面之電極和導 29中其第7圖，形成密封樹脂Μ而充填於分離溝 成型$路元件。可藉由❹熱硬讀樹脂的轉移 2或疋使隐塑性樹脂的射出成型來形成此密封樹脂 其次’參照第7圖⑻，將導電落3〇從背面予以入 ，移除(back etch)，從而使業已充填於分 ： 樹脂㈣背面露出，而將各導電圖樣21予以電=，」 316161 16 1301634 接著，形成光阻劑26，以及形成外部電極 第7圖⑹所示之電路裝置30A。 &27’<而形成如 其次，參照第8圖至第10圖說明第 20C ^ 0 , g ? 透過絕緣層22層疊第！導電落33以 衣備 層板。 矛2泠书泊34的積 梦其次’參照第8圖⑻，將第！導電们3予 和除，從而形成貫通孔35。藉 、伴性 _方法來繪卜卜# 猎由使H阻劑1G的濕式 4方法末進灯此步驟。於此所使用.的光阻劑仞 Λ 的面積。因此’能夠將其他區域使用為 的小型化。 此約K現爰置全體 、备之，參照第8圖（〇，將貫通丨 層夠㈣ 可使用二氧化二到達第2導電'落34的表面。 後，將光=Γ〇νΐ^Γ㈣“的移除步驟。其
^ ^ ^ 〇 ^ , # a, f 9 ^ ^ ^ "，J 成在貫通孔35中形;J 33和：_ ”予以電氣連將弟1導電羯 2導電落34進圖=為了對第1導㈣33以及第 刻光㈣从。由於係以在表面選擇性地形成钱 长卑1 η施型態說明過之方法形成 316161 1301634 該蝕刻光阻劑10’因此該蝕刻光阻齊，丨1〇係具有寬裙狀的 剖面形狀。 之，參照第9圖（C)，藉由濕式餘刻形成第工導電圖 二有=狀的，面形狀’因此能夠形成微細化的導電圖 後，將先阻劑1〇予以移除，而得到如第9圖⑼所
不之剖面形狀。 Μ、厂J
22Β ? 22A 件22B固者於^第1導雷圖择 ⑻，，卜然後，參照第10圖 形成赛封树脂28而將半導體元件 一 22B ^ ^ ^ ^ 5 « * ,U ^ ^ ^ # 5圖（C)所示之電路裝置。 处，教而完成如第 依據本發明，可形成具有丨 劑，並獅該光_ 丨狀之。彳面雜的光阻 式钱刻。因此， 為4遮罩而進行非蝕刻材的濕
此夠進行蝕刻因數 B t藉由則形成之導電圖樣的微細化。Λ。逛有，能夠進 【圖式簡單說明】 第1圖係為表示本發 第2圖⑷至(C)係為顯示本二方:::程圖； 第3圖㈧至（c)係 ^月之姓刻方法剖視圖； 第4圖⑷至_為：2明之韻刻方法剖視圖； 第5圖㈧至（c ti 發明之钱刻方法剖視圖； 的剖視圖； 糸為顯示本發明之電路裝置 製造方法 316161 18 l3〇l634 的剖視圖； 的剖^圖⑷至⑹係為顯示本發明之電路裂置製造方法 第8圖(A)至(D)係為顯示本發明之電路裝 的剖視圖； 置製造方法 顯示本發明之電路裝置製造方法 第9圖(A)至（D)係為 的剖視圖； 第魏圖(A)及⑻係為顯示 之 法的剖視圖；以及 X月之電路駿置製造方 第11圖(A)至（E)係為顯 【主要元件符號說明】 10 光祖劑 10B 曝光區域 12 基板 14 曝光遮罩 16 導電圖樣 20A、 20B、20C、30A 21 專電圖樣 21B 第2導電圖樣 22A -半導體元件 25 金屬細線 27 外部電極 29 分離溝 示習知蝕刻方法的剖視圖。 10A 非曝光區域 11 導電箔 13 光線 15 曝光圖樣 電路裝置 21A 第1導電圖樣 22 絕緣層 22B 晶片元件 26 光阻劑 28 密封樹脂 30 導電箔 316161 19 1301634 31 支持基板 32 絕緣層 33 第1導電箔 34 第2導電箔 35 貫通孔 36 連接部 100 光阻劑 101 導電箔 102 基板 103 光線 D 見度 Τ 深度 A1 區域 al 距離 LI、L2、L3 距離 PR 光阻劑 SI 步驟1 S2 步驟2 S3 步驟3 S4 步驟4 S5 步驟5 S6 步驟6 S7 步驟7 S 8 步驟8 S9 步驟9 S10 步驟10 S11 步驟11 S12 步驟12 S13 步驟13
20 316161

Claims (1)

1301634 第93124624號專利申請案 申請專利範圍修正本 (95年3月21日） I 一種蝕刻方法，包括下列步驟： 在由包括銅在内之金屬而成之被蝕刻材表面形成 蝕刻光阻層的步驟； 將經圖樣化之前述蝕刻光阻層予以選擇性地曝光 而使其變質，以形成剖面下部比上部大之殘存區域:步 驟； 將除了前述殘存區域以外的前述钱刻光阻 ' 移除的步驟； 曰 將前述殘存區域當作遮罩，而對前述被㈣材進行 濕式餘刻的步驟，以及 精由在前述濕式蝕刻的步驟使前述殘存區域之 側端部向外側凸出，而提高蝕刻因數者。 2.如申凊專利範圍第1 ^ 鄉刎万去，其中，前述蝕刻光 阻#之〜+、，— 便射至對應於該負型光 :層之^殘存區域的區域，而藉由穿透前述負 層而被前述被蝕刻材表面所 、 殘存區域的剖面下部比該剖面上部，使得前述 μ '、為 絲層，並使紐照射n·光阻声的 =區域’而藉由照射至前述殘存區域周邊 線在前述蝕列本阳庶X门透口Ρ的則述先 χ ㈢纟途中的衰減，使得前述殘存區域 (修正版)316】61 1301634 的剖面下部比該剖面上部大。 4.-種電路裝置製造方法，包括下列步驟： 由包括銅在内之金屬而成之導電落的步驟，· 在=述導電箱表面形絲刻光阻層的步驟； •將W述㈣光阻層予以選擇性地曝光，而使盆變 二樣化之編刻光阻層之剖面下部：上 1 Α之殘存區域的步驟； 雨述敍刻光阻層 予以
將除了前述殘存區域以外的 移除的步驟； 將前述殘存區域當作遮罩，而將前述導電箔予以渴 式儀刻而形成導電圖樣的步驟； “、 在前述導電圖樣上配置電路元件的步驟； 形成密封樹脂而將前述電路元件 酿：π 丨卞卞以覆盍的步 5. 藉由在前述濕式韻刻的步驟使前述殘存區域戈 側端部向外側凸出’而提高蝕刻因數者。
如:請專利第4項之電路裝置製造方法，其中， '前述蝕刻在諸前述導電圖樣彼此之間形成比、前述 電箔淺的分離溝， 在形成前述密封樹脂的步驟將前述密 於前述=溝中，而該電路裝置製造方法的步驟復包充括真 將前述導電ϋ的背面予以移除，直到業已充填於前 处/刀離溝中之前述密封樹脂露出為止的步騍。 I如申请專利範圍第4項之電路裝置製造方法，其中，前 (修正版）316161 1301634 圮蝕刻光阻層係為負型光阻層，並使光線照射至對應於 該負型光阻層之前述殘存區域的區域，而藉由穿透前述 f型光阻層而被前述被蝕刻材表面所反射的前述光 | ’使件w述殘存區域的剖面下部比該剖面上部大。 如申請專利範圍第4項之電路裝置製造方法，1中，前 述蝕刻光阻層係為正型光 、 光阻層的移除區域，畔二ί使:線照射至該正型 &+、丄向猎由妝射至珂述殘存區域周邊部 勺料光線在剛述㈣光阻層的途中的 殘存區域的剖面下部比該剖面上部大。 " 8.如申請專利範圍第4項之電路裝置 述導電箔係包括透過絕緣層 /八，則 形成有複數層之前述導電=：=層的後數層導電箱’並 (修正版）316161 3 1301634 糾年7月扣日修(更)正替換頁I (A) 100 101 102
(B)
100 101 1〇2
(C)
100 101 -j Q2 (D)
(E)
第11圖 11
TW93124624A 2003-09-02 2004-08-17 Etching method and method for making an electrical circuit device using such etching method TWI301634B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003310764A JP2005077955A (ja) 2003-09-02 2003-09-02 エッチング方法およびそれを用いた回路装置の製造方法

Publications (2)

Publication Number Publication Date
TW200511391A TW200511391A (en) 2005-03-16
TWI301634B true TWI301634B (en) 2008-10-01

Family

ID=34412505

Family Applications (1)

Application Number Title Priority Date Filing Date
TW93124624A TWI301634B (en) 2003-09-02 2004-08-17 Etching method and method for making an electrical circuit device using such etching method

Country Status (5)

Country Link
US (1) US20050101136A1 (zh)
JP (1) JP2005077955A (zh)
KR (1) KR100652099B1 (zh)
CN (1) CN1312533C (zh)
TW (1) TWI301634B (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7495179B2 (en) * 2003-10-06 2009-02-24 Tessera, Inc. Components with posts and pads
US7462936B2 (en) * 2003-10-06 2008-12-09 Tessera, Inc. Formation of circuitry with modification of feature height
US8641913B2 (en) * 2003-10-06 2014-02-04 Tessera, Inc. Fine pitch microcontacts and method for forming thereof
US8207604B2 (en) * 2003-12-30 2012-06-26 Tessera, Inc. Microelectronic package comprising offset conductive posts on compliant layer
JP2007266030A (ja) 2006-03-27 2007-10-11 Seiko Epson Corp 半導体装置の製造方法および半導体装置
KR101388538B1 (ko) 2007-09-28 2014-04-23 테세라, 인코포레이티드 이중 포스트를 사용하여 플립칩 상호연결한 마이크로전자 어셈블리
US8330272B2 (en) 2010-07-08 2012-12-11 Tessera, Inc. Microelectronic packages with dual or multiple-etched flip-chip connectors
US8580607B2 (en) 2010-07-27 2013-11-12 Tessera, Inc. Microelectronic packages with nanoparticle joining
US8853558B2 (en) 2010-12-10 2014-10-07 Tessera, Inc. Interconnect structure
JP6099370B2 (ja) * 2012-11-21 2017-03-22 Ｓｈマテリアル株式会社 半導体素子搭載用基板及びその製造方法
US9633971B2 (en) 2015-07-10 2017-04-25 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US10886250B2 (en) 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5098864A (en) * 1989-11-29 1992-03-24 Olin Corporation Process for manufacturing a metal pin grid array package
US5447810A (en) * 1994-02-09 1995-09-05 Microunity Systems Engineering, Inc. Masks for improved lithographic patterning for off-axis illumination lithography
KR0148610B1 (ko) * 1994-07-28 1998-12-01 김주용 반도체 소자의 패턴 형성방법
US6753584B1 (en) * 1997-08-21 2004-06-22 Micron Technology, Inc. Antireflective coating layer
US6224711B1 (en) * 1998-08-25 2001-05-01 International Business Machines Corporation Assembly process for flip chip package having a low stress chip and resulting structure
US6380611B1 (en) * 1998-09-03 2002-04-30 Micron Technology, Inc. Treatment for film surface to reduce photo footing
WO2000059275A1 (fr) * 1999-03-26 2000-10-05 Matsushita Electric Works, Ltd. Procede et systeme de traitement d'un lamine recouvert de metal pour carte a circuit imprime
US6451627B1 (en) * 1999-09-07 2002-09-17 Motorola, Inc. Semiconductor device and process for manufacturing and packaging a semiconductor device
JP2001308002A (ja) * 2000-02-15 2001-11-02 Canon Inc フォトマスクを用いたパターン作製方法、及びパターン作製装置
US6238952B1 (en) * 2000-02-29 2001-05-29 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
US6562660B1 (en) * 2000-03-08 2003-05-13 Sanyo Electric Co., Ltd. Method of manufacturing the circuit device and circuit device
US6372539B1 (en) * 2000-03-20 2002-04-16 National Semiconductor Corporation Leadless packaging process using a conductive substrate
JP4954401B2 (ja) * 2000-08-11 2012-06-13 株式会社半導体エネルギー研究所 半導体装置の製造方法
CN1216285C (zh) * 2001-08-10 2005-08-24 Hoya株式会社 灰调掩模缺陷检查方法及装置和光掩模缺陷检查方法及装置
US7035448B2 (en) * 2001-08-20 2006-04-25 Hoya Corporation Method of defect inspection of graytone mask and apparatus doing the same
US6713404B2 (en) * 2002-03-05 2004-03-30 Micron Technology, Inc. Methods of forming semiconductor constructions
US6534859B1 (en) * 2002-04-05 2003-03-18 St. Assembly Test Services Ltd. Semiconductor package having heat sink attached to pre-molded cavities and method for creating the package
US7119031B2 (en) * 2004-06-28 2006-10-10 Micron Technology, Inc. Methods of forming patterned photoresist layers over semiconductor substrates

Also Published As

Publication number Publication date
US20050101136A1 (en) 2005-05-12
KR20050025285A (ko) 2005-03-14
KR100652099B1 (ko) 2006-12-06
JP2005077955A (ja) 2005-03-24
CN1312533C (zh) 2007-04-25
CN1591191A (zh) 2005-03-09
TW200511391A (en) 2005-03-16

Similar Documents

Publication Publication Date Title
TWI343766B (en) Printed circuit board
TWI301634B (en) Etching method and method for making an electrical circuit device using such etching method
TWI360210B (en) Interposer and electronic device using the same
JP2006324489A (ja) チップコイル及びその製造方法
KR101519760B1 (ko) 금속 배선의 형성 방법 및 이에 의해 제조된 금속 배선 기판
JP6508333B2 (ja) 電子回路モジュール
CN109273483B (zh) 显示基板及其制备方法和显示装置
KR100258655B1 (ko) 접촉구조 형성방법
TWI304313B (en) Method for manufacturing a circuit board without incoming line
TW200828472A (en) Method for fabricating a circuit
JP2016514909A (ja) 酸化層を備える低コストインターポーザ
TW201126623A (en) Circuit board and method of manufacturing the same
TW200945519A (en) Substrate structure having fine circuits and manufacturing method thereof
JP2006041332A (ja) 半導体装置の製造方法
CN106851977B (zh) 印刷电路板及其制作方法
CN107785307B (zh) 具有台阶型的氮化钛图形的制造方法
TWI361483B (en) Aluminum oxide-based substrate and method for manufacturing the same
JP2008085238A (ja) 貫通電極付き基板の製造方法、及び貫通電極付き基板
TW200835411A (en) Circuit structure and process thereof
TWI787983B (zh) 印刷電路板結構及其製造方法
JP2006030230A (ja) 半導体装置の製造方法
KR100598308B1 (ko) 반도체 소자의 다마신 패턴 형성방법
TWI236320B (en) Method of forming sheet having foreign material portions used for forming multilayer wiring board and sheet having foreign portion
TWI333245B (en) Method for selectively thinning conductive layer
KR20050109653A (ko) 빌드업 기술을 이용한 반도체 실장기판의 제조방법

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees