丄叫245 九、發明說明·· 【發明所屬之技術領域】 方法，其特別是關於 本發明係有關於一種製作線路所需之導電層的 一種製作細線路所需之導電層的方法。 【先前技術】 電路設計與電路板上之元件的尺寸朝向縮小的方向發展如何製作出 縮小尺寸的電路載板亦成為重要課題之一。 舉例來說’第-A至第-D圖為傳統製作细線路(fine灿比加⑺) 的剖面不意圖。參照第-A圖，多層板完成内層至錄孔銅的步驟，多層 板包含若干線路層112(此處亦包含接地層）與兩相鄰線路層ιΐ2之間的絕 緣層no。經過傳統的濕製程步驟，於通孔118之側壁鑛上孔銅ιΐ6。於 形成孔銅116時’多層板的外層導電層，即所謂的基銅上亦會鑛上銅而 形成面銅114。 之後，利職脂或其_當醜緣獅⑽對觀ιΐ8進行塞石 ㈤卿㈣的麵，細避免孔銅116於後續步财流失如第一 B圖 所不。為了確保絕緣材料12〇填滿通孔118，因此一般通孔ιΐ8中的絕緯 材料120會凸出於_ 114之上。參縣—⑽為了抑化表面，一 般利用刷磨tonding)的物理方法到除凸出於面銅ιΐ4之上的絕緣材料 120。接耆，再利用化學_的濕钱刻方式薄化面銅山將面銅⑴的 銅層厚度降低才可進行後續的細線路製作，如第_ d圖所示。其中，由 於薄化咖_騎於絕賴料伽縣_或移_乍用， 5 因此當面銅114薄化之後，造成通孔118中的絕緣材料12〇再度凸出於 溥化的面銅114之上。如此一來，於進行後續的細線路製作之前，需再 進行次刷磨的物理方法到除凸出於面銅114之上的絕緣材料12〇。 然而，如上述之第二次的刷磨會對於薄化的面銅114造成不良的影 響，例如會造成後續步驟製作出的細線路表面粗糙不均，影響細線路= 電性性質。 f 【發明内容】 對於上述，欲避免導電層過厚增加製作細線路(如的困難 度一種選擇性薄化導電層的方法，利用光阻層覆蓋孔洞，便可將其他 被光阻層暴露出之區域的導電層薄化。 對於上述，欲敎樹餘制職生触點賴作細線路 =τ法，特別是可應用於球閘陣列的一 待表面導電層處理後再移除光阻層，可避免使用於塞孔洞 方法中的刮除步驟損傷細線路所需之導電層。 夕對於兼顧避免薄化孔洞中之導電層但需薄化表面導電層，一種處理 :層板導電層的方法，蓋孔的光阻層為遮罩移 層:了具有不同厚度之表面導電層，其 形成細線路。 W坪沒用采 所需之導電 根據上述，本發明之—實施例，提供—種處理導電線路 1333245 層的方法，首先載板具有兩個導 ,斧电層之表面與至少一導電通孔貫穿1 中’導電通隸於任-導電層之表 - s 第區域。一先阻層覆蓋於每 等電層之表面與導電通孔上，蛀装 可 部份光阻層以暴露出至少任—導 後移除 导電層之表面的一第二區域， 光阻層覆蓋第一區域。藉由移除部八g 保留邛刀 砂除。卩刀4二區域的導電層以使 之一導電層厚度不’第-輯之—導電層厚心 °° 【實施方式】 本發蚊實細歸意_纟响述如下，在料本购之實施例 時，表示電_腫結構的部份會放並制，糾應以此作為 有限定的認知。此外’在實際的多層板結構中，應包含此結射其他必 第二A圖至第二F圖說明本發明之一實施例選擇性薄化面銅製程的 剖面示意|參照第二A圖，提供—多層板(雙層板以上）已完成一般印 刷電路板中乾製程⑽）的步驟及轉程憎孔_步驟。於一實施例 中，此多層板為-雙數層多層板，包含二層線路層12(亦可以是接地層及 電源層）、兩相鄰線路層12之間的絕緣層1〇、及兩外層基銅。要說明的 是，本發明方法之應寫限於雙數層多層板，亦可為單❹層板。此外， 本發明亦可視需求而顧於内層製作中，而不限於進行至外層的多層板。 再者，於本實施财，已·適當的方式，例如化學銅的方式， 完成於通孔18之側㈣上脑I 16。於進行軸孔銅16時亦會於兩外 層基銅域上鋪’基銅舰上的崎兩者峨_ 14，其㈣多層板 7 1333245 上之導電層表面。一般而言，由於通孔18側壁的孔銅16肩負電性導通 的功能，因此孔銅16的厚度至少需15 um。再者，相同的電鍍條件下， 於表面上鍍銅厚度較孔洞中的鍍銅厚度厚，因此一約15咖厚的基銅加 上鑛銅層，則面銅14可達25 um以上。因此，如欲製作細線路時則必須 薄化面銅14。要制的是’本發财法稀於孔洞為舰18，亦可因所 需而應用於非通孔，例如盲埋孔。其次，本發明方法亦不限於孔洞或表 面之導電層為銅層，具㈣當步驟可形成之導紐射不脫本發明方法 之範圍。 之後’以-遮罩層，例如一光阻層24覆蓋於面銅14與通孔Μ上。 :本實g例中光阻層24為-感光乾膜，利用壓膜（lami_e)方式覆蓋 於面銅丨4與通孔18上，故通孔18保射空的狀態，與f知填滿樹脂的 狀態不同,轉的，嶋㈣光龍，目_u8的孔徑大小並 ，特別的_。穌發财法不限於此，其他方式覆蓋的乾膜，或 是甚至不會流入通孔18的液態光阻亦可作為光阻層％，此時通孔Μ的 孔徑相對較小。再者，於另一實施例中，如具有-開口的非通孔’則只 需一層光阻層覆蓋開口所在的表面即可。 參照第二B圖，般微影無刻步驟移除部分的光阻層24，保 ^孔^上的_ 24，其中，被絲層24覆蓋之通㈣ B表面上之第一區域。由於孔銅16厚度與電性表 :因此需避免孔銅16厚度於後續製程中消耗，於本實施例中，： 光阻層24蓋孔的方输通孔18,可保護通孔_壁的娜。 8 1333245 參照第二c圖，以保留於通孔18上的光阻層24為遮罩利用適當 的方式’例如濕钱刻的方式來薄化暴露出的面銅14。薄化的面銅14適^ 後續形成細線路(fine pitch trace)。於本實施例中，薄化的面銅㈣ 合後續形成間距(pitc_ _⑽左右的細訊號線路(si_ t聰)或 間距125⑽的鍵結塾(bonding _。本發明之實施例利用光阻層靠 護通孔18砸的孔銅！6，選擇性薄化要形成細線路的面銅14。要說明 的是，除了通孔18上方外，光阻層24亦可因需魏留於其他不需形成 細線路的Μ。也就是說，糊光阻層24上被移轉賴案，本發明之方 法可選擇性地薄化設計細線路輯的_ 14祕留其他輯的面銅Μ 厚度，其中當然包含若僅於-表面製作細線路時。#然本發明之方法亦 可僅保留孔洞，例如通孔18周圍的銅層厚度，而多層板上之其他區域的 面銅則被薄化。 參照第二D圖’ _適當的方式剝除通孔18上的絲層％，此時通 孔18暴露出來。由上述過程中’可以理解的，本實施例之選擇性薄化面 銅14 ’故通孔18周圍之表面銅層14b的厚度較定義為細線路區域之銅層 14a之厚度厚。於-實施例中，未薄化前之面銅14的厚度約為25咖，經 過選擇性薄化後，銅層14a的厚度約為15um，但通孔18周圍之表面鋼層 14b的厚度仍可維持大約25uffl。再者，通孔18周圍之表面銅層池的厚 度雖然較厚，㈣於應衫層板時的傳遞並“ _影響，因為通 孔18於電性傳遞上存在固有的雜訊，因此，即使銅層地與恤的厚度 不同，銅層Mb亦不會造成電性傳遞的雜訊或其他不良原因的突然^ 增加。 9 1333245 之後’於整個表面覆蓋另-層姐層26，經職影移轉外層線路圖 案與#刻移除部分光阻層26以形成_化光阻層26，如第二E圖所示。 於本實施例中’由於移轉圖案為外層線路_，故通孔18_案化光阻 層26為遮罩。參照第二F圖，以翁的方式，例如·财式將暴露出 的面銅移除娜轉細層26，軸細線路於兩外層（⑼面(Upside) 與錫球面(ball side))J^此時通孔18仍維射空狀態，因此，後續製 程於表面覆蓋如綠漆(s〇lder mask)之防銲層（圖上未示）時，具有流動性 的綠漆將以軌财並狀賴。_上述，本發财絲細線路形 成寺通孔18保持中空狀態，直至綠漆填滿。因此，根據上述，本發明 方法利用乾膜纽，避免傳統塞孔之樹脂形成凸點，如此便無須刷磨的 物理處理方式，避免_受到不當的處理。此外，·顏蓋孔可選擇 性地於局部區域’例如設計細線路區域，薄化而其他包含通孔U 周圍或非設計細線路區域的面銅可以薄化或不薄化，依需求而定。換句 話4 ’利財發财法，載板的導體表面可分為至少兩健域包含孔 洞的-第-區域之導電層厚度與作為細線路的_第二區域之導電層厚度 不同’且通常第—區域之導電層厚度較厚，故厚度㈣的第二㈣適^ 後續細線路的形成。 根據上述，-實施例巾，-種形成細間距線路的方法，其係可應用 於一球間陣列的載板’首先提供球閘陣列的載板上之—導電層表面Y導 電層表面之-第-區域内具有-導電通孔…光阻層形成於第一區域上 並暴露出導電層表面之-第二區域 <=之後移除部分第二區域之導電層表 面以使得第二區域之-導電層厚度小於第—區域之—導電層厚度。:除 10 i Θ後喊光阻層於導電通孔與部分第二區域上，最後移除暴 路出的第二區域的導電層以形成至少一線路。 以上所述之實施例僅係為說明本發明之技術思想及特點，其目的在 使熟習此項技藝之人士能夠瞭解本發明之内容並據以實施，當不能以之 限定本發明之翻細，即纽依本發明賴权精神所作之均 或L飾，仍應涵蓋在本發明之專利範圍内。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates, in particular, to a method for producing a conductive layer required for a fine wiring for a conductive layer required for a wiring. [Prior Art] It is also an important subject to develop the circuit design and the size of the components on the circuit board toward the reduction direction. For example, the 'A-A to D-D diagrams are not intended for the conventional fabrication of fine lines (fine Canby (7)). Referring to Fig. AA, the multi-layer board completes the step of the inner layer to the recording hole copper, and the multi-layer board comprises a plurality of circuit layers 112 (here also including the ground layer) and an insulating layer no between the two adjacent circuit layers ι2. After a conventional wet process step, a copper ΐ6 is drilled in the side wall of the through hole 118. When the hole copper 116 is formed, the outer conductive layer of the multilayer board, that is, the so-called base copper, also mineralizes copper to form the surface copper 114. After that, Lili fat or his _ ugly lion (10) on the ΐ ΐ 8 to the surface of the stone (five) Qing (four), to avoid the loss of the hole copper 116 in the subsequent step of the loss as shown in Figure B. In order to ensure that the insulating material 12 is filled with the through holes 118, the weft material 120 in the through holes ι 8 will generally protrude above the _114. Shenxian—(10) In order to suppress the surface, the physical method of brushing the toning is generally used to remove the insulating material 120 from the surface of the copper ΐ4. In the next step, the thickness of the copper layer of the copper (1) can be reduced by using the wet etch method of the chemical _, so that the subsequent fine line can be produced, as shown in the figure _d. Wherein, since the thinned coffee _ is used in the gamma _ or the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Above. In this way, before the subsequent fine line fabrication, the physical method of the secondary brushing is required to remove the insulating material 12 from the surface copper 114. However, the second brushing as described above may adversely affect the thinned surface copper 114, for example, causing uneven roughness of the fine line surface produced in the subsequent steps, affecting fine lines = electrical properties. f [Summary of the Invention] For the above, it is desirable to avoid excessive thickness of the conductive layer to make fine lines (such as the difficulty of selectively thinning the conductive layer, using the photoresist layer to cover the holes, the other photoresist layer can be exposed In the above region, the conductive layer is thinned. For the above, the remaining contact of the eucalyptus is based on the fine line = τ method, in particular, it can be applied to the surface conductive layer of the ball gate array to remove the photoresist layer. It can avoid the use of the scraping step in the plug hole method to damage the conductive layer required for the thin circuit. In order to avoid the thinning of the conductive layer in the hole but to thin the surface conductive layer, a treatment: the method of the conductive layer of the layer The photoresist layer of the cover hole is a mask shift layer: a surface conductive layer having different thicknesses, which forms a fine line. W Ping does not use the required conductivity. According to the above, the present invention provides a treatment The method of conductive layer 1333245, firstly, the carrier has two leads, and the surface of the axe layer and the at least one conductive via penetrate through the first portion of the surface of the any-conducting layer. At each isoelectric layer The surface and the conductive via are provided with a portion of the photoresist layer to expose at least a second region of the surface of the conductive layer after the conductive layer is removed, and the photoresist layer covers the first region. g Retain the trowel sanding. The conductive layer of the squeegee 4 area is such that the thickness of one of the conductive layers is not 'the first series' - the thickness of the conductive layer ° ° [Embodiment] As follows, in the case of the embodiment purchased, the part representing the electric-swelling structure is put into use, and the response is taken as a limited cognition. In addition, in the actual multi-layer structure, the same should be included in the actual multi-layer structure. FIG. 2A to FIG. 2F are schematic cross-sectional views showing a selective thinning surface copper process according to an embodiment of the present invention. Referring to FIG. 2A, a multi-layer board (above the double-layer board) has been completed. The process of the dry process (10)) and the transfer boring_step. In one embodiment, the multi-layer board is a double-layer multi-layer board comprising two circuit layers 12 (which may also be a ground layer and a power layer), an insulating layer between two adjacent circuit layers 12, and two outer layers. Base copper. It should be noted that the method of the present invention is limited to a double-layered multi-layer board, and may also be a single-layer board. In addition, the present invention can also be considered in the production of the inner layer, and is not limited to the multi-layer board to the outer layer. Further, in the present embodiment, an appropriate method, for example, a method of chemical copper, is completed on the side of the through hole 18 (four) upper brain I 16 . When the shaft hole copper 16 is used, the surface of the conductive layer on the base copper plate is also laid on the base copper field of the two base copper vessels _ 14, which (4) the multilayer plate 7 1333245. In general, the thickness of the via copper 16 is at least 15 um due to the negative electrical conduction of the via copper 16 on the sidewall of the via 18 . Furthermore, under the same plating conditions, the thickness of the copper plating on the surface is thicker than the thickness of the copper plating in the hole. Therefore, if the base copper is about 15 kPa thick and the copper layer is added, the copper surface 14 can be more than 25 um. Therefore, if a thin line is to be made, the surface copper 14 must be thinned. What is required is that the money is thinner than the hole 18, and it can also be applied to non-through holes, such as blind buried holes. Secondly, the method of the present invention is not limited to the fact that the conductive layer of the hole or surface is a copper layer, and (4) the guide which can be formed in the step does not depart from the scope of the method of the present invention. Thereafter, a mask layer, such as a photoresist layer 24, is applied over the surface copper 14 and the via holes. In the present example, the photoresist layer 24 is a photosensitive dry film, and is covered on the surface copper iridium 4 and the through hole 18 by a lamu_e method, so that the through hole 18 is kept in an empty state, and the filling is completed. The state of the resin is different, the turn, the 嶋 (four) light dragon, the pore size of the _u8 and the special _. The method of financing is not limited to this. The dry film covered by other means, or the liquid photoresist which does not even flow into the through hole 18 can also be used as the photoresist layer %, and the aperture of the through hole is relatively small. Furthermore, in another embodiment, such as a non-via having an opening, only one layer of photoresist is required to cover the surface on which the opening is located. Referring to the second B-picture, the lithography-free step removes a portion of the photoresist layer 24, which is _24 on the hole, wherein the first layer on the surface of the (four) B is covered by the layer 24. Because of the thickness of the copper 16 and the electrical meter: therefore, it is necessary to avoid the thickness of the copper 16 in the subsequent process. In this embodiment, the through-hole 18 of the photoresist layer 24 covers the through hole _ wall. Na. 8 1333245 Referring to the second c-figure, the exposed surface copper 14 is thinned by the photoresist layer 24 remaining on the via 18 as a mask in a suitable manner, such as wet etching. The thinned face copper 14 is suitable for subsequent formation of a fine pitch trace. In the present embodiment, the thinned surface copper (four) is subsequently formed with a pitch (a thin signal line (si_t) or a pitch of 125 (10)) (bonding _. The embodiment of the present invention utilizes a photoresist layer The hole copper of the through hole 18砸6 is selectively thinned to form the surface copper 14 of the thin line. It should be noted that, besides the top of the through hole 18, the photoresist layer 24 may also be left unneeded by others. The thin line is formed. That is to say, the paste photoresist layer 24 is transferred, and the method of the present invention can selectively thin the thickness of the surface copper ruthenium of the other series. Of course, it is only necessary to make a thin line only on the surface. However, the method of the present invention can also retain only the holes, such as the thickness of the copper layer around the through holes 18, and the surface copper of other areas on the multilayer board is thinned. The second D picture ' _ appropriate way to strip the wire layer % on the through hole 18, at this time the through hole 18 is exposed. As can be understood from the above process, the selective thinned surface copper 14 of the present embodiment The thickness of the surface copper layer 14b around the through hole 18 is defined as the thickness of the copper layer 14a of the thin line region. In the embodiment, the thickness of the surface copper 14 before the thinning is about 25 Å, and after selective thinning, the thickness of the copper layer 14a is about 15 um, but the thickness of the surface steel layer 14b around the through hole 18. It can still maintain about 25 uffs. Moreover, the thickness of the surface copper pool around the through hole 18 is thicker, and (4) the transmission of the slab layer and the " _ effect, because the through hole 18 is inherent in electrical transmission. Noise, therefore, even if the thickness of the copper layer is different from the thickness of the shirt, the copper layer Mb will not cause an abrupt increase in the noise of electrical transmission or other undesirable causes. 9 1333245 After that, the entire surface is covered with another layer. 26, shifting the outer layer pattern by the job shadow and #etching part of the photoresist layer 26 to form the _ photoresist layer 26, as shown in the second E. In this embodiment, 'because the transfer pattern is the outer layer line _, the through hole 18_the photoresist layer 26 is a mask. Referring to the second F picture, in the manner of Weng, for example, the exposed copper is removed from the thin layer 26, and the fine line is The two outer layers ((9) (Upside) and the ball side) (J) (the ball side) J^ at this time, the through hole 18 is still in the empty state, therefore, the subsequent process is When the surface is covered with a solder mask (not shown) such as a green paint, the green paint with fluidity will be in the form of a rail. The above-mentioned, the thin wire of the line forms a temple through hole. 18 is kept in a hollow state until the green paint is filled. Therefore, according to the above, the method of the present invention utilizes a dry film to avoid the formation of bumps of the resin of the conventional plug hole, so that the physical treatment method without brushing is avoided, and the improper treatment is avoided. In addition, the cover hole can be selectively applied to the local area, for example, the thin line area is thinned, and other surface copper including the surrounding area of the through hole U or the non-designed fine line area can be thinned or thinned, depending on the demand. In other words, in the case of 4 'profit making method, the conductor surface of the carrier board can be divided into at least two health fields, the hole-containing region-the region has a different thickness of the conductive layer than the thin layer of the second region. 'And usually the thickness of the first-region conductive layer is thicker, so the second (four) of the thickness (four) is suitable for the formation of the subsequent fine lines. According to the above, - the embodiment towel, a method for forming a fine pitch line, which can be applied to a carrier plate of an inter-ball array - first providing the surface of the conductive layer surface of the conductive layer surface - a conductive via in the first region... a photoresist layer is formed on the first region and exposes a surface of the conductive layer - a second region <= after removing a portion of the conductive layer surface of the second region such that the second region The thickness of the conductive layer is smaller than the thickness of the conductive layer of the first region. After the 10 i Θ, the photoresist layer is called on the conductive via and the second region, and finally the conductive layer of the second region of the storm is removed to form at least one line. The embodiments described above are merely illustrative of the technical spirit and features of the present invention, and the purpose of the present invention is to enable those skilled in the art to understand the contents of the present invention and to implement the present invention. That is, the average or L decoration made by New Zealand's invention of the spirit of the invention shall still be covered by the patent of the present invention.
【圖式簡單說明】 第一A至第一D 圖為傳統製作细線路(fine pitch trace)的到面示专 圖 第=A圖至第二F圖說明本發明之_實施例選擇性薄化面納製程 示意圖 的剖面 【主要元件符號說明】 10絕緣層 12線路層 14面銅 14a銅層 14b銅層 16孔銅 18通孔 24光阻層 26光阻層 110絕緣層 112線路層 114 面銅 1333245 116孔銅 118通孔BRIEF DESCRIPTION OF THE DRAWINGS First to first D drawings are conventional fine-grained traces to the surface of the drawings. Figures A to II represent the selective thinning of the present invention. Section of the surface-receiving process diagram [Main component symbol description] 10 insulation layer 12 circuit layer 14 surface copper 14a copper layer 14b copper layer 16 hole copper 18 through hole 24 photoresist layer 26 photoresist layer 110 insulation layer 112 circuit layer 114 surface copper 1333245 116 hole copper 118 through hole