JP2008085238A - Substrate having through electrode, and manufacturing method thereof - Google Patents

Substrate having through electrode, and manufacturing method thereof Download PDF

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JP2008085238A
JP2008085238A JP2006266203A JP2006266203A JP2008085238A JP 2008085238 A JP2008085238 A JP 2008085238A JP 2006266203 A JP2006266203 A JP 2006266203A JP 2006266203 A JP2006266203 A JP 2006266203A JP 2008085238 A JP2008085238 A JP 2008085238A
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hole
insulating film
pad portion
silicon substrate
substrate
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Tomoyuki Nakazawa
智之 中澤
Kazuhiro Chokai
和宏 鳥海
Kazuo Murata
一男 村田
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Citizen Miyota Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a substrate having a through electrode securing continuity reliability at a through electrode, and to provide the substrate having a through electrode. <P>SOLUTION: A first hole 1a having a pore size that is wider than that of a pad section 3 is formed by etching to depth reaching half the thickness of a silicon substrate 1 or more, and without reaching an insulation film 2; a second hole 1b having a pore size corresponding to the pad section region is formed by etching up to a position where the insulating film 2 is exposed from the first hole bottom section to the pad section; an insulating film 9 is formed in the first hole and on the inner surface of the second hole; the insulating film 9 positioned at the bottom section of the second hole and the insulating film 2 on one main surface of the silicon substrate are removed; one portion of the pad section is exposed; and the inside of first and second holes is filled with a conductive member. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、貫通電極付き基板の製造方法、及び貫通電極付き基板に関するものである。   The present invention relates to a method for manufacturing a substrate with a through electrode, and a substrate with a through electrode.

近年、複数の半導体チップを積み重ねたスタック構造の半導体装置や、半導体チップに他の電子部品を積み重ねたスタック構造の電子デバイスが開発されている。また、前記スタック構造の実装形態を実現するために、半導体チップの基板面に貫通電極を形成することが知られている。   In recent years, a semiconductor device having a stack structure in which a plurality of semiconductor chips are stacked and an electronic device having a stack structure in which other electronic components are stacked on a semiconductor chip have been developed. Further, it is known to form a through electrode on the substrate surface of a semiconductor chip in order to realize the mounting structure of the stack structure.

前記貫通電極は、半導体基板に貫通孔を形成し、当該貫通孔内面に絶縁膜を形成して絶縁処理した上、その内面に導電部材を充填して形成されるものである。   The through electrode is formed by forming a through hole in a semiconductor substrate, forming an insulating film on the inner surface of the through hole, performing an insulating treatment, and then filling the inner surface with a conductive member.

図２は従来技術による貫通電極付き基板の製造方法を説明する図で、（ａ）〜（ｆ）は、各工程における貫通電極部の状態を示す断面図である。以下、図２を参照して従来技術の貫通電極付き基板の製造方法を説明する。   FIG. 2 is a diagram for explaining a method of manufacturing a substrate with a through electrode according to the prior art, and (a) to (f) are cross-sectional views showing the state of the through electrode portion in each step. Hereinafter, with reference to FIG. 2, the manufacturing method of the board | substrate with a penetration electrode of a prior art is demonstrated.

（ａ）は孔形成工程を示す図である。
２０はシリコン基板で、２１はシリコン基板２０の一主面に形成された絶縁膜で、例えば、シリコン酸化膜（ＳｉＯ２）である。図示していないが、前記シリコン基板上２０の表面上には回路パターンが形成されている。２２は前記回路パターン（不図示）と接続されたアルミニウムから成るパッド部である。ここで形成しようとする貫通電極は、前記シリコン基板２０の一主面上にあるパッド部２２と、これに対向する反対側のシリコン基板２０の面側を導通可能にしようとしたものである。 (A) is a figure which shows a hole formation process.
Reference numeral 20 denotes a silicon substrate, and reference numeral 21 denotes an insulating film formed on one main surface of the silicon substrate 20, for example, a silicon oxide film (SiO 2 ). Although not shown, a circuit pattern is formed on the surface of the silicon substrate 20. Reference numeral 22 denotes a pad portion made of aluminum connected to the circuit pattern (not shown). The through electrode to be formed here is intended to allow conduction between the pad portion 22 on one main surface of the silicon substrate 20 and the surface side of the opposite silicon substrate 20 facing the pad portion 22.

２０ａは前記シリコン基板２０の所定位置に形成された孔で、当該孔２０ａは、ドライエッチングにより形成される。前記孔２０ａを形成するためのエッチング部は、フォトリソグラフィーによって形成されたマスクパターン２３によって決められる。前記マスクパターン２３の形成は、レジストをスピンコート法等により、前記シリコン基板２０上に塗布後、所望のマスクパターン形状を有するフォトマスクを被せて前記レジストの紫外線露光を行い、露光後、現像液を用いて光の当たった部分以外の領域を除去して形成される。前記レジストの、露光、現像により除去され、シリコン基板２０の面が露出した部位がエッチング部となる。以上により形成されたマスクパターン２３をマスクとして、エッチングを行い孔２０ａが形成される。   20a is a hole formed at a predetermined position of the silicon substrate 20, and the hole 20a is formed by dry etching. An etching portion for forming the hole 20a is determined by a mask pattern 23 formed by photolithography. The mask pattern 23 is formed by applying a resist on the silicon substrate 20 by spin coating or the like, and then covering the photomask having a desired mask pattern shape with ultraviolet exposure of the resist. It is formed by removing regions other than the portion exposed to light using A portion of the resist which is removed by exposure and development and the surface of the silicon substrate 20 is exposed becomes an etched portion. Etching is performed using the mask pattern 23 formed as described above as a mask to form the hole 20a.

前記マスクパターン２３は孔２０ａ形成後に除去される。また、前記孔２０ａは絶縁膜２１がエッチングストップ層となるため、前記絶縁膜２１が露出したところで終了となる。尚、図示する前記シリコン基板２０の厚みは約１００μｍで、これに形成される孔２０ａの直径はφ６０μｍ程度のごく小さな孔である。   The mask pattern 23 is removed after the hole 20a is formed. The hole 20a ends when the insulating film 21 is exposed because the insulating film 21 serves as an etching stop layer. The silicon substrate 20 shown in the figure has a thickness of about 100 μm, and the hole 20a formed in the silicon substrate 20 has a very small diameter of about 60 μm.

（ｂ）は孔内面に絶縁膜を形成する工程を示す図である。
前記（ａ）工程によって孔２０ａを形成した後、当該孔２０ａ内壁面に絶縁膜２４を形成する。前記絶縁膜２４は、ＣＶＤ（Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ）法等によって形成したもので、例えば、シリコン酸化膜（ＳｉＯ２）である。
前記絶縁膜２４は、後の工程で、前記孔１ａ内に充填される導電部材とシリコン基板２０とを絶縁処理するものである。 (B) is a figure which shows the process of forming an insulating film in the hole inner surface.
After the hole 20a is formed by the step (a), the insulating film 24 is formed on the inner wall surface of the hole 20a. The insulating film 24 is formed by a CVD (Chemical Vapor Deposition) method or the like, and is, for example, a silicon oxide film (SiO 2 ).
The insulating film 24 insulates the conductive member filled in the hole 1a and the silicon substrate 20 in a later step.

（ｃ）は孔底部に位置する絶縁膜を除去するためのマスクパターン形成工程を示す図である。
続いて、前記孔２０ａの底部に位置する前記絶縁膜２４と、その下層で、積層状態となっている絶縁膜２１をエッチング除去するためのマスクパターン２５をフォトリソグラフィーにより形成する。前記マスクパターン２５は、前記絶縁膜２４表面上に、レジストをスピンコート法等により塗布し、塗布後、所望のマスクパターン形状を有するフォトマスク２６を被せて前記レジストの紫外線露光を行い、露光後、現像液を用いて光の当たった部分以外の領域を除去して形成する。本工程はネガ型のフォトレジストによるものであるが、ポジ型であっても同様に形成できる。 (C) is a figure which shows the mask pattern formation process for removing the insulating film located in a hole bottom part.
Subsequently, the insulating film 24 located at the bottom of the hole 20a and a mask pattern 25 for etching and removing the insulating film 21 in the laminated state are formed by photolithography. The mask pattern 25 is obtained by applying a resist on the surface of the insulating film 24 by spin coating or the like, and then applying a photomask 26 having a desired mask pattern shape to expose the resist with ultraviolet rays. Then, a region other than the portion exposed to light is removed by using a developing solution. Although this step is based on a negative type photoresist, a positive type can be formed in the same manner.

（ｄ）は孔底部に位置する絶縁膜をエッチング除去し、貫通孔を形成する工程を示す図である。
前記（ｃ）工程において形成した絶縁膜除去用のマスクパターン２５をマスクとし、前記絶縁膜２４と絶縁膜２１をエッチングにより除去する。尚、前記絶縁膜２４及び絶縁膜２１は、いずれもシリコン酸化膜（ＳｉＯ２）である。また、前記エッチングはドライエッチング、ウェットエッチングのいずれを用いても良い。続いて、前記絶縁膜除去用のマスクパターン２５を剥離して貫通孔が形成される。当該貫通孔底部には下層のアルミニウムから成るパッド部２２の一部が露出した状態となる。 (D) is a figure which shows the process of etching away the insulating film located in a hole bottom part, and forming a through-hole.
Using the mask pattern 25 for removing the insulating film formed in the step (c) as a mask, the insulating film 24 and the insulating film 21 are removed by etching. The insulating film 24 and the insulating film 21 are both silicon oxide films (SiO 2 ). The etching may be either dry etching or wet etching. Subsequently, the mask pattern 25 for removing the insulating film is removed to form a through hole. A part of the pad portion 22 made of lower layer aluminum is exposed at the bottom of the through hole.

（ｅ）は孔内に導電部材を充填する前工程を示す図である。
導電部材の充填方法としては、種々の手法が用いられるが、小径の孔内に充填する場合は電解メッキによる手法が適している。
前記（ｄ）工程によって形成された孔２０ａ内に電解メッキ用の共通電極２７をスパッタリング若しくは蒸着により形成する。前記共通電極２７は、例えば、金（Ａｕ）である。その後、フォトリソグラフィーによって、電解メッキ用のマスクパターン２８を形成する。 (E) is a figure which shows the pre-process of filling an electroconductive member in a hole.
Various methods are used as a method for filling the conductive member, but a method using electrolytic plating is suitable for filling the small-diameter hole.
A common electrode 27 for electrolytic plating is formed in the hole 20a formed by the step (d) by sputtering or vapor deposition. The common electrode 27 is, for example, gold (Au). Thereafter, a mask pattern 28 for electrolytic plating is formed by photolithography.

（ｆ）は、孔内に導電部材を充填する工程を示す図である。
前記（ｅ）工程により電解メッキ用の共通電極２７と、電解メッキ用のマスクパターン２８を形成した後、電解メッキを行い孔２０ａ内に導電部材２９を充填する。尚、前記導電部材２９は、前記共通電極２７と同様、金（Ａｕ）である。これにより、貫通孔内は導電部材２９が充填され、シリコン基板２０の一方の面側のパッド部と導通可能な状態となる。以上の工程によって貫通電極付き基板が形成される。 (F) is a figure which shows the process of filling an electroconductive member in a hole.
After the common electrode 27 for electrolytic plating and the mask pattern 28 for electrolytic plating are formed by the step (e), electrolytic plating is performed to fill the conductive member 29 in the hole 20a. The conductive member 29 is gold (Au), like the common electrode 27. As a result, the inside of the through hole is filled with the conductive member 29 and becomes conductive with the pad portion on one surface side of the silicon substrate 20. A substrate with a through electrode is formed by the above steps.

貫通電極付き基板の製造方法に関連するものとしては、例えば、特許文献１による製造方法が開示されている。   As a thing relevant to the manufacturing method of the board | substrate with a penetration electrode, the manufacturing method by patent document 1 is disclosed, for example.

特開平５−１７５２４２号公報Japanese Patent Laid-Open No. 5-175242

しかしながら、前述の従来技術による貫通電極付き基板の製造方法では、一部工程において、以下のような問題点がある。   However, the above-described conventional method for manufacturing a substrate with a through electrode has the following problems in some steps.

まず、前記した（ｃ）工程において、孔２０ａ底部に位置する絶縁膜２４及び２１の一部を除去するためのマスクパターン２５を形成するために、レジスト膜を前記孔２０ａ内壁面に形成しなければならない。前述のごとく、前記孔２０ａの直径はφ６０μｍ程度の小さな孔であると同時に、約１００μｍの厚み（深さ）を有している上、前工程において、絶縁膜２４が内壁面に形成されており、孔２０ａの直径はさらに小さなものとなっている。前記寸法値は一例であるが、前記孔２０ａの直径は、あらかじめ設けられたシリコン基板１上のパッド部２２領域をターゲットに形成するので、前記パッド部２２の領域に制約される。したがって、さらに小さなものが要求される場合もある。このような孔２０ａ内にレジスト膜を均一の厚さで形成することは非常に難しい。図１（ｃ）に示すレジスト膜（マスクパターン２５）は模式的に示したもので、説明の便宜上、解り易くするために孔２０ａの内壁面に均一の厚みをもった状態で示しているが、実際は、図３や図４に示すような状態で形成される。   First, in the step (c) described above, a resist film must be formed on the inner wall surface of the hole 20a in order to form a mask pattern 25 for removing part of the insulating films 24 and 21 located at the bottom of the hole 20a. I must. As described above, the diameter of the hole 20a is a small hole of about φ60 μm, and at the same time has a thickness (depth) of about 100 μm, and the insulating film 24 is formed on the inner wall surface in the previous step. The diameter of the hole 20a is even smaller. Although the dimension value is an example, the diameter of the hole 20a is limited to the area of the pad portion 22 because the area of the pad portion 22 on the silicon substrate 1 provided in advance is formed as a target. Therefore, a smaller one may be required. It is very difficult to form a resist film in such a hole 20a with a uniform thickness. The resist film (mask pattern 25) shown in FIG. 1C is schematically shown. For convenience of explanation, the inner wall surface of the hole 20a has a uniform thickness for easy understanding. Actually, it is formed in the state shown in FIGS.

図３は、レジスト膜形成状態の一例を示す断面図である。３０は、レジスト膜で、絶縁膜２４及び２１の一部を除去するためのマスクパターンを形成するためのものである。本図に示すように、前記レジスト膜３０は、孔２０ａの開口端エッジ部で膜厚が薄い状態となり、また、孔２０ａ底部においては膜厚が厚くなる傾向にある。このような状態では、膜厚が厚い孔２０ａ底部へのマスクパターン形成精度が悪なってしまう。また、膜厚の薄い孔２０ａの開口端エッジ部においては、本来残すべき絶縁膜２４を除去してしまう虞がある。   FIG. 3 is a cross-sectional view showing an example of a resist film formation state. Reference numeral 30 denotes a resist film for forming a mask pattern for removing part of the insulating films 24 and 21. As shown in this figure, the resist film 30 tends to be thin at the opening edge portion of the hole 20a and thick at the bottom of the hole 20a. In such a state, the mask pattern forming accuracy on the bottom of the hole 20a having a large film thickness is deteriorated. Further, the insulating film 24 that should originally be left may be removed at the opening edge of the thin hole 20a.

図４は、レジスト膜形成状態の他の例を示す断面図である。本図に示すレジスト膜形成状態は、レジスト膜３１が孔２０ａ内に浸透せず、前記孔２０ａの開口部分を覆ってしまい、孔２０ａを塞いでしまった状態である。前記したように、ごく小径の孔２０ａを対象とする場合にはこのような状態が稀に発生する。   FIG. 4 is a cross-sectional view showing another example of a resist film formation state. The resist film formation state shown in this figure is a state in which the resist film 31 does not penetrate into the hole 20a, covers the opening of the hole 20a, and closes the hole 20a. As described above, such a state rarely occurs when a very small diameter hole 20a is targeted.

そこで、本発明は、容易、且つ正確に貫通孔の形成ができ、貫通電極の導通の信頼性を確保した貫通電極付き基板の製造方法、及び貫通電極付き基板を提供することを目的とする。   Accordingly, an object of the present invention is to provide a method for manufacturing a substrate with a through electrode, which can easily and accurately form a through hole and ensure the reliability of conduction of the through electrode, and a substrate with a through electrode.

一主面に絶縁膜と回路パターンを有し、前記絶縁膜上に回路パターンと接続されたパッド部を有するシリコン基板に、前記パッド部と電気的接続を成すよう形成された貫通電極を備えた貫通電極付き基板の製造方法であって、
少なくとも、
前記パッド部の領域よりも広い孔径を有する第１の孔を、前記シリコン基板の前記パッド部が形成された面とは反対側の面から、前記シリコン基板の厚みに対し、半分以上、且つ前記絶縁膜まで達しない深さまでエッチングにより形成する第１工程と、
前記第１の孔底部から、前記パッド部に向け、当該パッド部領域に対応した孔径を有する第２の孔を、前記絶縁膜が露出する位置までエッチングにより形成する第２工程と、
前記第１の孔と前記第２の孔内面に絶縁膜を形成する第３工程と、
前記第２の孔底部に位置する前記第３工程により形成された前記絶縁膜及び前記シリコン基板の一主面にある前記絶縁膜を除去し、前記パッド部の一部を露出させる第４工程と、
前記第１の孔及び前記第２の孔内に、導電部材を充填する第５工程と、
を有する貫通電極付き基板の製造方法とする。 A silicon substrate having an insulating film and a circuit pattern on one main surface and having a pad portion connected to the circuit pattern on the insulating film is provided with a through electrode formed to be electrically connected to the pad portion. A method of manufacturing a substrate with a through electrode,
at least,
The first hole having a larger hole diameter than the area of the pad portion is more than half of the thickness of the silicon substrate from the surface of the silicon substrate opposite to the surface on which the pad portion is formed, and the A first step of etching to a depth not reaching the insulating film;
A second step of forming a second hole having a hole diameter corresponding to the pad portion region by etching from the bottom of the first hole toward the pad portion to a position where the insulating film is exposed;
A third step of forming an insulating film on the inner surface of the first hole and the second hole;
A fourth step in which the insulating film formed in the third step located at the bottom of the second hole and the insulating film on one main surface of the silicon substrate are removed, and a part of the pad portion is exposed; ,
A fifth step of filling the first hole and the second hole with a conductive member;
A method for manufacturing a substrate with a through electrode having the following.

前記第１の孔及び前記第２の孔内に導電部材を充填する第５工程において、前記シリコン基板面の第１の孔上方に、前記導電部材と連続する外部接続用のパッド部を前記導電部材の充填を行うと同時に形成する貫通電極付き基板の製造方法とする。   In a fifth step of filling the first hole and the second hole with a conductive member, an external connection pad portion continuous with the conductive member is disposed above the first hole on the silicon substrate surface. A method of manufacturing a substrate with a through electrode formed simultaneously with filling of members.

前記製造方法により成る貫通電極付き基板であって、
一主面に絶縁膜と回路パターンを有し、前記絶縁膜上に回路パターンと接続されたパッド部を備えたシリコン基板に、当該シリコン基板の厚みに対し、半分以上、且つ前記絶縁膜まで達しない深さの、前記パッド部の領域よりも広い孔径を有する第１の孔と、当該第１の孔底部から、前記パッド部に向け、当該パッド部領域に対応した孔径を有する第２の孔とで貫通孔を構成し、当該貫通孔内に導電部材を充填して、前記シリコン基板の両面間を導通可能にした貫通電極付き基板とする。 A substrate with a through electrode formed by the manufacturing method,
A silicon substrate having an insulating film and a circuit pattern on one main surface, and having a pad portion connected to the circuit pattern on the insulating film, reaching more than half of the thickness of the silicon substrate and reaching the insulating film A first hole having a larger hole diameter than the area of the pad portion, and a second hole having a hole diameter corresponding to the pad portion area from the bottom of the first hole toward the pad portion. And a through hole is formed, and a conductive member is filled in the through hole to form a substrate with a through electrode that allows conduction between both surfaces of the silicon substrate.

前記導電部材は、前記第１の孔内からシリコン基板の表面上に突出するよう連続して形成されており、外部接続用のパッド部を構成している貫通電極付き基板とする。   The conductive member is continuously formed so as to protrude from the inside of the first hole onto the surface of the silicon substrate, and is a substrate with a through electrode constituting a pad portion for external connection.

シリコン基板のパッド部領域よりも広い孔径を有する第１の孔を、前記シリコン基板の前記パッド部が形成された面とは反対側の面から、前記シリコン基板の厚みに対し、半分以上、且つ前記絶縁膜まで達しない深さまでエッチングにより形成し、前記第１の孔底部から、前記パッド部に向け、当該パッド部領域に対応した孔径を有する第２の孔を形成するので、マスクパターンの形成が容易、且つ正確に行える。また、第１の孔１ａ側の径を大きく設定できるので、マスクパターンを形成するために塗布するレジストの浸透が良く、孔を塞いでしまうことがなくなる。   The first hole having a hole diameter wider than the pad portion region of the silicon substrate is more than half of the thickness of the silicon substrate from the surface opposite to the surface on which the pad portion of the silicon substrate is formed, and Forming by etching to a depth not reaching the insulating film, and forming a second hole having a hole diameter corresponding to the pad portion region from the first hole bottom toward the pad portion. Can be performed easily and accurately. Moreover, since the diameter on the first hole 1a side can be set large, the penetration of the resist applied to form the mask pattern is good, and the hole is not blocked.

一主面に絶縁膜と回路パターンを有し、前記絶縁膜上に回路パターンと接続されたパッド部を備えたシリコン基板に、当該シリコン基板の厚みに対し、半分以上、且つ前記絶縁膜まで達しない深さの、前記パッド部の領域よりも広い孔径を有する第１の孔と、当該第１の孔底部から、前記パッド部に向け、当該パッド部領域に対応した孔径を有する第２の孔とで貫通孔を構成したので、貫通孔内に充填する導電部材が確実に充填され、信頼性の高い貫通電極付き基板が得られる。   A silicon substrate having an insulating film and a circuit pattern on one main surface, and having a pad portion connected to the circuit pattern on the insulating film, reaching more than half of the thickness of the silicon substrate and reaching the insulating film A first hole having a larger hole diameter than the area of the pad portion, and a second hole having a hole diameter corresponding to the pad portion area from the bottom of the first hole toward the pad portion. Since the through hole is configured as described above, the conductive member filling the through hole is surely filled, and a highly reliable substrate with a through electrode is obtained.

以下、本発明の貫通電極付き基板の製造方法について、図面に基づいて詳細に説明する。図１は本発明の貫通電極付き基板の製造方法を説明する図で、（ａ）〜（ｉ）は各工程における貫通電極部の状態を示す断面図である。   Hereinafter, the manufacturing method of the board | substrate with a penetration electrode of this invention is demonstrated in detail based on drawing. FIG. 1 is a view for explaining a method of manufacturing a substrate with a through electrode according to the present invention, and (a) to (i) are cross-sectional views showing states of through electrode portions in each step.

（ａ）は第１の孔形成工程を示す図である。
１はシリコン基板で、２はシリコン基板１の一主面に形成された絶縁膜である。図示していないが、前記シリコン基板１は、その表面上に回路パターンが形成された基板であり、３は前記回路パターン（不図示）と接続されたアルミニウム等からなるパッド部である。当該パッド部３は、外部接続用の端子として用いられるものである。ここで形成しようとする貫通電極は、前記シリコン基板１の前記パッド部３が形成された面とは反対側から、前記パッド部に対応する位置に形成しようとするものである。 (A) is a figure which shows a 1st hole formation process.
Reference numeral 1 denotes a silicon substrate, and reference numeral 2 denotes an insulating film formed on one main surface of the silicon substrate 1. Although not shown, the silicon substrate 1 is a substrate having a circuit pattern formed on its surface, and 3 is a pad portion made of aluminum or the like connected to the circuit pattern (not shown). The pad portion 3 is used as a terminal for external connection. The through electrode to be formed here is to be formed at a position corresponding to the pad portion from the side opposite to the surface on which the pad portion 3 of the silicon substrate 1 is formed.

１ａは前記シリコン基板１の所定位置に形成された第１の孔で、当該第１の孔１ａは、ドライエッチングにより形成される。前記第１の孔１ａを形成するためのエッチング部は、フォトリソグラフィーによって形成されたマスクパターン４によって決められる。前記マスクパターン４の形成は、レジストをスピンコート法等により、前記シリコン基板１上に塗布後、所望のマスクパターン形状を有するフォトマスクを被せて前記レジストの紫外線露光を行い、露光後、現像液を用いて光の当たった部分以外の領域を除去して形成する。前記レジストの、露光、現像により除去され、シリコン基板１表面が露出した部位がエッチング部である。以上により形成されたマスクパターン４をマスクとして、前記シリコン基板１の厚みに対して中間位置の深さまでエッチングを行い第１の孔１ａを形成する。前記第１の孔１ａの深さは、前記シリコン基板１の厚みの半分以上で、前記絶縁膜２まで達しない深さであることが望ましい。   Reference numeral 1a denotes a first hole formed at a predetermined position of the silicon substrate 1, and the first hole 1a is formed by dry etching. The etching portion for forming the first hole 1a is determined by the mask pattern 4 formed by photolithography. The mask pattern 4 is formed by applying a resist on the silicon substrate 1 by spin coating or the like, and then covering the photomask having a desired mask pattern shape with ultraviolet exposure of the resist. A region other than the portion exposed to light is removed by using. A portion of the resist which is removed by exposure and development and the surface of the silicon substrate 1 is exposed is an etched portion. Using the mask pattern 4 formed as described above as a mask, etching is performed to a depth at an intermediate position with respect to the thickness of the silicon substrate 1 to form the first hole 1a. The depth of the first hole 1a is preferably half or more than the thickness of the silicon substrate 1 and does not reach the insulating film 2.

前記マスクパターン４は第１の孔１ａ形成後に除去する。尚、図示する前記シリコン基板１の厚みは約１００μｍで、これに形成される第１の孔１ａの直径は前記パッド部３の領域よりも大きく設定する。   The mask pattern 4 is removed after the first hole 1a is formed. The thickness of the silicon substrate 1 shown in the figure is about 100 μm, and the diameter of the first hole 1 a formed in the silicon substrate 1 is set larger than the area of the pad portion 3.

（ｂ）は第１の孔底部から連続する第２の孔を形成するためのマスクパターン形成工程を示す図である。
レジストをスピンコート法等により、前記シリコン基板１上に塗布後、所望のマスクパターン形状を有するフォトマスク５を被せて前記レジストの紫外線露光を行い、露光後、現像液を用いて光の当たった部分以外の領域を除去してマスクパターン６を前記孔１ａ内に形成する。 (B) is a figure which shows the mask pattern formation process for forming the 2nd hole continuous from the 1st hole bottom part.
After applying a resist on the silicon substrate 1 by spin coating or the like, the resist is exposed to ultraviolet light by covering with a photomask 5 having a desired mask pattern shape, and exposed to light using a developer. A region other than the portion is removed to form a mask pattern 6 in the hole 1a.

（ｃ）は第２の孔形成工程を示す図である。
前記（ｂ）工程で形成したマスクパターン６を利用し、ドライエッチングにより第２の孔１ｂを形成する。本工程においては、前記絶縁膜２がストップ層となるため、絶縁膜２が露出したところでエッチングが終了する。こうして形成される第２の孔１ｂは、第１の孔１ａよりもその直径が小さく、且つパッド部３の領域に収まる孔径で形成される。 (C) is a figure which shows a 2nd hole formation process.
The second hole 1b is formed by dry etching using the mask pattern 6 formed in the step (b). In this step, since the insulating film 2 becomes a stop layer, the etching is finished when the insulating film 2 is exposed. The second hole 1 b formed in this way is formed with a hole diameter that is smaller than that of the first hole 1 a and that fits in the region of the pad portion 3.

（ｄ）は第１の孔及び第２の孔内面に絶縁膜を形成する工程を示す図である。
前記（ａ）〜（ｃ）工程を経て第１の孔１ａと第２の孔１ｂを形成した後、当該第１の孔１ａ及び第２の孔１ｂ内壁面に絶縁膜７を形成する。前記絶縁膜７は、ＣＶＤ（Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ）法等によって形成したもので、例えば、シリコン酸化膜（ＳｉＯ２）である。当該絶縁膜７は、後の工程で、前記第１の孔１ａ及び第２の孔１ｂ内に充填される導電部材とシリコン基板１とを絶縁処理するためのものである。 (D) is a figure which shows the process of forming an insulating film in the 1st hole and the 2nd hole inner surface.
After forming the first hole 1a and the second hole 1b through the steps (a) to (c), the insulating film 7 is formed on the inner wall surfaces of the first hole 1a and the second hole 1b. The insulating film 7 is formed by a CVD (Chemical Vapor Deposition) method or the like, and is, for example, a silicon oxide film (SiO 2 ). The insulating film 7 is for insulating the conductive member filled in the first hole 1a and the second hole 1b and the silicon substrate 1 in a later step.

（ｅ）は前記第２の孔底部に位置する絶縁膜除去用のマスクパターン形成工程を示す図である。
レジストをスピンコート法等により、前記シリコン基板１上に塗布後、所望のマスクパターン形状を有するフォトマスク８を被せて前記レジストの紫外線露光を行い、露光後、現像液を用いて光の当たった部分以外の領域を除去してマスクパターン９を前記第１の孔１ａ及び第２の孔１ｂ内壁面に形成する。ここで、前記第１の孔１ａの直径は大きく設定されており、且つシリコン基板１の厚みに対し半分以上の深さを有しているので、これよりも小径の第２の孔１ｂ内へも前記レジストが浸透し易くなる。 (E) is a figure which shows the mask pattern formation process for the insulating film removal located in the said 2nd hole bottom part.
After applying a resist on the silicon substrate 1 by spin coating or the like, the resist is covered with a photomask 8 having a desired mask pattern shape, and the resist is exposed to ultraviolet light. After exposure, the resist is exposed to light using a developer. A region other than the portion is removed to form a mask pattern 9 on the inner wall surfaces of the first hole 1a and the second hole 1b. Here, since the diameter of the first hole 1a is set to be large and has a depth of more than half the thickness of the silicon substrate 1, it enters into the second hole 1b having a smaller diameter. However, the resist is likely to penetrate.

（ｆ）前記第２の孔底部に位置する絶縁膜を除去する工程を示す図である。
前記（ｅ）工程で形成した絶縁膜除去用のマスクパターン９を利用し、ドライエッチング又はウェットエッチングによって前記第２の孔１ｂ底部に位置する絶縁膜を除去する。尚、除去する絶縁膜は、前記第２の孔１ｂ内に露出する絶縁膜７と、その下部に積層された状態となっている前記シリコン基板１面上に事前に形成されている絶縁膜２の両方である。尚、本工程において、前記絶縁膜７及び絶縁膜２の一部が除去されると、前記パッド部３の一部が前記第１の孔１ａ及び第２の孔１ｂ内に露出した状態となる。 (F) It is a figure which shows the process of removing the insulating film located in the said 2nd hole bottom part.
Using the mask pattern 9 for removing the insulating film formed in the step (e), the insulating film located at the bottom of the second hole 1b is removed by dry etching or wet etching. The insulating film to be removed is the insulating film 7 exposed in the second hole 1b and the insulating film 2 formed in advance on the surface of the silicon substrate 1 stacked below the insulating film 7. Both. In this step, when a part of the insulating film 7 and the insulating film 2 is removed, a part of the pad portion 3 is exposed in the first hole 1a and the second hole 1b. .

（ｇ）は前記第１の孔及び第２の孔内に導電部材を充填する前工程を示す図である。
導電部材の充填方法は、種々の手法が用いられるが、小径の孔内に充填する場合は電解メッキによる手法が適しているため、本手法を採用する。
前記第１の孔１ａ及び第２の孔１ｂ内に電解メッキ用の共通電極１０（例えば、金（Ａｕ））をスパッタリング若しくは蒸着により形成する。 (G) is a figure which shows the pre-process which fills a conductive member in the said 1st hole and 2nd hole.
Various methods are used for filling the conductive member, but this method is adopted because a method using electrolytic plating is suitable when filling into a small-diameter hole.
A common electrode 10 (for example, gold (Au)) for electrolytic plating is formed in the first hole 1a and the second hole 1b by sputtering or vapor deposition.

（ｈ）は前記第１の孔及び第２の孔内に導電部材を充填する工程を示す図である。
前記（ｇ）工程において、電解メッキ用の共通電極１０を形成した後、続いて、電解メッキ用のマスクパターン１１を形成する。マスクパターン形成は、フォトリソグラフィーによる。尚、電解メッキ用のマスクパターン１１は、前記シリコン基板１の表面上に外部接続用のパッド部を同時に形成するようなパターン形状とすることも可能である。この場合、パッド部サイズは任意に設定可能である。
その後、電解メッキを行い第１の孔１ａ及び第２の孔１ｂ内に導電部材１２（例えば、金（Ａｕ））を充填する。以上の工程により、前記第１の孔１ａ及び第２の孔１ｂ内への導電部材１２の充填が完了し、前記パッド部３と前記導電部材１２は接触状態となり、導通可能となる。 (H) is a figure which shows the process of filling an electroconductive member in the said 1st hole and 2nd hole.
In the step (g), after the common electrode 10 for electrolytic plating is formed, subsequently, a mask pattern 11 for electrolytic plating is formed. The mask pattern is formed by photolithography. Incidentally, the mask pattern 11 for electrolytic plating can be formed into a pattern shape that simultaneously forms a pad portion for external connection on the surface of the silicon substrate 1. In this case, the pad portion size can be arbitrarily set.
Thereafter, electrolytic plating is performed to fill the first hole 1a and the second hole 1b with a conductive member 12 (for example, gold (Au)). Through the above steps, the filling of the conductive member 12 into the first hole 1a and the second hole 1b is completed, and the pad portion 3 and the conductive member 12 are brought into contact with each other and can be conducted.

（ｉ）はシリコン基板面上の不要共通電極を除去する工程を示す図である。
前記（ｇ）工程において、導電部材１２を充填した後、不要共通電極除去用のマスクパターン１３をフォトリソグラフィーにより形成し、不要となる共通電極１０の一部（図中破線で示した部分）をウエットエッチングにより除去してから、不要共通電極除去用のマスクパターン１３を除去し、本発明の貫通電極付き基板が完成する。 (I) is a figure which shows the process of removing the unnecessary common electrode on a silicon substrate surface.
In the step (g), after the conductive member 12 is filled, a mask pattern 13 for removing unnecessary common electrodes is formed by photolithography, and a part of the common electrode 10 that is not necessary (portion indicated by a broken line in the drawing) is formed. After removing by wet etching, the unnecessary common electrode removing mask pattern 13 is removed, and the substrate with through electrodes of the present invention is completed.

前述の製造方法により製造された貫通電極付き基板は、前記パッド部３の領域よりも大きい径を有する第１の孔１ａをシリコン基板１の厚みに対し、半分以上で、且つ前記絶縁膜２まで達しない深さまで形成し、第２の孔１ｂを前記パッド部３の領域に対応した孔径で形成するので、レジスト膜形成が問題なく行え、後工程における導電部材１２の充填が確実になされるので、導通状態は良好で、信頼性の高い貫通電極付き基板が得られる。   In the substrate with a through electrode manufactured by the above-described manufacturing method, the first hole 1a having a diameter larger than the area of the pad portion 3 is more than half of the thickness of the silicon substrate 1 and up to the insulating film 2. Since the second hole 1b is formed with a hole diameter corresponding to the area of the pad portion 3, the resist film can be formed without any problem, and the conductive member 12 can be reliably filled in a subsequent process. In addition, a conductive substrate is good and a highly reliable substrate with a through electrode can be obtained.

また、前記第１の孔１ａ上面に露出する前記導電部材１２は、外部接続用の端子として利用できるものであるため、これに接続される、例えば、電子部品のパッド部に対応させた大きさの孔径で形成することができる。ただし、第２の孔１ｂの孔径は、前記パッド部３の領域に収まるサイズに制約される。   Further, the conductive member 12 exposed on the upper surface of the first hole 1a can be used as a terminal for external connection, and is therefore connected to this, for example, in a size corresponding to a pad portion of an electronic component. It can be formed with a hole diameter of. However, the hole diameter of the second hole 1 b is limited to a size that can be accommodated in the area of the pad portion 3.

また、前記第１の孔１ａ上方に、前記導電部材１２を充填させるためのマスクパターン形状を用い、前記導電部材１２と同時に、別途、外部接続用のパッド部を形成することができる。前記外部接続用のパッド部は、前記マスクパターン形状を変更するのみで可能なため、その形成が容易であり、任意の形状、サイズで形成することができる。よって、種々の電子部品等のパッド面に対応させて形成できる。   Further, a pad portion for external connection can be separately formed simultaneously with the conductive member 12 by using a mask pattern shape for filling the conductive member 12 above the first hole 1a. Since the pad portion for external connection can be formed only by changing the mask pattern shape, it can be easily formed, and can be formed in any shape and size. Therefore, it can be formed corresponding to the pad surface of various electronic components.

本発明の貫通電極付き基板の製造方法を説明する図で、（ａ）〜（ｉ）は各工程における貫通電極部の状態を示す断面図。It is a figure explaining the manufacturing method of the board | substrate with a penetration electrode of this invention, (a)-(i) is sectional drawing which shows the state of the penetration electrode part in each process. 従来技術による貫通電極付き基板の製造方法を説明する図で、（ａ）〜（ｆ）は、各工程における貫通電極部の状態を示す断面図。It is a figure explaining the manufacturing method of the board | substrate with a penetration electrode by a prior art, (a)-(f) is sectional drawing which shows the state of the penetration electrode part in each process. レジスト膜形成状態の一例を示す断面図。Sectional drawing which shows an example of a resist film formation state. レジスト膜形成状態の他の例を示す断面図。Sectional drawing which shows the other example of a resist film formation state.

符号の説明Explanation of symbols

１ シリコン基板
１ａ 第１の孔
１ｂ 第２の孔
２ 絶縁膜
３ パッド部
４ マスクパターン
５ フォトマスク
６ マスクパターン
７ 絶縁膜
８ フォトマスク
９ マスクパターン
１０ 共通電極
１１ マスクパターン
１２ 導電部材
１３ マスクパターン
２０ シリコン基板
２０ａ 孔
２１ 絶縁膜
２２ パッド部
２３ マスクパターン
２４ 絶縁膜
２５ マスクパターン
２６ フォトマスク
２７ 共通電極
２８ マスクパターン
２９ 導電部材
３０ レジスト膜
３１ レジスト膜 DESCRIPTION OF SYMBOLS 1 Silicon substrate 1a 1st hole 1b 2nd hole 2 Insulating film 3 Pad part 4 Mask pattern 5 Photomask 6 Mask pattern 7 Insulating film 8 Photomask 9 Mask pattern 10 Common electrode 11 Mask pattern 12 Conductive member 13 Mask pattern 20 Silicon substrate 20a Hole 21 Insulating film 22 Pad part 23 Mask pattern 24 Insulating film 25 Mask pattern 26 Photomask 27 Common electrode 28 Mask pattern 29 Conductive member 30 Resist film 31 Resist film

Claims (4)

一主面に絶縁膜と回路パターンを有し、前記絶縁膜上に回路パターンと接続されたパッド部を有するシリコン基板に、前記パッド部と電気的接続を成すよう形成された貫通電極を備えた貫通電極付き基板の製造方法であって、
少なくとも、
前記パッド部の領域よりも広い孔径を有する第１の孔を、前記シリコン基板の前記パッド部が形成された面とは反対側の面から、前記シリコン基板の厚みに対し、半分以上、且つ前記絶縁膜まで達しない深さまでエッチングにより形成する第１工程と、
前記第１の孔底部から、前記パッド部に向け、当該パッド部領域に対応した孔径を有する第２の孔を、前記絶縁膜が露出する位置までエッチングにより形成する第２工程と、
前記第１の孔と前記第２の孔内面に絶縁膜を形成する第３工程と、
前記第２の孔底部に位置する前記第３工程により形成された前記絶縁膜及び前記シリコン基板の一主面にある前記絶縁膜を除去し、前記パッド部の一部を露出させる第４工程と、
前記第１の孔及び前記第２の孔内に、導電部材を充填する第５工程と、
を有することを特徴とする貫通電極付き基板の製造方法。 A silicon substrate having an insulating film and a circuit pattern on one main surface and having a pad portion connected to the circuit pattern on the insulating film is provided with a through electrode formed to be electrically connected to the pad portion. A method of manufacturing a substrate with a through electrode,
at least,
The first hole having a larger hole diameter than the area of the pad portion is more than half of the thickness of the silicon substrate from the surface of the silicon substrate opposite to the surface on which the pad portion is formed, and the A first step of etching to a depth not reaching the insulating film;
A second step of forming a second hole having a hole diameter corresponding to the pad portion region by etching from the bottom of the first hole toward the pad portion to a position where the insulating film is exposed;
A third step of forming an insulating film on the inner surface of the first hole and the second hole;
A fourth step in which the insulating film formed in the third step located at the bottom of the second hole and the insulating film on one main surface of the silicon substrate are removed, and a part of the pad portion is exposed; ,
A fifth step of filling the first hole and the second hole with a conductive member;
A method for producing a substrate with a through electrode, comprising: 前記第１の孔及び前記第２の孔内に導電部材を充填する第５工程において、前記シリコン基板面の第１の孔上方に、前記導電部材と連続する外部接続用のパッド部を前記導電部材の充填を行うと同時に形成することを特徴とする請求項１に記載の貫通電極付き基板の製造方法。   In a fifth step of filling the first hole and the second hole with a conductive member, an external connection pad portion continuous with the conductive member is disposed above the first hole on the silicon substrate surface. The method for producing a substrate with through electrodes according to claim 1, wherein the formation is performed simultaneously with filling of the members. 前記請求項１又は２の製造方法により成る貫通電極付き基板であって、
一主面に絶縁膜と回路パターンを有し、前記絶縁膜上に回路パターンと接続されたパッド部を備えたシリコン基板に、当該シリコン基板の厚みに対し、半分以上、且つ前記絶縁膜まで達しない深さの、前記パッド部の領域よりも広い孔径を有する第１の孔と、当該第１の孔底部から、前記パッド部に向け、当該パッド部領域に対応した孔径を有する第２の孔とで貫通孔を構成し、当該貫通孔内に導電部材を充填して、前記シリコン基板の両面間を導通可能にしたことを特徴とする貫通電極付き基板。 A substrate with a through electrode comprising the manufacturing method according to claim 1 or 2,
A silicon substrate having an insulating film and a circuit pattern on one main surface, and having a pad portion connected to the circuit pattern on the insulating film, reaching more than half of the thickness of the silicon substrate and reaching the insulating film A first hole having a larger hole diameter than the area of the pad portion, and a second hole having a hole diameter corresponding to the pad portion area from the bottom of the first hole toward the pad portion. And a through-hole is formed, and a conductive member is filled in the through-hole so as to allow conduction between both surfaces of the silicon substrate. 前記導電部材は、前記第１の孔内からシリコン基板の表面上に突出するよう連続して形成されており、外部接続用のパッド部を構成していることを特徴とする請求項３に記載の貫通電極付き基板。   The said conductive member is continuously formed so that it may protrude on the surface of a silicon substrate from the inside of the said 1st hole, The pad part for external connection is comprised, It is characterized by the above-mentioned. Substrate with through electrode.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013028598A1 (en) * 2011-08-19 2013-02-28 William Marsh Rice University Anode battery materials and methods of making the same
JP2013239589A (en) * 2012-05-15 2013-11-28 Rohm Co Ltd Semiconductor device, manufacturing method of the same and electronic component
US9543200B2 (en) 2013-02-21 2017-01-10 Samsung Electronics Co., Ltd. Methods for fabricating semiconductor devices having through electrodes

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013028598A1 (en) * 2011-08-19 2013-02-28 William Marsh Rice University Anode battery materials and methods of making the same
US9340894B2 (en) 2011-08-19 2016-05-17 William Marsh Rice University Anode battery materials and methods of making the same
JP2013239589A (en) * 2012-05-15 2013-11-28 Rohm Co Ltd Semiconductor device, manufacturing method of the same and electronic component
US9425138B2 (en) 2012-05-15 2016-08-23 Rohm Co., Ltd. Semiconductor device having through-electrode
US10147675B2 (en) 2012-05-15 2018-12-04 Rohm Co., Ltd. Semiconductor device having through-electrode
US9543200B2 (en) 2013-02-21 2017-01-10 Samsung Electronics Co., Ltd. Methods for fabricating semiconductor devices having through electrodes

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