JP2009267215A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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JP2009267215A
JP2009267215A JP2008116997A JP2008116997A JP2009267215A JP 2009267215 A JP2009267215 A JP 2009267215A JP 2008116997 A JP2008116997 A JP 2008116997A JP 2008116997 A JP2008116997 A JP 2008116997A JP 2009267215 A JP2009267215 A JP 2009267215A
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film
photosensitive polyimide
polyimide precursor
resist
precursor
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Masashi Kanamori
正志 金森
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Fuji Electric Co Ltd
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Fuji Electric Device Technology Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device for reducing the variations in the dimension precision of a polyimide film, and for suppressing the occurrence of any cracks by suppressing an internal stress, and for reducing the appearance failure of an element. <P>SOLUTION: A non-photosensitive polyimide film 3 is laminated on a photosensitive polyimide film 2 in a double-layer structure so that the thickness of each film can be made thinner than the case of forming those films in a single-layer. Thus, the occurrence of any cracks is suppressed, and the appearance failure of an element related with the cracks is reduced. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

この発明は、半導体装置の製造方法に関し、特に、表面保護膜として多用されるポリイミド膜の形成方法に関する。   The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a polyimide film frequently used as a surface protective film.

ポリイミド膜は電気絶縁性や耐熱性等に優れているため、半導体装置の表面保護膜として多用されている。ポリイミドには、非感光性ポリイミドと感光性ポリイミドがある。非感光性ポリイミドは安価ではあるがパターニングの寸法精度が必ずしも良くない。一方、感光性ポリイミドは光が当たった箇所が正確にパターニングされるので寸法精度はよいが、高価である。
通常は安価な非感光性ポリイミドが半導体装置の表面保護膜として多用されている。つぎに、従来の非感光性ポリイミド膜の形成方法を説明する。
図2は、従来の非感光性ポリイミド膜の形成方法であり、同図(a)〜同図(d)は工程順に示した要部製造工程断面図である。
まず、液体状の感光剤を含有しない非感光性ポリイミド前駆体を、回転塗布しベーク(熱処理)して半導体ウェハ51上に非感光性ポリイミド前駆体膜52aを形成する。さらに感光剤を含有するポジ型レジスト前駆体を同様に回転塗布し、ベークして非感光性ポリイミド前駆体膜52a上にレジスト膜53を形成する(同図(a))。
次に、パターンが描画されたマスク54を使用して紫外線55を照射して露光処理をすると、レジスト膜53が感光される。図中の符号の56が感光した箇所のレジスト膜である(同図(b))。
Polyimide films are widely used as surface protective films for semiconductor devices because they are excellent in electrical insulation and heat resistance. Polyimide includes non-photosensitive polyimide and photosensitive polyimide. Although non-photosensitive polyimide is inexpensive, the dimensional accuracy of patterning is not always good. On the other hand, the photosensitive polyimide has a good dimensional accuracy because the portion exposed to light is accurately patterned, but is expensive.
Usually, inexpensive non-photosensitive polyimide is frequently used as a surface protective film of a semiconductor device. Next, a conventional method for forming a non-photosensitive polyimide film will be described.
FIG. 2 shows a conventional method for forming a non-photosensitive polyimide film, and FIGS. 2A to 2D are cross-sectional views of the main part manufacturing process shown in the order of processes.
First, a non-photosensitive polyimide precursor containing no liquid photosensitizer is spin-coated and baked (heat treatment) to form a non-photosensitive polyimide precursor film 52 a on the semiconductor wafer 51. Further, a positive resist precursor containing a photosensitive agent is similarly spin-coated and baked to form a resist film 53 on the non-photosensitive polyimide precursor film 52a ((a) in the figure).
Next, when an exposure process is performed by irradiating ultraviolet rays 55 using a mask 54 on which a pattern is drawn, the resist film 53 is exposed. In the figure, reference numeral 56 denotes a resist film at the exposed portion ((b) in the figure).

現像処理を行うと、感光した箇所のレジスト膜56が溶解してパターンが形成される。さらに、現像液が非感光性ポリイミド前駆体膜52aのエッチング液でもあるため、現像処理中には、レジスト膜53が溶解した部分の直下にある非感光性ポリイミド前駆体膜52aも同時にパターン形成される。非感光性ポリイミド前駆体膜52aの厚さは10μm程度あるため、レジスト膜53の開口部から進入するエッチング液(現像液)による作用で、非感光性ポリイミド前駆体膜52aは等方性エッチングされる。等方性エッチングによって非感光性ポリイミド前駆体膜52aのパターンは、レジストパターンよりも大幅に後退した状態に形成される(同図(c))。
次に、残ったレジスト膜53を除去して、最後に加熱処理を行えば、パターン形成された非感光性ポリイミド膜52が完成する(同図(d))。
また、特許文献1には、非感光性ポリイミドをポジ型レジストをマスクにエッチングを行い、エッチングによって形成される非感光性ポリイミドのオーバーハング部を再度のウェットエッチングで除去して庇部分を丸めることが開示されている。このオーバーハング部の断面は、参考までに図2(c)に点線58で示した。
また、特許文献2には、非感光性ポリイミド前駆体または感光性ポリイミド前駆体をフォトリソグラフィーした後、160°以上で加熱することで開口部にテーパーを付けることが開示されている。
特開平6−268378号公報 特開平6−318539号公報
When the development process is performed, the resist film 56 at the exposed portion is dissolved to form a pattern. Further, since the developing solution is also an etching solution for the non-photosensitive polyimide precursor film 52a, the non-photosensitive polyimide precursor film 52a immediately below the portion where the resist film 53 is dissolved is simultaneously patterned during the developing process. The Since the thickness of the non-photosensitive polyimide precursor film 52a is about 10 μm, the non-photosensitive polyimide precursor film 52a is isotropically etched by the action of the etching solution (developer) entering from the opening of the resist film 53. The By the isotropic etching, the pattern of the non-photosensitive polyimide precursor film 52a is formed so as to recede significantly from the resist pattern ((c) in the figure).
Next, if the remaining resist film 53 is removed and finally heat treatment is performed, a patterned non-photosensitive polyimide film 52 is completed ((d) in the figure).
In Patent Document 1, non-photosensitive polyimide is etched using a positive resist as a mask, and the overhang portion of the non-photosensitive polyimide formed by etching is removed by wet etching again to round the ridge portion. Is disclosed. The cross section of the overhang portion is indicated by a dotted line 58 in FIG.
Patent Document 2 discloses that after opening a non-photosensitive polyimide precursor or a photosensitive polyimide precursor, the opening is tapered by heating at 160 ° or more.
JP-A-6-268378 JP-A-6-318539

前記した非感光性ポリイミド前駆体は塗布された後、ベーク処理されて非感光性ポリイミド前駆体膜52aとなり、その後にレジスト膜53をマスクとしてパターンニングされる。このベーク処理で半導体ウェハ51内に温度の低い箇所があると、その箇所の非感光ポリイミド前駆体膜52aのサイドエッチング量は大きくなる。そのため、温度むらがあるとサイドエッチング量にバラツキが生じて、そのバラツキが非感光性ポリイミド膜52のパターンの寸法精度のバラツキになる。
また、ポリイミド前駆体を1回の回転塗布で10μm程度の厚い膜厚にする場合、一般的には高粘度のポリイミド前駆体を使用することになる。この高粘度のポリイミド前駆体は、回転塗布後の膜厚にバラツキが発生し易い。そのため、パターンの寸法精度のバラツキが生じ易い。
また、表面保護膜としての信頼性を確保するために、非感光性ポリイミド膜52の膜厚を10μm程度に厚くすると、加熱処理される際に非感光性ポリイミド前駆体膜52aが収縮して、内部応力が発生しパターンの端部に亀裂を多数発生させる(図2(d))。
一方、寸法精度のバラツキを小さくするために、サイドエッチング量の小さい感光性ポリイミド膜を用いる方法がある。しかし、感光性ポリイミド膜の膜厚は7μmを超えると、非感光性ポリイミド膜52と同様に加熱処理工程で内部応力が発生し出し、パターン端部に亀裂が生じ易くなる。信頼性を確保するために、この膜厚を10μm以上にすると亀裂(図2(d)の亀裂57に相当する)が大きくなり素子の外観不良になる割合が高くなる。この亀裂57は表面層に形成される場合が多いために信頼性上は問題にならないことが多い。
The non-photosensitive polyimide precursor described above is applied and then baked to form a non-photosensitive polyimide precursor film 52a, and then patterned using the resist film 53 as a mask. If there is a low temperature part in the semiconductor wafer 51 by this baking process, the side etching amount of the non-photosensitive polyimide precursor film 52a at that part becomes large. Therefore, if the temperature is uneven, the amount of side etching varies, and the variation results in variations in the dimensional accuracy of the pattern of the non-photosensitive polyimide film 52.
Moreover, when making a polyimide precursor into a thick film thickness of about 10 micrometers by one time spin-coating, generally a highly viscous polyimide precursor will be used. This high-viscosity polyimide precursor tends to vary in film thickness after spin coating. Therefore, variations in the dimensional accuracy of the pattern are likely to occur.
Further, in order to ensure the reliability as the surface protective film, when the film thickness of the non-photosensitive polyimide film 52 is increased to about 10 μm, the non-photosensitive polyimide precursor film 52a is contracted during the heat treatment, Internal stress is generated, and many cracks are generated at the end of the pattern (FIG. 2D).
On the other hand, in order to reduce variation in dimensional accuracy, there is a method using a photosensitive polyimide film having a small side etching amount. However, if the film thickness of the photosensitive polyimide film exceeds 7 μm, internal stress is generated in the heat treatment step as in the case of the non-photosensitive polyimide film 52, and cracks are likely to occur at the pattern end. In order to ensure reliability, when the film thickness is 10 μm or more, cracks (corresponding to the cracks 57 in FIG. 2D) increase, and the ratio of defective appearance of the element increases. Since the crack 57 is often formed in the surface layer, there is often no problem in terms of reliability.

前記の特許文献1および特許文献2では、ポリイミド膜に発生する亀裂については記載されていない。また、感光性ポリイミド膜上に非感光性ポリイミド膜を積層した2層構造にして、亀裂発生の抑制やパターンの寸法精度のバラツキを低減することについては記載されていない。
この発明の目的は、前記の課題を解決して、ポリイミド膜のパターンの寸法精度のバラツキを小さく抑え、内部応力を抑制して亀裂の発生を抑え、素子の外観不良を低減できる半導体装置の製造方法を提供することにある。
In Patent Document 1 and Patent Document 2 described above, there is no description of cracks generated in the polyimide film. Further, there is no description about suppressing the occurrence of cracks or reducing variations in the dimensional accuracy of a pattern by forming a two-layer structure in which a non-photosensitive polyimide film is laminated on a photosensitive polyimide film.
The object of the present invention is to manufacture a semiconductor device that solves the above-mentioned problems, suppresses variations in the dimensional accuracy of the polyimide film pattern, suppresses internal stress, suppresses the occurrence of cracks, and reduces the appearance defects of the element. It is to provide a method.

前記の目的を達成するために、半導体基板上に感光性ポリイミド前駆体を回転塗布する工程と、該感光性ポリイミド前駆体を熱処理(ベーク)して感光性ポリイミド前駆体膜を形成する工程と、該感光性ポリイミド前駆体上に非感光性ポリイミド前駆体を回転塗布する工程と、該非感光性ポリイミド前駆体を熱処理して非感光性ポリイミド前駆体膜を形成する工程と、該非感光性ポリイミド前駆体膜上にレジスト前駆体を回転塗布する工程と、
該レジスト前駆体を熱処理してレジスト膜とする工程と、パターンが描画されたマスクを用いて前記レジスト膜および前記感光性ポリイミド前駆体膜を露光する工程と、前記レジスト膜、前記非感光性ポリイミド前駆体膜および前記感光性ポリイミド前駆体膜を現像液で現像しパターニングする工程と、前記非感光性ポリイミド前駆体膜と前記感光性ポリイミド前駆体膜を加熱処理して、非感光性ポリイミド膜および感光性ポリイミド膜からなる2層構造のポリイミド膜を形成する工程と、を含む製造方法とする。
また、前記感光性ポリイミド前駆体および前記レジスト前駆体が、それぞれポジ型であるとよい。
また、前記非感光性ポリイミド膜の膜厚と前記感光性ポリイミド膜の膜厚がそれぞれ3μm〜7μmであるとよい。
In order to achieve the above object, a step of spin-coating a photosensitive polyimide precursor on a semiconductor substrate, a step of heat-treating (baking) the photosensitive polyimide precursor to form a photosensitive polyimide precursor film, A step of spin-coating a non-photosensitive polyimide precursor on the photosensitive polyimide precursor; a step of heat-treating the non-photosensitive polyimide precursor to form a non-photosensitive polyimide precursor film; and the non-photosensitive polyimide precursor A step of spin-coating a resist precursor on the film;
A step of heat-treating the resist precursor to form a resist film; a step of exposing the resist film and the photosensitive polyimide precursor film using a mask on which a pattern is drawn; and the resist film and the non-photosensitive polyimide. A step of developing and patterning the precursor film and the photosensitive polyimide precursor film with a developing solution, heat-treating the non-photosensitive polyimide precursor film and the photosensitive polyimide precursor film, and a non-photosensitive polyimide film and Forming a two-layered polyimide film made of a photosensitive polyimide film.
The photosensitive polyimide precursor and the resist precursor may be positive types.
The film thickness of the non-photosensitive polyimide film and the film thickness of the photosensitive polyimide film may be 3 μm to 7 μm, respectively.

また、前記レジスト膜、前記非感光性ポリイミド前駆体膜および前記感光性ポリイミド前駆体膜を同一の現像液で現像しパターニングするとよい。   The resist film, the non-photosensitive polyimide precursor film, and the photosensitive polyimide precursor film may be developed and patterned with the same developer.

この発明によれば、感光性ポリイミド膜上に非感光性ポリイミド膜を積層する2層構造にして、それぞれの膜厚を1層で形成するより薄くすることで、亀裂の発生を抑制できる。亀裂の発生が抑制されることで、亀裂に係わる素子の外観不良を低減できる。
また、感光性ポリイミド膜を下地にすることで、パターンの寸法精度のバラツキを小さくできる。
また、感光性ポリイミド膜上に非感光性ポリイミド膜を積層することで開口部の側壁が階段状となりパターン端部(開口部)での内部応力を分散できるのでパターン端部に亀裂が発生するのを抑制できる。
また、感光性ポリイミド膜と非感光性ポリイミド膜のそれぞれの膜厚を薄くできるので、低粘度のポリイミド前駆体を用いることができて、回転塗布での膜厚を均一化できる。それによって、パターンの寸法精度のバラツキを低減できる。
According to the present invention, the occurrence of cracks can be suppressed by forming a two-layer structure in which a non-photosensitive polyimide film is laminated on a photosensitive polyimide film, and making each film thickness thinner than that formed by a single layer. By suppressing the occurrence of cracks, it is possible to reduce the appearance defects of the elements related to the cracks.
Further, by using the photosensitive polyimide film as a base, variation in pattern dimensional accuracy can be reduced.
In addition, by laminating a non-photosensitive polyimide film on the photosensitive polyimide film, the side wall of the opening becomes stepped, and internal stress at the pattern edge (opening) can be dispersed, so cracks occur at the pattern edge. Can be suppressed.
Moreover, since each film thickness of a photosensitive polyimide film and a non-photosensitive polyimide film can be made thin, a low viscosity polyimide precursor can be used and the film thickness by spin coating can be made uniform. Thereby, variations in the dimensional accuracy of the pattern can be reduced.

実施の形態を以下の実施例で図面を示しながら説明する。   Embodiments will be described in the following examples with reference to the drawings.

図1は、この発明の半導体装置の製造方法であり、同図(a)〜同図(d)は工程順に示した要部製造工程断面図である。この半導体装置の製造方法は、表面保護膜であるポリイミド膜の形成方法について説明したものである。
まず、液体状の感光剤を含有するポジ型感光性ポリイミド前駆体(例えば、東レ製フォトニース PW−1200シリーズなど)を半導体ウェハ1に回転塗布し、続いプリベーク(熱処理)して7μm程度の膜厚のポジ型感光性ポリイミド前駆体膜2aを半導体ウェハ1上に形成する。続いて感光剤を含有しない非感光性ポリイミド前駆体(例えば、東レ製セミコンファイン SP−400シリーズなど)を同様に感光性ポリイミド前駆体膜2aに回転塗布し、続いてプリベークして7μm程度の膜厚の非感光性ポリイミド前駆体膜3aを感光性ポリイミド前駆体膜2a上に形成する。さらに感光剤を含有するポジ型レジスト前駆体を同様に非感光性ポリイミド前駆体膜3aに回転塗布し、続いてプリベークしてレジスト膜4を非感光性ポリイミド前駆体膜3a上に形成する(同図(a))。
次に、パターンが描画されたマスク5を使用して紫外線6を照射して露光処理をすると、レジスト膜4と下層の感光性ポリイミド前駆体膜2aが感光される.図中の符号の7は感光した箇所のレジスト膜であり、8は感光した箇所の感光性ポリイミド前駆体膜である(同図(b))。
FIG. 1 shows a method of manufacturing a semiconductor device according to the present invention. FIGS. 1A to 1D are cross-sectional views showing a main part manufacturing process shown in the order of steps. This method for manufacturing a semiconductor device describes a method for forming a polyimide film which is a surface protective film.
First, a positive photosensitive polyimide precursor containing a liquid photosensitive agent (for example, Toray Photo Nice PW-1200 series) is spin-coated on the semiconductor wafer 1, followed by pre-baking (heat treatment) to form a film having a thickness of about 7 μm. A thick positive photosensitive polyimide precursor film 2 a is formed on the semiconductor wafer 1. Subsequently, a non-photosensitive polyimide precursor containing no photosensitizer (for example, Semicon Fine SP-400 series manufactured by Toray Industries, Inc.) is similarly spin-coated on the photosensitive polyimide precursor film 2a, followed by pre-baking to form a film of about 7 μm. A thick non-photosensitive polyimide precursor film 3a is formed on the photosensitive polyimide precursor film 2a. Further, a positive resist precursor containing a photosensitive agent is similarly spin-coated on the non-photosensitive polyimide precursor film 3a, and then pre-baked to form a resist film 4 on the non-photosensitive polyimide precursor film 3a (same as above). Figure (a)).
Next, when an exposure process is performed by irradiating ultraviolet rays 6 using a mask 5 on which a pattern is drawn, the resist film 4 and the underlying photosensitive polyimide precursor film 2a are exposed. In the figure, reference numeral 7 denotes a resist film at the exposed portion, and reference numeral 8 denotes a photosensitive polyimide precursor film at the exposed portion ((b) in the figure).

現像処理を行うと、感光した箇所のレジスト膜7が溶解してパターンが形成される。さらに、現像液が非感光性ポリイミド前駆体膜3aのエッチング液でもあるため、現像処理中には、感光した箇所のレジスト膜7が溶解した部分の直下にある非感光性ポリイミド前駆体膜3aも同時にパターン形成される。続いて、下層の感光された部分の感光性ポリイミド前駆体膜8においても、現像液に溶解されるため、同時に感光性ポリイミド前駆体膜2aはパターン形成される(同図(c))。
次に、残ったレジスト膜4を除去して、最後に加熱処理(ポストベーク)を行えば、前駆体膜が縮小し、5μmの膜厚の感光性ポリイミド膜2上に5μmの膜厚の非感光性ポリイミド膜3が形成された10μmの膜厚のパターン形成されたポリイミド膜9が完成する。尚、非感光性ポリイミド前駆体膜3aの開口部の側壁10が例えオーバーハングされても、この加熱処理で表面の庇が丸められてオーバーハング部は消滅する(同図(d))。
完成後のポリイミド膜9は、非感光性ポリイミド膜3と感光性ポリイミド膜2の2層構造となっており、それぞれの膜厚は5μmでパターンの端部は階段状になっている。それぞれの膜厚が5μmと薄くなっており、さらにパターンの端部であるA部は階段状となっているため、パターンの端部での内部応力が分散され、しかも小さくなる。
When the development process is performed, the resist film 7 at the exposed portion is dissolved to form a pattern. Furthermore, since the developing solution is also an etching solution for the non-photosensitive polyimide precursor film 3a, the non-photosensitive polyimide precursor film 3a directly under the portion where the resist film 7 in the exposed portion is dissolved is also developed during the developing process. A pattern is formed at the same time. Subsequently, the photosensitive polyimide precursor film 8 in the exposed portion of the lower layer is also dissolved in the developer, so that the photosensitive polyimide precursor film 2a is simultaneously patterned ((c) in the figure).
Next, if the remaining resist film 4 is removed and finally heat treatment (post-bake) is performed, the precursor film is reduced, and a non-coated film having a film thickness of 5 μm is formed on the photosensitive polyimide film 2 having a film thickness of 5 μm. A patterned polyimide film 9 having a thickness of 10 μm on which the photosensitive polyimide film 3 is formed is completed. Even if the side wall 10 of the opening of the non-photosensitive polyimide precursor film 3a is overhanged, the surface wrinkles are rounded by this heat treatment, and the overhang portion disappears ((d) in the figure).
The completed polyimide film 9 has a two-layer structure of a non-photosensitive polyimide film 3 and a photosensitive polyimide film 2, each having a film thickness of 5 μm and a pattern end portion being stepped. Each film thickness is as thin as 5 μm, and the A portion which is the end portion of the pattern is stepped, so that the internal stress at the end portion of the pattern is dispersed and becomes smaller.

そのため、感光性ポリイミド膜2や非感光性ポリイミド膜3に発生する亀裂は大幅に低減される。
また、下地は感光性ポリイミド膜2であるため、開口部11の寸法はマスクパターンの露光精度で決定される。そのため、パターンの寸法精度のバラツキが少くなる。
前記の感光性ポリイミド膜2と非感光性ポリイミド膜3を合わせた膜厚を10μm以上とすると信頼性の観点からよい。また、感光性ポリイミド膜と非感光性ポリイミド膜のそれぞれの厚さを3μm〜7μmとするとよい。これは、感光性ポリイミド膜と非感光性ポリイミド膜のそれぞれの厚さが3μm未満では、開口部以外の箇所でのステップカバレージに不具合(露出するなど)が生じ組立てが困難になるためである。また、感光性ポリイミド膜と非感光性ポリイミド膜のそれぞれの厚さが7μmを超えると、前記したようにパターンエッジに亀裂が入り易くなり外観不良の発生する割合が増加する。
本実施例のように、2回の回転塗布でポリイミド膜を形成する場合では、1回で回転塗布されるポリイミド前駆体膜の厚さは薄くできるので、低粘度のポリイミド前駆体を使用できる。
低粘度のポリイミド前駆体を使用することで、高粘度のポリイミド前駆体を使用する場合に比べ、ポリイミド膜の厚さのバラツキは少なくできる。ポリイミド膜の厚さのバラツキが小さくなると、寸法精度のバラツキが小さくできる。このようにポリイミド膜を2層構造とすることで、半導体装置の量産を行うとき、品質が安定した良好なポリイミド膜を使用することができる。
Therefore, the crack which generate | occur | produces in the photosensitive polyimide film 2 and the non-photosensitive polyimide film 3 is reduced significantly.
Further, since the base is the photosensitive polyimide film 2, the dimension of the opening 11 is determined by the exposure accuracy of the mask pattern. For this reason, variations in the dimensional accuracy of the pattern are reduced.
From the viewpoint of reliability, the total thickness of the photosensitive polyimide film 2 and the non-photosensitive polyimide film 3 is 10 μm or more. The thicknesses of the photosensitive polyimide film and the non-photosensitive polyimide film are preferably 3 μm to 7 μm. This is because if the thickness of each of the photosensitive polyimide film and the non-photosensitive polyimide film is less than 3 μm, the step coverage in a portion other than the opening portion becomes defective (exposed) and it is difficult to assemble. On the other hand, when the thickness of each of the photosensitive polyimide film and the non-photosensitive polyimide film exceeds 7 μm, as described above, the pattern edge is easily cracked and the rate of appearance failure increases.
In the case where the polyimide film is formed by two spin coatings as in this embodiment, the polyimide precursor film that is spin-coated once can be made thin, so that a low-viscosity polyimide precursor can be used.
By using a low-viscosity polyimide precursor, variations in the thickness of the polyimide film can be reduced as compared with the case of using a high-viscosity polyimide precursor. When the variation in the thickness of the polyimide film is reduced, the variation in dimensional accuracy can be reduced. Thus, when the polyimide film has a two-layer structure, a good polyimide film with stable quality can be used when mass-producing semiconductor devices.

この発明の半導体装置の製造方法であり、(a)〜(d)は工程順に示した要部製造工程断面図BRIEF DESCRIPTION OF THE DRAWINGS It is a manufacturing method of the semiconductor device of this invention, (a)-(d) is principal part manufacturing process sectional drawing shown to process order 従来の非感光性ポリイミド膜の形成方法であり、(a)〜(d)は工程順に示した要部製造工程断面図It is the formation method of the conventional non-photosensitive polyimide film, (a)-(d) is principal part manufacturing process sectional drawing shown to process order

符号の説明Explanation of symbols

1 半導体ウェハ
2 感光性ポリイミド膜
2a 感光性ポリイミド前駆体膜
3 非感光性ポリイミド膜
3a 非感光性ポリイミド前駆体膜
4 レジスト膜
5 マスク
6 紫外線
7 感光された箇所のレジスト膜
8 感光された箇所の感光性ポリイミド前駆体膜
9 ポリイミド膜
10 側壁
11 開口部
DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2 Photosensitive polyimide film 2a Photosensitive polyimide precursor film 3 Non-photosensitive polyimide film 3a Non-photosensitive polyimide precursor film 4 Resist film 5 Mask 6 Ultraviolet light 7 Resist film of the exposed part 8 Resist film of the exposed part Photosensitive polyimide precursor film 9 Polyimide film 10 Side wall 11 Opening

Claims (4)

半導体基板上に感光性ポリイミド前駆体を回転塗布する工程と、
該感光性ポリイミド前駆体を熱処理して感光性ポリイミド前駆体膜を形成する工程と、
該感光性ポリイミド前駆体上に非感光性ポリイミド前駆体を回転塗布する工程と、
該非感光性ポリイミド前駆体を熱処理して非感光性ポリイミド前駆体膜を形成する工程と、
該非感光性ポリイミド前駆体膜上にレジスト前駆体を回転塗布する工程と、
該レジスト前駆体を熱処理してレジスト膜とする工程と、
パターンが描画されたマスクを用いて前記レジスト膜および前記感光性ポリイミド前駆体膜を露光する工程と、
前記レジスト膜、前記非感光性ポリイミド前駆体膜および前記感光性ポリイミド前駆体膜を現像液で現像しパターニングする工程と、
前記非感光性ポリイミド前駆体膜と前記感光性ポリイミド前駆体膜を加熱処理して、非感光性ポリイミド膜および感光性ポリイミド膜からなる2層構造のポリイミド膜を形成する工程と、
を含むことを特徴とする半導体装置の製造方法。
A step of spin-coating a photosensitive polyimide precursor on a semiconductor substrate;
Heat-treating the photosensitive polyimide precursor to form a photosensitive polyimide precursor film; and
A step of spin-coating a non-photosensitive polyimide precursor on the photosensitive polyimide precursor;
Heat-treating the non-photosensitive polyimide precursor to form a non-photosensitive polyimide precursor film;
A step of spin-coating a resist precursor on the non-photosensitive polyimide precursor film;
Heat-treating the resist precursor to form a resist film;
Exposing the resist film and the photosensitive polyimide precursor film using a mask on which a pattern is drawn; and
Developing and patterning the resist film, the non-photosensitive polyimide precursor film and the photosensitive polyimide precursor film with a developer; and
Heat-treating the non-photosensitive polyimide precursor film and the photosensitive polyimide precursor film to form a two-layer structure polyimide film comprising a non-photosensitive polyimide film and a photosensitive polyimide film;
A method for manufacturing a semiconductor device, comprising:
前記感光性ポリイミド前駆体および前記レジスト前駆体が、それぞれポジ型であることを特徴とする請求項1に記載の半導体装置の製造方法。 2. The method of manufacturing a semiconductor device according to claim 1, wherein each of the photosensitive polyimide precursor and the resist precursor is a positive type. 前記非感光性ポリイミド膜の膜厚と前記感光性ポリイミド膜の膜厚がそれぞれ3μm〜7μmであることを特徴とする請求項1または2に記載の半導体装置の製造方法。 3. The method of manufacturing a semiconductor device according to claim 1, wherein the film thickness of the non-photosensitive polyimide film and the film thickness of the photosensitive polyimide film are 3 μm to 7 μm, respectively. 前記レジスト膜、前記非感光性ポリイミド前駆体膜および前記感光性ポリイミド前駆体膜を同一の現像液で現像しパターニングすることを特徴とする請求項1または2に記載の半導体装置の製造方法。
3. The method of manufacturing a semiconductor device according to claim 1, wherein the resist film, the non-photosensitive polyimide precursor film, and the photosensitive polyimide precursor film are developed and patterned with the same developer.
JP2008116997A 2008-04-28 2008-04-28 Method for manufacturing semiconductor device Withdrawn JP2009267215A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103065961A (en) * 2011-10-21 2013-04-24 上海华虹Nec电子有限公司 Polyimide passivation layer manufacture processing method applied to high voltage devices
CN103887287A (en) * 2012-12-21 2014-06-25 瑞萨电子株式会社 Semiconductor Device And Method Of Manufacturing The Same

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04199849A (en) * 1990-11-29 1992-07-21 Nec Corp Manufacture of semiconductor device
JPH06268378A (en) * 1993-03-12 1994-09-22 Oki Electric Ind Co Ltd Formation method for via hole of multilayer interconnection board
JPH06318539A (en) * 1993-03-12 1994-11-15 Toray Ind Inc Formation of polyimide pattern
JPH07191469A (en) * 1993-12-25 1995-07-28 Sony Corp Selective formation of polyimide film
JPH07288280A (en) * 1994-04-18 1995-10-31 Hitachi Denshi Ltd Manufacture of semiconductor device
JPH0917777A (en) * 1995-06-30 1997-01-17 Nec Corp Manufacture of semiconductor device
JPH11145129A (en) * 1997-11-12 1999-05-28 Nec Corp Manufacture of semiconductor device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04199849A (en) * 1990-11-29 1992-07-21 Nec Corp Manufacture of semiconductor device
JPH06268378A (en) * 1993-03-12 1994-09-22 Oki Electric Ind Co Ltd Formation method for via hole of multilayer interconnection board
JPH06318539A (en) * 1993-03-12 1994-11-15 Toray Ind Inc Formation of polyimide pattern
JPH07191469A (en) * 1993-12-25 1995-07-28 Sony Corp Selective formation of polyimide film
JPH07288280A (en) * 1994-04-18 1995-10-31 Hitachi Denshi Ltd Manufacture of semiconductor device
JPH0917777A (en) * 1995-06-30 1997-01-17 Nec Corp Manufacture of semiconductor device
JPH11145129A (en) * 1997-11-12 1999-05-28 Nec Corp Manufacture of semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103065961A (en) * 2011-10-21 2013-04-24 上海华虹Nec电子有限公司 Polyimide passivation layer manufacture processing method applied to high voltage devices
CN103887287A (en) * 2012-12-21 2014-06-25 瑞萨电子株式会社 Semiconductor Device And Method Of Manufacturing The Same
JP2014123671A (en) * 2012-12-21 2014-07-03 Renesas Electronics Corp Semiconductor device and semiconductor device manufacturing method
US9818815B2 (en) 2012-12-21 2017-11-14 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
US10157974B2 (en) 2012-12-21 2018-12-18 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same

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