JP2009139695A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device, capable of easily forming different-pitch patterns. <P>SOLUTION: The method includes steps of: forming, on a film 20 of a processing object, resist patterns 31B containing a component capable of generating an acid by heating with pitches being differed between a memory cell forming area 11 and a peripheral circuit forming area 12; forming a fine pattern forming film 32 containing a component crosslinkable by the acid on the film 20; forming a sidewall film 33 on the circumference of the resist patterns 31B by crosslinking the fine pattern forming film 32 in the range to which the acid is supplied from the resist patterns 31B by heating; and forming a pattern composed of the sidewall film 33 on the memory cell forming area 11 and a pattern composed of the sidewall film 33 and the resist pattern 31B on the peripheral circuit forming area 12 by removing the fine pattern forming film 32 and the resist patterns 31B on the memory cell forming area 11. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing method for forming a fine pattern in a semiconductor device.

In the development of semiconductor integrated circuits, miniaturization of pattern dimensions is accelerating year by year. The promotion of this pattern dimension miniaturization is carried out by the optical lithography technology, and it is thought that the flow of pattern dimension miniaturization will continue for a while. The resolution (pattern dimension) of optical lithography is the Rayleigh equation expressed by the following equation (1) using the wavelength (λ) of the exposure apparatus and the lens numerical aperture (NA) used to realize the pattern dimension. Described.
Resolution = k ₁ × λ / NA (1)

If the pattern dimension (resolution) is determined by market requirements (cost, device performance), the k ₁ factor included in this equation is a value indicating the difficulty of the lithography technology that realizes it (specifically, Process constants determined mainly by resist performance, apparatus control, reticle pattern and process control). That is, when the k ₁ factor is small, lithography is difficult.

The recent acceleration of miniaturization of semiconductor devices has demanded pattern dimensions below the theoretical lithography limit of k ₁ = 0.25. In this region, a technique for forming a pattern pitch finer than the minimum pattern pitch that can be formed by lithography is required. As one of such methods, a microfabrication method using a side wall leaving process has been conventionally proposed (see, for example, Patent Document 1).

A description will be given of a microfabrication method by this conventional sidewall leaving process. First, a resist pattern made of a photoresist that becomes a dummy pattern in a later step is formed on a lower layer material such as a substrate. Next, a RELACS ^™ (Resist Enhancement Lithography Assisted by Chemical Shrink) polymer is applied around and above the resist pattern to form a RELACS polymer layer. Next, etching is performed to remove the RELACS polymer layer on the upper and lower layers of the resist pattern so as to leave the side wall of the resist pattern. Thereafter, the lower layer material is exposed and developed to remove the resist pattern, thereby forming a side wall portion. Then, an etching process is performed on the lower layer material using the side wall portion.

  However, the formation of a fine pattern by the conventional side wall leaving process only discloses a method for forming a fine pattern having a line and space with a pitch less than the resolution limit of lithography of light such as light and an electron beam. A method for easily forming a pattern and a pattern having a pitch larger than the fine pattern has not been disclosed.

US Pat. No. 6,383,952

  The present invention can easily form patterns with different pitches in the manufacture of a semiconductor device using a sidewall-remaining process, and in particular, a line-and-space fine pattern with a pitch below the resolution limit of lithography using radiation and its pattern An object of the present invention is to provide a semiconductor device manufacturing method capable of easily forming a line-and-space pattern having a pitch larger than that of a fine pattern.

  According to one embodiment of the present invention, a first line-and-space first resist pattern and a second resist pattern including a component capable of generating an acid by heating are formed on a film to be processed. A resist pattern forming step, a fine pattern forming film forming step of forming a fine pattern forming film containing a component crosslinkable with an acid on the processed film on which the first and second resist patterns are formed, and the first The first and second resist patterns and the fine pattern forming film are subjected to a heat treatment to crosslink the fine pattern forming film in a range where an acid is supplied from the resist pattern. A cross-linking step of forming a sidewall film around the substrate, and the fine pattern forming film and the first resist pattern that are not cross-linked from above the film to be processed And a sidewall film pattern forming step of forming a pattern made of the sidewall film and the second resist pattern on which the sidewall film is formed. Is done.

  According to the present invention, it is possible to easily form line and space patterns with different pitches in the side wall leaving process.

  Exemplary embodiments of a method for manufacturing a semiconductor device according to the present invention will be explained below in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments. The cross-sectional views of the semiconductor devices used in the following embodiments are schematic, and the relationship between the thickness and width of the layers, the ratio of the thicknesses of the layers, and the like are different from the actual ones. Moreover, the film thickness shown below is an example and is not limited to this.

(First embodiment)
1 to 2 are cross-sectional views schematically showing an example of the procedure of the semiconductor device manufacturing method according to the first embodiment of the present invention. Here, a memory cell portion in which a memory cell is formed, an operation of writing data to each memory cell of the memory cell portion, or an operation of reading data from each memory cell electrically connected to each memory cell of the memory cell portion, etc. An example in which a semiconductor device such as a NAND flash memory having a peripheral circuit portion necessary for the above-described peripheral circuit is processed by a process of leaving a side wall will be described as an example. In addition, here, a memory cell portion composed of a fine line and space pattern below the resolution limit of lithography by radiation such as light and an electron beam, and a rougher (pitch of the pitch) than the line and space pattern of the memory cell portion. A procedure of a manufacturing method in the case of processing a peripheral circuit portion configured by a large) line and space pattern will be described. In the following description, a region where the memory cell portion is formed is referred to as a memory cell formation region 11, and a region where the peripheral circuit portion is formed is referred to as a peripheral circuit formation region 12.

  First, as shown in FIG. 1A, a substrate 10 on which a film 20 to be processed is formed is prepared. The film 20 to be processed is a conductive material film that serves as a base for the gate electrode of the memory cell transistor that forms the memory cell of the memory cell portion formed on the substrate 10 or the field effect transistor of the peripheral circuit portion, for example. Alternatively, there is an electrical connection between the gate electrode and source / drain regions of the memory cell transistor in the memory cell portion formed on the substrate 10 and the field effect transistor in the peripheral circuit portion, and the wiring formed in the upper layer. An insulating film such as an insulating interlayer may be used. Here, the substrate 10 includes not only a substrate such as a silicon substrate but also a substrate in which a film such as a metal film or an insulating film or an element is formed on the upper surface. However, the drawings attached to this specification show the case where a semiconductor substrate is used as the substrate 10 and the case where a metal is used as the film 20 to be processed.

  Next, a resist composition is applied onto the film 20 to be processed formed on the substrate 10 by using a spin coating method or the like to form a resist film. The thickness of the resist film is, for example, about 0.7 μm to 1.0 μm. As the resist composition, a material that generates an acid component in the resist by heating is used. Examples of such materials include, in addition to positive resists composed of film-forming substances such as acrylic resins and novolac resins, and naphthoquinone diazide photosensitizers, chemically amplified resists that generate acid upon heating. Can do. The resist composition may be either a positive resist or a negative resist. However, in the first embodiment, a case where a positive resist composition is used is taken as an example.

  Next, a pre-bake process is performed to evaporate the solvent contained in the resist film. The pre-bake treatment is performed, for example, by performing a heat treatment for about 1 minute at a temperature of 70 ° C. to 110 ° C. using a hot plate. Thereafter, a mask is applied so that a predetermined region of the resist film is irradiated, and the resist film is irradiated with, for example, KrF excimer laser light (248 nm) from a light source. After exposure of the resist film, post-exposure heat treatment (hereinafter referred to as PEB treatment) is performed as necessary. Thereby, the resolution of the resist film can be improved. The PEB treatment can be performed, for example, by performing a heat treatment at 50 ° C. to 130 ° C. In addition to the KrF excimer laser light, the resist film may be exposed to a film corresponding to the sensitivity wavelength of the resist film, such as g-line, i-line, deep ultraviolet light, ArF excimer laser light (193 nm). ), EB (electron beam) or X-ray radiation.

  Thereafter, as shown in FIG. 1B, a resist pattern 31A having a predetermined line and space is formed through a development process. Here, as a developing solution, about 0.05 to 3.0 weight% alkaline aqueous solution, such as TMAH (tetramethylammonium hydroxide), can be used, for example. As shown in this figure, in the memory cell formation region 11 constituted by a relatively simple and periodic line and space pattern, compared to the peripheral circuit formation region 12 generally constituted by an irregular pattern. The width of the resist pattern to be formed is narrow. In addition, after developing, you may perform a post-development baking process as needed. Since the post-development baking process affects the subsequent mixing reaction, it is desirable to set the temperature condition to be appropriate depending on the resist composition and the fine pattern forming material to be used. For example, heating is performed at 60 ° C. to 120 ° C. for about 60 seconds using a hot plate.

  Next, as shown in FIG. 1C, the resist pattern 31A formed in the previous step is subjected to a slimming process to form a resist pattern 31B that is thinned to a preset thinness. As the slimming treatment, wet etching or the like can be used. At this time, a fine first line and space resist pattern 31B is formed on the memory cell formation region 11, and a second pitch having a pitch larger than that of the first line and space is formed on the peripheral circuit formation region 12. The line and space resist pattern 31B is formed.

  Next, as shown in FIG. 1D, a fine pattern forming film 32 is formed on the workpiece film 20 including the resist pattern 31B by applying a material containing a component that can be cross-linked by the presence of an acid. The application method of the fine pattern forming film 32 is not particularly limited as long as it can be applied uniformly on the resist pattern 31B. For example, a spray method, a spin coating method, or the like can be used. Here, the fine pattern forming film 32 contains at least one water-soluble component that can be cross-linked by the presence of an acid, and water and / or a water-soluble organic solvent. That is, since any one of water, a water-soluble organic solvent, or a mixed solvent of water and a water-soluble organic solvent is used as the solvent, the underlying resist pattern 31B insoluble in water is not dissolved. Further, the water-soluble component that can be cross-linked by the presence of an acid may be any of a polymer, a monomer, and an oligomer. In this example, it is preferable to use a monomer, an oligomer, or a low-polymerized polymer. In particular, it is preferable to use a monomer or a monomer dimer to 240 monomer or an oligomer having an average molecular weight of up to 10,000.

  Thereafter, a pre-bake process is performed to evaporate the solvent contained in the fine pattern formation film 32. This pre-baking process is performed, for example, by performing a heat treatment for about 1 minute at a temperature of about 85 ° C. using a hot plate.

  After the pre-baking process, as shown in FIG. 2A, the resist pattern 31B formed on the processed film 20 and the fine pattern forming film 32 formed on the processed film 20 are heated ( Mixing baking process (hereinafter referred to as MB process). The MB processing temperature and time are set to appropriate values in accordance with the type of resist pattern 31B and the thickness of a sidewall film 33 described later. In this example, for example, MB processing is performed at 85 ° C. to 150 ° C. for 60 seconds to 120 seconds using a hot plate.

  By this MB process, the resist pattern 31B is heated to generate an acid in the resist pattern 31B, and the diffusion of the generated acid is promoted to supply the acid from the resist pattern 31B to the fine pattern forming film 32. At this time, the crosslinkable water-soluble component contained in the fine pattern forming film 32 causes a cross-linking reaction in the portion where the fine pattern forming film 32 is in contact with the resist pattern 31B, and the portion is water or alkaline water soluble. It becomes insoluble in the developer. Then, the supply of acid from the resist pattern 31B to the fine pattern forming film 32 and the crosslinking reaction are performed in the MB processing time in the direction from the interface between the resist pattern 31B and the fine pattern forming film 32 toward the fine pattern forming film 32. proceed. It should be noted that since the acid generated in the resist pattern 31B is not supplied in the portion of the fine pattern forming film 32 other than the vicinity of the interface with the resist pattern 31B, the crosslinking reaction does not occur. It remains soluble in Here, the vicinity of the interface between the fine pattern forming film 32 and the resist pattern 31B refers to a region where a crosslinking reaction has occurred within a range in which the acid generated in the resist pattern 31B can be diffused by the MB treatment. In this way, a thin sidewall film 33 that is insoluble in the developer is formed around the resist pattern 31B. The thickness of the sidewall film 33 can be controlled by process conditions and material characteristics to be used.

  Thereafter, as shown in FIG. 2B, only the memory cell formation region 11 of the substrate 10 on which the resist pattern 31B and the fine pattern formation film 32 including the sidewall film 33 are formed is exposed again by the exposure apparatus. At this time, between the light source of the exposure apparatus and the substrate 10, a transparent substrate such as glass is used so that light from the light source is transmitted in the memory cell formation region 11 and light from the light source is blocked in the peripheral circuit formation region 12. A mask 100 in which a light shielding film 102 is patterned on 101 is used. The exposure apparatus used in this exposure step does not need to use a scanner, and may be an apparatus having any configuration as long as the resist in the memory cell formation region 11 can be exposed.

  By this exposure, the resist pattern 31B portion of the memory cell formation region 11 is exposed, so that it becomes soluble in the developer. Since the resist pattern 31B portion of one peripheral circuit formation region 12 is not exposed, it remains insoluble in the developer.

  Next, as shown in FIG. 2C, when the substrate 10 on which the resist pattern 31B and the fine pattern forming film 32 including the sidewall film 33 are formed is developed with an alkaline aqueous solution, the resist pattern 31B in the memory cell forming region 11 is developed. Is dissolved in the developing solution, and the portions other than the sidewall film 33 of the fine pattern forming film 32 in the memory cell forming region 11 and the peripheral circuit forming region 12 are also dissolved in the developing solution, and from the substrate 10 (on the processing target film 20). Removed. On the other hand, the sidewall film 33 in the memory cell formation region 11 and the resist pattern 31B and the sidewall film 33 in the peripheral circuit formation region 12 remain as patterns without being dissolved in the developer. That is, the sidewall film 33 in the memory cell formation region 11 and the resist pattern 31B and the sidewall film 33 in the peripheral circuit formation region 12 can be formed simultaneously.

  Thereafter, the film to be processed 20 is etched using the sidewall film 33 as a mask in the memory cell formation region 11 and the structure of the resist pattern 31B and the sidewall film 33 formed on the side surface as a mask in the peripheral circuit formation region 12. The semiconductor device is manufactured. Here, since the sidewall film 33 of the resist pattern 31B remains as a mask material for the film to be processed 20 in the memory cell formation region 11, the fine line and space dimension of the memory cell is determined by the film thickness of the sidewall film 33. In the peripheral circuit formation region 12, the resist pattern 31B and the side wall film 33 formed around the resist pattern 31B remain as a mask material for the film 20 to be processed. Therefore, the peripheral circuit depends on the size of the slimmed resist pattern 31B and the side wall film 33. The line and space dimensions are determined. Therefore, in consideration of the dimensions of the mask material formed in the memory cell formation region 11 and the peripheral circuit formation region 12, the dimensions of the resist pattern 31A, the slimming process from the resist pattern 31A to the resist pattern 31B, and the sidewall film 33 formation process Parameters are set as appropriate.

  According to the first embodiment, a NAND type comprising: a memory cell unit that requires a fine pattern that is less than the resolution limit of lithography; and a peripheral circuit unit that has a pattern having a larger pitch than the memory cell unit. As in a semiconductor device such as a flash memory, there is an effect that a plurality of patterns having different pitches can be easily formed.

(Second Embodiment)
In the first embodiment, MB processing is performed after the fine pattern forming film 32 is formed on the film 20 to be processed including the resist pattern 31B. This is based on the premise that the fine pattern formation film 32 is not formed on the resist pattern 31B, but actually, the fine pattern formation film 32 may cover the upper surface of the resist pattern 31B. In this case, even if the subsequent exposure processing is performed, the light from the light source of the exposure apparatus reaches the resist pattern 31B by the fine pattern forming film 32 formed on a part or all of the upper surface of the memory cell formation region 11. Otherwise, the resist pattern 31B is not removed by the subsequent development process. Therefore, in the second embodiment, a method of manufacturing a semiconductor device using a sidewall leaving process that can reliably remove the resist pattern 31B during development processing will be described. In the following description, only portions different from the first embodiment will be described as an example.

  FIG. 3 is a cross-sectional view schematically showing an example of the procedure of the method for manufacturing the semiconductor device according to the second embodiment of the present invention. First, as shown in FIG. 1A to FIG. 2A of the first embodiment, a resist composition is applied to a film to be processed 20 formed on a substrate 10 to form a resist film. Then, a resist pattern 31A having a predetermined shape is formed in the memory cell formation region 11 and the peripheral circuit formation region 12 by exposure and development processing. Next, a resist pattern 31B slimmed by slimming the resist pattern 31A is formed, and a material containing a component that can be cross-linked by the presence of an acid is applied on the film to be processed 20 including the resist pattern 31B. A fine pattern forming film 32 is formed, and the solvent contained in the fine pattern forming film 32 is evaporated by pre-baking. Then, MB processing is performed on the resist pattern 31B and the fine pattern forming film 32 to form a sidewall film 33 insolubilized in the developer around the resist pattern 31B.

  Next, as shown in FIG. 3 (a), the substrate 10 on which the fine pattern forming film 32 including the sidewall film 33 and the resist pattern 31B are formed is soluble in the developer regardless of the presence or absence of exposure. A development soluble film 41 having properties is formed. As the development soluble film 41, for example, a top coat protective film for alkali-soluble immersion lithography can be used. The method for forming the development soluble film 41 is not particularly limited as long as it can be uniformly formed on the fine pattern forming film 32. For example, a spin coating method can be used. Further, the development soluble film 41 is formed such that the surface position thereof is higher than the surface position of the resist pattern 31B. Further, FIG. 3A shows a state in which a sidewall film 33 in which the fine pattern forming film 32 is insolubilized in the developer is formed around and on the upper surface of the resist pattern 31B.

  Thereafter, as shown in FIG. 3B, the upper surface of the development soluble film 41 is flattened by a chemical mechanical polishing (CMP) method. At this time, the time for performing the CMP process is controlled so that polishing is performed until the upper surfaces of all the resist patterns 31B are exposed. After the CMP process, as shown in the drawing, a development soluble film 41 is formed so as to fill in the space between the insoluble films formed around the resist pattern 31B.

  Next, as shown in FIG. 3C, only the memory cell formation region 11 of the substrate 10 on which the resist pattern 31B, the fine pattern formation film 32 including the sidewall film 33, and the development soluble film 41 are formed. Is again exposed by an exposure apparatus. By this exposure, the resist pattern 31B in the memory cell formation region 11 is exposed to be in a soluble state with respect to the developer. Since the resist pattern 31B in one peripheral circuit formation region 12 is not exposed, it remains insoluble in the developer. Further, the development soluble film 41 is in a state soluble in the developer regardless of the presence or absence of exposure.

  Thereafter, as shown in FIG. 2C of the first embodiment, the substrate 10 on which the fine pattern forming film 32 including the resist pattern 31B, the sidewall film 33, and the development soluble film 41 are formed is made alkaline. Develop with aqueous solution. As a result, the resist pattern 31B in the memory cell formation region 11, the portion other than the sidewall film 33 of the fine pattern formation film 32 in the memory cell formation region 11 and the peripheral circuit formation region 12, and the development soluble film 41 are dissolved in the developer. Then, it is removed from the substrate 10 (on the film 20 to be processed). On the other hand, the sidewall film 33 in the memory cell formation region 11 and the resist pattern 31B and the sidewall film 33 in the peripheral circuit formation region 12 remain as patterns without being dissolved in the developer. The processed film 20 is etched using the sidewall film 33 as a mask in the memory cell formation region 11 and using the structure of the resist pattern 31B and the sidewall film 33 formed on the side surface as a mask in the peripheral circuit formation region 12. The semiconductor device is manufactured.

  According to the second embodiment, the development soluble film 41 is formed before the exposure process after the MB process, and the polishing is performed so that the upper surface of the resist pattern 31B is exposed by the CMP method. In addition to the effects of the first embodiment, the resist pattern 31B is prevented from remaining at the time of development due to the fine pattern forming film 32 remaining on the upper surface of the resist pattern 31B, and a pattern in which only the sidewall film 33 is left is formed reliably. It has the effect that it can be done.

  In the example described above, a case where a positive resist is used as the resist pattern 31B is shown, but a negative resist can also be used as the resist pattern 31B. However, in this case, an etching solution or etching gas having a high selection ratio of the resist pattern 31B with respect to the sidewall film 33 is used. In the case of the first embodiment, after the resist pattern 31B in FIG. The fine pattern formation film 32 is etched, and in the case of the second embodiment, the resist pattern 31B, the fine pattern formation film 32, and the development soluble film 41 may be etched after FIG. Thereby, the resist pattern 31B formed of the negative resist can be removed. If the fine pattern forming film 32 or the fine pattern forming film 32 and the development soluble film 41 remain after etching, these films may be removed with a developer. Further, for example, when removing only the resist pattern 31B in the memory cell formation region 11, the peripheral circuit formation region 12 is covered with a mask material such as a resist, and etching is performed with only the memory cell formation region 11 opened. Good.

  When a negative resist is used as the resist pattern 31B in this manner, in order to finally remove the resist pattern 31B and the fine pattern forming film 32 by etching, similar to the removal of the dummy pattern by the etching of the sidewall leaving process of the conventional example. In addition, it takes some time for processing in this step. However, as compared with the case where a positive resist is used, an exposure process is not required, and in addition to the case where a positive resist is used, each step other than the removal process by etching of the resist pattern 31B and the fine pattern forming film 32 is performed. The processing time in the process can be shortened compared to the conventional example. As a result, the TAT can be shortened and the manufacturing cost of the semiconductor device can be reduced as compared with the conventional sidewall leaving process.

  In the above description, the resist pattern 31B in the memory cell formation region 11 is formed in the first line and space pattern, and the resist pattern 31B in the peripheral circuit formation region 12 is pitched more than the first line and space. In the above description, the first line and space pattern having a large width is described. However, the second line and space pitch may be the same as the first line and space pitch. In this case, a wide sidewall film 33 is formed around the resist pattern 31B in the peripheral circuit formation region 12 during MB processing, so that a resist pattern 31B having a width different from that of the resist pattern 31B in the memory cell formation region 11 is formed. It becomes possible to form.

  Furthermore, in the above description, the resist pattern 31B in the peripheral circuit formation region 12 is line and space, but it is not necessarily line and space. Various pattern shapes are employed according to the function of the peripheral circuit.

  In the above description, the method of manufacturing a semiconductor device has been described by taking a NAND flash memory as an example. However, the method of manufacturing a semiconductor device such as a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory). The present invention can be similarly applied.

Sectional drawing which shows typically an example of the procedure of the manufacturing method of the semiconductor device concerning 1st Embodiment (the 1). Sectional drawing which shows typically an example of the procedure of the manufacturing method of the semiconductor device concerning 1st Embodiment (the 2). Sectional drawing which shows typically an example of the procedure of the manufacturing method of the semiconductor device concerning 2nd Embodiment.

Explanation of symbols

  20 ... film to be processed, 31A, 31B ... resist pattern, 32 ... fine pattern forming film, 33 ... sidewall film, 41 ... development soluble film, 100 ... mask, 101 ..Transparent substrate, 102 ... light-shielding film

Claims (5)

A resist pattern forming step for forming a first line-and-space first resist pattern and a second resist pattern on the film to be processed, which includes a component capable of generating an acid by heating;
A fine pattern forming film forming step of forming a fine pattern forming film containing a component crosslinkable with an acid on the processed film on which the first and second resist patterns are formed;
The first and second resist patterns and the fine pattern forming film are subjected to a heat treatment to crosslink the fine pattern forming film in a range where an acid is supplied from the resist pattern, thereby the first and second resist patterns are cross-linked. A crosslinking step of forming a sidewall film around the resist pattern;
The fine pattern forming film and the first resist pattern that have not been cross-linked are removed from the film to be processed, the pattern made of the side wall film, and the second resist pattern on which the side wall film is formed, Forming a sidewall film pattern,
A method for manufacturing a semiconductor device, comprising: After the cross-linking step and before the sidewall film pattern forming step, exposure is performed on the film to be processed on which the first resist pattern and the fine pattern forming film other than the formation position of the second resist pattern are formed. Further comprising an exposure step to
In the side wall film pattern forming step, the fine pattern forming film that has not been cross-linked and the exposed first resist pattern are removed from the processed film by development to form a pattern made of the side wall film The method for manufacturing a semiconductor device according to claim 1, wherein the second resist pattern having the sidewall film formed thereon is formed. After the crosslinking step and before the exposure step,
A development soluble film in which a development soluble film containing a component soluble in a developer regardless of the presence or absence of exposure is applied on the fine pattern forming film so as to be higher than the height of the first and second resist patterns. A film forming step;
A resist pattern exposing step of removing the development soluble film until the upper surfaces of the first and second resist patterns are exposed;
Further including
In the development step, the fine pattern forming film that has not been crosslinked, the exposed first resist pattern, and the development soluble film are removed from the processed film by development, and the side wall is removed. 3. The method of manufacturing a semiconductor device according to claim 2, wherein a pattern made of a film and the second resist pattern in which the sidewall film is formed are formed.   2. The second resist pattern has a second line and space, and a pitch of the second line and space is larger than a pitch of the first line and space. The manufacturing method of the semiconductor device as described in any one of -3. In the memory cell formation region in which the memory cell of the semiconductor device is formed, the first resist pattern of the first line and space is formed,
5. The second resist pattern of the second line and space is formed in a peripheral circuit formation region where a peripheral circuit electrically connected to the memory cell is formed. Semiconductor device manufacturing method.

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