JPH07226356A - Pattern forming method using multilayer resistance - Google Patents

Abstract

PURPOSE: To enable the formation of a pattern across a large difference in level by a method wherein a first foundation resist layer is formed on the low level region of a lower structure to level the surface of the lower structure. CONSTITUTION: A 1st foundation resist layer 13 is applied to the surface of a substrate 11 on which steps are formed by the formation of a device 12 and the substrate surface on which the differences in level are formed is primarily levelled. At this point, if the thickness of the 1st foundation resist layer 13 on a circumferential part III is equivalent to the step between a cell part II and the circumferential part III or larger than 70% of the difference in level, it is advantageous to the levelling. Then, if the 1st foundation resist layer 13 is exposed by utilizing, for instance, a cell threshold voltage adjusting ion implantation mask 14 as a mask for exposing the cell part II only and developed, all the resist layer on the cell part II is removed and the surface of the substrate can be levelled. After a development process is finished, a heat treatment is applied to maintain the hardness of the 1st foundation resist layer 13 and remaining developer is removed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of semiconductor integrated circuit devices, and more particularly to a pattern forming method using a multilayer resist.

[0002]

2. Description of the Related Art Design rules (design rules) at the time of designing an element for forming a semiconductor integrated circuit are gradually becoming strict, and the surface step of the semiconductor element serves as a constraint for pattern formation. As a result, the conventional pattern formation method using a single-layer resist is changed to a lithography technique using a multi-layer resist.

In order to solve such problems, a two-layer resist process and a three-layer resist process have been developed.
In these methods, the lower layer resist is applied thickly to mitigate the step, and then the upper layer resist is formed thereon to reduce the effect of the step and to prevent pattern defects due to light scattering during exposure by the reticle. It is an elaborate technique that can be minimized.

A conventional pattern forming method using a three-layer resist process will be described below by taking as an example a semiconductor memory structure in which a step difference between a cell portion and a peripheral circuit portion after forming a capacitor is different by about 1.5 μm or more. Is. 1 and 2 show a pattern forming method using the conventional three-layer resist process described above. First, as shown in FIG. 1A, a lower layer resist 3 is applied on a substrate 1 on which a step is formed by forming an element 2 to reduce the step. Where I is the isolation region between elements in the semiconductor memory, and II
Indicates a region where a capacitor or the like is formed, I and II are cell portions, and III is a peripheral portion.

As shown in FIG. 1B, an intermediate layer 5 is formed on the lower layer resist 3. This intermediate layer is formed by using a substance capable of blocking the light scattering effect of the upper layer resist to be formed on the intermediate layer in a later step. Figure 1
As shown in (c), the upper layer resist 6 is formed on the intermediate layer 5.
2D, the upper layer resist 6 is patterned in a predetermined pattern by a lithography process using a mask (not shown), as shown in FIG. Figure 2 (e)
As shown in FIG. 3, the patterned upper layer resist pattern 6 is used as a mask to etch the intermediate layer 5 thereunder to transfer the mask pattern to the intermediate layer and then remove the upper layer resist. As shown in FIG. 2F, the lower layer resist pattern 3 is finally formed by etching the lower layer resist using the intermediate layer pattern 5 as a mask.

[0006]

However, the above-mentioned conventional multi-layer resist process can easily improve the resolution limit and the depth of focus when the step difference is 1.0 μm or less. Is 1.0 μm or more, the effect is reduced. As shown in FIG. 1, when the step is 1.5 μm or more, even if the resist is applied in multiple layers, the step is not completely eliminated. Therefore, when patterning the upper layer resist, non-uniform exposure occurs. It causes a bridge at the time of pattern formation. In addition, even if the CD (critical dimension) is adjusted appropriately by the step when the lower resist pattern is finally formed, a problem of CD-bias that a uniform pattern cannot be obtained over the entire pattern occurs.

In addition to the conventional method described above, there is a method of US Pat. No. 4,557,797 as a pattern forming method utilizing a multi-layer resist process. The upper layer resist and the lower layer resist are formed of a photoresist, and the intermediate layer is formed of a resist-free non-reflective material, so that the blocking effect of the upper layer resist during exposure is maintained. However, even with this method, when the step is large, the step is not completely flattened, and thus the above-mentioned problems of the conventional technique remain.

The lower layer and the upper layer are organic layers (Novol).
AK photo resist) and the intermediate layer is formed of a silicon-based polymer as described in US Pat. No. 4,891,303, and the lower layer is formed by a UV-sensitive resist and the upper layer is formed by deep UV (Dee).
p-UV) US Pat.
There are methods of forming multiple layers of various substances such as the method of No. 0,739, but these methods also cannot solve the above-mentioned problems when the level difference is very large.

That is, as the conventional multi-layer resist method, for example, in the case of manufacturing a semiconductor memory device, the focus of word line straps, main cells, sensor amplifiers, row decoders, etc., having different steps during the exposure process of the upper layer resist. Since the depths of the regions do not match, a defect such as a bridge between the lines and spaces or a short circuit occurs in each part within the same exposure field, and it is very difficult to pattern the peripheral region and the cell region having large steps at the same time. It's difficult. An object of the present invention is to provide a pattern forming method using a multi-layer resist, which can form a pattern even if there are high steps.

[0010]

In order to achieve the above object, according to the present invention, a first lower resist layer is formed on an area of a lower structure having steps to form a lower structure. Planarizing the surface of the substrate, applying a second lower layer resist on the lower structure having the surface planarized, forming an intermediate layer on the second lower layer resist, and forming the intermediate layer on the intermediate layer. A step of applying an upper layer resist to, a step of patterning the upper layer resist in a predetermined pattern, a step of transferring the upper layer resist layer pattern to the intermediate layer, and a pattern transferred to the intermediate layer to the lower layer resist. And a transfer step.

[0011]

The present invention will be described in detail below with reference to the accompanying drawings. 3 to 5 show a pattern forming method using a multilayer resist according to an embodiment of the present invention in the order of steps. First, as shown in FIG. 3A, the first lower layer resist 13 is applied to the substrate 11 having a step formed by the formation of the element 12 to a thickness of about 1.5 μm so that the substrate surface having the step is primarily flattened. Turn into

As the first lower resist layer, a resist sensitive to an optical spectrum, for example, PMMA (poly) is used.
(methylmethacrylate) is used. Alternatively, a photoresist based on Novolak can be used. In the semiconductor memory, I indicates an element isolation region, II indicates an element, that is, a region where a capacitor is formed, I and II are cell portions, and III is a peripheral portion. At this time, if the coating thickness of the first lower layer resist 13 on the peripheral portion (III) is equal to the step difference between the cell portion (II) and the peripheral portion (III) or is 70% or more, the flattening is achieved. It is advantageous.
As shown in FIG. 3B, as a mask for exposing only the cell portion (II), the first lower layer resist 13 is formed on the CANON 2000il stepper (365 nm) by using, for example, an ion implantation mask 14 for adjusting a cell threshold voltage. 8) after overexposure with energy of 500 mj / cm ²
By developing with a developing solution for 0 seconds, as shown in FIG.
The resist of the cell part (II) is completely removed to flatten the substrate surface.

After the developing process is completed, in order to maintain the hardness of the first lower layer resist 13,
For example, a heat treatment process is performed at a temperature of 230 ° C. for 6 minutes to remove the residual developer. As a method of flattening the surface of the substrate, an etching pack process may be used after applying the first lower layer resist.

As shown in FIG. 4 (d), a novolak photoresist as the second lower layer resist 15 having a thickness of 1 to 4 .mu.m, for example, 2 .mu.m, is formed on the resultant product which is flattened by the exposure and development process of the first lower layer resist. By applying the above thickness, the stepped substrate is completely flattened by the first and second lower layer resists 13 and 15. As shown in FIG. 4E, the intermediate layer 16 is formed on the second lower resist layer 15.
It is formed in a thickness range of 1 to 0.5 μm, for example, a thickness of 0.15 μm. The intermediate layer is an inorganic material that is not sensitive to the light spectrum and is preferably formed of a material that can be formed at a temperature of 300 ° C. or lower. For example, SOG (spin o
glass) or SiH ₄ − oxide film. As shown in FIG. 4 (f), a novolak photoresist is used as the upper resist 17 on the intermediate layer 16 in an amount of 0.1 to 0.9.
The coating is performed in a thickness range of μm, for example, 0.4 μm.

As shown in FIG. 5G, after the upper resist 17 is patterned by a photolithography process using a predetermined mask (not shown) to form a predetermined pattern, it is shown in FIG. As described above, the intermediate layer 16 is etched using the formed upper layer resist 17 as a mask to transfer the pattern to the intermediate layer. Figure 5
As shown in (i), the patterned intermediate layer 1
The lower layer resists 13 and 15 are etched using 6 as a mask to finally form a lower layer resist pattern, and the intermediate layer residue and the generated polymer are removed with a 20: 1 BOE (Buf
It is removed by immersing it in a ferred oxide etchant).

On the other hand, in order to clearly see the effect obtained by the present invention, the depth of the focus depending on the exposure dose after developing the upper resist pattern is shown in FIGS. The monitored parts are word line strap (), main cell (), sensor amplifier (), row decoder ().
4 parts. In the drawings, a thick solid line portion is a case where the method of the present invention is applied, and a thin solid line portion is a conventional solid line portion.
This is the case when the layer resist process is applied. (A) is 140
This shows the case where the exposure amount is insufficient due to exposure with energy of mj / cm ^{2, and} the overlap (o
The depth of focus (D.O.F.) to be overlapped is +0.5 to 1.5 .mu.m in the past and is only a margin of 0.5 .mu.m, but in the case of the present invention, it is +0.5 to. 2.
It is 5 μm and has a margin of 1.0 μm.
(B) shows an optimum exposure state by exposing with energy of 160 mj / cm ² , and the depth of focus (DOF) at which four monitor portions overlap is +2.
0 to 2.5 μm, which is a margin of 0.5 μm, while in the case of the present invention, +0.5 to 2.5 μm,
It has a margin of 1.5 μm. (C) is 180 mj /
It shows the transient exposure state by exposing with energy of cm ² ,
The overlapping focal depths of the four monitor portions are 0 in the past, but in the case of the present invention, +1.0 to
+2.0 μm with a margin of 1.5 μm. In order to compare the depth of the focal point when there is no step with (d), the depth of focus is 0.
160mj / cm after applying 4μm thick resist
^It shows the result of exposure with the energy of ^2.
+1.0 μm with a margin of 1.5 μm.

As can be seen from the results of FIGS. 6 and 7, according to the present invention, after the upper layer resist pattern is formed by flattening the lower layer resist applied thereon so as not to affect the step of the lower structure. Flat surface [Fig. 7
Since the depth of focus can be maintained in the same manner as in the case where the pattern is formed in [(d)], the resolution limit can be improved twice or more as compared with the conventional multi-layer resist method. It is possible to achieve a uniform depth of focus regardless of position within a one shot field during the exposure process. As a result, the present invention can be applied even to a step due to a capacitor having a three-dimensional structure of a semiconductor memory device.

Further, the present invention has an effect also on the entire flattened surface, and such a flattening effect solves the problem that a microbridge or the like occurs in the final pattern formation, and the CD bias of Improvements are possible.

The present invention can also be applied to the step of forming a contact hole in a semiconductor device. The contact holes have different resolution limits at the same exposure energy depending on the formation position. For example, in the case of forming contact holes of the same size in patterns having different steps such as an active region, a gate, a bit line, a word line strap, etc., if the present invention is applied, each part is not separated and one mask is used. Can be exposed to form a pattern.

[0020]

As described above, according to the present invention,
Since the influence of the step is eliminated by applying the lower layer resist, when the upper layer resist is developed, it has a depth of focus similar to that of a wafer having a flat surface, and the resolution limit is doubled compared with the conventional case. The above can be improved and the entire pattern (cell pattern and peripheral pattern) can be simultaneously developed with one mask even when the level difference is increased to 1.5 μm or more during the exposure of the upper layer resist, so that the process is simplified and the cost is reduced. There is.

[Brief description of drawings]

FIG. 1 is a process diagram showing a pattern forming method using a multilayer resist according to a conventional technique.

FIG. 2 is a process diagram showing a pattern forming method using a multi-layer resist according to a conventional technique.

FIG. 3 is a process drawing showing a pattern forming method using a multilayer resist according to the present invention.

FIG. 4 is a process drawing showing a pattern forming method using a multilayer resist according to the present invention.

FIG. 5 is a process chart showing a pattern forming method using a multilayer resist according to the present invention.

FIG. 6 is a diagram showing a comparison of the depths of focus depending on the amount of exposure when forming a pattern using a multilayer resist according to the present invention and the prior art.

FIG. 7 is a diagram showing a comparison of the depth of focus depending on the amount of exposure when forming a pattern using a multilayer resist according to the present invention and the prior art.

[Explanation of symbols]

 Reference Signs List 11 substrate 12 lower structure having steps (semiconductor memory device) 13 first lower layer resist 14 mask 15 first lower layer resist 16 intermediate layer 17 upper layer resist

Claims (9)

[Claims] 1. A step of forming a first lower resist layer (13) on a low step region of a stepped lower structure (12) to planarize a surface of the lower structure, and the surface is flattened. Applying a second lower layer resist (15) on the converted lower structure, forming an intermediate layer (16) on the second lower layer resist (15), and forming an intermediate layer (16) on the intermediate layer (16). Applying an upper layer resist (17), patterning the upper layer resist (17) in a predetermined pattern, transferring the upper layer resist layer pattern to the intermediate layer, and transferring the pattern transferred to the intermediate layer And a step of transferring the above to the lower layer resists (13) and (15). 2. The step of forming a first lower resist layer (13) on the low step area of the stepped lower structure (12) to planarize the surface of the lower step is performed. After the first lower layer resist (13) is applied to the entire surface of the lower structure (12), the predetermined lower mask is applied to selectively expose only a portion having a high step to a transition, and the step of developing is performed. A pattern forming method using the multilayer resist according to claim 1. 3. The step of planarizing the surface of the lower structure by forming a first lower resist layer (13) on the low step region of the lower structure (12) having the step has a step of forming the step. The first lower layer resist (13) is applied to the entire surface of the lower structure (12), and then the first lower layer resist (13) is etched by an etching back step. A pattern forming method using a multilayer resist. 4. The first lower layer resist (13),
PMMA (polymethylmethacrylic)
te) is used, The pattern formation method using the multilayer resist according to claim 1. 5. The first lower layer resist (13),
The pattern forming method using a multilayer resist according to claim 1, wherein a novolak photoresist is used. 6. The thickness of the first lower resist layer is equal to that of the lowest step of the lower structure,
Alternatively, the pattern forming method using a multilayer resist according to claim 1, wherein the step difference is within 30%. 7. The pattern forming method using a multilayer resist according to claim 1, wherein the intermediate layer (15) is formed of an inorganic material that is not sensitive to an optical spectrum. 8. The intermediate layer comprises SOG or SiH ₄ −.
It is formed by any one of oxide films.
A method for forming a pattern using the described multilayer resist. 9. The novolak photoresist is used as the upper layer resist (17).
A method for forming a pattern using the described multilayer resist.