KR20010011143A - Forming method for fine pattern of semiconductor device - Google Patents
Forming method for fine pattern of semiconductor device Download PDFInfo
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- KR20010011143A KR20010011143A KR1019990030381A KR19990030381A KR20010011143A KR 20010011143 A KR20010011143 A KR 20010011143A KR 1019990030381 A KR1019990030381 A KR 1019990030381A KR 19990030381 A KR19990030381 A KR 19990030381A KR 20010011143 A KR20010011143 A KR 20010011143A
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- 238000000034 method Methods 0.000 title claims abstract description 36
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 33
- 238000005530 etching Methods 0.000 claims abstract description 7
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 7
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 230000005540 biological transmission Effects 0.000 claims description 5
- 229910052741 iridium Inorganic materials 0.000 claims description 2
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 claims 2
- 229910052454 barium strontium titanate Inorganic materials 0.000 claims 1
- HTXDPTMKBJXEOW-UHFFFAOYSA-N iridium(IV) oxide Inorganic materials O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 claims 1
- 229910052451 lead zirconate titanate Inorganic materials 0.000 claims 1
- 230000010354 integration Effects 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/004—Photosensitive materials
- G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
- G03F7/095—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers having more than one photosensitive layer
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Architecture (AREA)
- Structural Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
본 발명은 반도체소자의 미세패턴 형성방법에 관한 것으로, 특히 하나의 노광마스크를 이용하여 반도체소자의 고집적화에 따른 미세패턴을 형성할 수 있도록 하는 기술에 관한 것이다.The present invention relates to a method of forming a fine pattern of a semiconductor device, and more particularly, to a technique for forming a fine pattern according to high integration of a semiconductor device using one exposure mask.
종래기술에서 미세 패턴 구현 방법은 레티클을 신규로 제작하여 사용가능하나 이방법은 레티클 상에 미세 패턴 제작기술 부족에서 오는 레티클 제작 에러가 증폭되어 실제로 웨이퍼 공정 마진 감소를 초래하게 되어 공정개발에 어려움이 따르며, 기존 레티클로 포토 바이어스 ( photo bias ) 를 이용하면 어느 정도 축소 ( shrink ) 된 패턴을 형성할 수는 있으나, 패턴 크기가 점점 작아지면 포토 바이어스 변화에 따른 패턴의 CD 정확도에 대한 재현성 확보가 불가능해져 결국 서브 마이크론 패터닝 포토 공정을 수행할 수 없게 된다.In the prior art, a fine pattern realization method can be used by newly manufacturing a reticle, but this method is difficult to develop a process due to the amplification of a reticle manufacturing error resulting from the lack of a fine pattern fabrication technology on the reticle, which actually reduces the wafer process margin. If the pattern size is getting smaller, it is impossible to secure the reproducibility of the CD accuracy of the pattern due to the change of the photo bias. As a result, the submicron patterning photo process cannot be performed.
참고로, 상기 포토 바이어스는 노광공정시 마스크의 크기보다 넓거나 좁게 노광되는 현상을 말하며, 상기 포토 바이어스는 노광공정시 감광막의 특성을 고려하여 에너지 또는 포커스를 조절함으로써 그 크기를 조절할 수 있다.For reference, the photo bias refers to a phenomenon in which the exposure is wider or narrower than the size of the mask during the exposure process, and the photo bias may be adjusted by adjusting energy or focus in consideration of characteristics of the photosensitive film during the exposure process.
도 1a 및 도 1b 는 종래기술에 따른 반도체소자의 미세패턴 형성방법을 도시한 단면도이다.1A and 1B are cross-sectional views illustrating a method for forming a fine pattern of a semiconductor device according to the prior art.
먼저, 피식각층(도시안됨)이 형성된 반도체기판(11) 상부에 포지티브형 감광막(13)을 형성한다.First, a positive photosensitive film 13 is formed on the semiconductor substrate 11 on which an etched layer (not shown) is formed.
그리고, 미세패턴을 형성할 수 있는 노광마스크(15)를 이용하여 상기 감광막(13)을 노광시킴으로써 노광된 부분(17)을 형성한다. (도 1a)Then, the exposed portion 17 is formed by exposing the photosensitive film 13 using an exposure mask 15 capable of forming a fine pattern. (FIG. 1A)
상기 도 1b 는 상기 도 1a 와 같은 공정으로 감광막(13)을 노광시켜 노광된 부분(17)과 상기 노광된 부분(17)의 양측으로 포토 바이어스 부분(19)을 도시한다. (도 1b)FIG. 1B shows the photosensitive film 13 in the same process as that of FIG. 1A to show the exposed portion 17 and the photo bias portion 19 on both sides of the exposed portion 17. (FIG. 1B)
상기한 바와같이 종래기술에 따른 반도체소자의 미세패턴 형성방법은, 포토 바이어스 부분(19)에 의하여 서브 마이크론 이하의 디자인룰을 가지는 반도체소자의미세패턴을 형성하기 어렵고 그에 따른 반도체소자의 고집적화를 어렵게 하는 문제점이 있다.As described above, in the method of forming a fine pattern of a semiconductor device according to the related art, it is difficult to form a fine pattern of a semiconductor device having a design rule of sub-micron or less by the photo bias portion 19, and thus high integration of the semiconductor device is difficult. There is a problem.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 포지티브형과 네가티브형 감광막을 패터닝하고 노광공정시 포토 바이어스를 이용하여 노광 영역을 조절하여 하나의 노광마스크를 이용하여 서브 마이크론 크기 이하의 미세패턴을 형성할 수 있는 반도체소자의 미세패턴 형성방법을 제공하는데 그 목적이 있다.The present invention, in order to solve the above problems of the prior art, by patterning the positive and negative photosensitive film, and adjusting the exposure area by using the photo bias during the exposure process using a single exposure mask sub-micron size or less fine pattern It is an object of the present invention to provide a method for forming a fine pattern of a semiconductor device capable of forming a semiconductor device.
도 1a 및 도 1b 는 종래기술에 따른 반도체소자의 미세패턴 형성방법을 도시한 단면도.1A and 1B are cross-sectional views illustrating a method for forming a fine pattern of a semiconductor device according to the prior art.
도 2a 내지 도 2f 는 본 발명의 실시예에 따른 반도체소자의 미세패턴 형성방법을 도시한 단면도.2A to 2F are cross-sectional views illustrating a method for forming a fine pattern of a semiconductor device according to an embodiment of the present invention.
〈 도면의 주요부분에 대한 부호의 설명 〉<Description of the reference numerals for the main parts of the drawings>
11,21 : 반도체기판 13,25 : 포지티브형 감광막11,21: semiconductor substrate 13,25: positive photosensitive film
15,27 : 노광마스크 17 : 노광된 영역15,27: exposure mask 17: exposed area
23 : 금속산화막 28 : 제1노광영역23 metal oxide film 28 first exposure area
29 : 네가티브형 감광막 30 : 제2노광영역29: negative photosensitive film 30: second exposure area
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 미세패턴 형성방법은,In order to achieve the above object, the method of forming a fine pattern of a semiconductor device according to the present invention,
피식각층이 구비되는 반도체기판 상부에 포지티브형 감광막을 도포하는 공정과,Applying a positive photosensitive film on an upper portion of the semiconductor substrate having an etched layer;
상기 포지티브형 감광막을 노광하되, 포토 바이어스를 조절하여 노광마스크의 투과영역보다 넓게 또는 좁게 실시함으로써 제1노광영역을 형성하는 공정과,Exposing the positive photoresist film, but adjusting the photo bias to form a first exposure region by making the photosensitive film wider or narrower than the transmission region of the exposure mask;
상기 포지티브형 감광막을 현상하여 상기 제1노광영역이 제거된 포지티브형 감광막패턴을 형성하는 공정과,Developing the positive photosensitive film to form a positive photosensitive film pattern from which the first exposure region is removed;
상기 포지티브형 감광막패턴 사이를 매립하는 네가티브형 감광막을 전체표면상부에 도포하는 공정과,Applying a negative photosensitive film filling the positive photosensitive film pattern on the entire surface;
상기 포지티브형 감광막패턴 상측이 노출될때까지 평탄화식각하는 공정과,Planarizing etching until the upper side of the positive photoresist pattern is exposed;
상기 노광마스크를 이용하여 예정된 상기 포지티브형 및 네가티브형 감광막을 노광하되, 포토 바이어스를 조절하여 노광마스크의 투과영역보다 좁게 또는 넓게 실시함으로써 제2노광영역을 형성하는 공정과,Exposing the predetermined positive and negative photosensitive films by using the exposure mask, and adjusting the photo bias to form a second exposure region by making the photomask narrower or wider than the transmission region of the exposure mask;
상기 포지티브형 감광막의 노광영역과 상기 네가티브형 감광막의 비노광영역의 제2노광영역을 현상공정으로 제거하여 상기 포지티브형 감광막의 비노광영역과 상기 네가티브형 감광막의 노광영역에 구성되는 감광막패턴을 형성하는 공정과,The exposure region of the positive photoresist film and the second exposure region of the non-exposed region of the negative photoresist film are removed by a developing process to form a photoresist pattern composed of the non-exposed region of the positive photoresist film and the exposure region of the negative photoresist film. Process to do,
상기 마스크용 감광막패턴을 마스크로하여 피식각층을 식각하고 상기 마스크용 감광막패턴을 제거하는 공정을 포함하는 것을 특징으로한다.And etching the layer to be etched using the mask photoresist pattern as a mask and removing the mask photoresist pattern.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2f 는 본 발명의 실시예에 따른 반도체소자의 미세패턴 형성방법을 도시한 단면도이다.2A to 2F are cross-sectional views illustrating a method for forming a fine pattern of a semiconductor device according to an embodiment of the present invention.
먼저, 반도체기판(21) 상부에 금속산화막(23)을 형성하고 그 상부에 포지티브형 감광막(25)을 도포한다.First, a metal oxide film 23 is formed on the semiconductor substrate 21 and a positive photosensitive film 25 is coated on the semiconductor oxide film 21.
이때, 상기 금속산화막(23)은 Pt, SBT, PZT, BST, IrO2, RuO2, Ir, Ru, Cu 등과 같은 재료로 형성할 수 있다.In this case, the metal oxide layer 23 may be formed of a material such as Pt, SBT, PZT, BST, IrO 2, RuO 2, Ir, Ru, Cu, or the like.
그 다음, 상기 노광마스크(27)를 이용한 노광공정으로 상기 포지티브형 감광막(25)을 노광하되, 예정된 노광영역 보다 넓게 노광될 수 있도록 포토 바이어스를 조절하여 실시함으로써 제1노광영역(28)을 형성한다.Subsequently, the positive photosensitive film 25 is exposed by an exposure process using the exposure mask 27, and the first exposure area 28 is formed by adjusting the photo bias so as to be exposed wider than a predetermined exposure area. do.
이때, 상기 포토 바이어스는 예정된 영역보다 넓게 노광되도록 에너지와 포커스를 조절하여 실시한 것이다. (도 2a)In this case, the photo bias is performed by adjusting energy and focus to expose a wider area than a predetermined area. (FIG. 2A)
그 다음, 상기 제1노광영역(28)을 현상공정으로 제거하여 포지티브형 감광막(25)패턴을 형성한다. (도 2b)Next, the first exposure region 28 is removed by a developing process to form a positive photosensitive film 25 pattern. (FIG. 2B)
그리고, 상기 포지티브형 감광막(25)패턴 사이를 매립하는 네가티브형 감광막(29)을 전체표면상부에 도포한다. (도 2c)Then, the negative photosensitive film 29 filling the pattern between the positive photosensitive film 25 is applied over the entire surface. (FIG. 2C)
그리고, 상기 포지티브형 감광막(25)패턴 상측이 노출되도록 상기 네가티브형 감광막(29)을 평탄화식각하여 평탄화시킨다.The negative photoresist layer 29 is planarized by etching so as to expose the upper side of the positive photoresist layer 25 pattern.
그 다음, 상기 노광마스크(27)를 이용하여 상기 네가티브형 감광막(29)을 노광시키되, 포토 바이어스를 상기 노광마스크(27)의 투과영역 내측으로 형성되도록 노광에너지 및 포커스를 조절하여 실시함으로써 제2노광영역(30)을 형성한다.Next, the negative photosensitive film 29 is exposed using the exposure mask 27, and a photo bias is controlled by adjusting exposure energy and focus so as to be formed inside the transmission region of the exposure mask 27. An exposure area 30 is formed.
이때, 상기 제2노광영역(30)은 상기 네가티브형 감광막(29)에만 형성된다. (도 2d)In this case, the second exposure region 30 is formed only in the negative photosensitive film 29. (FIG. 2D)
그리고, 상기 네가티브형 감광막(29)을 현상하여 상기 제2노광영역(30)의 네가티브형 감광막(29)만을 남기는 네가티브형 감광막(29)패턴을 형성한다.The negative photosensitive film 29 is developed to form a negative photosensitive film 29 pattern leaving only the negative photosensitive film 29 of the second exposure area 30.
이때, 상기 포지티브형 감광막(25)패턴은 노광되지않아 현상공정시 제거되지않음으로써 그대로 남게 되어 포지티브형 감광막(25)과 네가티브형 감광막(29)이 번갈아 형성되는 형태로 감광막패턴이 구비된다. (도 2f)At this time, the positive photosensitive film 25 pattern is not exposed and is not removed during the development process, and thus remains as it is, so that the positive photosensitive film 25 and the negative photosensitive film 29 are alternately formed. (FIG. 2F)
그 다음, 상기 포지티브형 감광막(25)패턴과 상기 네가티브형 감광막(29)패턴을 마스크로하여 상기 금속산화막(23)을 식각하여 패터닝함으로써 금속산화막(23)패턴을 형성하고 상기 포지티브형 감광막(25)패턴과 상기 네가티브형 감광막(29)패턴을 제거한다. (도 2f)Next, the metal oxide film 23 is etched and patterned using the positive photoresist 25 pattern and the negative photoresist 29 pattern as a mask to form a metal oxide 23 pattern, and the positive photoresist 25 ) Pattern and the negative photosensitive film 29 pattern are removed. (FIG. 2F)
본 발명의 다른 실시예는 포지티브형 감광막(25)의 노광공정시 포토 바이어스를 노광마스크의 투과 영역보다 좁게 노광되도록 조절하고 네가티브형 감광막(29)의 노광공정시 노광마스크의 투과영역보다 넓게 노광되도록 조절하여 미세패턴을 형성하는 것이다.Another embodiment of the present invention is to adjust the photo bias in the exposure process of the positive photosensitive film 25 to be narrower than the transmissive area of the exposure mask and to be exposed wider than the transmissive area of the exposure mask in the exposure process of the negative photosensitive film 29. It is to form a fine pattern by adjusting.
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 미세패턴 형성방법은, 노광공정시 에너지와 포커스를 조절하여 포토 바이어스의 폭을 조절하고 그에 따른 노광영역의 폭을 조절하여 네가티브형과 포지티브형 감광막으로 미세패턴을 형성함으로써 반도체소자의 고집적화를 가능하게 하는 효과를 제공한다.As described above, in the method of forming a micropattern of a semiconductor device according to the present invention, the width of the photo bias is controlled by adjusting the energy and focus during the exposure process, and the width of the exposure area is adjusted to the negative type and the positive type photoresist. The formation of the fine pattern provides an effect of enabling high integration of the semiconductor device.
Claims (2)
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| KR1019990030381A KR20010011143A (en) | 1999-07-26 | 1999-07-26 | Forming method for fine pattern of semiconductor device |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100449319B1 (en) * | 2001-12-20 | 2004-09-18 | 동부전자 주식회사 | Method of forming miniature pattern semiconductor device |
| KR100676607B1 (en) * | 2005-12-29 | 2007-01-30 | 동부일렉트로닉스 주식회사 | Method for forming photoresist pattern of semiconductor device |
| KR100802296B1 (en) * | 2006-12-27 | 2008-02-11 | 동부일렉트로닉스 주식회사 | Method for manufacturing semiconductor device |
| KR100863421B1 (en) * | 2006-06-28 | 2008-10-14 | 주식회사 하이닉스반도체 | Method of forming a word line in the semiconductor memory device |
| KR100866725B1 (en) * | 2008-03-21 | 2008-11-05 | 주식회사 하이닉스반도체 | Method for manufacturing fine pattern of a semiconductor device |
| KR100912959B1 (en) * | 2006-11-09 | 2009-08-20 | 주식회사 하이닉스반도체 | Method for fabricating fine pattern in semiconductor device |
| CN118016745A (en) * | 2024-04-07 | 2024-05-10 | 浙江晶科能源有限公司 | Solar cell, preparation method thereof, laminated cell and photovoltaic module |
-
1999
- 1999-07-26 KR KR1019990030381A patent/KR20010011143A/en not_active Application Discontinuation
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100449319B1 (en) * | 2001-12-20 | 2004-09-18 | 동부전자 주식회사 | Method of forming miniature pattern semiconductor device |
| KR100676607B1 (en) * | 2005-12-29 | 2007-01-30 | 동부일렉트로닉스 주식회사 | Method for forming photoresist pattern of semiconductor device |
| KR100863421B1 (en) * | 2006-06-28 | 2008-10-14 | 주식회사 하이닉스반도체 | Method of forming a word line in the semiconductor memory device |
| KR100912959B1 (en) * | 2006-11-09 | 2009-08-20 | 주식회사 하이닉스반도체 | Method for fabricating fine pattern in semiconductor device |
| KR100802296B1 (en) * | 2006-12-27 | 2008-02-11 | 동부일렉트로닉스 주식회사 | Method for manufacturing semiconductor device |
| KR100866725B1 (en) * | 2008-03-21 | 2008-11-05 | 주식회사 하이닉스반도체 | Method for manufacturing fine pattern of a semiconductor device |
| CN118016745A (en) * | 2024-04-07 | 2024-05-10 | 浙江晶科能源有限公司 | Solar cell, preparation method thereof, laminated cell and photovoltaic module |
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