CN118016745A

CN118016745A - Solar cell, preparation method thereof, laminated cell and photovoltaic module

Info

Publication number: CN118016745A
Application number: CN202410405152.3A
Authority: CN
Inventors: 柴嘉磊; 张晓雯; 滕佳镔; 李文琪; 杨洁; 郑霈霆
Original assignee: Zhejiang Jinko Solar Co Ltd
Current assignee: Zhejiang Jinko Solar Co Ltd
Priority date: 2024-04-07
Filing date: 2024-04-07
Publication date: 2024-05-10

Abstract

The embodiment of the application relates to the field of photovoltaics, and provides a solar cell, a preparation method thereof, a laminated cell and a photovoltaic module, wherein the solar cell comprises: the substrate is provided with a front surface and a back surface which are oppositely arranged, and the back surface is provided with a first area and a second area which are alternately arranged; the passivation contact structure is positioned on the first region and comprises a first tunneling dielectric layer and a first doped conductive layer, the first tunneling dielectric layer is positioned on the back surface, the first doped conductive layer is positioned on the first tunneling dielectric layer, and holes are formed in the first doped conductive layer; the passivation layer is positioned on the second region and the surface of the first doped conductive layer; the electrodes are located on the orthographic projection of the reference surface and correspond to the first areas one by one, penetrate through the thickness of the passivation layer, are in electrical contact with the first doped conductive layer and fill the holes. The solar cell provided by the embodiment of the application can improve the cell efficiency.

Description

Solar cell, preparation method thereof, laminated cell and photovoltaic module

Technical Field

The embodiment of the application relates to the field of photovoltaics, in particular to a solar cell, a preparation method thereof, a laminated cell and a photovoltaic module.

Background

Currently, with the gradual depletion of fossil energy, solar cells are increasingly used as new energy alternatives. A solar cell is a device that converts solar light energy into electrical energy. The solar cell generates carriers by utilizing the photovoltaic principle, and then the carriers are led out by using the electrodes, so that the electric energy can be effectively utilized.

Current solar cells mainly include IBC cells (crossed back electrode contact cells, INTERDIGITATED BACK CONTACT), TOPCON (Tunnel Oxide Passivated Contact, tunnel oxide passivation contact) cells, PERC cells (passivation emitter and back cells, PASSIVATED EMITTER AND REAL CELL), heterojunction cells, and the like. The photoelectric conversion efficiency of the solar cell is improved by reducing optical loss and reducing photo-generated carrier recombination on the surface and in the body of the silicon substrate through different film layer arrangement and functional limitation.

However, in the process of preparing the solar cell, the film layer arrangement of different regions and the matching relationship between the film layers need to be reasonably constructed and tested, so that the further improvement of the efficiency of the solar cell is limited.

Disclosure of Invention

The embodiment of the application provides a solar cell, a preparation method thereof, a laminated cell and a photovoltaic module, which are at least beneficial to improving the cell efficiency of the solar cell.

According to some embodiments of the present application, an aspect of an embodiment of the present application provides a solar cell, including: a substrate having a front side and a back side disposed opposite to each other, the back side having first and second regions alternately arranged; the passivation contact structure is positioned on the first region and comprises a first tunneling dielectric layer and a first doped conductive layer, the first tunneling dielectric layer is positioned on the back surface, the first doped conductive layer is positioned on the first tunneling dielectric layer, and holes are formed in the first doped conductive layer; a passivation layer on the second region and on a surface of the first doped conductive layer; the electrodes are located on the orthographic projection of the reference surface and correspond to the first areas one by one, penetrate through the thickness of the passivation layer and are in electrical contact with the first doped conductive layer, and the holes are filled with the electrodes; wherein the reference plane is a plane perpendicular to the thickness direction of the substrate.

In some embodiments, the hole comprises: a first type of hole, the first type of hole not penetrating the first doped conductive layer; a second type of hole, the second type of hole penetrating the first doped conductive layer; the electrode fills the first type of holes and the second type of holes.

In some embodiments, the ratio of the number of the first type of holes to the number of the second type of holes is in the range of 5:1 to 1:10.

In some embodiments, for the same first doped conductive layer, the total area of orthographic projections of the holes on the reference surface is a first area, the area of the first doped conductive layer on the reference surface is a second area, and the ratio of the first area to the second area is less than or equal to 20%.

In some embodiments, the size of the hole along the first direction is in a range of 5 μm to 30 μm, and the first direction is a direction parallel to the reference plane.

In some embodiments, the depth range of the holes is less than or equal to 200nm.

In some embodiments, the plurality of consecutively arranged first regions comprises alternating N regions and P regions, with the second region between the N regions and the P regions; the first doped conductive layer comprises a first sub-doped conductive layer positioned on the P region and a second sub-doped conductive layer positioned on the N region, and at least one of the first sub-doped conductive layer and the second sub-doped conductive layer is provided with the hole.

In some embodiments, the first sub-doped conductive layer has a first sub-aperture and the second sub-doped conductive layer has a second sub-aperture, the first sub-aperture having a dimension in the first direction that is less than or equal to a dimension of the second sub-aperture in the first direction.

In some embodiments, the substrate is doped with one of an N-type doping element or a P-type doping element, and the first doped conductive layer is doped with the other of the N-type doping element or the P-type doping element.

In some embodiments, the substrate is doped with one of an N-type doping element or a P-type doping element, the doping element within the first doped conductive layer having the same conductivity type as the doping element within the substrate.

In some embodiments, the passivation contact structure further comprises: the second tunneling dielectric layer is positioned on the first region, the second doped conductive layer is positioned between the first tunneling dielectric layer and the second tunneling dielectric layer, and the doping elements in the second doped conductive layer and the doping elements in the first doped conductive layer have the same conductivity type.

In some embodiments, the second tunneling dielectric layer is further located in the second region, and the second doped conductive layer is further located between the passivation layer and the second tunneling dielectric layer.

In some embodiments, the thickness of the second doped conductive layer is less than or equal to the thickness of the first doped conductive layer.

According to some embodiments of the present application, another aspect of the embodiments of the present application further provides a method for manufacturing a solar cell, including: providing a substrate, wherein the substrate is provided with a front surface and a back surface which are oppositely arranged, and the back surface is provided with a first area and a second area which are alternately arranged; forming a passivation contact structure, wherein the passivation contact structure is positioned on the first region and comprises a first tunneling dielectric layer and a first doped conductive layer, the first tunneling dielectric layer is positioned on the back surface, the first doped conductive layer is positioned on the first tunneling dielectric layer, and holes are formed in the first doped conductive layer; forming a passivation layer on the second region and on the surface of the first doped conductive layer; forming a plurality of electrodes, wherein orthographic projections of the electrodes on the reference surface correspond to the first areas one by one, the electrodes penetrate through the thickness of the passivation layer and are in electrical contact with the first doped conductive layer, and the electrodes fill the holes; wherein the reference plane is a plane perpendicular to the thickness direction of the substrate.

In some embodiments, the process steps of forming the passivation contact structure include: forming an initial dielectric layer and a doped conductive film on the surface of the substrate, wherein the initial dielectric layer is positioned on the first region and the second region, and the doped conductive film is positioned on the surface of the initial dielectric layer; removing the initial dielectric layer and the doped conductive film of the second region; and forming holes in the doped conductive film on the first region, wherein the rest of the doped conductive film is used as the first doped conductive layer, and the rest of the initial dielectric layer is used as the first tunneling dielectric layer.

In some embodiments, prior to forming the hole in the doped conductive film, comprising: forming a mask, wherein bubbles are arranged in the mask; the orthographic projection of the mask on the reference surface is positioned in the first area; performing a first step for removing a portion of the thickness of the mask until the bubbles are exposed; performing a second step, the second step comprising: continuing to etch the mask which does not contain the bubbles, etching the mask positioned at the bottom of the bubbles and the exposed doped conductive film along the bubbles, and forming holes in the doped conductive film; until the mask is removed.

In some embodiments, the mask is formed after removing the initial dielectric layer and the doped conductive film of the second region.

In some embodiments, the mask is formed prior to removing the initial dielectric layer and the doped conductive film of the second region; the first step is used for removing the doped conductive film with the first thickness and the mask with the second thickness in the second region until the bubbles are exposed; the second step includes: continuing to etch the doped conductive film, the initial dielectric layer and the mask which does not contain the bubbles, etching the mask positioned at the bottom of the bubbles and the exposed doped conductive film along the bubbles, and forming holes in the doped conductive film; until the initial dielectric layer in the second region is removed.

In some embodiments, the bubbles have a first dimension in a first direction prior to forming the holes; the hole has a second dimension along a first direction, the first dimension being less than or equal to the second dimension.

In some embodiments, for the same mask, the total area of orthographic projections of the bubbles on the reference plane is a third area, the area of the mask on the reference plane is a fourth area, and the ratio of the third area to the fourth area is less than or equal to 50%.

According to some embodiments of the present application, there is also provided a laminated battery including: a bottom cell which is the solar cell according to any one of the above embodiments or the solar cell produced by the production method according to any one of the above embodiments; and a top cell positioned on a side of the base away from the electrode in the bottom cell.

According to some embodiments of the present application, a further aspect of the embodiments of the present application provides a photovoltaic module, including: a cell string formed by connecting a plurality of solar cells according to any one of the above embodiments, solar cells produced by the production method according to any one of the above embodiments, or stacked cells according to the above embodiments; the packaging adhesive film is used for covering the surface of the battery string; and the cover plate is used for covering the surface of the packaging adhesive film, which is away from the battery strings.

The technical scheme provided by the embodiment of the application has at least the following advantages:

The embodiment of the application provides a solar cell, wherein the back surface of the solar cell is provided with a first region corresponding to an electrode and a second region not corresponding to the electrode. The passivation structure formed between the first tunneling dielectric layer and the first doped conductive layer of the passivation contact structure can passivate the composite defect of the back surface, so that the carrier composite loss of the back surface is reduced. The first doped conductive layer is internally provided with holes, and the electrodes are filled in the holes and are in contact with the corresponding first doped conductive layers, so that the contact area between the first doped conductive layers and the electrodes can be increased by the existence of the holes, the contact resistance between the first doped conductive layers and the electrodes is reduced, the holes can also serve as migration channels between the first doped conductive layers and the electrodes, and partial carriers can be allowed to directly reach the electrodes through the holes, so that partial migration loss is reduced, and the battery efficiency is improved.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, which are not to be construed as limiting the embodiments unless specifically indicated otherwise; in order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the drawings required for the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.

Fig. 1 is a schematic structural diagram of a solar cell according to an embodiment of the present application;

FIG. 2 is an enlarged view of a portion of FIG. 1 at C;

FIG. 3 is a schematic view of a first cross-sectional structure of FIG. 2 along the line A1-A2;

fig. 4 is a schematic structural diagram of a first doped conductive layer in a solar cell according to an embodiment of the present application;

FIG. 5 is a schematic cross-sectional view of the structure of FIG. 4 along the section B1-B2;

FIG. 6 is a schematic view of a second cross-sectional structure of FIG. 2 along the line A1-A2;

FIG. 7 is a schematic view of a third cross-sectional structure of FIG. 2 along the line A1-A2;

fig. 8 is a schematic structural diagram of a solar cell according to an embodiment of the present application;

FIG. 9 is a partial enlarged view at D in FIG. 8;

FIG. 10 is a schematic cross-sectional view of the structure of FIG. 9 along the section E1-E2;

FIG. 11 is a schematic cross-sectional view of a substrate provided in a method for fabricating a solar cell according to another embodiment of the present application;

Fig. 12 is a schematic cross-sectional structure of a mask layer formed in a method for manufacturing a solar cell according to another embodiment of the present application;

Fig. 13 is a schematic cross-sectional view illustrating a first step in a method for manufacturing a solar cell according to another embodiment of the present application;

fig. 14 is a schematic cross-sectional view illustrating a second step in a method for manufacturing a solar cell according to another embodiment of the present application;

Fig. 15 is a schematic cross-sectional view illustrating a mask layer formed in a method for manufacturing a solar cell according to another embodiment of the present application;

fig. 16 is a schematic cross-sectional view illustrating a method for forming a through hole in a solar cell according to another embodiment of the present application;

Fig. 17 is a schematic cross-sectional view illustrating a passivation layer formed in a method for manufacturing a solar cell according to another embodiment of the present application;

Fig. 18 is a schematic cross-sectional view of a stacked cell according to another embodiment of the present application;

fig. 19 is a schematic structural view of a photovoltaic module according to still another embodiment of the present application;

FIG. 20 is a schematic cross-sectional view of the structure of FIG. 19 along the line M1-M2.

Detailed Description

As known from the background art, the current solar cell has poor cell efficiency.

As used herein, the terms "vertical," "longitudinal," "horizontal," and "transverse" are the principal planes of the reference structure and are not necessarily defined by the earth's gravitational field. A "horizontal" or "lateral" direction is a direction that is substantially parallel to the major plane of the structure, while a "vertical" or "longitudinal" direction is a direction that is substantially perpendicular to the major plane of the structure. The major plane of the structure is defined by the surface of the structure having a relatively large area compared to the other surfaces of the structure. Referring to the figures, a "horizontal" or "lateral" direction may be perpendicular to the indicated "Z" axis, and may be parallel to the indicated "X" axis and/or parallel to the indicated "Y" axis; and the "vertical" or "longitudinal" direction may be parallel to the indicated "Z" axis, may be perpendicular to the indicated "X" axis, and may be perpendicular to the indicated "Y" axis.

As used herein, features (e.g., regions, structures, devices) described as being "adjacent" to each other are intended to mean and include features having one or more of the disclosed identifiers positioned closest (e.g., closest) to each other. One or more additional features (e.g., additional regions, additional structures, additional devices) of the disclosed identification that do not match "adjacent" features may be disposed between the "adjacent" features. In other words, the "adjacent" features may be positioned directly adjacent to each other such that no other features are interposed between the "adjacent" features; or "adjacent" features may be positioned indirectly adjacent to each other such that at least one feature having an identification other than the identification associated with the at least one "adjacent" feature is positioned between the "adjacent" features. Thus, features described as being "vertically adjacent" to each other are intended to mean and include one or more of the features disclosed as being located vertically closest (e.g., vertically closest) to each other. Further, features described as being "horizontally adjacent" to each other are intended to mean and include one or more of the disclosed identified features that are located closest to each other (e.g., closest to each other).

In the following description, an embodiment in which a second member is formed or provided over or on a first member, or a second member is formed or provided on a surface of the first member, or a second member is formed or provided on one side of the first member may be included, and an embodiment in which the first member and the second member are in direct contact may be included, and an embodiment in which additional members may be included between the first member and the second member, so that the first member and the second member may not be in direct contact may be included. The various components may be arbitrarily drawn for simplicity and clarity. In the drawings, some layers/components may be omitted for simplicity.

Unless otherwise specified, the formation or disposition of a second component on the surface of a first component means that the first component is in direct contact with the second component.

Where the above-described "component" may refer to a layer, film, region, portion, structure, etc.

Moreover, for ease of description, relative terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein to describe one element or component's relationship to another element(s) or component(s) as illustrated. Apart from the orientations shown in the figures, the relative terms are intended to include different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing used herein is similarly explained with respect to the descriptors. In addition, the term "made of …" may mean "comprising" or "consisting of …". Furthermore, in subsequent manufacturing processes, there may be one or more additional operations during/between the operations described, and the order of the operations may be changed. In the following embodiments, the terms "upper", "above …" and/or "over" are defined along a direction of increasing distance from the front and rear surfaces. Materials, configurations, dimensions, processes and/or operations as illustrated in the embodiments may be adopted in other embodiments, and detailed descriptions thereof may be omitted.

Spatially relative terms, such as "below," "lower," "bottom," "above," "upper," "top," "front," "back," "left," "right," and the like, as used herein, may be used for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. Unless otherwise specified, spatially relative terms are intended to encompass different orientations of the material in addition to the orientation depicted in the figures. For example, if the material in the illustrations is inverted, elements described as "below" or "beneath" or "lower" or "bottom" other elements or features would then be oriented "above" or "top" the other elements or features. Thus, the term "below" may depend on both the orientation above and below the upper and lower Wen Han covers where the term is used, as will be apparent to one of ordinary skill in the art. The material may be otherwise oriented (e.g., rotated 90 degrees, inverted, flipped) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. As used herein, "and/or" includes any and all combinations of one or more of the associated listed items.

As used herein, the term "substantially" or "essentially" with respect to a given parameter, property, or condition means and includes the degree to which the given parameter, property, or condition meets a degree of deviation (e.g., within acceptable tolerances) as would be understood by one of ordinary skill in the art. By way of example, depending on the particular parameter, property, or condition that is substantially met, the parameter, property, or condition may meet at least 90.0%, meet at least 95.0%, meet at least 99.0%, meet at least 99.9%, or even meet 100.0%.

As used herein, "about," "approximately" or "approximately" with reference to a numerical value of a particular parameter includes the numerical value, and a person of ordinary skill in the art will understand that the degree of deviation from the numerical value is within acceptable tolerances for the particular parameter. For example, "about" or "approximately" with respect to a numerical value may include additional numerical values in the range of 90.0% to 110.0% of the numerical value, such as in the range of 95.0% to 105.0% of the numerical value, in the range of 97.5% to 102.5% of the numerical value, in the range of 99.0% to 101.0% of the numerical value, in the range of 99.5% to 100.5% of the numerical value, or in the range of 99.9% to 100.1% of the numerical value.

As used herein, "conductive material" means and includes conductive materials such as one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)), alloys (e.g., co-based alloys, fe-based alloys, ni-based alloys, fe-and Ni-based alloys, co-and Ni-based alloys, fe-and Co-based alloys, co-and Ni-and Fe-based alloys, AI-based alloys, cu-based alloys, magnesium (Mg) -based alloys, steel, mild steel, stainless steel), conductive metal-containing materials (e.g., conductive metal nitrides, conductive metal carbides, conductive metal oxides), and conductive doped semiconductor materials (e.g., conductive doped polysilicon, conductive doped germanium (Ge), conductive doped silicon (SiGe)). In addition, "conductive structure" means and includes a structure formed of and including a conductive material.

As used herein, "insulating material" means and includes electrically insulating material such as one or more of the following: at least one dielectric oxide material (e.g., one or more of silicon oxide (SiOx), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, aluminum oxide (AlOx), hafnium oxide (HfOx), niobium oxide (NbOx), titanium oxide (TiOx), zirconium oxide (ZrOx), tantalum oxide (TaOx), and magnesium oxide (MgOx); at least one dielectric nitride material (e.g., silicon nitride (SiNy)); at least one dielectric oxynitride material (e.g., silicon oxynitride (SiOxNy)); at least one dielectric oxycarbide material (e.g., silicon oxycarbide (SiOxCy)); at least one hydrogenated dielectric oxycarbide material (e.g., hydrogenated silicon oxycarbide (SiCxOyHz)); and at least one dielectric carbon oxynitride material (e.g., silicon carbon oxynitride (SiOxCzNy)). Formulas (e.g., siOx, alOx, hfOx, nbOx, tiOx, siNy, siOxNy, siOxCy, siCxOyHz, siOxCzNy) containing one or more of "x", "y", and "z" herein represent materials containing the average ratio of "x" atoms of one element, the "y" atoms of another element, and the "z" atoms of additional elements (if present) for each atom of another element (e.g., si, al, hf, nb, ti). Since the chemical formulas represent relative atomic ratios rather than strict chemical structures, the insulating material may include one or more stoichiometric compounds and/or one or more non-stoichiometric compounds, and the values of "x", "y", and "z" (if present) may be integers or may be non-integers. As used herein, the term "non-stoichiometric compound" means and includes a compound having a composition of some element that cannot be represented by a ratio of well-defined natural numbers and that violates the law of definite ratios. In addition, the "insulating structure" means and includes a structure formed of an insulating material and including an insulating material.

Unless the context indicates otherwise, the materials described herein may be formed by any suitable technique, including but not limited to spin coating, blanket coating, chemical Vapor Deposition (CVD), plasma Enhanced CVD (PECVD), atomic Layer Deposition (ALD), plasma Enhanced ALD (PEALD), physical Vapor Deposition (PVD) (e.g., sputtering), or epitaxial growth. The technique used to deposit or grow the material may be selected by one of ordinary skill in the art depending on the particular material to be formed. In addition, unless the context indicates otherwise, the material removal described herein may be accomplished by any suitable technique including, but not limited to, etching (e.g., dry etching, wet etching, vapor phase etching), ion milling, polish planarization (e.g., chemical Mechanical Planarization (CMP)), or other known methods.

The term "semiconductor" as used herein may refer to, for example, a layer of material, a base, a wafer, or a substrate, and includes any base semiconductor structure. "semiconductor" is understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin Film Transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon layers supported by a base semiconductor structure, as well as other semiconductor structures well known to one skilled in the art. Furthermore, when referring to a semiconductor in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure, and the term semiconductor may include underlayers that contain such regions/junctions.

Unless otherwise apparent from the context, the term conductive (conductive) and its various related forms, such as conductive (conduct, conducting, conduction), conductive ground (conductively), conductive (conductivity), and the like, are used herein to refer to electrical conduction. Similarly, the terms connected and their various forms of correlation, such as connection (connect, connected, connection) and the like, are used herein to refer to electrical connections unless otherwise apparent from the context.

Embodiments of the present application will be described in detail below with reference to the attached drawings. However, it will be understood by those of ordinary skill in the art that in various embodiments of the present application, numerous specific details are set forth in order to provide a thorough understanding of the present application. The claimed application may be practiced without these specific details and with various changes and modifications based on the following embodiments.

Fig. 1 is a schematic structural diagram of a solar cell according to an embodiment of the present application; FIG. 2 is an enlarged view of a portion of FIG. 1 at C; fig. 3 is a schematic view of a first cross-sectional structure of fig. 2 along the line A1-A2.

According to some embodiments of the present application, referring to fig. 1 to 3, an aspect of an embodiment of the present application provides a solar cell, including: the substrate 100, the substrate 100 has a front surface 11 and a back surface 12 disposed opposite to each other, and the back surface 12 has first areas i and second areas ii alternately arranged.

In some embodiments, the material of the substrate 100 may be an elemental semiconductor material. Specifically, the elemental semiconductor material is composed of a single element, which may be silicon or germanium, for example. The elemental semiconductor material may be in a single crystal state, a polycrystalline state, an amorphous state, or a microcrystalline state (a state having both a single crystal state and an amorphous state, referred to as a microcrystalline state), and for example, silicon may be at least one of single crystal silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon.

In some embodiments, the material of the substrate 100 may also be a compound semiconductor material. Common compound semiconductor materials include, but are not limited to, silicon germanium, silicon carbide, gallium arsenide, indium gallium, perovskite, cadmium telluride, copper indium selenium, and the like. The substrate 100 may also be a sapphire substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate.

In some embodiments, the substrate 100 may be an N-type semiconductor substrate or a P-type semiconductor substrate. The N-type semiconductor substrate is doped with an N-type doping element, which may be any of v group elements such As phosphorus (P) element, bismuth (Bi) element, antimony (Sb) element, and arsenic (As) element. The P-type semiconductor substrate is doped with a P-type element, and the P-type doped element may be any one of group iii elements such as boron (B) element, aluminum (Al) element, gallium (Ga) element, and indium (In) element.

In some embodiments, the solar cell is a single-sided cell, the front side 11 may be a light receiving surface for receiving incident light, and the back side 12 may be a back side. The backlight surface can also receive the incident light, but the efficiency of receiving the incident light is weaker than that of the light receiving surface.

In some embodiments, the solar cell is a double sided cell, i.e. both the front side and the back side of the substrate can be used as light receiving surfaces for receiving incident light.

In some embodiments, the front face 11 has a textured structure 13, and the textured structure 13 may include regular shaped pyramid-shaped textured structures as well as irregularly shaped black silicon. The inclined surface of the suede structure 13 can increase the internal reflection of the incident light, so as to improve the absorption and utilization rate of the substrate 100 to the incident light, and further improve the cell efficiency of the solar cell.

In some embodiments, the pile structure 13 includes a plurality of raised structures 105, and the shape of the raised structures 105 may include a pyramid shape, a parabolic shape, or an elliptical sphere shape.

In some embodiments, the back side 12 is a polished surface, which refers to a flat surface formed by removing the original suede structure of the surface by a polishing solution or laser etching. The flatness of the polished back surface 12 is increased, the reflection of long-wave light is increased, and the secondary absorption of projection light is promoted, so that the short-circuit current is improved, meanwhile, the recombination of the back surface 12 is reduced due to the reduction of the specific surface area of the back surface 12, and the passivation effect of the back surface 12 can be improved. A planar surface refers to a surface that has a relative roughness of + -5%, i.e., a planar surface that is not absolutely flush.

In some embodiments, the first region i refers to the region where the orthographic projection of the electrode on the back surface of the substrate is located, and the first region i serves as a functional region for forming a metal electrode; on the contrary, the second area ii refers to the area where the orthographic projection of the electrode on the back surface of the substrate is not overlapped, i.e., the second area ii is used as a functional area where the metal electrode is not formed. That is, the first region i (again, the metal electrode region) and the second region ii (again, the non-metal electrode region) are based on the functional partitioning of the substrate 100 to illustrate the distribution of the film structures of the solar cell, and the first region i and the second region ii are actually the back surfaces of the substrate.

It should be noted that, in order to ensure that the film layers contacted by the electrodes are all corresponding functional film layers, the range of the first area i is set to be greater than or equal to the orthographic projection range of the electrodes on the back surface, that is, any orthographic projection of the electrodes on the back surface is located in the first area i, and the distance between the edge of the first area i and the edge of the orthographic projection pattern is greater than or equal to 0.

In addition, if the back surface of the substrate is a flat surface, the front projection of the electrode on the back surface means that the front projection of the electrode on the reference surface is located within the front projection of the electrode on the back surface. The reference surface is a flat surface perpendicular to the thickness direction of the substrate.

With continued reference to fig. 3, the solar cell includes: the passivation contact structure is located on the first region i, and the passivation contact structure includes a first tunneling dielectric layer 111 and a first doped conductive layer 112, where the first tunneling dielectric layer 111 is located on the back surface 12, the first doped conductive layer 112 is located on the first tunneling dielectric layer 111, and the first doped conductive layer 112 has a hole 160 therein.

In some embodiments, a passivation contact structure is formed between the first tunneling dielectric layer 111 and the first doped conductive layer 112, where the first doped conductive layer 112 can form an energy band bend on the surface of the substrate 100, and the first tunneling dielectric layer 111 shifts the energy band on the surface of the substrate 100 asymmetrically, so that a potential barrier to multiple carriers (also called majority carriers) in carriers is lower than a potential barrier to fewer carriers (also called minority carriers) in carriers, so that multiple carriers can more easily perform quantum tunneling through the first tunneling dielectric layer 111, and fewer carriers can more easily pass through the first tunneling dielectric layer 111 to achieve selective transmission of carriers.

In addition, the first tunneling dielectric layer 111 plays a role of chemical passivation. Specifically, since the interface between the substrate 100 and the first tunneling dielectric layer 111 has an interface state defect, the interface state density of the back surface 12 is relatively high, and the increase of the interface state density promotes the recombination of photo-generated carriers, and increases the filling factor, the short-circuit current and the open-circuit voltage of the solar cell, so as to improve the photoelectric conversion efficiency of the solar cell. The first tunneling dielectric layer 111 is disposed on the back surface 12, so that the first tunneling dielectric layer 111 has a chemical passivation effect on the surface of the substrate 100, specifically: by saturating dangling bonds of the substrate 100, the defect state density of the substrate 100 is reduced, and the recombination center of the substrate 100 is reduced to reduce the carrier recombination rate.

The first doped conductive layer 112 acts as a field passivation effect. Specifically, an electrostatic field pointing to the inside of the substrate 100 is formed on the surface of the substrate 100, so that minority carriers escape from the interface, thereby reducing minority carrier concentration, reducing carrier recombination rate at the interface of the substrate 100, increasing open-circuit voltage, short-circuit current and filling factor of the solar cell, and improving photoelectric conversion efficiency of the solar cell.

In some embodiments, the substrate 100 is doped with one of an N-type doping element or a P-type doping element, and the doping element in the first doped conductive layer 112 has the same conductivity type as the doping element in the substrate 100. For example, the doping element type of the substrate 100 is N-type, and the first doped conductive layer 112 is doped with N-type doping element.

The concentration of the doping element in the first doped conductive layer 112 is greater than that of the substrate 100, a high-low junction is formed between the first doped conductive layer 112 and the substrate 100, and a high enough potential barrier can be formed on the surface of the substrate 100 under an electric field formed by the high-low junction, so that the multiple electrons in the substrate 100 can pass through the first tunneling dielectric layer 111 to the first doped conductive layer 112, which is beneficial to improving the carrier mobility.

In some embodiments, the substrate 100 is doped with one of an N-type doping element or a P-type doping element, and the first doped conductive layer 112 is doped with the other of the N-type doping element or the P-type doping element. In other words, the first doped conductive layer 112 may be doped with a doping element of a different conductivity type from the substrate 100, for example, the doping element type of the substrate 100 is P-type, and the doping element type of the first doped conductive layer 112 may be N-type. Thus, a PN junction is formed between the first doped conductive layer 112 and the substrate 100, and a new hole-electron pair is formed by solar irradiation on the PN junction, and under the action of an electric field built in the PN junction, a photo-generated hole flows to the P region, and a photo-generated electron flows to the N region, so that a current is generated after a circuit is turned on.

In some embodiments, the thickness of the first tunneling dielectric layer 111 is 0.5nm to 10nm. The thickness of the first tunneling dielectric layer 111 ranges from 0.5nm to 1.3nm, from 1.3nm to 4.6nm, from 4.6nm to 6.1nm, or from 6.1nm to 10nm. The thickness of the first tunneling dielectric layer 111 is thinner in any range, so that the quantum tunneling can be easily performed by the first tunneling dielectric layer 111, and the selective transmission of carriers can be realized by the minority carrier through the first tunneling dielectric layer 111.

In some embodiments, the material of the first tunneling dielectric layer 111 includes at least one of silicon oxide, amorphous silicon, microcrystalline silicon, nanocrystalline silicon, or silicon carbide.

In some embodiments, the first doped conductive layer 112 includes at least one of a doped amorphous silicon layer, a doped polysilicon layer, a doped microcrystalline silicon layer, a doped silicon carbide layer, or a doped crystalline silicon layer.

In some embodiments, referring to fig. 4 and 5, the thickness h0 of the first doped conductive layer 112 is 50nm to 200nm. The thickness h0 of the first doped conductive layer 112 ranges from 50nm to 80nm, 80nm to 130nm, 130nm to 160nm, or 160nm to 200nm. The thickness h0 of the first doped conductive layer 112 is within any range, the first doped conductive layer 112 can resist the condition that the electrode 114 penetrates through the first doped conductive layer 112 in a large range and then penetrates through the first tunneling dielectric layer 111, firstly, the passivation effect of the first tunneling dielectric layer 111 and the first doped conductive layer 112 can be ensured, secondly, the situation that the interface recombination between the substrate 100 and the first tunneling dielectric layer 111 is increased due to the first doped conductive layer 112 with high doping concentration on the surface of the substrate 100 and the oxygen density and the tunneling effect in the first tunneling dielectric layer 111 are also influenced along with the occurrence of the influence can be avoided. Wherein, the thickness h0 of the first doped conductive layer 112 refers to the thickness of the first doped conductive layer 112 including the hole, and not to the thickness of the first doped conductive layer 112 located under the hole.

Fig. 4 is a schematic structural diagram of a first doped conductive layer in a solar cell according to an embodiment of the present application; fig. 5 is a schematic cross-sectional view of fig. 4 along the section B1-B2.

In some embodiments, the first doped conductive layer 112 has a hole 160 therein, the hole 160 can be used as a light trapping structure, and the hole 160 enhances the internal reflection of the incident light in the first doped conductive layer 112, thereby improving the cell efficiency.

In addition, the electrode 114 fills the hole 160, the hole 160 can increase the contact area between the first doped conductive layer 112 and the electrode 114, thereby reducing the contact resistance between the first doped conductive layer 112 and the electrode 114, and the hole 160 can also serve as a migration channel between the first doped conductive layer 112 and the electrode 114, and can allow part of carriers to directly reach the electrode 114 through the hole 160, thereby reducing part of migration loss and improving the cell efficiency.

In some embodiments, referring to fig. 5, the holes 160 comprise: the first type holes 161, the first type holes 161 do not penetrate through the first doped conductive layer 112; a second type hole 162, the second type hole 162 penetrating the first doped conductive layer 112; the electrode 114 fills the first type of holes 161 and the second type of holes 162. The first type holes 161 and the second type holes 162 are matched with each other, the first type holes 161 can increase the contact area between the electrode 114 and the first doped conductive layer 112, and the number of the control electrodes 114 penetrating through the first doped conductive layer 112 is controlled, so that the passivation effect of the first doped conductive layer 112 is ensured. The second type of holes 162 serve as migration channels for carriers to migrate to the electrode 114, thereby increasing carrier migration rate.

In some embodiments, the ratio of the number of the first type holes 161 to the number of the second type holes 162 is in the range of 5:1 to 1:10. The ratio of the number of the first type holes 161 to the number of the second type holes 162 ranges from 5:1 to 2:1, from 2:1 to 1:1, from 1:1 to 3:1, from 1:3 to 1:5, from 1:5 to 1:8, or from 1:8 to 1:10. The ratio of the number of the first holes 161 to the number of the second holes 162 is in any range, so that the number of the first holes 161 can ensure that the contact area between the electrode 114 and the first doped conductive layer 112 is increased, and the number of the electrode 114 penetrating through the first doped conductive layer 112 is smaller, thereby ensuring the integrity of the first doped conductive layer 112, namely the strength and passivation performance of the first doped conductive layer 112 are better; the number of second type holes 162 may act as tunneling channels, causing a portion of the carriers to migrate directly to the electrode 114 via the holes 160, thereby reducing the migration loss of the carriers within the first doped conductive layer 112.

It should be noted that, because the thickness of the first tunneling dielectric layer 111 is smaller, the thickness is 0.5nm to 20nm, and in an actual solar cell, the position of the first tunneling dielectric layer 111 corresponding to the second type hole 162 may also have a through hole, that is, the electrode 114 penetrates through the first doped conductive layer 112 and also penetrates through the thickness of the first tunneling dielectric layer 111 and is in electrical contact with the substrate 100.

In some embodiments, for the same first doped conductive layer 112, the total area of orthographic projections of the holes 160 on the reference plane is a first area, the area of orthographic projections of the first doped conductive layer 112 on the reference plane is a second area, and the ratio of the first area to the second area is less than or equal to 20%. The area ratio between the hole 160 and the first doped conductive layer 112 is used to ensure that the first doped conductive layer 112 has a relatively large passivation property and strength, so as to avoid damage to the first doped conductive layer 112. In addition, the area of the hole 160 is also used to increase the mobility of carriers and the contact area between the electrode 114 and the first doped conductive layer 112 as a tunneling path of the electrode 114.

In some embodiments, referring to fig. 4, the dimension d of the hole 160 along the first direction is in the range of 5 μm to 30 μm, and the first direction is a direction parallel to the reference plane. The size d of the holes 160 ranges from 5 μm to 8 μm, from 8 μm to 13 μm, from 13 μm to 18 μm, from 18 μm to 23 μm or from 23 μm to 30 μm, and the size d of the holes 160 ranges from any of the above ranges, the size of the holes 160 is suitable, so that the existence of the holes 160 has less influence on the strength of the first doped conductive layer 112 itself, and the peeling between the first doped conductive layer 112 and the substrate 100 is effectively avoided. The size d of the hole 160 is within any of the above ranges, and the hole 160 may be filled with the electrode 114 without forming a void, thereby improving the cell efficiency of the solar cell.

In some embodiments, referring to fig. 4, the shape of the holes 160 may be circular or elliptical as shown in fig. 4. The shape of the holes 160 may also be rectangular, polygonal or triangular.

In some embodiments, the first direction may be an X-direction or a Y-direction, i.e., the first direction is perpendicular to the Z-direction and is any direction parallel to the reference plane.

In some embodiments, the dimension d of the hole 160 may be a circular diameter, an oval long or short diameter, a rectangular or triangular side length, and the dimension d may be a line between two corners.

In some embodiments, the dimension d of the holes 160 is within any of the above ranges, and the number of holes 160 and the dimension d can be used to provide space for thermal deformation of the first doped conductive layer 112 and thermal deformation of the electrode 114, so as to reduce the possibility of curling the solar cell.

In some embodiments, referring to fig. 5, the depth h1 of the holes 160 ranges less than or equal to 200nm. Thus, the depth h1 of the hole 160 may indicate that the first type hole 161 does not penetrate the first doped conductive layer 112, and the second type hole 162 does not penetrate the first doped conductive layer 112.

With continued reference to fig. 3, the solar cell further includes: the doped layer 101, the doped layer 101 is located on the front surface of the substrate 100, and the doped layer 101 has a doped element, where the doped element is an N-type doped element or a P-type doped element.

In some embodiments, the doping type of the first doped conductive layer 112 is the same as that of the doping element in the substrate 100, the doping element of different conductivity type from the substrate 100 is doped in the doping layer 101, and the doping layer is the emitter of the solar cell. The doping element type in the doping layer 101 is different from the doping element type of the substrate 100. The doping treatment is performed on a part of the thickness of the original substrate, and a part of the original substrate subjected to the doping treatment is used as the doping layer 101, and the remaining original substrate is used as the substrate 100.

In some embodiments, the doped layer 101 is made of the same material as the substrate 100, and the doped layer 101 and the substrate 100 may be formed by doping the same original substrate.

In some embodiments, the doped layer 101 is a doped layer formed on the front surface of the substrate 100, and the doped N-type doped element or P-type doped element semiconductor layer formed through a deposition process may be silicon, germanium or polysilicon.

In some embodiments, the doping type of the first doped conductive layer 112 is different from that of the doping element in the substrate 100, and the doping element with the same conductivity type as that of the substrate 100 is doped in the doping layer, so that a high-low junction is formed between the doping layer and the substrate 100 for enhancing the mobility of the multiple electrons.

Referring to fig. 3, the solar cell includes: and a passivation layer 113, wherein the passivation layer 113 is located on the second region ii and on the surface of the first doped conductive layer 112.

In some embodiments, the passivation layer 113 may have a single-layer structure or a stacked-layer structure, and the material of the passivation layer 113 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, titanium oxide, hafnium oxide, or aluminum oxide.

In some embodiments, the solar cell further comprises an anti-reflective layer on a surface of the passivation layer, the electrode in electrical contact with the first doped conductive layer through a thickness of the anti-reflective layer. The anti-reflection layer is used for reducing or eliminating reflected light of the surface of the solar cell, so that the light transmission quantity of the surface of the solar cell is increased, and stray light of the system is reduced or eliminated. The material of the anti-reflection layer comprises silicon nitride or silicon oxynitride.

In some embodiments, the solar cell further comprises a front passivation layer 103, the front passivation layer 103 covering the surface of the doped layer 101.

In some embodiments, the front passivation layer 103 may have a single-layer structure or a stacked-layer structure, and the material of the front passivation layer 103 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, titanium oxide, hafnium oxide, or aluminum oxide.

In some embodiments, the material of the front passivation layer 103 is the same as the material of the passivation layer 113, and the front passivation layer 103 and the passivation layer 113 are prepared in the same manufacturing process.

With continued reference to fig. 3, the solar cell includes: the electrodes 114 are located on the orthographic projection of the reference surface and are in one-to-one correspondence with the first areas I, the electrodes 114 penetrate through the thickness of the passivation layer 113, the electrodes 114 are in electrical contact with the first doped conductive layer 112, and the electrodes 114 fill the holes 160; wherein the reference plane is a plane perpendicular to the thickness direction of the substrate 100.

In some embodiments, the solar cell further comprises a front electrode 104, the front electrode 104 extending through the thickness of the front passivation layer 113, and the front electrode 104 being in electrical contact with the doped layer 101.

In some embodiments, any of the electrode 114 and the front electrode 104 may be sintered from a burn-through metal paste, which may include at least one of silver, aluminum, copper, tin, gold, lead, or nickel.

In some embodiments, the substrate 100 corresponding to the second region ii may have a concave-convex structure, and the concave-convex structure may increase internal reflection of the incident light, thereby improving the utilization rate of the incident light, and further improving the cell efficiency of the solar cell.

In some embodiments, the electrodes extend along the Y direction and are sequentially arranged along the X direction, and the reference plane is a plane constructed by the X direction and the Y direction.

FIG. 6 is a schematic view of a second cross-sectional structure of FIG. 2 along the line A1-A2; fig. 7 is a schematic view of a third cross-sectional structure of fig. 2 along the section A1-A2.

Referring to fig. 6 or 7, in some embodiments, the passivation contact structure further includes: the second tunneling dielectric layer 121 and the second doped conductive layer 122, the second tunneling dielectric layer 121 is located on the first region i, the second doped conductive layer 122 is located between the first tunneling dielectric layer 111 and the second tunneling dielectric layer 121, and the doped element in the second doped conductive layer 122 and the doped element in the first doped conductive layer 112 have the same conductivity type. Therefore, by arranging two passivation contact structures (the tunneling dielectric layer and the doped conductive layer form a passivation contact structure), the thickness of one doped conductive layer can be reduced, and the optical loss of one thicker doped conductive layer per se can be reduced.

In some embodiments, referring to fig. 6, the second tunneling dielectric layer 121 is further located in the second region ii, and the second doped conductive layer 122 is further located between the passivation layer and the second tunneling dielectric layer 121. The second tunneling dielectric layer 121 and the second doped conductive layer 122 can passivate the surface of the second region ii, so as to reduce the surface defect of the second region ii.

In some embodiments, the doping concentration of the first doped conductive layer 112 is greater than the doping concentration of the second doped conductive layer 122, and the doping concentration of the first doped conductive layer 112 is used to ensure that the region contacted by the electrode 114 is a highly doped region, thereby reducing the contact resistance between the electrode 114 and the first doped conductive layer 112. The doping concentration of the second doped conductive layer 122 is lower, so that the doping element can be prevented from penetrating the second tunneling dielectric layer 121, and thus the interface between the substrate 100 and the second tunneling dielectric layer 121 is adversely affected.

In some embodiments, the thickness of the second doped conductive layer 122 is less than or equal to the thickness of the first doped conductive layer 112. The first doped conductive layer 112 and the second doped conductive layer 122 with different thicknesses can ensure that the electrode 114 does not penetrate through the first doped conductive layer 112, and cause adverse effects on the first tunneling dielectric layer 111 and the second tunneling dielectric layer 121.

For details of the material and thickness of the second doped conductive layer 122, please refer to the material and thickness of the first doped conductive layer 112, and detailed descriptions thereof are omitted herein. Similarly, for the content of the material and thickness of the second tunneling dielectric layer 121, please refer to the material and thickness of the first tunneling dielectric layer 111.

Correspondingly, the present application also provides a solar cell, where electrodes (a first electrode and a second electrode) of different conductivity types of the solar cell are all located on the back surface of the substrate 100, which is the same as or corresponding to the above embodiment, and detailed description thereof is omitted herein.

Fig. 8 is a schematic structural diagram of a solar cell according to an embodiment of the present application; FIG. 9 is a partial enlarged view at D in FIG. 8; FIG. 10 is a schematic cross-sectional view of FIG. 9 taken along the line E1-E2. The dashed lines in fig. 8 represent that the first electrode and the second electrode are located on the back surface of the substrate, that is, the first electrode and the second electrode are not visible on the front surface of the solar cell.

Referring to fig. 8 to 10, a plurality of first regions i arranged in succession include N regions and P regions arranged alternately with a second region ii therebetween; the first doped conductive layer includes a first sub-doped conductive layer 244 located on the P region and a second sub-doped conductive layer 254 located on the N region, at least one of the first sub-doped conductive layer 244 and the second sub-doped conductive layer 254 having a hole.

In some embodiments, the first sub-doped conductive layer 244 has a first sub-aperture 271, and the second sub-doped conductive layer 254 has a second sub-aperture 272, and a dimension d1 of the first sub-aperture 271 along the first direction is less than or equal to a dimension d2 of the second sub-aperture 272 along the first direction.

In some embodiments, the first tunneling dielectric layer includes a first sub-tunneling dielectric layer 243 on the P region and a second sub-tunneling dielectric layer 253 on the N region; the electrodes include a first electrode 245 in the P region and a second electrode 255 in the N region.

The substrate 200, the front surface 21, the back surface 22, the textured structure 23, the bump structure 205, the front passivation layer 203, and the passivation layer 213 of the solar cell are described in detail with reference to the substrate 100, the front surface 11, the back surface 12, the textured structure 13, the bump structure 105, the front passivation layer 103, and the passivation layer 113 in the above embodiment.

Correspondingly, according to some embodiments of the present application, another aspect of the embodiments of the present application further provides a method for manufacturing a solar cell, which is used for manufacturing the solar cell provided in the foregoing embodiments, and the technical features of the solar cell are the same as or corresponding to those of the foregoing embodiments, and are not described in detail herein.

The embodiment of the present application takes the preparation method of the solar cell shown in fig. 3 as an example, and other types of solar cells are cross-illustrated therein, and will be described in detail with reference to the related drawings.

FIG. 11 is a schematic cross-sectional view of a substrate provided in a method for fabricating a solar cell according to another embodiment of the present application; fig. 12 is a schematic cross-sectional structure of a mask layer formed in a method for manufacturing a solar cell according to another embodiment of the present application; fig. 13 is a schematic cross-sectional view illustrating a first step in a method for manufacturing a solar cell according to another embodiment of the present application; fig. 14 is a schematic cross-sectional view illustrating a second step in a method for manufacturing a solar cell according to another embodiment of the present application; fig. 15 is a schematic cross-sectional view illustrating a mask layer formed in a method for manufacturing a solar cell according to another embodiment of the present application; fig. 16 is a schematic cross-sectional view illustrating a method for forming a through hole in a solar cell according to another embodiment of the present application; fig. 17 is a schematic cross-sectional structure of a passivation layer formed in a method for manufacturing a solar cell according to another embodiment of the application.

Referring to fig. 11, the preparation method includes: a substrate 100 is provided, the substrate 100 having a front face 11 and a back face 12 disposed opposite each other, the back face having alternating first regions i and second regions ii.

Referring to fig. 11, a base substrate is provided, and the first surface and the second surface of the base substrate are modified flat surfaces. And carrying out texturing treatment on the first surface. The textured first surface is subjected to a diffusion process and a doped layer 101 is formed in a portion of the thickness of the original substrate. The interface of the doped layer 101 with the original substrate not subjected to the diffusion process is taken as the front surface 11 of the substrate 100, and the original substrate not subjected to the diffusion process is taken as the substrate 100. The second surface of the original substrate serves as the back surface 12 of the substrate 100.

In some embodiments, the texturing process includes: the substrate 100 may be cleaned by chemical etching, for example, using a mixed solution of potassium hydroxide and hydrogen peroxide solution, and specifically, the ratio of the concentrations of the potassium hydroxide and the hydrogen peroxide solution may be controlled to form a textured structure having a desired topography. In some embodiments, laser etching, mechanical or plasma etching may be used to form the textured structure. In laser etching, the suede structure with the shape conforming to the expected is obtained by controlling laser process parameters.

In some embodiments, after forming doped layer 101, a polishing process is further included on the back side of substrate 100 to form a polished surface on the back side of substrate 100.

Referring to fig. 11 to 14, the preparation method includes: a passivation contact structure is formed and is located on the first region i, the passivation contact structure includes a first tunneling dielectric layer 111 and a first doped conductive layer 112, the first tunneling dielectric layer 111 is located on the back surface 12, the first doped conductive layer 112 is located on the first tunneling dielectric layer 111, and a hole 160 is formed in the first doped conductive layer 112.

Referring to fig. 11, an initial dielectric layer 131 and a doped conductive film 132 are formed on the surface of the substrate 100, the initial dielectric layer 131 is located on the first region i and the second region ii, and the doped conductive film 132 is located on the surface of the initial dielectric layer 131.

In some embodiments, referring to fig. 11, the initial dielectric layer 131 is formed using a thermal oxygen method or a chemical deposition method.

In some embodiments, the method of forming doped conductive film 132 includes: the first deposition, wherein the deposition gas comprises silane, the flow is controlled to be 100 sccm~1000sccm, and the deposition temperature is between 400 and 700 ℃ to form an intrinsic semiconductor film; the second deposition, wherein the deposition gas comprises doping source gas and oxygen, the flow is controlled to be 100-3000 sccm, and the deposition temperature is 700-100 ℃ to form a doping type semiconductor film; the high temperature oxidation step, in which the gas includes nitrogen and oxygen, converts the doped semiconductor film into the doped conductive film 132.

Referring to fig. 12 to 14, the initial dielectric layer 131 and the doped conductive film 132 of the second region ii are removed; a hole 160 is formed in the doped conductive film 132 located on the first region i, the remaining doped conductive film serves as the first doped conductive layer 112, and the remaining initial dielectric layer 131 serves as the first tunneling dielectric layer 111.

Embodiments of the present application may include two schemes for forming the first doped conductive layer 112 and the first tunneling dielectric layer 111.

The first scheme is as follows: a mask 123 is formed before removing the initial dielectric layer and doping conductive film of the second region ii. Referring to fig. 12, a mask 123 is formed, the mask 123 having bubbles 1230 therein; the orthographic projection of the mask 123 on the reference plane is located in the first region i.

Referring to fig. 13, a first step for removing the doped conductive film 132 of the first thickness and the mask 123 of the second thickness located in the second region ii until the bubble 1230 is exposed is performed.

Referring to fig. 14, a second step is performed, the second step including: continuing to etch the doped conductive film 132 and the initial dielectric layer 131, and the mask 123 containing no air bubbles, and etching the mask 123 at the bottom of the air bubbles and the exposed doped conductive film 132 along the air bubbles 1230, and forming holes 160 in the doped conductive film 132; until the initial dielectric layer 131 located in the second region ii is removed.

The second scheme is as follows: after removing the initial dielectric layer and doping conductive film of the second region ii, a mask 123 is formed.

In some embodiments, doped silicon glass layer 124 is also formed on the surface of doped conductive film 132 at the same time that doped conductive film 132 is formed.

In some embodiments, referring to fig. 15, a mask 123 is formed, the mask 123 having air bubbles 1230 therein; the orthographic projection of the mask 123 on the reference plane is located in the first region i; referring to fig. 16, a first step for removing a portion of the thickness of the mask 123 until the air bubble 1230 is exposed is performed; and performing a second step, wherein the second step comprises the following steps: the etching of the mask 123 without bubbles is continued and the mask 123 at the bottom of the bubbles and the exposed doped silicate glass layer 124 are etched along with the bubbles 1230 and a via 1240 is formed in the doped silicate glass layer 124 until the mask is removed. Etching the doped conductive film 132 along the via 1240 and forming a hole 160 in the doped conductive film 132; and removing the doped silicon glass layer.

In some embodiments, the doped conductive film is not doped with a silicon glass layer, i.e., in a second step, etching a mask located at the bottom of the bubble along the bubble and the exposed doped conductive film, and forming a hole 160 in the doped conductive film; until the mask is removed.

In some embodiments, prior to forming the aperture 160, the air bubble 1230 has a first dimension d0 in a first direction; the hole 160 has a second dimension d along the first direction, and the first dimension d0 is less than or equal to the second dimension d.

In some embodiments, for the same mask 123, the total area of orthographic projection of the bubble 1230 on the reference plane is a third area, the area of the mask 123 on the reference plane is a fourth area, and the ratio of the third area to the fourth area is less than or equal to 50%.

Referring to fig. 17, the preparation method includes: a passivation layer 113 is formed, the passivation layer 113 being located on the second region ii and on the surface of the first doped conductive layer 112.

Referring to fig. 3, the preparation method includes: forming a plurality of electrodes 114, wherein the orthographic projections of the electrodes 114 on the reference surface correspond to the first areas I one by one, the electrodes 114 penetrate through the thickness of the passivation layer and the electrodes 114 are in electrical contact with the first doped conductive layer 112, and the electrodes 114 fill the holes 160; wherein the reference plane is a plane perpendicular to the thickness direction of the substrate 100.

Accordingly, according to some embodiments of the present application, referring to fig. 18, a further aspect of the embodiment of the present application provides a laminated battery, including: a bottom cell, which is a solar cell as in any of the above embodiments or a solar cell prepared by the method of preparation as in any of the above embodiments; and a top cell positioned on a side of the base away from the electrode in the bottom cell. Fig. 18 is a schematic cross-sectional view of a stacked battery according to another embodiment of the present application.

In some embodiments, the stacked cell has a first gate line 186 of a first polarity and a second gate line of a second polarity, the first gate line 186 being in electrical contact with the top cell 180 and the second gate line being in electrical contact with the bottom cell 150. Wherein the second grid line is the front electrode 104 of the bottom cell.

In some embodiments, an interfacial layer 181 is provided between the top cell and the bottom cell, the interfacial layer 181 filling the hole 160.

It should be noted that, the stacked solar cell in the embodiment of the present application only illustrates two layers of solar cells, and those skilled in the art may set three layers of solar cells and more than three layers of stacked solar cells according to actual requirements.

In some embodiments, the top cell 180 may be a perovskite solar cell comprising: a first transport layer 182, a perovskite substrate 183, a second transport layer 184, a transparent conductive layer 185, and an anti-reflection layer (not shown) are stacked. Wherein the first transmission layer is opposite to the bottom cell.

In some embodiments, the first transport layer may be one of an electron transport layer or a hole transport layer, and the second transport layer may be the other of the electron transport layer or the hole transport layer.

Accordingly, according to some embodiments of the present application, referring to fig. 19 and 20, a further aspect of an embodiment of the present application further provides a photovoltaic module, including: a battery string formed by connecting a plurality of battery pieces 30, which may be the solar cell according to any one of the above embodiments, the solar cell prepared by the preparation method according to any one of the above embodiments, or the laminate battery according to the above embodiments; a packaging adhesive film 31 for covering the surface of the battery string; and a cover plate 32 for covering the surface of the packaging adhesive film 31 facing away from the battery strings. Fig. 19 is a schematic structural view of a photovoltaic module according to still another embodiment of the present application; FIG. 20 is a schematic cross-sectional view of the structure of FIG. 19 along the line M1-M2.

Specifically, in some embodiments, the plurality of battery strings may be electrically connected by the connection member 318, and the connection member 318 is welded with the main/sub grid on the battery sheet 30. Fig. 19 illustrates only a positional relationship between solar cells, that is, the arrangement directions of electrodes having the same polarity for the battery sheets are the same or electrodes having positive polarity for each battery sheet are arranged toward the same side, so that the connection members 318 respectively connect different sides of two adjacent battery sheets. In some embodiments, the battery plates may also be arranged in order of the electrodes with different polarities facing the same side, that is, the electrodes of the adjacent battery plates are respectively arranged in the order of the first polarity, the second polarity, and the first polarity, so that the conductive strip connects two adjacent battery plates on the same side.

In some embodiments, no space is provided between the battery cells, i.e., the battery cells overlap each other.

In some embodiments, the connection member 318 is soldered between a sub-grid on the battery plate, the sub-grid including an electrode and a front electrode. In some embodiments, the connection member 318 is soldered to the main grids on the battery plate, which include a first main grid soldered to the front electrode and a second main grid soldered to the electrode.

In some embodiments, the packaging adhesive film 31 includes a first packaging adhesive film and a second packaging adhesive film, wherein the first packaging adhesive film covers one of the front surface or the back surface of the solar cell, and the second packaging adhesive film covers the other of the front surface or the back surface of the solar cell, specifically, at least one of the first packaging adhesive film or the second packaging adhesive film may be an organic packaging adhesive film such as a polyvinyl butyral (Polyvinyl Butyral, abbreviated as PVB) adhesive film, an ethylene-vinyl acetate copolymer (EVA) adhesive film, a polyethylene octene co-elastomer (POE) adhesive film, or a polyethylene terephthalate (PET) adhesive film.

It should be noted that, the first packaging film and the second packaging film have a parting line before the lamination process, and the concept of forming the photovoltaic module after the lamination process does not have the first packaging film and the second packaging film any more, that is, the first packaging film and the second packaging film are formed into the integral packaging film 37.

In some embodiments, the cover plate 32 may be a glass cover plate, a plastic cover plate, or the like having a light transmitting function. Specifically, the surface of the cover plate 32 facing the encapsulation film 31 may be a concave-convex surface, thereby increasing the utilization rate of incident light. The cover plate 32 includes a first cover plate opposite to the first packaging adhesive film and a second cover plate opposite to the second packaging adhesive film; or the first cover plate is opposite to one side of the solar cell, and the second cover plate is opposite to the other side of the solar cell.

While the application has been described in terms of the preferred embodiment, it is not intended to limit the scope of the claims, and any person skilled in the art can make many variations and modifications without departing from the spirit of the application, so that the scope of the application shall be defined by the claims. Furthermore, the embodiments of the present application described in the specification and the illustrated figures are illustrative only and are not intended to be limiting as to the full scope of the application as claimed.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of carrying out the application and that various changes in form and details may be made therein without departing from the spirit and scope of the application. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the application, and the scope of the application should be assessed accordingly to that of the appended claims.

Claims

1. A solar cell, comprising:

a substrate having a front side and a back side disposed opposite to each other, the back side having first and second regions alternately arranged;

The passivation contact structure is positioned on the first region and comprises a first tunneling dielectric layer and a first doped conductive layer, the first tunneling dielectric layer is positioned on the back surface, the first doped conductive layer is positioned on the first tunneling dielectric layer, and holes are formed in the first doped conductive layer;

A passivation layer on the second region and on a surface of the first doped conductive layer;

The electrodes are located on the orthographic projection of the reference surface and correspond to the first areas one by one, penetrate through the thickness of the passivation layer and are in electrical contact with the first doped conductive layer, and the holes are filled with the electrodes; wherein the reference plane is a plane perpendicular to the thickness direction of the substrate.

2. The solar cell of claim 1, wherein the hole comprises:

A first type of hole, the first type of hole not penetrating the first doped conductive layer;

a second type of hole, the second type of hole penetrating the first doped conductive layer; the electrode fills the first type of holes and the second type of holes.

3. The solar cell of claim 2, wherein the ratio of the number of the first type of holes to the number of the second type of holes is in the range of 5:1 to 1:10.

4. The solar cell of claim 1, wherein for the same first doped conductive layer, the total area of orthographic projections of the holes on the reference surface is a first area, the area of the first doped conductive layer on the reference surface is a second area, and the ratio of the first area to the second area is less than or equal to 20%.

5. The solar cell according to claim 1, wherein the size of the hole along a first direction is in a range of 5 μm to 30 μm, the first direction being a direction parallel to the reference plane.

6. The solar cell according to claim 1, wherein the depth range of the holes is less than or equal to 200nm.

7. The solar cell of claim 1, wherein the plurality of consecutively arranged first regions comprises alternating N regions and P regions, the second regions being between the N regions and the P regions; the first doped conductive layer comprises a first sub-doped conductive layer positioned on the P region and a second sub-doped conductive layer positioned on the N region, and at least one of the first sub-doped conductive layer and the second sub-doped conductive layer is provided with the hole.

8. The solar cell of claim 7, wherein the first sub-doped conductive layer has a first sub-aperture and the second sub-doped conductive layer has a second sub-aperture, the first sub-aperture having a dimension in a first direction that is less than or equal to a dimension of the second sub-aperture in the first direction.

9. The solar cell of claim 1, wherein one of an N-type doping element or a P-type doping element is doped within the substrate, and the other of the N-type doping element or the P-type doping element is doped within the first doped conductive layer.

10. The solar cell of claim 1, wherein the substrate is doped with one of an N-type doping element or a P-type doping element, the doping element in the first doped conductive layer having the same conductivity type as the doping element in the substrate.

11. The solar cell according to claim 9 or 10, wherein the passivation contact structure further comprises: the second tunneling dielectric layer is positioned on the first region, the second doped conductive layer is positioned between the first tunneling dielectric layer and the second tunneling dielectric layer, and the doping elements in the second doped conductive layer and the doping elements in the first doped conductive layer have the same conductivity type.

12. The solar cell of claim 11, wherein the second tunneling dielectric layer is further located in the second region, and the second doped conductive layer is further located between the passivation layer and the second tunneling dielectric layer.

13. The solar cell according to claim 11 or 12, wherein the thickness of the second doped conductive layer is less than or equal to the thickness of the first doped conductive layer.

14. A method of manufacturing a solar cell, comprising:

Providing a substrate, wherein the substrate is provided with a front surface and a back surface which are oppositely arranged, and the back surface is provided with a first area and a second area which are alternately arranged;

Forming a passivation contact structure, wherein the passivation contact structure is positioned on the first region and comprises a first tunneling dielectric layer and a first doped conductive layer, the first tunneling dielectric layer is positioned on the back surface, the first doped conductive layer is positioned on the first tunneling dielectric layer, and holes are formed in the first doped conductive layer;

Forming a passivation layer on the second region and on the surface of the first doped conductive layer;

Forming a plurality of electrodes, wherein orthographic projections of the electrodes on the reference surface correspond to the first areas one by one, the electrodes penetrate through the thickness of the passivation layer and are in electrical contact with the first doped conductive layer, and the electrodes fill the holes; wherein the reference plane is a plane perpendicular to the thickness direction of the substrate.

15. The method of manufacturing of claim 14, wherein the process step of forming the passivated contact structure comprises: forming an initial dielectric layer and a doped conductive film on the surface of the substrate, wherein the initial dielectric layer is positioned on the first region and the second region, and the doped conductive film is positioned on the surface of the initial dielectric layer;

removing the initial dielectric layer and the doped conductive film of the second region;

and forming holes in the doped conductive film on the first region, wherein the rest of the doped conductive film is used as the first doped conductive layer, and the rest of the initial dielectric layer is used as the first tunneling dielectric layer.

16. The method of manufacturing according to claim 15, comprising, before forming a hole in the doped conductive film:

Forming a mask, wherein bubbles are arranged in the mask; the orthographic projection of the mask on the reference surface is positioned in the first area;

Performing a first step for removing a portion of the thickness of the mask until the bubbles are exposed; performing a second step, the second step comprising: continuing to etch the mask which does not contain the bubbles, etching the mask positioned at the bottom of the bubbles and the exposed doped conductive film along the bubbles, and forming holes in the doped conductive film; until the mask is removed.

17. The method of manufacturing according to claim 16, wherein the mask is formed after removing the initial dielectric layer and the doped conductive film of the second region.

18. The method of manufacturing according to claim 16, wherein the mask is formed before removing the initial dielectric layer and the doped conductive film of the second region;

the first step is used for removing the doped conductive film with the first thickness and the mask with the second thickness in the second region until the bubbles are exposed;

The second step includes: continuing to etch the doped conductive film, the initial dielectric layer and the mask which does not contain the bubbles, etching the mask positioned at the bottom of the bubbles and the exposed doped conductive film along the bubbles, and forming holes in the doped conductive film; until the initial dielectric layer in the second region is removed.

19. The method of manufacturing according to claim 17 or 18, wherein the bubbles have a first dimension in a first direction prior to forming the holes; the hole has a second dimension along a first direction, the first dimension being less than or equal to the second dimension.

20. The method of manufacturing according to claim 16 or 17, wherein for the same mask, the total area of orthographic projections of the bubbles on the reference surface is a third area, the area of the mask on the reference surface is a fourth area, and the ratio of the third area to the fourth area is less than or equal to 50%.

21. A laminated battery, characterized by comprising:

A bottom cell which is a solar cell according to any one of claims 1 to 11 or a solar cell produced by a production method according to any one of claims 14 to 20;

And a top cell positioned on a side of the base away from the electrode in the bottom cell.

22. A photovoltaic module, comprising:

A cell string formed by connecting a plurality of solar cells according to any one of claims 1 to 13, solar cells produced by the production method according to any one of claims 14 to 20, or laminated cells according to claim 21;

The packaging adhesive film is used for covering the surface of the battery string;

and the cover plate is used for covering the surface of the packaging adhesive film, which is away from the battery strings.