KR100515372B1 - Method for forming fine pattern of semiconductor device - Google Patents
Method for forming fine pattern of semiconductor device Download PDFInfo
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- KR100515372B1 KR100515372B1 KR10-2003-0101795A KR20030101795A KR100515372B1 KR 100515372 B1 KR100515372 B1 KR 100515372B1 KR 20030101795 A KR20030101795 A KR 20030101795A KR 100515372 B1 KR100515372 B1 KR 100515372B1
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- Prior art keywords
- forming
- photoresist
- insulating film
- contact hole
- pattern
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Abstract
보다 미세한 패턴의 형성을 가능하게 하여 사진식각 공정의 마진을 확보할 수 있는 반도체 소자의 미세 패턴 형성 방법은, 반도체 기판 상에 하부 및 상부 절연막을 차례로 형성하는 단계와, 상부 절연막 위에 콘택홀이 형성될 영역을 한정하는 제1 포토레지스트 패턴을 형성하는 단계와, 제1 포토레지스트 패턴을 마스크로 하여 상부 절연막을 식각하는 단계와, 전면에 제2 포토레지스트를 도포하는 단계와, 제2 포토레지스트를 노광 및 현상하는 단계, 그리고 제2 포토레지스트를 마스크로 하여 하부 절연막을 식각하여 콘택홀을 형성하는 단계로 이루어진다.In the method of forming a fine pattern of a semiconductor device capable of forming a finer pattern and securing a margin of a photolithography process, a method of forming a lower and an upper insulating film in turn on a semiconductor substrate, and forming a contact hole on the upper insulating film Forming a first photoresist pattern defining a region to be formed, etching the upper insulating film using the first photoresist pattern as a mask, applying a second photoresist to the entire surface, and Exposing and developing, and forming a contact hole by etching the lower insulating film using the second photoresist as a mask.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 공정 마진을 확보하면서 미세한 콘택홀 패턴을 형성할 수 있는 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method capable of forming a fine contact hole pattern while securing a process margin.
반도체 장치의 고집적화가 급속히 진행되면서 라인 패턴(line pattern)과 콘택홀 패턴(contact hole pattern)을 형성하기 위한 고해상도의 패터닝 기술이 필요하게 되었다. 라인/ 스페이스(space) 패턴에 대한 패터닝 기술은 콘택홀 패턴에 대한 기술보다 유리하여 좁은 라인패턴의 경우 어느 정도 해상도를 확보할 수 있지만, 매우 작은 크기의 콘택홀 패턴을 형성하기는 매우 어렵다. 따라서, 콘택홀을 미세한 크기로 형성하기 어려울 경우, 그 위에 형성되는 라인 패턴의 경우 콘택홀을 완전히 감싸도록 형성되지 않아서 콘택홀이 노출되는 문제가 발생하는데, 미스 얼라인이 발생할 경우 더욱 문제가 심각해진다.As the integration of semiconductor devices has been rapidly progressed, high resolution patterning techniques for forming line patterns and contact hole patterns have been required. The patterning technique for the line / space pattern is advantageous over the technique for the contact hole pattern, so that the resolution can be secured to some extent in the case of narrow line patterns, but it is very difficult to form a very small contact hole pattern. Therefore, when it is difficult to form the contact hole in a fine size, the line pattern formed thereon is not formed to completely surround the contact hole, so that the contact hole is exposed, which is more serious when a misalignment occurs. Become.
한편, 콘택홀 패턴의 크기가 작아짐에 따라 사진공정에서의 공정마진(process margin)을 확보하기 위하여 몇 가지 기술이 사용되고 있지만, 패턴의 종류가 다양하고 패턴의 크기 또한 다양한 비 메모리소자의 경우에는 사용상 어려운 점이 있기 때문에 보다 업그레이드(upgrade)된 장비의 구매가 요구되는 등 문제점이 있다. 또한, 일반적으로 콘택홀을 형성하기 위한 사진공정 전에 반도체 기판에는 이미 절연막 또는 층간 절연막 등이 단일막이 아닌 여러 층 증착되어 있다. 이러한 경우에는 상부 층간 절연막 위에 콘택홀 형성을 위한 포토레지스트 패턴을 형성하고, 이를 마스크로 하여 상부 층간 절연막과 하부 층간 절연막 등을 차례로 식각하여 최종적으로 콘택홀을 형성한다. 따라서, 한 번 형성된 포토레지스트 패턴의 사이즈보다 콘택홀의 크기를 더 축소시킬 수는 없는 것이다.On the other hand, as the size of the contact hole pattern decreases, some techniques are used to secure a process margin in the photolithography process, but in the case of non-memory devices having various types of patterns and various pattern sizes, Because of the difficulty, there are problems such as the purchase of more upgraded equipment. In general, before the photolithography process for forming contact holes, an insulating film or an interlayer insulating film is already deposited on the semiconductor substrate instead of a single film. In this case, a photoresist pattern for forming a contact hole is formed on the upper interlayer insulating layer, and the upper interlayer insulating layer and the lower interlayer insulating layer are etched sequentially to form a contact hole. Therefore, it is not possible to reduce the size of the contact hole more than the size of the once formed photoresist pattern.
본 발명이 이루고자 하는 기술적 과제는 보다 미세한 패턴의 형성을 가능하게 하여 사진식각 공정의 마진을 확보할 수 있는 반도체 소자의 미세 패턴 형성 방법을 제공하는 것이다.The technical problem to be achieved by the present invention is to provide a method of forming a fine pattern of a semiconductor device capable of forming a finer pattern, thereby securing a margin of a photolithography process.
상기 기술적 과제를 달성하기 위하여 본 발명에 따른 반도체 소자의 미세 패턴 형성 방법은, 반도체 기판 상에 하부 및 상부 절연막을 차례로 형성하는 단계와, 상기 상부 절연막 위에 콘택홀이 형성될 영역을 한정하는 제1 포토레지스트 패턴을 형성하는 단계와, 상기 제1 포토레지스트 패턴을 마스크로 하여 상기 상부 절연막을 식각하는 단계와, 전면에 제2 포토레지스트를 도포하는 단계와, 상기 제2 포토레지스트를 노광 및 현상하는 단계, 및 상기 제2 포토레지스트를 마스크로 하여 상기 하부 절연막을 식각하여 콘택홀을 형성하는 단계를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a fine pattern of a semiconductor device, the method including sequentially forming a lower and an upper insulating film on a semiconductor substrate, and defining a region where a contact hole is to be formed on the upper insulating film Forming a photoresist pattern, etching the upper insulating film using the first photoresist pattern as a mask, applying a second photoresist to the entire surface, and exposing and developing the second photoresist. And etching the lower insulating film using the second photoresist as a mask to form contact holes.
이하 첨부 도면을 참조하면서 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
본 발명에서는 다층으로 형성된 층간 절연막을 식각하여 콘택홀을 형성할 때, 상부 층간 절연막을 식각한 후 다시 포토레지스트를 도포하고 하부 층간 절연막을 식각하기 때문에 종래에 비해 콘택홀의 크기를 작게 할 수가 있다.In the present invention, when forming the contact hole by etching the interlayer insulating film formed of a multi-layer, since the upper interlayer insulating film is etched, the photoresist is applied again and the lower interlayer insulating film is etched, so that the size of the contact hole can be made smaller than before.
도 1 내지 도 3은 본 발명의 패턴 형성 방법을 설명하기 위하여 도시한 단면도들이다.1 to 3 are cross-sectional views for explaining the pattern forming method of the present invention.
먼저 도 1을 참조하면, 트랜지스터와 같은 소자들(도시되지 않음)이 형성되어 있는 반도체 기판(10) 위에, 상기 소자들을 서로 분리하고 다른 도전영역들과 절연시키기 위한 하부 및 상부 층간 절연막(12, 14)을 차례로 형성한다. 다음, 상부 층간 절연막(14) 위에, 포토레지스트를 도포한 다음 노광 및 현상을 실시하여 콘택홀 패턴이 형성될 영역을 한정하는 포토레지스트 패턴(16)을 형성한다. 다음에, 이 포토레지스트 패턴(16)을 마스크로 사용하여 상부 층간 절연막(14)을 이방성식각한다.Referring first to FIG. 1, a lower and upper interlayer insulating layer 12 is formed on a semiconductor substrate 10 on which devices such as transistors (not shown) are formed, to separate the devices from each other and to insulate other conductive regions. 14) are formed in sequence. Next, a photoresist is applied on the upper interlayer insulating film 14, followed by exposure and development to form a photoresist pattern 16 defining a region where a contact hole pattern is to be formed. Next, the upper interlayer insulating film 14 is anisotropically etched using this photoresist pattern 16 as a mask.
도 2를 참조하면, 상부 층간 절연막(14)이 패터닝된 상태에서 다시 전면에 포토레지스트(18)를 도포한 다음 노광 및 현상을 실시한다. 그러면, 상부 층간 절연막(14)의 측벽에 도포된 포토레지스트(18)의 두께만큼 노출된 영역의 크기를 줄일 수 있다.Referring to FIG. 2, in the state where the upper interlayer insulating layer 14 is patterned, the photoresist 18 is coated on the entire surface, followed by exposure and development. Then, the size of the exposed area can be reduced by the thickness of the photoresist 18 applied to the sidewall of the upper interlayer insulating film 14.
도 3을 참조하면, 포토레지스트(18)를 마스크로 사용하여 노출된 하부 층간 절연막(12)을 이방성 식각하여 반도체 기판(10)을 노출시키는 최종 콘택홀을 형성한다. 이렇게 하여 형성된 최종 콘택홀의 크기는 종래에 비해 상부 층간 절연막의 측벽에 도포된 포토레지스트의 두께만큼 줄어들게 되므로, 보다 미세한 콘택홀 패턴을 형성할 수 있으며, 사진공정 단계의 마진을 크게할 수 있다.Referring to FIG. 3, the lower contact interlayer insulating layer 12 is anisotropically etched using the photoresist 18 as a mask to form a final contact hole exposing the semiconductor substrate 10. Since the size of the final contact hole thus formed is reduced by the thickness of the photoresist applied to the sidewall of the upper interlayer insulating film, a finer contact hole pattern can be formed and the margin of the photo process step can be increased.
이상, 본 발명의 실시예를 설명하였으나, 본 발명은 상술한 실시예에 국한되는 것이 아니라 후술되는 청구범위에 기재된 본 발명의 기술적 사상과 범주내에서 당업자에 의해 여러 가지 변형이 가능하다.As mentioned above, although embodiment of this invention was described, this invention is not limited to the above-mentioned embodiment, A various deformation | transformation is possible for a person skilled in the art within the technical idea and scope of this invention described in the claim mentioned later.
이상의 설명에서와 같이, 본 발명에 따른 반도체 소자의 패턴 형성 방법에 따르면, 다층으로 이루어진 층간 절연막을 식각하여 콘택홀 패턴을 형성할 때 상부 층간 절연막을 식각한 상태에서 다시 포토레지스트를 전면에 도포한 다음 하부 층간 절연막을 식각함으로써, 보다 미세한 콘택홀 패턴을 형성할 수 있으며, 사진공정 단계의 마진을 크게 할 수 있다.As described above, according to the method of forming a pattern of a semiconductor device according to the present invention, when forming a contact hole pattern by etching an interlayer insulating film made of a multi-layer, the photoresist is applied to the entire surface again while the upper interlayer insulating film is etched. By etching the lower interlayer insulating film, a finer contact hole pattern can be formed, and the margin of the photolithography step can be increased.
도 1 내지 도 3은 본 발명의 미세 패턴 형성 방법을 설명하기 위하여 도시한 단면도들이다.1 to 3 are cross-sectional views illustrating a method for forming a fine pattern of the present invention.
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| Application Number | Priority Date | Filing Date | Title |
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| KR10-2003-0101795A KR100515372B1 (en) | 2003-12-31 | 2003-12-31 | Method for forming fine pattern of semiconductor device |
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| KR10-2003-0101795A KR100515372B1 (en) | 2003-12-31 | 2003-12-31 | Method for forming fine pattern of semiconductor device |
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| KR100515372B1 true KR100515372B1 (en) | 2005-09-14 |
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