TW201537646A - 半導體封裝及其製造方法 - Google Patents

半導體封裝及其製造方法 Download PDF

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Publication number
TW201537646A
TW201537646A TW103111955A TW103111955A TW201537646A TW 201537646 A TW201537646 A TW 201537646A TW 103111955 A TW103111955 A TW 103111955A TW 103111955 A TW103111955 A TW 103111955A TW 201537646 A TW201537646 A TW 201537646A
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Taiwan
Prior art keywords
photosensitive conductive
carrier substrate
photosensitive
conductive material
semiconductor package
Prior art date
Application number
TW103111955A
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English (en)
Inventor
Chien-Chih Huang
Original Assignee
Chipmos Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Chipmos Technologies Inc filed Critical Chipmos Technologies Inc
Priority to TW103111955A priority Critical patent/TW201537646A/zh
Priority to CN201410325053.0A priority patent/CN104952740A/zh
Priority to US14/642,122 priority patent/US20150279771A1/en
Publication of TW201537646A publication Critical patent/TW201537646A/zh

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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Abstract

本發明揭露一種半導體封裝及其製造方法。半導體封裝包括：一感光導電層，包含至少一導電區域及至少一絕緣區域；一晶片配置於感光導電層上，並與至少一導電區域電性連接；以及一封裝材料，覆蓋晶片及感光導電層。

Description

半導體封裝及其製造方法
本發明係有關於一種半導體封裝及其製造方法，且特別是有關於以感光導電材料作為電路層的一種半導體封裝及其製造方法。
隨著技術的演進，半導體封裝技術與材料也日新月異。由於半導體晶片的積集度提高，所以半導體封裝的腳位數量與密度也逐漸提高。為了符合高腳位數的需求，許多半導體封裝都會採用高密度的印刷電路基板(printed circuit substrate)作為封裝載體，習知印刷電路基板的線路，係在一核心板上形成由多個金屬層與絕緣層交互層疊的增層結構，且其中之金屬層係經過微影技術及蝕刻而圖案化，以形成線路。因此，習知印刷電路基板的製程複雜且耗時，且其厚度無法有效縮減。因此，如何簡化製程、降低製造成本，一直以來都是此領域持續研發的方向。
本發明的觀點之一在於提供一種半導體封裝方法，利用曝光感光導電材料形成線路層，以簡化製程步驟，且可以降低製造成本。
根據本發明的上述及其他觀點，提供一種半導體封裝方法，包括後續步驟：提供一承載基板，具有一第一表面及相對之一第二表面；形成一感光導電材料於承載基板之第一表面上；曝光感光導電材料，使得 感光導電材料形成一感光導電層，包含至少一導電區域及至少一絕緣區域；配置一晶片於感光導電層上；將晶片與至少一導電區域電性連接；形成一封裝材料，覆蓋晶片及感光導電層；以及形成至少一導電貫孔於承載基板中，導電貫孔電性連接導電區域。
在本發明的一個或多個實施例中，於形成導電貫孔於承載基板中之後，更包括形成至少一外接端子於承載基板之第二表面上，外接端子電性連接導電貫孔。
在本發明的一個或多個實施例中，形成感光導電材料的步驟更包括：塗佈感光導電材料於承載基板之第一表面上；以及烘烤固化感光導電材料。
在本發明的一個或多個實施例中，曝光感光導電材料的步驟包括利用紫外光或X光進行曝光。
根據本發明的上述及其他觀點，提供一種半導體封裝方法，包括下列步驟：提供一承載基板；形成一感光導電材料於承載基板之一表面上；曝光感光導電材料，使得感光導電材料形成一感光導電層，包含至少一導電區域及至少一絕緣區域；配置一晶片於感光導電層上；將晶片與至少一導電區域電性連接；形成一封裝材料，覆蓋晶片及感光導電層；以及去除承載基板。
在本發明的一個或多個實施例中，於去除承載基板之後，更包括形成至少一外接端子，電性連接導電區域。
在本發明的一個或多個實施例中，形成該感光導電材料的步驟更包括：塗佈感光導電材料於承載基板之表面上；以及烘烤固化感光導 電材料。
根據本發明的上述及其他觀點，提供一種半導體封裝方法，包括下列步驟：提供一承載基板，承載基板具有一第一表面、相對之一第二表面及至少一貫孔；形成一感光導電材料於承載基板之第一表面上；曝光感光導電材料，使得感光導電材料形成一感光導電層，包含至少一導電區域及至少一絕緣區域，且貫孔對應並連接導電區域；配置一晶片於感光導電層上；將晶片與導電區域電性連接；以及形成一封裝材料，覆蓋晶片及感光導電層。
在本發明的一個或多個實施例中，於形成封裝材料之後，更包括形成至少一外接端子於承載基板之第二表面上，外接端子電性連接導電區域。
在本發明的一個或多個實施例中，形成感光導電材料的步驟更包括：塗佈感光導電材料於承載基板之第一表面上；以及烘烤固化感光導電材料。
在本發明的一個或多個實施例中，曝光感光導電材料的步驟包括利用紫外光或X光進行曝光。
在本發明的一個或多個實施例中，塗佈感光導電材料於承載基板之第一表面上時，感光導電材料同時填充於貫孔中，且導電區域包含貫孔中的感光導電材料。
在本發明的一個或多個實施例中，提供承載基板步驟中，貫孔中已填入一導電材料。
在本發明的一個或多個實施例中，形成外接端子於承載基板 之第二表面上更包括填充一導電材料於貫孔中。
根據本發明的上述及其他觀點，提供一種半導體封裝，包括：一承載基板，具有一第一表面及相對之一第二表面；一感光導電層配置於承載基板之第一表面上，感光導電層包含至少一導電區域及至少一絕緣區域；一晶片配置於感光導電層上，並與導電區域電性連接；一封裝材料，覆蓋晶片及感光導電層；以及至少一導電貫孔，配置於承載基板中，並電性連接導電區域。
在本發明的一個或多個實施例中，半導體封裝更包括至少一外接端子，配置於承載基板之第二表面上，且電性連接導電貫孔。
在本發明的一個或多個實施例中，導電區域係藉由以紫外光或X光照射感光導電材料而形成。
根據本發明的上述及其他觀點，提供一種半導體封裝，包括：一感光導電層，包含至少一導電區域及至少一絕緣區域；一晶片配置於感光導電層上，並與至少一導電區域電性連接；以及一封裝材料，覆蓋晶片及感光導電層。
在本發明的一個或多個實施例中，半導體封裝更包括至少一外接端子，電性連接導電區域。
在本發明的一個或多個實施例中，導電區域係藉由以紫外光或X光照射感光導電材料而形成。
在本發明中，由於封裝載體係以感光導電材料所形成，所以直接經由曝光即可形成線路層，而無須顯影或蝕刻步驟，可以簡化製程，相對地可以降低製造成本；並且因封裝載體的厚度縮減，進一步使半導體 封裝達到薄化的效果。
100‧‧‧承載基板
100A‧‧‧第一表面
100B‧‧‧第二表面
102‧‧‧感光導電材料
104‧‧‧感光導電層
104A‧‧‧導電區域
104B‧‧‧絕緣區域
105‧‧‧圖案化防焊層
112‧‧‧導電凸塊
114‧‧‧封裝材料
116‧‧‧導電貫孔
118、120‧‧‧外接端子
122‧‧‧銲線
200‧‧‧承載基板
200A‧‧‧第一表面
200B‧‧‧第二表面
106‧‧‧光罩
107‧‧‧開孔
108‧‧‧光源
110‧‧‧晶片
216‧‧‧貫孔
圖一至圖五為依照本發明之一實施例，一種半導體封裝方法，各步驟的剖面示意圖。
圖五A及圖五B為依照本發明之另一實施例，一種半導體封裝方法，對應圖四步驟後的另一製程的剖面示意圖。
圖六為依照本發明之又一實施例，一種半導體封裝的剖面示意圖。
圖七至圖十為依照本發明之再一實施例，一種半導體封裝方法，各步驟的剖面示意圖。
關於本發明的優點，精神與特徵，將以實施例並參照所附圖式，進行詳細說明與討論。值得注意的是，為了讓本發明能更容易理解，後附的圖式僅為示意圖，相關尺寸並非以實際比例繪示。
為了讓本發明的優點，精神與特徵可以更容易且明確地了解，後續將以實施例並參照所附圖式進行詳述與討論。值得注意的是，這些實施例僅為本發明代表性的實施例，其中所舉例的特定方法、裝置、條件、材質等並非用以限定本發明或對應的實施例。
請參照圖一至圖五，其繪示依照本發明之一實施例，一種半導體封裝方法，各步驟的剖面示意圖。請先參照圖一，本發明的封裝方法，係在一個承載基板100上進行，承載基板100具有一第一表面100A及相對之一第二表面100B。承載基板100可以是任意材質，比如金屬材料、絕緣材料、 半導體材料，或者上述之組成的複合材料等等。在本實施例中，承載基板100的材料為絕緣材料，比如環氧樹脂、聚醯亞胺(Polyimide)、玻璃等。接著，形成一感光導電材料102於承載基板100之第一表面100A上。
請參照圖二，接著曝光感光導電材料102以形成一感光導電層104，比如以一具有線路圖案的光罩106，透過一光源108，照射部分感光導電材料102，使得感光導電材料102形成包含至少一導電區域104A及至少一絕緣區域104B的感光導電層104。光源108可以是紫外光、X光或其他適合之光源。感光導電材料102經過光源108照射後，部分區域即具有導電性，形成導電區域104A。熟習此技藝者應知，除了透過光罩106進行曝光外，也可以是直寫式的曝光，直接利用光束將圖案寫於感光導電材料102上，此時光罩106即非必要。詳細來說，形成感光導電材料102的方法可以利用塗佈的方式，將感光導電材料102形成於承載基板100之第一表面100A上。接著進行烘烤固化感光導電材料102，再以紫外光或X光進行曝光步驟。在本發明其他實施例中，感光導電材料102也可以利用貼附薄膜方式形成於承載基板100之第一表面100A上，且於曝光感光導電材料102同時藉由光固化感光導電材料102。
請參照圖三，接著配置一晶片110於感光導電層104上，且將晶片110與導電區域104A電性連接，比如利用覆晶(flip chip)的方式，以導電凸塊112(conductive bump)電性連接晶片110之接點(未繪示)與導電區域104A。接著請參照圖四，形成一封裝材料114，覆蓋晶片110、導電凸塊112及感光導電層104，封裝材料114之材質比如是環氧樹脂。值得一提的是，在形成封裝材料114之前，也可以選擇性在晶片110與感光導電層104之間形 成底填材料(underfill)，以保護導電凸塊112。
請參照圖五，於承載基板100中形成導電貫孔116(conductive via)，這些導電貫孔116電性連接導電區域104A。詳細來說，可以先於承載基板100形成孔洞，比如利用鑽孔的方法或者微影蝕刻的方法形成之。然後再填入導電材料，比如焊錫，即可形成導電貫孔116。於形成導電貫孔116於承載基板100中之後，可以選擇性形成外接端子118，比如錫球(solder ball)於承載基板100之第二表面100B上。外接端子118電性連接導電貫孔116，做為對外連接之用，比如可以做為表面焊接(SMT)的接點。
請參照圖五A及圖五B，圖五A及圖五B為依照本發明之另一實施例，一種半導體封裝方法，對應圖四步驟後的另一製程的剖面示意圖。在本發明的另一實施例中，在圖四形成封裝材料114之後，可以將承載基板100去除，形成如圖五A的結構，此時暴露出感光導電層104。接著參照圖五B，可以選擇性形成外接端子120，比如錫球，於感光導電層104之導電區域104A，並與導電區域104A電性連接，以做為對外連接之用，比如可以做為表面焊接(SMT)的接點。值得一提的是，在本實施例中之半導體封裝，由於感光導電層104會暴露於外界，所以感光導電層104的選擇較佳是採用X光曝光型的感光導電材料，以避免大自然的紫外線照射後產生感光導電材料的光反應作用，而改變其導電性。當然，也可以選擇性先形成一圖案化防焊層105於感光導電層104之外露表面，該圖案化防焊層105具有至少一開孔107暴露出部分導電區域104A，再於該些開孔107中形成外接端子120。又或者如果本發明的半導體封裝使用時，可以對其做適當的遮蔽或包覆，防止大自然紫外線的照射，則仍可以採用紫外光曝光型的感光導電材料。
請參照圖六，圖六為依照本發明之又一實施例，一種半導體封裝的剖面示意圖。請同時參照圖五與圖六，圖五與圖六主要的不同在於，圖五中晶片110係以覆晶方式，透過導電凸塊112與導電區域104A電性連接。而圖六中晶片110係直接以背面貼附於感光導電層104上，比如藉由一黏著膠(未繪示)與感光導電層104貼合，然後利用打線步驟(wire bonding)，以銲線122將晶片110主動面上之接點(未繪示)與導電區域104A電性連接。
請參照圖七至圖十，其繪示依照本發明之再一實施例，一種半導體封裝方法，各步驟的剖面示意圖。請先參照圖七，本發明的封裝方法，係在一個承載基板200上進行，承載基板200具有一第一表面200A及相對之一第二表面200B。在此實施例中，承載基板200的材料為絕緣材料，比如環氧樹脂、聚醯亞胺(Polyimide)、玻璃等，且已形成貫孔216於其中。接著，形成一感光導電材料102於承載基板200之第一表面200A上。
請參照圖八，接著曝光感光導電材料102以形成一感光導電層104，比如以一具有線路圖案的光罩106，透過一光源108，照射部分感光導電材料102，使得感光導電材料102形成包含至少一導電區域104A及至少一絕緣區域104B的感光導電層104。光源108可以是紫外光、X光或其他適合之光源。感光導電材料102經過光源108照射後，部分區域即具有導電性，形成導電區域104A，其中貫孔216分別對應並連接導電區域104A。熟習此技藝者應知，除了透過光罩106進行曝光外，也可以是直寫式的曝光，直接利用光束將圖案寫於感光導電材料102上，此時光罩106即非必要。詳細來說，形成感光導電材料102的方法可以利用塗佈的方式，將感光導電材料102形成於承載基板200之第一表面200A上。接著進行烘烤固化感光導電材料 102，再以紫外光或X光進行曝光步驟。在本發明其他實施例中，感光導電材料102也可以利用貼附薄膜方式形成於承載基板200之第一表面200A上，且於曝光感光導電材料102同時藉由光固化感光導電材料102。
請參照圖九，接著配置一晶片110於感光導電層104上，且將晶片110與導電區域104A電性連接。詳細來說，晶片110係直接以背面貼附於感光導電層104上，比如藉由一黏著膠(未繪示)與感光導電層104貼合，然後利用打線步驟(wire bonding)，以銲線122將晶片110主動面上之接點(未繪示)與導電區域104A電性連接。接著請參照圖十，形成一封裝材料114，覆蓋晶片110、銲線122及感光導電層104，封裝材料114之材質比如是環氧樹脂。最後，選擇性形成外接端子118，比如錫球(solder ball)於承載基板200之第二表面200B上。外接端子118藉由貫孔116電性連接導電區域104A，並做為對外連接之用，比如可以做為表面焊接(SMT)的接點。
值得一提的是，在本實施例中貫孔116中亦包含導電材料，以作為電性連接之用，而此導電材料的形成可以藉由下列方式。第一，當塗佈感光導電材料102於承載基板200之第一表面200A上時，感光導電材料102同時填充於貫孔116中。透過曝光步驟，照射貫孔116中的感光導電材料102，使得貫孔116中的感光導電材料102亦形成導電區域104A之一部分。第二，在提供承載基板200時，貫孔116中已填入一導電材料，比如焊錫。也就是說，承載基板200可以是已形成線路及/或導電貫孔之印刷電路基板。第三，在形成外接端子118於承載基板200之第二表面200B的同時，將一導電材料填充於貫孔116中。舉例而言，可在形成錫球/錫墊時，將焊錫材料同時填入貫孔116中。
綜上所述，由於本發明之半導體封裝載體係以感光導電材料直接經由曝光形成包含線路層(即導電區域)及承載線路層之絕緣層(即絕緣區域)的電路層，而無須顯影或蝕刻步驟，可以簡化製程，相對地可以降低製造成本；並且因封裝載體的厚度縮減，進一步達到半導體封裝薄化的效果。
藉由以上較佳具體實施例之詳述，係希望能更加清楚描述本發明之特徵與精神，而並非以上述所揭露的較佳具體實施例來對本發明之範疇加以限制。相反地，其目的是希望能涵蓋各種改變及具相等性的安排於本發明所欲申請之專利範圍的範疇內。雖然本發明已以實施方式揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本創作之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧承載基板
100A‧‧‧第一表面
100B‧‧‧第二表面
104‧‧‧感光導電層
104A‧‧‧導電區域
104B‧‧‧絕緣區域
110‧‧‧晶片
112‧‧‧導電凸塊
114‧‧‧封裝材料
116‧‧‧導電貫孔
118‧‧‧外接端子

Claims (21)

  1. 一種半導體封裝方法，包括：提供一承載基板，該承載基板具有一第一表面及相對之一第二表面；形成一感光導電材料於該承載基板之該第一表面上；曝光該感光導電材料，使得該感光導電材料形成一感光導電層，包含至少一導電區域及至少一絕緣區域；配置一晶片於該感光導電層上；將該晶片與該至少一導電區域電性連接；形成一封裝材料，覆蓋該晶片及該感光導電層；以及形成至少一導電貫孔於該承載基板中，該至少一導電貫孔電性連接該導電區域。
  2. 如請求項1所述之半導體封裝方法，其中於形成該至少一導電貫孔於該承載基板中之後，更包括形成至少一外接端子於該承載基板之該第二表面上，該至少一外接端子電性連接該導電貫孔。
  3. 如請求項1所述之半導體封裝方法，其中形成該感光導電材料的步驟更包括：塗佈該感光導電材料於該承載基板之該第一表面上；以及烘烤固化該感光導電材料。
  4. 如請求項1所述之半導體封裝方法，其中曝光該感光導電材料的步驟包括利用紫外光或X光進行曝光。
  5. 一種半導體封裝方法，包括：提供一承載基板； 形成一感光導電材料於該承載基板之一表面上；曝光該感光導電材料，使得該感光導電材料形成一感光導電層，包含至少一導電區域及至少一絕緣區域；配置一晶片於該感光導電層上；將該晶片與該至少一導電區域電性連接；形成一封裝材料，覆蓋該晶片及該感光導電層；以及去除該承載基板。
  6. 如請求項5所述之半導體封裝方法，其中於去除該承載基板之後，更包括形成至少一外接端子，電性連接該至少一導電區域。
  7. 如請求項5所述之半導體封裝方法，其中形成該感光導電材料的步驟更包括：塗佈該感光導電材料於該承載基板之該表面上；以及烘烤固化該感光導電材料。
  8. 如請求項7所述之半導體封裝方法，其中曝光該感光導電材料的步驟包括利用紫外光或X光進行曝光。
  9. 一種半導體封裝方法，包括：提供一承載基板，該承載基板具有一第一表面、相對之一第二表面及至少一貫孔；形成一感光導電材料於該承載基板之該第一表面上；曝光該感光導電材料，使得該感光導電材料形成一感光導電層，包含至少一導電區域及至少一絕緣區域，且該貫孔對應並連接該導電區域；配置一晶片於該感光導電層上； 將該晶片與該些導電區域電性連接；以及形成一封裝材料，覆蓋該晶片及該感光導電層。
  10. 如請求項9所述之半導體封裝方法，其中於形成該封裝材料之後，更包括形成至少一外接端子於該承載基板之該第二表面上，該至少一外接端子電性連接該導電區域。
  11. 如請求項9所述之半導體封裝方法，其中形成該感光導電材料的步驟更包括：塗佈該感光導電材料於該承載基板之該第一表面上；以及烘烤固化該感光導電材料。
  12. 如請求項9所述之半導體封裝方法，其中曝光該感光導電材料的步驟包括利用紫外光或X光進行曝光。
  13. 如請求項11所述之半導體封裝方法，其中塗佈該感光導電材料於該承載基板之該第一表面上時，該感光導電材料同時填充於該貫孔中，且該導電區域包含該貫孔中的該感光導電材料。
  14. 如請求項9所述之半導體封裝方法，其中提供該承載基板步驟中，該貫孔中已填入一導電材料。
  15. 如請求項10所述之半導體封裝方法，其中形成該外接端子於該承載基板之該第二表面上更包括填充一導電材料於該貫孔中。
  16. 一種半導體封裝，包括：一承載基板，具有一第一表面及相對之一第二表面；一感光導電層配置於該承載基板之該第一表面上，該感光導電層包含至少一導電區域及至少一絕緣區域； 一晶片配置於該感光導電層上，並與該至少一導電區域電性連接；一封裝材料，覆蓋該晶片及該感光導電層；以及至少一導電貫孔，配置於該承載基板中，並電性連接該導電區域。
  17. 如請求項16所述的半導體封裝，更包括至少一外接端子，配置於該承載基板之該第二表面上，且電性連接該導電貫孔。
  18. 如請求項16所述的半導體封裝，其中該導電區域係藉由以紫外光或X光照射該感光導電材料而形成。
  19. 一種半導體封裝，包括：一感光導電層，包含至少一導電區域及至少一絕緣區域；一晶片配置於該感光導電層上，並與該至少一導電區域電性連接；以及一封裝材料，覆蓋該晶片及該感光導電層。
  20. 如請求項19所述的半導體封裝，更包括至少一外接端子，電性連接該導電區域。
  21. 如請求項19所述的半導體封裝，其中該導電區域係藉由以紫外光或X光照射該感光導電材料而形成。
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