CN206584922U - 预包封无导线可电镀引线框架封装结构 - Google Patents

预包封无导线可电镀引线框架封装结构 Download PDF

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CN206584922U
CN206584922U CN201720298246.0U CN201720298246U CN206584922U CN 206584922 U CN206584922 U CN 206584922U CN 201720298246 U CN201720298246 U CN 201720298246U CN 206584922 U CN206584922 U CN 206584922U
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copper
metallic circuit
circuit layer
wire
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陈灵芝
徐杰
邹建安
郁科锋
刘凯
邹晓春
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Jiangyin Xinzhilian Electronics Technology Co ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49579Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582Metallic layers on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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Abstract

本实用新型涉及一种预包封无导线可电镀引线框架封装结构,它包括金属线路层(1),所述金属线路层(1)背面设置有金属引脚层(2),所述金属线路层(1)和金属引脚层(2)外围包封有第一塑封料(3),所述金属引脚层(2)背面设置有蚀刻凹槽(4),所述金属线路层(1)正面设置有预镀铜层(5),所述预镀铜层(5)正面设置有表面处理电镀层(6),所述表面处理电镀层(6)上贴装有芯片(7),所述预镀铜层(5)、表面处理电镀层(6)和芯片(7)外围包封有第二塑封料(8)。本实用新型以整面预镀的铜材为基材,对金属线路层表面所需处理电镀区域进行电镀,电镀完成后再蚀刻掉多余的预镀铜材,从而实现无导线可电镀的结构,增加引线框架的高密度、高可靠性及优秀的性能。

Description

预包封无导线可电镀引线框架封装结构
技术领域
本实用新型涉及一种预包封无导线可电镀引线框架封装结构,属于半导体封装技术领域。
背景技术
当前引线框架产品结构工艺主要有:
一、冲压法:一般采用高精度带材经自动化程度很高的高速冲床冲制而成,得到许多具有独立功能的单颗产品(如SOT、SOP等低密度产品),所有单颗产品通过导电线与边筋连接成一个整体,在单颗产品所需区域电镀NiAu、Ag、NiPtAu等,封装完成后切成单颗,导电线可以冲切掉。
二、蚀刻法:采用掩膜曝光、显影、蚀刻等工艺对金属载板进行蚀刻,得到许多具有独立功能的单颗产品(如QFN、DFN等高密度产品),所有单颗产品通过导电线与边筋连接成一个整体,如图16所示,在单颗产品所需区域电镀NiAu、Ag、NiPtAu等;封装完成后切成单颗,导电线无法去除。
当前引线框架制作(如QFN)工艺存在以下不足和缺陷:
1、随着封装产品小型化、超薄化、高密度的要求不断提高,对引线框架或者基板制作要求也小型化、超薄化、高密度,受电镀导线的布线限制,产品的布线能力无法做到小型化、超薄化、高密度;
2、采用导电线可电镀引线框架,增加了单位面积的布线数量,导线会增加高频信号对外的发射及相互间的耦合,增加信号的损耗,相互干扰和寄生耦合,制约高频产品的性能;
3、采用导电线可电镀引线框架,导电线的存在增加了与绝缘材料的接触面积,在后续使用过程中增加了铜与绝缘材料分层的风险,导致产品失效;
4、采用导电线可电镀引线框架,产品切割后会在侧面露出所电镀的导电线,在切割过程中导电线与绝缘材料间因机械应力,易出现分层,进而降低产品的可靠性等级,影响产品的寿命;
5、采用导电线可电镀引线框架,因增加了铜的含量,易导致铜与绝缘材料之间不匹配,影响产品的翘曲,影响后续封装的作业性。
实用新型内容
本实用新型所要解决的技术问题是针对上述现有技术提供一种预包封无导线可电镀引线框架封装结构,它以整面预镀的铜材为基材,对金属线路层表面所需处理电镀区域进行电镀,电镀完成后再蚀刻掉多余的预镀铜材,从而实现无导线可电镀的结构,增加引线框架的高密度、高可靠性及优秀的性能。
本实用新型解决上述问题所采用的技术方案为:一种预包封无导线可电镀引线框架封装结构,它包括金属线路层,所述金属线路层背面设置有金属引脚层,所述金属线路层和金属引脚层外围包封有第一塑封料,所述金属引脚层背面设置有蚀刻凹槽,所述金属线路层正面设置有预镀铜层,所述预镀铜层正面设置有表面处理电镀层,所述表面处理电镀层上贴装有芯片,所述预镀铜层、表面处理电镀层和芯片外围包封有第二塑封料。
与现有技术相比,本实用新型的优点在于:
1、本实用新型采用在整面预镀铜层的基材载板上电镀线路层,无需设计导电线,增加了布线的空间,可以做到更高的密度,更薄的厚度,实现高集成的电镀设计能力;
2、本实用新型因无导电线存在最终的产品内,减低了高频信号对外的发射及相互间的耦合,减少了信号的损耗,相互干扰和寄生耦合,提升高频产品的性能;
3、本实用新型取消了导电线设计,产品切割后侧面无露出的导电线,取消了导电线与绝缘材料间因机械应力,切割过程中应力小,进而提升产品的可靠性等级,延长产品的寿命;
4、本实用新型无导电线设计,铜的比率降低,产品的翘曲会更加的小,降低后段封装过程的难度。
附图说明
图1~图13为本实用新型一种预包封无导线可电镀引线框架封装结构制造方法的各工序流程示意图。
图14为本实用新型一种预包封无导线可电镀引线框架封装结构的示意图。
图15为本实用新型一种预包封无导线可电镀引线框架封装结构另一实施例的结构示意图。
图16为现有采用蚀刻法得到的单颗产品通过导电线与边筋连接成一个整体的示意图。
其中:
金属线路层1
金属引脚层2
第一塑封料3
蚀刻凹槽4
预镀铜层5
表面处理电镀层6
芯片7
第二塑封料 8
导电线9
边筋10。
具体实施方式
以下结合附图实施例对本实用新型作进一步详细描述。
参见图14、15,本实施例中的一种预包封无导线可电镀引线框架封装结构,它包括金属线路层1,所述金属线路层1背面设置有金属引脚层2,所述金属线路层1和金属引脚层2外围包封有第一塑封料3,所述金属引脚层2背面设置有蚀刻凹槽4,所述金属线路层1正面设置有预镀铜层5,所述预镀铜层5正面设置有表面处理电镀层6,所述表面处理电镀层6上贴装有芯片7,所述预镀铜层5、表面处理电镀层6和芯片7外围包封有第二塑封料8;
所述芯片7的贴装方式采用正装或倒装。
其制造方法包括如下步骤:
步骤一、取一基材载板;
参见图1,取一片厚度合适的基材载板,基材载板的材质可以依据设计的功能与特性进行变换,例如:铜材、铁材、镍铁材或锌铁材等;
步骤二、基材载板表面预镀铜层
参见图2,在基材载板表面电镀一层铜层,目的是为后续电镀作基础,所述电镀的方式可以采用化学镀或是电解电镀;
步骤三、电镀金属线路层
参见图3,在完成预镀铜材的基材载板表面通过电镀形成所需的金属线路层;
步骤四、电镀金属引脚层
参见图4,在金属线路层的表面通过电镀形成所需的金属引脚层;
步骤五、填充绝缘材料
参见图5,利用压膜、包封、印刷等工艺在金属线路层及金属引脚层外围填充绝缘材料,对金属线路层及金属引脚层形成绝缘保护;
步骤六、去除基材载板
参见图6,通过蚀刻、peeling等方式去除基材载板,保留基材载板正面的预镀铜层;
步骤七、形成金属引脚层深度
参见图7,通过蚀刻等方式使金属引脚层具有一定的深度;
步骤八、形成表面处理电镀层
参见图8,在去除基材载板后保留的预镀铜层表面通过化学沉铜或电镀的方式形成一层薄的表面处理电镀层;
步骤九、去除预镀铜层
参见图9,通过蚀刻等方式去除无表面处理电镀层处的预镀铜层,露出金属线路层;
步骤十、装片
参加图10,在装芯片区域装芯片,芯片可以是正装,也可以倒装;
步骤十一、打线
参见图11,正装芯片的产品进行打线,使芯片与框架进行导通,满足电性能要求,倒装芯片不需要打线;
步骤十二、包封
参见图12,对芯片外围进行包封,对芯片进行保护;
步骤十三、切割成型
参加图13,切割成单颗具有独立电性能的产品。
除上述实施例外,本实用新型还包括有其他实施方式,凡采用等同变换或者等效替换方式形成的技术方案,均应落入本实用新型权利要求的保护范围之内。

Claims (1)

1.一种预包封无导线可电镀引线框架封装结构,其特征在于:它包括金属线路层(1),所述金属线路层(1)背面设置有金属引脚层(2),所述金属线路层(1)和金属引脚层(2)外围包封有第一塑封料(3),所述金属引脚层(2)背面设置有蚀刻凹槽(4),所述金属线路层(1)正面设置有预镀铜层(5),所述预镀铜层(5)正面设置有表面处理电镀层(6),所述表面处理电镀层(6)上贴装有芯片(7),所述预镀铜层(5)、表面处理电镀层(6)和芯片(7)外围包封有第二塑封料(8)。
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