CN106684050A - 一种金属柱导通埋芯片线路板结构及其工艺方法 - Google Patents
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Abstract
本发明涉及一种金属柱导通埋芯片线路板结构及其工艺方法,所述结构包括金属板(1),所述金属板(1)包括镂空区域(2)和金属柱(3),所述镂空区域(2)内设置有芯片(5),所述芯片(5)周围填充有塑封料(4),所述金属柱(3)与芯片(5)的焊垫(6)之间设置有第一导电层(8),所述金属柱(3)背面设置有第二导电层(9),所述第一导电层(8)和第二导电层(9)上设置有线路层(10),所述线路层(10)上设置有抗氧化金属层(11),所述金属板(1)正面和背面包覆有第二绝缘材料(12)。本发明不使用制作繁琐的基板,直接使用金属板冲切或者蚀刻形成金属柱板,以便后续电性导通,制作周期较短,且金属柱板材制作成本低,生产效率高。
Description
技术领域
本发明涉及一种金属柱导通埋芯片线路板结构及其工艺方法,属于半导体封装技术领域。
背景技术
常规的基板埋芯片的结构都是在具有开口的基板内埋入芯片,然后进行芯片的电性连接,一般使用制作完整的基板进行制程,首先基板的制作流程相对复杂,需花费周期较长,成本相对比较高,而且基板内的层数多,层间材料比较复杂,各类材料的热膨胀系数和收缩率不同,所以基板会翘曲变形,使得后续制程有影响。
发明内容
本发明所要解决的技术问题是针对上述现有技术提供一种金属柱导通埋芯片线路板结构及其工艺方法,它不使用制作繁琐的基板,直接使用金属板冲切或者蚀刻形成金属柱板,以便后续电性导通,制作周期较短,且金属柱板材制作成本低,生产效率高。
本发明解决上述问题所采用的技术方案为:一种金属柱导通埋芯片线路板结构,它包括金属板,所述金属板中间形成镂空区域,所述镂空区域周围形成一圈或多圈金属柱,所述镂空区域内设置有芯片,所述芯片周围填充有塑封料,所述塑封料正面和芯片正面均与金属板正面齐平,所述塑封料背面与金属板背面齐平,所述芯片正面设置有焊垫,所述芯片周围以及芯片上除焊垫以外的区域涂覆有第一绝缘材料,所述金属柱正面与芯片的焊垫之间通过第一导电层相连接,所述金属柱背面设置有第二导电层,所述第一导电层和第二导电层上均设置有线路层,所述线路层上设置有抗氧化金属层,所述金属板正面和背面均包覆有第二绝缘材料,所述抗氧化金属层露出于第二绝缘材料表面。
一种金属柱导通埋芯片线路板结构的工艺方法,它包括以下步骤:
步骤一、取一片金属板;
步骤二、采用冲切或蚀刻工艺将金属板形成中间镂空、周围有一圈或多圈金属柱的金属柱板;
步骤三、将金属柱板通过粘性材料放置于载板上;
步骤四、将芯片放置于金属柱板的镂空区域,贴合在载板上的粘性材料上;
步骤五、对金属柱板利用环氧树脂材料进行塑封保护;
步骤六、进行环氧树脂表面研磨,露出金属柱表面;
步骤七、去除载板和粘性材料;
步骤八、在露出的芯片表面涂覆绝缘材料,露出焊垫部分;
步骤九、在线路板上下表面进行选择性的线路层电镀,将芯片焊垫部分通过电镀层电性连接;
步骤十、将线路板上下表面选择性的涂覆绝缘材料,暴露出后续需要电性连接的区域;
步骤十一、在步骤十暴露出的后续需要电性连接的区域进行抗氧化金属层电镀。
所述金属柱板可根据需要设计不同的形状和线路。
所述塑封方式采用模具灌胶方式、喷涂设备喷涂方式、贴膜方式或是刷胶的方式。
所述抗氧化金属层材料为金、镍金、镍钯金或锡。
与现有技术相比,本发明的优点在于:
1、本发明不使用制作繁琐的基板,可使用金属板冲切或者蚀刻形成金属柱板,后续可以在金属柱板上下表面继续制作所需线路层,且金属柱板材制作成本低,制作周期较短,生产效率高;
2、本发明的金属柱板材料简单,具有极佳的平整度,方便后续制程,且可以对上下表面的线路进行灵活性的设计,适用范围较广;
3、本发明可以根据系统或功能需要在需要的位置或是区域埋入主动/被动元器件以及其他需要的芯片,以提升基板的集成度,从而可以降低整个封装体的尺寸。
附图说明
图1为本发明一种金属柱导通埋芯片线路板结构的示意图。
图2~图16为本发明一种金属柱导通埋芯片线路板结构工艺方法的各工序示意图。
其中:
金属板1
镂空区域2
金属柱3
塑封料4
芯片5
焊垫6
第一绝缘材料7
第一导电层8
第二导电层9
线路层10
抗氧化金属层11
第二绝缘材料12。
具体实施方式
以下结合附图实施例对本发明作进一步详细描述。
参见图1,本实施例中的一种金属柱导通埋芯片线路板结构,它包括金属板1,所述金属板1中间采用冲切或蚀刻方式形成镂空区域2,所述镂空区域2周围形成一圈或多圈金属柱3,所述镂空区域2内设置有芯片5,所述芯片5周围填充有塑封料4,所述塑封料4正面和芯片5正面均与金属板1正面齐平,所述塑封料4背面与金属板1背面齐平,所述芯片5正面设置有焊垫6,所述芯片5周围以及芯片5上除焊垫6以外的区域涂覆有第一绝缘材料7,所述金属柱3正面与芯片5的焊垫6之间通过第一导电层8相连接,所述金属柱3背面设置有第二导电层9,所述第一导电层8和第二导电层9上均设置有线路层10,所述线路层10上设置有抗氧化金属层11,所述金属板1正面和背面均包覆有第二绝缘材料12,所述抗氧化金属层11露出于第二绝缘材料12表面。
其工艺方法包括如下步骤:
步骤一、参见图2,取一片厚度合适的金属板;
步骤二、参见图3,采用冲切或蚀刻工艺将金属板形成中间镂空、周围有一圈或多圈金属柱的金属柱板,中间镂空的部分用于后续工序中置入所需功能芯片,周围的金属柱用于上下表面的电性连接;
步骤三、参见图4,将金属柱板通过粘性材料放置于载板上,以增强金属柱板的强度,以便后续制程;
步骤四、参见图5,将芯片放置于金属柱板的镂空区域,贴合在载板上的粘性材料上;
步骤五、参见图6,对金属柱板利用环氧树脂材料进行塑封保护,环氧树脂材料可以依据产品特性选择有填料或者没有填料的种类,塑封方式可以采用模具灌胶方式、喷涂设备喷涂方式、贴膜方式或是刷胶的方式;
步骤六、参见图7,进行环氧树脂表面研磨,露出金属柱表面;
步骤七、参见图8,去除载板和粘性材料;
步骤八、参见图9,在露出芯片周围及其表面需要的地方涂覆绝缘材料,露出焊垫部分以便后续的电性连接;
步骤九、参见图10,在线路板上下表面通过化学镀的方式制备一层导电层;
步骤十、参见图11,在线路板上下表面贴覆感光膜,通过曝光显影暴露出后续需要电镀的区域;
步骤十一、参见图12,在线路板上下表面暴露出的电镀区域进行线路层电镀;
步骤十二、参见图13,去除感光膜;
步骤十三、参见图14,微蚀去除线路板上下表面多余露出的导电层;
步骤十四、参见图15,将线路板上下表面选择性的涂覆绝缘材料,暴露出后续需要电性连接的区域;
步骤十五、参见图16,在步骤十四暴露出的后续需要电性连接的区域进行抗氧化金属层电镀,如如金、镍金、镍钯金、锡等。
除上述实施例外,本发明还包括有其他实施方式,凡采用等同变换或者等效替换方式形成的技术方案,均应落入本发明权利要求的保护范围之内。
Claims (5)
1.一种金属柱导通埋芯片线路板结构,其特征在于:它包括金属板(1),所述金属板(1)中间形成镂空区域(2),所述镂空区域(2)周围形成一圈或多圈金属柱(3),所述镂空区域(2)内设置有芯片(5),所述芯片(5)周围填充有塑封料(4),所述塑封料(4)正面和芯片(5)正面均与金属板(1)正面齐平,所述塑封料(4)背面与金属板(1)背面齐平,所述芯片(5)正面设置有焊垫(6),所述芯片(5)周围以及芯片(5)上除焊垫(6)以外的区域涂覆有第一绝缘材料(7),所述金属柱(3)正面与芯片(5)的焊垫(6)之间通过第一导电层(8)相连接,所述金属柱(3)背面设置有第二导电层(9),所述第一导电层(8)和第二导电层(9)上均设置有线路层(10),所述线路层(10)上设置有抗氧化金属层(11),所述金属板(1)正面和背面均包覆有第二绝缘材料(12),所述抗氧化金属层(11)露出于第二绝缘材料(12)表面。
2.一种金属柱导通埋芯片线路板结构的工艺方法,其特征在于所述方法包括以下步骤:
步骤一、取一片金属板;
步骤二、采用冲切或蚀刻工艺将金属板形成中间镂空、周围有一圈或多圈金属柱的金属柱板;
步骤三、将金属柱板通过粘性材料放置于载板上;
步骤四、将芯片放置于金属柱板的镂空区域,贴合在载板上的粘性材料上;
步骤五、对金属柱板利用环氧树脂材料进行塑封保护;
步骤六、进行环氧树脂表面研磨,露出金属柱表面;
步骤七、去除载板和粘性材料;
步骤八、在露出的芯片周围及其表面需要的地方涂覆绝缘材料;
步骤九、在线路板上下表面进行线路层电镀,将芯片焊垫部分通过电镀层电性连接;
步骤十、将线路板上下表面选择性的涂覆绝缘材料,暴露出后续需要电性连接的区域;
步骤十一、在步骤十暴露出的后续需要电性连接的区域进行抗氧化金属层电镀。
3.根据权利要求2所述的一种金属柱导通埋芯片线路板结构的工艺方法,其特征在于:所述金属柱板可根据需要设计不同的形状和线路。
4.根据权利要求2所述的一种金属柱导通埋芯片线路板结构的工艺方法,其特征在于:所述塑封方式采用模具灌胶方式、喷涂设备喷涂方式、贴膜方式或是刷胶的方式。
5.根据权利要求2所述的一种金属柱导通埋芯片线路板结构的工艺方法,其特征在于:所述抗氧化金属层材料为金、镍金、镍钯金或锡。
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111739810A (zh) * | 2020-06-22 | 2020-10-02 | 矽磐微电子(重庆)有限公司 | 半导体封装方法及半导体装置 |
CN111883441A (zh) * | 2020-07-31 | 2020-11-03 | 矽磐微电子(重庆)有限公司 | 半导体封装方法及半导体封装结构 |
CN113594052A (zh) * | 2021-07-29 | 2021-11-02 | 矽磐微电子(重庆)有限公司 | 半导体封装方法 |
WO2024016525A1 (zh) * | 2022-07-21 | 2024-01-25 | 深南电路股份有限公司 | 底部封装体及其制作方法以及堆叠封装结构及其制作方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1524293A (zh) * | 2000-10-19 | 2004-08-25 | ض� | 具有集成器件的微电子衬底 |
US20130252380A1 (en) * | 2009-09-08 | 2013-09-26 | Unimicron Technology Corporation | Method for fabricating packaging structure having embedded semiconductor element |
CN103730425A (zh) * | 2013-09-12 | 2014-04-16 | 太阳诱电株式会社 | 部件内置基板 |
-
2017
- 2017-01-25 CN CN201710056086.3A patent/CN106684050A/zh active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1524293A (zh) * | 2000-10-19 | 2004-08-25 | ض� | 具有集成器件的微电子衬底 |
US20130252380A1 (en) * | 2009-09-08 | 2013-09-26 | Unimicron Technology Corporation | Method for fabricating packaging structure having embedded semiconductor element |
CN103730425A (zh) * | 2013-09-12 | 2014-04-16 | 太阳诱电株式会社 | 部件内置基板 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111739810A (zh) * | 2020-06-22 | 2020-10-02 | 矽磐微电子(重庆)有限公司 | 半导体封装方法及半导体装置 |
CN111883441A (zh) * | 2020-07-31 | 2020-11-03 | 矽磐微电子(重庆)有限公司 | 半导体封装方法及半导体封装结构 |
CN113594052A (zh) * | 2021-07-29 | 2021-11-02 | 矽磐微电子(重庆)有限公司 | 半导体封装方法 |
CN113594052B (zh) * | 2021-07-29 | 2024-02-27 | 矽磐微电子(重庆)有限公司 | 半导体封装方法 |
WO2024016525A1 (zh) * | 2022-07-21 | 2024-01-25 | 深南电路股份有限公司 | 底部封装体及其制作方法以及堆叠封装结构及其制作方法 |
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