WO2024016525A1 - 底部封装体及其制作方法以及堆叠封装结构及其制作方法 - Google Patents

底部封装体及其制作方法以及堆叠封装结构及其制作方法 Download PDF

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Publication number
WO2024016525A1
WO2024016525A1 PCT/CN2022/131396 CN2022131396W WO2024016525A1 WO 2024016525 A1 WO2024016525 A1 WO 2024016525A1 CN 2022131396 W CN2022131396 W CN 2022131396W WO 2024016525 A1 WO2024016525 A1 WO 2024016525A1
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organic resin
chip
resin core
core board
pad side
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PCT/CN2022/131396
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English (en)
French (fr)
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朱凯
黄立湘
缪桦
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深南电路股份有限公司
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Publication of WO2024016525A1 publication Critical patent/WO2024016525A1/zh

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Definitions

  • the present application relates to the field of semiconductor packaging, and in particular to a bottom package and a manufacturing method thereof, as well as a stacked packaging structure and a manufacturing method thereof.
  • PoP package on package
  • the main idea is to stack and package (or flip) a memory chip on top of a logic chip. Of course, it can also be further implemented on the logic chip. Top mounted passive components.
  • the first type of method is based on traditional packaging technology, that is, after the chip is plastic-sealed on the packaging substrate, it is used as the bottom package, and then holes are drilled in the plastic layer of the bottom package, and interconnection is achieved by filling the holes with conductive paste, and then in The top of the bottom package is flipped onto the packaged top package.
  • the biggest disadvantage of this solution is the large size of laser openings or solder balls, so the density of the three-dimensional interconnection structure is low.
  • the second type of method is based on advanced packaging technology.
  • a seed layer is made on a temporary carrier, and then dry film is electroplated to form copper pillars, and the seed layer is etched. This results in a three-dimensional interconnection structure for further chip mounting.
  • the chip is molded and polished to expose the copper pillars, thus obtaining a three-dimensional interconnection structure.
  • the advantage of this solution is the high density of the three-dimensional interconnection structure, but the production cost is also high.
  • the chip is molded, the flow distance of the plastic molding material is relatively large, which has a negative impact on the placement accuracy of the chip.
  • the modulus of the plastic molding material is not high, this solution will be difficult to transport for large sizes such as board-level packaging. That is, there is a risk of sample fragmentation after the temporary carrier is removed.
  • the third type of method is also based on advanced packaging technology.
  • through holes are processed on an organic resin core board for printed circuit boards, then electroplating is used to interconnect both sides of the organic resin core board, and then through slots are processed at designated positions.
  • tape is applied in sequence, and the chip is attached to the tape in the through slot, and finally the chip is plastic-sealed, thus obtaining a three-dimensional interconnection structure.
  • the biggest advantage of this solution is its low cost, the limitation of the through-slot, and the short flow distance of the plastic molding material, which can reduce the impact on the chip position accuracy.
  • Another advantage is that the organic resin core board is reinforced with fiberglass cloth, so it has a larger modulus, is less difficult to transport during processing, and has strong resistance to warping.
  • the thermal expansion coefficient of the tape is larger than that of the organic resin core board and plastic packaging material.
  • This mismatch in thermal expansion coefficient leads to a very large position deviation of the chip during the plastic packaging process, and the heating may be uneven. Therefore, it is difficult to completely avoid irregular chip deflection through pre-compensation for differences in thermal expansion coefficients. Since the flatness of the organic resin core board is worse than that of a special temporary carrier such as glass, the fineness of its surface lines is also affected.
  • a bottom package and its manufacturing method as well as a stacked packaging structure and its manufacturing method are provided to solve the problems of low density, high manufacturing cost, and low precision of circuits on the chip surface of the three-dimensional interconnection structure in the existing technology.
  • An embodiment of the present application provides a method for manufacturing a bottom package.
  • the method includes:
  • the preset chip in the through slot is plastic-sealed from the pad side of the preset chip, and the pad side of the molded organic resin core board is ground to expose the pad of the preset chip;
  • a first connection line is formed on the pad side of the ground organic resin core board
  • the hard temporary carrier is released, and a second connection line is formed on the non-pad side of the preset chip to form the bottom package.
  • the manufacturing method of the bottom package provided by this application uses an organic resin core board to assist in chip molding. It can not only make interconnected metal pillars at low cost and high yield, but also improve the mechanical strength of the chip molding layer. It is especially suitable for large-size advanced packaging. , it can also reduce the amount of plastic packaging material and reduce the material cost of plastic packaging.
  • the use of organic resin core boards to assist chip molding can improve the anti-warping ability of the package, which is beneficial to realizing larger-sized packages and improving the integration of packaged products.
  • Using a hard temporary carrier to assist in molding the chip Specifically, choosing a hard temporary carrier with a small thermal expansion coefficient and isotropy can significantly improve the predictability of chip position deviation during chip molding and the position accuracy after chip molding.
  • An embodiment of the present application provides a method for manufacturing a stacked packaging structure.
  • the method includes:
  • the preset chip in the through slot is plastic-sealed from the pad side of the preset chip, and the pad side of the molded organic resin core board is ground to expose the pad of the preset chip;
  • a first connection line is formed on the pad side of the ground organic resin core board
  • One side of the bottom package is soldered to the printed circuit board, and the top package is mounted on the other side of the bottom package.
  • the manufacturing method of the stacked packaging structure Compared with conventional stacked packaging technology, the manufacturing method of the stacked packaging structure provided by this application has the advantages of fine circuits, small chip drift, and good predictability.
  • the use of organic resin core boards to produce three-dimensional interconnect structures has the advantages of low production cost, short plastic flow distance, low difficulty in processing and transportation, and good warpage resistance, thereby avoiding the shortcomings of conventional stacked packaging solutions.
  • An embodiment of the present application provides a bottom package, which includes:
  • An organic resin core plate of organic resin material the organic resin core plate has a through hole, and interconnecting metal pillars are electroplated in the through hole;
  • a first connection line is formed on the pad side of the organic resin core board; a second connection line is formed on the non-pad side of the organic resin core board.
  • the chip is embedded in an organic resin core board, and the three-dimensional interconnection structure is made of the organic resin core board. Therefore, the three-dimensional interconnection structure has high density, high efficiency, and low cost.
  • the organic resin in the core board structure has the characteristics of short flow distance, which is beneficial to improving the chip placement accuracy.
  • the bottom package has fine lines, which also avoids the problem of large chip drift, and the packaging structure density is also higher.
  • the embodiment of the present application provides a stacked packaging structure.
  • the stacked packaging structure includes:
  • An organic resin core board of organic resin material the organic resin core board has a through hole, and interconnecting metal pillars are electroplated in the through hole; a through groove is opened on the organic resin core board, and a plastic seal is formed in the through hole.
  • the top package includes: a top package chip and a passive component;
  • the bottom package is installed on the printed circuit board through the second connection line or the first connection line, and the top package chip and the passive component in the top package are installed on the bottom package. on the first connection line or the second connection line.
  • the stacked packaging structure Compared with conventional stacked packaging structures, the stacked packaging structure provided by this application has the advantages of fine lines, small chip drift, and good predictability.
  • the use of organic resin core boards to produce three-dimensional interconnect structures has the advantages of low production cost, short plastic flow distance, low difficulty in processing and transportation, and good warpage resistance, thereby avoiding the shortcomings of conventional stacked packaging solutions.
  • Figure 1 is a flow chart of a method for manufacturing a bottom package provided by an embodiment of the present application
  • Figure 2 is a flow chart of a method for manufacturing a stacked packaging structure provided by an embodiment of the present application
  • Figure 3-1 is a schematic diagram of processing through holes on a core plate according to an embodiment of the present application.
  • Figure 3-2 is a schematic diagram of through-hole plating on a core plate provided by an embodiment of the present application.
  • Figure 3-3 is a schematic diagram of processing a through slot on a core plate according to an embodiment of the present application
  • Figure 3-4 is a schematic diagram of pasting adhesive glue on the core board according to an embodiment of the present application.
  • Figure 3-5 is a schematic diagram after removing the adhesive glue in the through groove on the core board according to an embodiment of the present application
  • Figures 3-6 are schematic diagrams of attaching a hard temporary carrier to a core board through adhesive glue according to an embodiment of the present application
  • Figure 3-7 is a schematic diagram of pasting a preset chip in a slot on a hard temporary carrier according to an embodiment of the present application
  • Figure 3-8 is a schematic diagram of plastically sealing a preset chip in a through slot according to an embodiment of the present application
  • Figure 3-9 is a schematic diagram of grinding the preset chip plastic packaging layer according to an embodiment of the present application.
  • Figure 3-10 is a schematic diagram of forming a first connection line on the surface of the core board according to an embodiment of the present application
  • Figure 3-11 is a schematic diagram of removing the hard temporary carrier and grinding the side of the core plate with the hard temporary carrier removed according to an embodiment of the present application;
  • Figure 3-12 is a schematic diagram of the connection pad produced on the non-pad side of the core board provided by an embodiment of the present application;
  • Figure 3-13 is a schematic diagram of making a second connection line on the non-pad side of the core board provided by an embodiment of the present application;
  • Figure 3-14 is a schematic diagram of ball planting of the first connection line provided by an embodiment of the present application.
  • Figure 3-15 is a schematic diagram of the bottom package provided by an embodiment of the present application being welded to a printed circuit board;
  • Figure 3-16 is a schematic diagram of a bottom package mounted on a top package provided by an embodiment of the present application.
  • Figure 4-1 is a schematic diagram of ball planting of the second connection line provided by another embodiment of the present application.
  • Figure 4-2 is a schematic diagram of the bottom package provided by another embodiment of the present application being welded to a printed circuit board;
  • Figure 4-3 is a schematic diagram of a bottom package mounted on a top package provided by another embodiment of the present application.
  • Figure 5 is a schematic diagram of a stacked packaging structure provided by an embodiment of the present application.
  • Figure 6 is a schematic diagram of a stacked packaging structure provided by another embodiment of the present application.
  • 1 is the organic resin core board
  • 2 is the through hole
  • 3 is the interconnecting metal column
  • 4 is the through groove
  • 5 is the adhesive glue
  • 6 is the hard temporary carrier
  • 7 is the chip
  • 8 is the plastic sealing material
  • 9 is Connection pad
  • 10 is the first connection line
  • 11 is the second connection line
  • 12 is BGA solder ball
  • 13 is printed circuit board
  • 14 is passive component
  • 15 is top package chip
  • 16 is chip attach film
  • 17 is The top package body
  • 18 is the bottom package body
  • 19 is the printed circuit board.
  • FIG. 1 is a flow chart of a method for manufacturing a bottom package provided by an embodiment of the present application.
  • the method includes:
  • the organic resin core board 1 can be an organic resin core board 1 with a surface covered with copper foil.
  • the organic resin core board 1 needs to be made Through-holes 2 are processed at preset positions of the interconnection metal posts 3 .
  • the method of processing the through hole 2 on the organic resin core board 1 can be to use a mechanical drill to drill the through hole 2 on the organic resin core board 1 , or to use a laser to process the through hole 2 on the organic resin core board 1 .
  • Electroplating is performed by electroplating the upper and lower surfaces of the organic resin core board 1 and the through holes 2.
  • the electroplating material can be metallic copper.
  • the electroplating method is: using sputtering, evaporation or chemical copper plating, adsorption of conductive substances and other methods in the existing technology.
  • the through-hole walls are covered with a conductive seed layer, and then electroplating is used to fill the through-holes 2 of the organic resin core board 1 with metal, that is, copper, to form interconnected metal pillars 3, also known as three-dimensional interconnect structures.
  • a through groove 4 is processed at the position where the preset chip needs to be buried in the organic resin core board 1, and the size of the through groove 4 is larger than the size of the preset chip.
  • the space of the through slot 4 can accommodate one preset chip or two or more preset chips.
  • the method of processing the through groove 4 on the organic resin core board 1 may be to use a laser to process the organic resin core board 1 so that the organic resin core board 1 exposes the through groove 4; or mechanical processing may be used to make the organic resin core board 1 Expose slot 4.
  • fixing the organic resin core board 1 after processing the through groove 4 on the hard temporary carrier 6 includes:
  • adhesive glue is pasted on one side of the organic resin core board 1 after processing the through groove 4;
  • the adhesive may be a double-sided adhesive, with one side used to adhere to one side of the organic resin core board 1 and the other side used to adhere to the hard temporary carrier 6 .
  • the function of the adhesive is to better fix the organic resin core board on the hard temporary carrier 6 .
  • the hard temporary carrier 6 can be one of a glass carrier, a stainless steel carrier or a silicon wafer carrier. When a silicon wafer is used as the hard temporary carrier 6, the hard temporary carrier 6 must be circular. When glass or stainless steel is used as the hard temporary carrier 6, the hard temporary carrier 6 can be circular or square.
  • the number of preset chips 7 that can be accommodated in the slot above the hard temporary carrier 6 is not limited, and can be one, two or more.
  • placing the preset chip 7 in the slot above the hard temporary carrier 6, and keeping the pad side of the preset chip 7 away from the hard temporary carrier specifically includes:
  • the preset chip is attached to the through groove 4 above the hard temporary carrier 6 through the chip attachment film 16 .
  • the chip attach film 16 is used on the non-pad side of the preset chip 7 to replace the original tape, and the preset chip 7 is mounted on a hard temporary carrier 6 with good thermal expansion coefficient matching and good uniformity, thus avoiding the original tape.
  • the preset chip 7 drifts significantly due to the large difference in thermal expansion coefficient of the tapes.
  • the fixing effect of the chip attach film using the resin curing fixation method is better than that of the tape whose viscosity is greatly affected by temperature. good.
  • a release layer is provided on the side of the hard temporary carrier 6 close to the organic resin core board 1, and the adhesive glue and the chip attach film are attached to the release layer.
  • the release layer can be a photosensitive debonding release layer or a heat-sensitive debonding release layer, preferably a photosensitive debonding release layer.
  • the release layer is provided to facilitate the peeling of the organic resin core board 1 and the chip attach film 16 from the hard temporary carrier.
  • the release layer can ensure that the adhesive glue and the cured chip attach film 16 are peeled off from the hard temporary carrier. The huge stress during peeling will not cause the hard temporary carrier to break, adhesive residue, chip attach film to break, etc.
  • S104 Molding the preset chip in the through groove from the pad side of the preset chip, and grinding the pad side of the plastic-sealed organic resin core board to expose the pad of the preset chip.
  • the pad side in this article refers to the pad side of the preset chip
  • the non-pad side in this article also refers to the non-pad side of the preset chip
  • the preset chip 7 in the through slot 4 is plastic-sealed from the pad side of the preset chip 7 by filling the plastic compound 8 between the through-slot wall of the organic resin core board 1 and the preset chip 7 gap and covers the upper surface of the organic resin core board 1 .
  • the plastic sealant 8 also needs to fill the gaps between the preset chips 7 .
  • Plastic sealant 8 also known as epoxy sealant, is a packaging material for electronic components. It is made of epoxy resin and phenolic resin as the base resin, silica powder as the filler, and a variety of additives. It is an existing technology.
  • the plastic sealant 8 can be granular, liquid or film type, and the sealing method can be compression molding or vacuum lamination. When vacuum lamination is used, only film-type epoxy sealant can be used.
  • the pad side of the plastic-sealed organic resin core board 1 is ground to expose the pad of the preset chip 7.
  • grinding can use mechanical grinding to grind away the plastic sealing material 8 and the metal layer on the upper surface of the pad side of the preset chip 7, so that all the metal layers on the pad side surface of the organic resin core board 1 are ground away and the preset chip is exposed. 7 surface pads. Because the surface of the hard temporary carrier has high flatness, a highly flat surface can be obtained after grinding the organic resin core board 1, which is beneficial to the production of fine circuits.
  • forming the first connection line 10 on the pad side of the ground organic resin core board 1 specifically includes:
  • the stacking method is used to produce several cyclic conductive circuits on the pad side of the predetermined chip 7, and each time the semi-additive method is used to produce the first connection circuit 10 with a preset number of layers.
  • the stacking method is used to perform several cycles on the pad side of the preset chip 7 to produce a target number of conductive circuit layers.
  • the conductive circuit layer includes conductive circuits and insulating media.
  • the semi-additive method is preferred for the production of conductive lines.
  • the photoresist material is selected according to the fineness of the conductive lines. Liquid photosensitive glue is preferred for lines below 8 ⁇ m, and dry film is preferred for lines 8 ⁇ m and above.
  • the insulating medium is selected according to the fineness of the conductive lines. Photosensitive is preferred for lines below 8 ⁇ m.
  • ABF Ajinomoto build-up film
  • glass fiber cloth-reinforced epoxy resin can be used for lines of 50 ⁇ m and above.
  • the process of making the first connection line 10 is an existing technology and will not be described in detail here.
  • the method of releasing the hard temporary carrier can be determined according to the type of release layer. It is an existing technology and will not be described again here.
  • the metal layer on the disk side surface is flush or slightly dented, that is, after the hard temporary carrier 6 is released, part of the chip attach film 16 is removed, so that the surface of the remaining chip attach film 16 is lower than or flush with the non-standard surface of the preset chip 7 .
  • forming the second connection line 11 on the non-pad side of the preset chip 7 specifically includes:
  • connection pad 9 is made at the position of the interconnection metal pillar 3 on the non-pad side surface of the organic resin core board 1 by the subtractive method; the diameter of the connection pad 9 is larger than the diameter of the interconnection metal pillar 3;
  • connection pad is made at the position of the interconnection metal pillar on the non-pad side surface of the organic resin core board by the subtractive method.
  • the subtractive method can also be directly used after the interconnection metal pillar 3 is obtained by electroplating in step S101.
  • the step of using plasma to remove part of the protruding chip attach film in the release of the hard temporary carrier in step S106 can be omitted.
  • the disadvantage is that the chip in this example is not a pad.
  • the connection pads on the side organic resin core board surface will be embedded in the adhesive glue, and the adhesive glue is directly bonded to the non-metal layer part of the organic resin core board surface. Therefore, the organic resin core board will bulge when attaching it to the hard temporary carrier.
  • the local pressure on the connection pad is greater, and the etching of the metal layer on the surface of the organic resin core board leaves a porous structure, which will increase the risk of adhesive residue when the adhesive is removed after the hard temporary carrier is debonded.
  • the adhesive residue will increase the packaging The risk of body delamination reduces the reliability of the package.
  • no connection pads may be made at the position of the interconnection metal pillars 3 on the non-pad side surface of the organic resin core board 1 to make finer circuits, thereby obtaining a higher density packaging structure.
  • the stacking method is used to fabricate the second connection line 11 with the target number of layers on the non-pad side surface of the organic resin core board 1 through several cycles.
  • the conductive circuit layer includes conductive circuits and insulating media; the semi-additive method is preferred for the production of conductive circuits, and subtractive methods can also be used. Method; choose photoresist material according to the fineness of conductive lines, and dry film is preferred for photoresist material.
  • the insulating medium is selected according to the fineness of the conductive lines.
  • the insulating medium layer is preferably ABF, and glass fiber cloth reinforced epoxy resin can also be used.
  • connection line 11 The process of forming the second connection line 11 is an existing technology and will not be described again here.
  • the method further includes the step of forming a surface treatment layer on the surface of the first connection line and the second connection line.
  • an organic resin core board is used to assist chip molding, which can not only make interconnection metal pillars at low cost and high yield, but also improve the mechanical strength of the chip molding layer, which is especially suitable for large-size applications.
  • Advanced packaging can also reduce the amount of plastic packaging materials and reduce the material cost of plastic packaging.
  • the use of organic resin core boards to assist chip molding can improve the anti-warping ability of the package, which is beneficial to realizing larger-sized packages and improving the integration of packaged products.
  • Using a hard temporary carrier to assist in molding the chip Specifically, choosing a hard temporary carrier with small thermal expansion and isotropy can significantly improve the predictability of chip position deviation during chip molding and the position accuracy after chip molding.
  • FIG. 2 it is a flow chart of a method for manufacturing a stacked packaging structure provided by an embodiment of the present application.
  • the method includes:
  • the bottom package is manufactured according to the above bottom package manufacturing method, which will not be described again.
  • balls are planted on the first connection line surface on the preset chip pad side of the bottom package to form BGA (Ball Gird Array, ball grid array package) solder balls 12, see Figure 3 -15.
  • BGA All Gird Array, ball grid array package
  • the top package chip 15 and the passive component 14 are surface mounted on the conductive circuit on the non-pad side of the chip of the bottom package. If the top package chip is flip-chip welded, glue dispensing is also required to realize the top package. Bottom padding.
  • the filler used in dispensing is non-conductive glue or capillary underfill glue.
  • the top package is flipped on the pad side of the embedded chip, see Figure 4-1, that is, balls are planted on the surface of the second connection line 11 on the non-pad side of the preset chip 7 of the bottom package, forming a BGA solder balls 12, see Figure 4-2, solder the bottom package to the printed circuit board 13, and dispense glue to fill the bottom of the package.
  • the top package chip 15 and the passive component 14 are surface mounted on the conductive circuit on the pad side of the chip 7 of the bottom package. The advantage of this is that the interconnection distance between the embedded chip 7 and the top package is shortened.
  • the disadvantage is that the chip fan-out circuit density, that is, the number of solder balls interconnected with the printed circuit board, is limited by the density of interconnected metal pillars, so it can only be suitable for chips with a small number of inputs and outputs.
  • the manufacturing method of the stacked packaging structure compared with the conventional stacked packaging technology, it has the advantages of fine circuits, small chip drift, and good predictability.
  • the use of organic resin core boards to produce three-dimensional interconnect structures has the advantages of low production cost, short plastic flow distance, low difficulty in processing and transportation, and good warpage resistance, and avoids the shortcomings of conventional stacked packaging solutions.
  • FIG. 3-13 is a schematic diagram of a bottom package provided by an embodiment of the present application.
  • the bottom package includes:
  • Organic resin core board 1 of organic resin material the organic resin core board 1 has a through hole, and interconnecting metal pillars 3 are electroplated in the through hole;
  • a first connection line 10 is formed on the pad side of the organic resin core board 1
  • a second connection line 11 is formed on the non-pad side of the organic resin core board 1 .
  • a chip attach film 16 is provided between the non-pad side of the preset chip 7 and the organic resin core board 1 .
  • the chip is embedded in an organic resin core board, and the three-dimensional interconnection structure is made of the organic resin core board. Therefore, the three-dimensional interconnection structure has low density, high efficiency, and low cost.
  • the organic resin in the core board structure has the characteristics of short flow distance, which is beneficial to improving the chip placement accuracy.
  • This application uses a hard temporary carrier, and the chip pad side is ground to have a high surface flatness, so finer circuits can be made.
  • the stacked packaging structure includes:
  • the top package 17 includes: top package chip and passive components;
  • the bottom package 18 is mounted on the printed circuit board 19 through the second connection line, and the top package chip and passive components in the top package 17 are mounted on the first connection line of the bottom package 18 .
  • FIG. 6 is a schematic diagram of a stacked packaging structure provided by an embodiment of the present application.
  • the stacked packaging structure includes:
  • the top package 17 includes: top package chip and passive components;
  • the bottom package 18 is mounted on the printed circuit board 19 through a first connection line, and the top package chip and passive components in the top package 17 are mounted on a second connection line of the bottom package 18 .
  • the stacked packaging structure Compared with conventional stacked packaging structures, the stacked packaging structure provided by this application has the advantages of fine lines, small chip drift, and good predictability.
  • the use of organic resin core boards to produce three-dimensional interconnect structures has the advantages of low production cost, short plastic flow distance, low difficulty in processing and transportation, and good warpage resistance, and avoids the shortcomings of conventional stacked packaging solutions.

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Abstract

本申请公开了一种底部封装体及其制作方法以及堆叠封装结构及其制作方法，底部封装体的制作方法包括:在有机树脂芯板上加工通孔，并进行电镀，在通孔内形成互连金属柱；在电镀后的有机树脂芯板上加工通槽，将加工通槽过后的有机树脂芯板固定于硬质临时载体上；在硬质临时载体上方的通槽内放置预设芯片，使预设芯片的焊盘侧远离硬质临时载体；从预设芯片的焊盘侧塑封通槽内的预设芯片，并对塑封后的有机树脂芯板焊盘侧进行研磨，以露出预设芯片的焊盘；在研磨后的有机树脂芯板的焊盘侧制作形成第一连接线路；解除硬质临时载体，在预设芯片的非焊盘侧制作形成第二连接线路。本申请可以使三维互连结构的密度高、制作成本低、芯片表面线路更精细。

Description

底部封装体及其制作方法以及堆叠封装结构及其制作方法
本申请以2022年7月21日提交的申请号为202210867742.9，名称为“底部封装体及其制作方法以及堆叠封装结构及其制作方法”的中国发明申请为基础，并要求其优先权。
技术领域
本申请涉及半导体封装领域，尤其涉及一种底部封装体及其制作方法以及堆叠封装结构及其制作方法。
背景技术
在现代芯片封装技术中，一个广泛应用的芯片封装技术就是堆叠封装(Packageon Package，PoP)，其主要思路就是逻辑芯片顶部堆叠封装(或倒装)一个存储芯片，当然，也可以进一步在逻辑芯片顶部贴装被动元件。
发明人意识到，芯片堆叠封装最大的一个技术挑战是底部封装体与顶部封装体的互连问题。目前，底部封装体与顶部封装体的互连主要采用三类方法：
第一类方法是基于传统封装技术，即在封装基板上塑封好芯片后，作为底部封装体，然后在底部封装体的塑封层钻孔，通过在孔内填塞导电膏来实现互连，然后在底部封装体的顶部倒装已经封装好的顶部封装体。该方案的最大劣势是激光开孔或锡球尺寸较大，因此三维互连结构的密度低。
第二类方法是基于先进封装技术，首先，在一个临时载体上制作种子层，然后贴干膜电镀出铜柱，并蚀刻种子层，这样就得到了一个三维互连结构，进一步地贴装芯片，最后塑封芯片，研磨露出铜柱，这样就得到了三维互连结构。该方案的优势是三维互连结构的密度高，但制作成本也较高。在芯片塑封时，塑封料流动距离较大，对芯片的贴装精度有不利影响。除此之外，由于塑封料的模量不高，因此对于大尺寸如板级封装，该方案会存在转运难度，即临时载体移除后，会存在样品碎裂风险。
第三类方法也是基于先进封装技术，首先，在一个印制电路板用的有机树脂芯板上加工通孔，然后电镀实现有机树脂芯板的两侧互连，然后在指定位置加工通槽，然后在依次 贴胶带，并把芯片贴附在通槽内的胶带上，最后塑封芯片，这样得到了一个三维互连结构。该方案的最大优势是成本低，而且有通槽的限制，塑封料流动距离短，可以减少对芯片位置精度的影响。还有一个优点是有机树脂芯板由于采用了玻纤布增强，因此模量更大，加工过程转运难度低，产品抗翘曲能力强。但缺点也很明显，那就是胶带的热膨胀系数比有机树脂芯板和塑封料都大，这种热膨胀系数的不匹配导致在塑封过程中芯片的位置偏移非常大，而且由于受热可能不均匀，因此也难以通过热膨胀系数差异来预先补偿的方式完全规避芯片不规则偏移。由于有机树脂芯板的平整度比专用临时载体如玻璃差，因此，其表面线路的精细程度也受到影响。
综上所述，现有封装技术中存在的三维互连结构的密度低、制作成本高、芯片表面线路精细度不高等问题。
发明内容
基于此，提供一种底部封装体及其制作方法以及堆叠封装结构及其制作方法，以解决现有技术中三维互连结构的密度低、制作成本高、芯片表面线路精细度不高等问题。
本申请实施例提供了一种底部封装体的制作方法，所述方法包括：
在有机树脂芯板上加工通孔，并进行电镀，在所述通孔内形成互连金属柱；
在电镀后的所述有机树脂芯板上加工通槽，将加工通槽过后的所述有机树脂芯板固定于硬质临时载体上；
在所述硬质临时载体上方的所述通槽内放置预设芯片，使所述预设芯片的焊盘侧远离所述硬质临时载体；
从所述预设芯片的焊盘侧塑封所述通槽内的所述预设芯片，并对塑封后的有机树脂芯板的焊盘侧进行研磨，以露出所述预设芯片的焊盘；
在研磨后的有机树脂芯板的焊盘侧制作形成第一连接线路；
解除所述硬质临时载体，在所述预设芯片的非焊盘侧制作形成第二连接线路，形成所述底部封装体。
本申请提供的底部封装体的制作方法，采用有机树脂芯板辅助芯片塑封，既可以低成本、高良率制作互连金属柱，又可以提高芯片塑封层的机械强度，尤其适用于大尺寸先进封装，还可以减少塑封料的用量，降低塑封的材料成本。除此之外，采用有机树脂芯板辅助芯片塑封，可以提高封装体的抗翘曲能力，有利于实现更大尺寸的封装体以及提高封装 产品的集成度。采用硬质临时载体辅助塑封芯片，具体而言，选择热膨胀系数较小且各向同性的硬质临时载体，可以显著提高芯片塑封时芯片位置偏移的可预测性以及芯片塑封后的位置精度，还有利于提高芯片焊盘侧导电线路与芯片的对位精度。采用硬质临时载体辅助线路制作，具体而言，选择高平整度硬质临时载体，结合研磨技术，可以在芯片焊盘侧得到高平整度的表面，有利于在芯片焊盘侧制作高精度导电线路，提高芯片封装密度。
本申请实施例提供了一种堆叠封装结构的制作方法，所述方法包括：
在有机树脂芯板上加工通孔，并进行电镀，在所述通孔内形成互连金属柱；
在电镀后的所述有机树脂芯板上加工通槽，将加工通槽过后的所述有机树脂芯板固定于硬质临时载体上；
在所述硬质临时载体上方的所述通槽内放置预设芯片，使所述预设芯片的焊盘侧远离所述硬质临时载体；
从所述预设芯片的焊盘侧塑封所述通槽内的所述预设芯片，并对塑封后的有机树脂芯板的焊盘侧进行研磨，以露出所述预设芯片的焊盘；
在研磨后的有机树脂芯板的焊盘侧制作形成第一连接线路；
解除所述硬质临时载体，在所述预设芯片的非焊盘侧制作形成第二连接线路，形成所述底部封装体；
将所述底部封装体的一侧焊接到印制电路板上，在所述底部封装体的另一侧贴装顶部封装体。
本申请提供的堆叠封装结构的制作方法，与常规堆叠封装技术相比，同时具备了线路精细、芯片漂移小以及可预测性好的优点。采用有机树脂芯板制作三维互连结构具有制作成本低、塑封料流胶距离短、加工转运难度低以及抗翘曲能力好的优点，从而规避了常规堆叠封装方案的缺点。
本申请实施例提供了一种底部封装体，所述底部封装体包括：
有机树脂材料的有机树脂芯板，所述有机树脂芯板具有通孔，所述通孔内电镀有互连金属柱；
所述有机树脂芯板上开有通槽，所述通槽内塑封有预设芯片；塑封的所述预设芯片的焊盘从中露出；
所述有机树脂芯板的焊盘侧形成有第一连接线路；所述有机树脂芯板的非焊盘侧形成有第二连接线路。
本申请提供的底部封装体，芯片被嵌入在一个有机树脂芯板中，三维互连结构由有机树脂芯板制作，因此，三维互连结构的密度高，效率高、成本低，除此之外，芯板结构的有机树脂具有流动距离短的特点，有利于提高芯片的贴装精度。该底部封装体线路精细，也规避了芯片大幅度漂移的问题，封装结构密度也更高。
本申请实施例提供了一种堆叠封装结构，所述堆叠封装结构包括：
底部封装体、印制电路板以及顶部封装体，其中，所述底部封装体包括：
有机树脂材料的有机树脂芯板，所述有机树脂芯板具有通孔，所述通孔内电镀有互连金属柱；所述有机树脂芯板上开有通槽，所述通槽内塑封有预设芯片；塑封的所述预设芯片的焊盘从中露出；所述有机树脂芯板的焊盘侧形成有第一连接线路；所述有机树脂芯板的非焊盘侧形成有第二连接线路；
所述顶部封装体包括：顶部封装芯片以及被动元件；
所述底部封装体通过第二连接线路或第一连接线路安装在所述印制电路板上，所述顶部封装体中的所述顶部封装芯片和所述被动元件安装在所述底部封装体的所述第一连接线路或所述第二连接线路上。
本申请提供的堆叠封装结构，与常规堆叠封装结构相比，同时具备了线路精细、芯片漂移小以及可预测性好的优点。采用有机树脂芯板制作三维互连结构具有制作成本低、塑封料流胶距离短、加工转运难度低以及抗翘曲能力好的优点，从而规避了常规堆叠封装方案的缺点。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例的描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本申请一实施例提供的底部封装体的制作方法的流程图；
图2是本申请一实施例提供的堆叠封装结构的制作方法的流程图；
图3-1是本申请一实施例提供的在芯板上加工通孔示意图；
图3-2是本申请一实施例提供的在芯板上通孔电镀示意图；
图3-3是本申请一实施例提供的在芯板上加工通槽示意图；
图3-4是本申请一实施例提供的在芯板上粘贴粘结胶示意图；
图3-5是本申请一实施例提供的将芯板上通槽内粘结胶去除后的示意图；
图3-6是本申请一实施例提供的将芯板上通过粘结胶粘贴硬质临时载体的示意图；
图3-7是本申请一实施例提供的将预设芯片粘贴在硬质临时载体上通槽内的示意图；
图3-8是本申请一实施例提供的将预设芯片塑封在通槽内的示意图；
图3-9是本申请一实施例提供的将预设芯片塑封层研磨的示意图；
图3-10是本申请一实施例提供的将芯板表面形成第一连接线路的示意图；
图3-11是本申请一实施例提供的移除硬质临时载体并对芯板移除硬质临时载体侧进行研磨的示意图；
图3-12是本申请一实施例提供的芯板非焊盘侧制作连接盘的示意图；
图3-13是本申请一实施例提供的芯板非焊盘侧制作第二连接线路的示意图；
图3-14是本申请一实施例提供的第一连接线路植球的示意图；
图3-15是本申请一实施例提供的底部封装体焊接至印制电路板的示意图；
图3-16是本申请一实施例提供的底部封装体贴装顶部封装体的示意图；
图4-1是本申请另一实施例提供的第二连接线路植球的示意图；
图4-2是本申请另一实施例提供的底部封装体焊接至印制电路板的示意图；
图4-3是本申请另一实施例提供的底部封装体贴装顶部封装体的示意图；
图5是本申请一实施例提供的堆叠封装结构的示意图；
图6是本申请另一实施例提供的堆叠封装结构的示意图；
其中，1为有机树脂芯板，2为通孔，3为互连金属柱，4为通槽，5为粘结胶，6为硬质临时载体，7为芯片，8为塑封料，9为连接盘，10为第一连接线路，11为第二连接线路，12为BGA锡球，13为印制电路板，14为被动元件，15为顶部封装芯片，16为芯片贴附膜，17为顶部封装体，18为底部封装体，19为印制电路板。
具体实施方式
为了说明本申请的技术方案，下面通过具体实施例来进行说明。
参见图1，是本申请一实施例提供的底部封装体的制作方法的流程图，所述方法包括：
S101、在有机树脂芯板上加工通孔，并进行电镀，在通孔内形成互连金属柱。
参见图3-1和图3-2，选取有机树脂芯板1一张，作为优选地，有机树脂芯板1可以 为表面覆盖铜箔的有机树脂芯板1，在有机树脂芯板1需要制作互连金属柱3的预设位置处加工通孔2。在有机树脂芯板1上加工通孔2的方法可以选用机械钻在有机树脂芯板1上钻取通孔2，也可以采用激光来对有机树脂芯板1进行加工出通孔2。进行电镀是将有机树脂芯板1的上下表面以及通孔2进行电镀，电镀材料可以为金属铜，电镀方式为：采用现有技术中的溅射、蒸发或化学镀铜、吸附导电物等方法来使得通孔孔壁覆盖有导电种子层，然后采用电镀使得有机树脂芯板1的通孔2内填充有金属即铜，来形成互连金属柱3也称三维互连结构。
S102、在电镀后的有机树脂芯板上加工通槽，将加工通槽过后的有机树脂芯板固定于硬质临时载体上。
参见图3-3，在有机树脂芯板1需要埋入预设芯片的位置加工通槽4，通槽4的尺寸大于预设芯片的尺寸。可选地，通槽4的空间可以容纳一个预设芯片或两个及以上数量的预设芯片。在有机树脂芯板1上加工通槽4的方式可以为采用激光对有机树脂芯板1进行加工，使得有机树脂芯板1露出通槽4；还可以采用机械加工的方式使得有机树脂芯板1露出通槽4。
在一示例中，将加工通槽4过后的有机树脂芯板1固定于硬质临时载体6上包括：
如图3-4所示，在加工通槽4过后的有机树脂芯板1的一侧粘贴粘结胶；
如图3-5所示，切割掉通槽处的粘结胶；
如图3-6所示，将有机树脂芯板1贴有粘结胶的一侧贴附于硬质临时载体6上。
在一示例中，粘结胶可以为双面粘结胶，一面用于贴附于有机树脂芯板1的一侧，另一面用于贴附于硬质临时载体6上。粘结胶的作用为将有机树脂芯板更好的固定于硬质临时载体6上。切割上述通槽内的粘结胶时，可以采用本领域技术人员所公知的技术，比如可以采用激光加工的方式进行切割。
硬质临时载体6可以为玻璃载体、不锈钢载体或硅片载体中的一种。当使用硅片作为硬质临时载体6时，硬质临时载体6一定为圆形，而使用玻璃或不锈钢作为硬质临时载体6时，硬质临时载体6可以是圆形，也可以是方形。
S103、在硬质临时载体上方的通槽内放置预设芯片，使预设芯片的焊盘侧远离硬质临时载体。
参见图3-7，硬质临时载体6上方的通槽可容纳预设芯片7的数量不做限制，可以为 一个、两个或两个以上。
在一示例中，在硬质临时载体6上方的通槽内放置预设芯片7，使预设芯片7的焊盘侧远离硬质临时载体具体包括：
将预设芯片7的非焊盘侧贴附芯片贴附膜16；
通过芯片贴附膜16将预设芯片贴附于硬质临时载体6上方的通槽4内。
在预设芯片7的非焊盘侧采用芯片贴附膜16来替代原本的胶带，将预设芯片7贴装到热膨胀系数匹配性好、均一性好的硬质临时载体6上，规避了原有技术方案中因胶带热膨胀系数差异大带来的预设芯片7大幅度漂移的问题，而且采用树脂固化固定方式的芯片贴附膜的固定效果也比粘度受温度影响大的胶带的固定效果更好。
在一示例中，硬质临时载体6靠近有机树脂芯板1的一侧设有离型层，粘结胶和芯片贴附膜贴附于离型层上。
离型层可以为光敏解键合离型层，还可以是热敏解键合离型层，优选光敏解键合离型层。
离型层的设置是为了方便有机树脂芯板1和芯片贴附膜16与硬质临时载体剥离，离型层可以保证粘结胶和固化的芯片贴附膜16从硬质临时载体上剥离，不会因为剥离时巨大的应力而导致硬质临时载体碎裂、粘结胶残留、芯片贴附膜碎裂等。
S104、从预设芯片的焊盘侧塑封通槽内的预设芯片，并对塑封后的有机树脂芯板的焊盘侧进行研磨，以露出预设芯片的焊盘。
特别说明的是，文中焊盘侧均指的是预设芯片焊盘侧，文中非焊盘侧也均指的是预设芯片的非焊盘侧。
参见图3-8，从预设芯片7的焊盘侧塑封通槽4内的预设芯片7，是将塑封料8填充于有机树脂芯板1通槽槽壁与预设芯片7之间的缝隙且覆盖有机树脂芯板1的上表面。当一个通槽4内放置两个以上预设芯片7时，塑封料8还要填充预设芯片7之间的缝隙。
塑封料8也称环氧塑封料，是电子元器件的封装材料,它是以环氧树脂、酚醛树脂为基体树脂,硅微粉为填料配合多种助剂加工制成的，为现有技术。
塑封料8可以为颗粒型、液态型或者薄膜型，塑封方式可以为压缩成型或真空贴膜，当采用真空贴膜塑封时，只能使用薄膜型环氧塑封料。
参见图3-9，对塑封后的有机树脂芯板1的焊盘侧进行研磨，以露出预设芯片7的焊盘。其中，研磨可以采用机械研磨的方式，研磨掉预设芯片7焊盘侧上表面的塑封料8以及金属层，使得有机树脂芯板1焊盘侧表面金属层全部被研磨掉且露出预设芯片7表面的焊盘。因为硬质临时载体表面的平整度高，因此，有机树脂芯板1研磨过后可以得到高平整度的表面，这有利于制作精细的线路。
S105、在研磨后的有机树脂芯板的焊盘侧制作形成第一连接线路。
参见图3-10，在一示例中，在研磨后的有机树脂芯板1的焊盘侧制作形成第一连接线路10具体包括：
采用积层法在预设芯片7的焊盘侧进行若干次循环导电线路制作，每次均采用半加成法进行制作，得到预设层数的第一连接线路10。
采用积层法在预设芯片7的焊盘侧进行若干次循环制作得到目标层数导电线路层，导电线路层包括导电线路、绝缘介质。导电线路的制作优选半加成法，根据导电线路精细程度选择光阻材料，8μm以下线路优选液态感光胶，8μm及以上线路优选干膜；根据导电线路精细程度选择绝缘介质，8μm以下线路优选感光聚酰亚胺，8μm及以上线路优选ABF(Ajinomoto build-up film，味之素堆积膜)，50μm及以上线路可以选择玻璃纤维布增强的环氧树脂。
制作形成第一连接线路10的过程为现有技术，在此不再赘述。
S106、解除硬质临时载体，在预设芯片的非焊盘侧制作形成第二连接线路，形成底部封装体。
参见图3-11，解除硬质临时载体的方式可以根据离型层类型决定,为现有技术，在此不再赘述。除去有机树脂芯板1非焊盘侧的粘结层即粘结胶，采用plasma的方式咬蚀除去部分突出的芯片贴附膜16，使芯片贴附膜16表面与有机树脂芯板1非焊盘侧表面金属层平齐或略微凹陷即解除硬质临时载体6后，去除部分芯片贴附膜16，使剩余部分的芯片贴附膜16的表面低于或平齐于预设芯片7的非焊盘侧处有机树脂芯板1表面。
可选地，在预设芯片7的非焊盘侧制作形成第二连接线路11具体包括：
参见图3-12，通过减成法在有机树脂芯板1的非焊盘侧表面的互连金属柱3位置处制作连接盘9；连接盘9的直径大于互连金属柱3的直径；
在一示例中，通过减成法在有机树脂芯板的非焊盘侧表面的互连金属柱位置处制作连 接盘，也可以在步骤S101电镀得到互连金属柱3后，直接采用减成法在有机树脂芯板两侧的金属柱位置制作连接盘；该方案的优势是连接盘可以作为芯片贴装的位置参考点，而且减少步骤S104中对塑封后的有机树脂芯板的焊盘侧进行研磨中研磨有机树脂芯板的焊盘侧的金属层的研磨量。除此之外，在该示例中，可以省去步骤S106中解除硬质临时载体当中采用plasma的方式咬蚀除去部分突出的芯片贴附膜这一步骤，但缺点是该示例中芯片非焊盘侧有机树脂芯板表面连接盘会嵌入到粘结胶中，而且粘结胶直接与有机树脂芯板表面无金属层部分粘结，因此，贴附有机树脂芯板与硬质临时载体时凸起连接盘局部压强更大，且有机树脂芯板表面金属层蚀刻后留下了多孔结构，会增加硬质临时载体解键合后粘结胶去除时的粘结胶残留风险，粘结胶残留会增加封装体分层风险，降低封装体可靠性。
在一示例中，在有机树脂芯板1的非焊盘侧表面的互连金属柱3位置处也可以不制作连接盘，用于制作更精细的线路，从而获得更高密度的封装结构。
参见图3-13，采用积层法在有机树脂芯板1的非焊盘侧表面若干次循环制作得到目标层数的第二连接线路11。
采用积层法在预设芯片7非焊盘侧多次循环制作得到目标层数导电线路层，导电线路层包括导电线路、绝缘介质；导电线路的制作优选半加成法，也可以使用减成法；根据导电线路精细程度选择光阻材料，光阻材料优选干膜。根据导电线路精细程度选择绝缘介质，绝缘介质层优选ABF，也可以使用玻璃纤维布增强的环氧树脂。
制作形成第二连接线路11的过程为现有技术，在此不再赘述。
可选地，还包括在第一连接线路和第二连接线路表面制作表面处理层的步骤。
在本申请提供的底部封装体的制作方法中，采用有机树脂芯板辅助芯片塑封，既可以低成本、高良率制作互连金属柱，又可以提高芯片塑封层的机械强度，尤其适用于大尺寸先进封装，还可以减少塑封料的用量，降低塑封的材料成本。除此之外，采用有机树脂芯板辅助芯片塑封，可以提高封装体的抗翘曲能力，有利于实现更大尺寸的封装体以及提高封装产品的集成度。采用硬质临时载体辅助塑封芯片，具体而言，选择热膨胀较小且各向同性的硬质临时载体，可以显著提高芯片塑封时芯片位置偏移的可预测性以及芯片塑封后的位置精度，还有利于提高芯片焊盘侧导电线路与芯片的对位精度。采用硬质临时载体辅助线路制作，具体而言，选择高平整度硬质临时载体，结合研磨技术，可以在芯片焊盘侧得到高平整度的表面，有利于在芯片焊盘侧制作高精度导电线路，提高芯片封装密度。
参见图2，是本申请一实施例提供的堆叠封装结构的制作方法的流程，所述方法包括：
S201、获取根据上述底部封装体的制作方法所制作的底部封装体；
参见前实施例中图3-1至图3-13，根据上述底部封装体制作方法来制作底部封装体，在此不再赘述。
S202、在底部封装体的上侧贴装顶部封装体，将底部封装体的下侧焊接到印制电路板上。
在一示例中，参见图3-14，在底部封装体的预设芯片焊盘侧的第一连接线路表面植球，形成BGA(Ball Gird Array，球栅阵列封装)锡球12，参见图3-15，将底部封装体焊接至印制电路板13上，并点胶实现封装体底部填充。参见图3-16，在底部封装体的芯片非焊盘侧导电线路表面贴装顶部封装芯片15和被动元件14，其中，如果顶部封装芯片是倒装焊接，那么还需要点胶实现顶部封装体底部填充。
点胶所使用的填充剂为非导电胶或毛细管底部填充胶。
在一示例中，顶部封装体倒装在埋入芯片的焊盘侧，参见图4-1，即在底部封装体的预设芯片7非焊盘侧的第二连接线路11表面植球，形成BGA锡球12，参见图4-2，将底部封装体焊接至印制电路板13上，并点胶实现封装体底部填充。参见图4-3，在底部封装体的芯片7焊盘侧导电线路表面贴装顶部封装芯片15和被动元件14，这样的好处是缩短了埋入芯片7与顶部封装体间的互连距离，有利于降低信号传输损耗，但缺点是芯片扇出线路密度即与印制电路板互连焊球数量受限于互连金属柱的密度，因此只能适合输入输出数较少的芯片。
在本申请提供的堆叠封装结构的制作方法中，与常规堆叠封装技术相比，同时具备了线路精细、芯片漂移小以及可预测性好的优点。采用有机树脂芯板制作三维互连结构具有制作成本低、塑封料流胶距离短、加工转运难度低以及抗翘曲能力好的优点，规避了常规堆叠封装方案的缺点。
参见图3-13，是本申请一实施例提供的底部封装体的示意图，底部封装体包括：
有机树脂材料的有机树脂芯板1，有机树脂芯板1具有通孔，通孔内电镀有互连金属柱3；
有机树脂芯板1上开有通槽，通槽内塑封有预设芯片7；塑封的预设芯片7的焊盘从中露出；
有机树脂芯板1的焊盘侧形成有第一连接线路10；有机树脂芯板1的非焊盘侧形成有第二连接线路11。
在一示例中，预设芯片7非焊盘侧与有机树脂芯板1之间还设置有芯片贴附膜16。
本申请提供的底部封装体，芯片被嵌入在一个有机树脂芯板中，三维互连结构由有机树脂芯板制作，因此，三维互连结构的密度低，效率高、成本低，除此之外，芯板结构的有机树脂具有流动距离短的特点，有利于提高芯片的贴装精度。本申请采用硬质临时载体，芯片焊盘侧经过研磨，表面平整度高，因此可以制作更精细的线路。
参见图5，是本申请一实施例提供的堆叠封装结构的示意图，堆叠封装结构包括：
上述底部封装体18、印制电路板19以及顶部封装体17，顶部封装体17包括：顶部封装芯片以及被动元件；
底部封装体18通过第二连接线路安装在印制电路板19上，顶部封装体17中的顶部封装芯片和被动元件安装在底部封装体18的第一连接线路上。
参见图6，是本申请一实施例提供的堆叠封装结构的示意图，堆叠封装结构包括：
上述底部封装体18、印制电路板19以及顶部封装体17，顶部封装体17包括：顶部封装芯片以及被动元件；
底部封装体18通过第一连接线路安装在印制电路板19上，顶部封装体17中的顶部封装芯片和被动元件安装在底部封装体18的第二连接线路上。
本申请提供的堆叠封装结构，与常规堆叠封装结构相比，同时具备了线路精细、芯片漂移小以及可预测性好的优点。采用有机树脂芯板制作三维互连结构具有制作成本低、塑封料流胶距离短、加工转运难度低以及抗翘曲能力好的优点，规避了常规堆叠封装方案的缺点。
以上所述实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围，均应包含在本申请的保护范围之内。

Claims (20)

  1. 一种底部封装体的制作方法，其中，包括：
    在有机树脂芯板上加工通孔，并进行电镀，在所述通孔内形成互连金属柱；
    在电镀后的所述有机树脂芯板上加工通槽，将加工通槽过后的所述有机树脂芯板固定于硬质临时载体上；
    在所述硬质临时载体上方的所述通槽内放置预设芯片，使所述预设芯片的焊盘侧远离所述硬质临时载体；
    从所述预设芯片的焊盘侧塑封所述通槽内的所述预设芯片，并对塑封后的有机树脂芯板的焊盘侧进行研磨，以露出所述预设芯片的焊盘；
    在研磨后的有机树脂芯板的焊盘侧制作形成第一连接线路；
    解除所述硬质临时载体，在所述预设芯片的非焊盘侧制作形成第二连接线路，形成所述底部封装体。
  2. 如权利要求1所述的底部封装体的制作方法，其中，所述将加工通槽过后的所述有机树脂芯板固定于硬质临时载体上包括：
    在加工通槽过后的所述有机树脂芯板的一侧粘贴粘结胶；
    切割掉所述通槽处的所述粘结胶；
    将所述有机树脂芯板贴有所述粘结胶的一侧贴附于所述硬质临时载体上。
  3. 如权利要求1所述的底部封装体的制作方法，其中，在所述硬质临时载体上方的所述通槽内放置预设芯片，使所述预设芯片的焊盘侧远离所述硬质临时载体具体包括：
    将所述预设芯片的非焊盘侧贴附芯片贴附膜；
    通过所述芯片贴附膜将所述预设芯片贴附于所述硬质临时载体上方的所述通槽内。
  4. 如权利要求2所述的底部封装体的制作方法，其中，所述硬质临时载体靠近所述有机树脂芯板的一侧有离型层，所述粘结胶和所述芯片贴附膜贴附于所述离型层上。
  5. 如权利要求3所述的底部封装体的制作方法，其中，所述硬质临时载体靠近所述有机树脂芯板的一侧有离型层，所述粘结胶和所述芯片贴附膜贴附于所述离型层上。
  6. 如权利要求3所述的底部封装体的制作方法，其中，还包括：解除所述硬质临时载体后，去除部分所述芯片贴附膜，使剩余部分的所述芯片贴附膜的表面低于或平齐于所述预设芯片的非焊盘侧处有机树脂芯板表面。
  7. 如权利要求1所述的底部封装体的制作方法，其中，所述在研磨后的有机树脂芯板的焊盘侧制作形成第一连接线路具体包括：
    采用积层法在所述预设芯片的焊盘侧进行若干次循环导电线路制作，每次均采用半加成法进行制作，得到预设层数的第一连接线路。
  8. 如权利要求1所述的底部封装体的制作方法，其中，所述在所述预设芯片的非焊盘侧制作形成第二连接线路具体包括：
    通过减成法在所述有机树脂芯板的非焊盘侧表面的互连金属柱位置处制作连接盘；所述连接盘的直径大于所述互连金属柱的直径；
    采用积层法在所述有机树脂芯板的非焊盘侧表面多次循环制作得到目标层数的第二连接线路。
  9. 如权利要求1所述的底部封装体的制作方法，其中，还包括在所述第一连接线路和所述第二连接线路表面制作表面处理层的步骤。
  10. 一种堆叠封装结构的制作方法，其中，包括：
    在有机树脂芯板上加工通孔，并进行电镀，在所述通孔内形成互连金属柱；
    在电镀后的所述有机树脂芯板上加工通槽，将加工通槽过后的所述有机树脂芯板固定于硬质临时载体上；
    在所述硬质临时载体上方的所述通槽内放置预设芯片，使所述预设芯片的焊盘侧远离所述硬质临时载体；
    从所述预设芯片的焊盘侧塑封所述通槽内的所述预设芯片，并对塑封后的有机树脂芯板的焊盘侧进行研磨，以露出所述预设芯片的焊盘；
    在研磨后的有机树脂芯板的焊盘侧制作形成第一连接线路；
    解除所述硬质临时载体，在所述预设芯片的非焊盘侧制作形成第二连接线路，形成所述底部封装体；
    将所述底部封装体的一侧焊接到印制电路板上，在所述底部封装体的另一侧贴装顶部 封装体。
  11. 如权利要求10所述的堆叠封装结构的制作方法，其中，所述将加工通槽过后的所述有机树脂芯板固定于硬质临时载体上包括：
    在加工通槽过后的所述有机树脂芯板的一侧粘贴粘结胶；
    切割掉所述通槽处的所述粘结胶；
    将所述有机树脂芯板贴有所述粘结胶的一侧贴附于所述硬质临时载体上。
  12. 如权利要求10所述的堆叠封装结构的制作方法，其中，在所述硬质临时载体上方的所述通槽内放置预设芯片，使所述预设芯片的焊盘侧远离所述硬质临时载体具体包括：
    将所述预设芯片的非焊盘侧贴附芯片贴附膜；
    通过所述芯片贴附膜将所述预设芯片贴附于所述硬质临时载体上方的所述通槽内。
  13. 如权利要求11所述的堆叠封装结构的制作方法，其中，所述硬质临时载体靠近所述有机树脂芯板的一侧有离型层，所述粘结胶和所述芯片贴附膜贴附于所述离型层上。
  14. 如权利要求12所述的堆叠封装结构的制作方法，其中，所述硬质临时载体靠近所述有机树脂芯板的一侧有离型层，所述粘结胶和所述芯片贴附膜贴附于所述离型层上。
  15. 如权利要求12所述的堆叠封装结构的制作方法，其中，还包括：解除所述硬质临时载体后，去除部分所述芯片贴附膜，使剩余部分的所述芯片贴附膜的表面低于或平齐于所述预设芯片的非焊盘侧处有机树脂芯板表面。
  16. 如权利要求10所述的堆叠封装结构的制作方法，其中，所述在研磨后的有机树脂芯板的焊盘侧制作形成第一连接线路具体包括：
    采用积层法在所述预设芯片的焊盘侧进行若干次循环导电线路制作，每次均采用半加成法进行制作，得到预设层数的第一连接线路。
  17. 如权利要求10所述的堆叠封装结构的制作方法，其中，所述在所述预设芯片的非焊盘侧制作形成第二连接线路具体包括：
    通过减成法在所述有机树脂芯板的非焊盘侧表面的互连金属柱位置处制作连接盘；所述连接盘的直径大于所述互连金属柱的直径；
    采用积层法在所述有机树脂芯板的非焊盘侧表面多次循环制作得到目标层数的第二 连接线路。
  18. 如权利要求10所述的堆叠封装结构的制作方法，其中，还包括在所述第一连接线路和所述第二连接线路表面制作表面处理层的步骤。
  19. 一种底部封装体，其中，包括：
    有机树脂材料的有机树脂芯板，所述有机树脂芯板具有通孔，所述通孔内电镀有互连金属柱；
    所述有机树脂芯板上开有通槽，所述通槽内塑封有预设芯片；塑封的所述预设芯片的焊盘从中露出；
    所述有机树脂芯板的焊盘侧形成有第一连接线路；所述有机树脂芯板的非焊盘侧形成有第二连接线路。
  20. 一种堆叠封装结构，其中，包括：
    底部封装体、印制电路板以及顶部封装体，其中，所述底部封装体包括：
    有机树脂材料的有机树脂芯板，所述有机树脂芯板具有通孔，所述通孔内电镀有互连金属柱；所述有机树脂芯板上开有通槽，所述通槽内塑封有预设芯片；塑封的所述预设芯片的焊盘从中露出；所述有机树脂芯板的焊盘侧形成有第一连接线路；所述有机树脂芯板的非焊盘侧形成有第二连接线路；
    所述顶部封装体包括：顶部封装芯片以及被动元件；
    所述底部封装体通过第二连接线路或第一连接线路安装在所述印制电路板上，所述顶部封装体中的所述顶部封装芯片和所述被动元件安装在所述底部封装体的所述第一连接线路或所述第二连接线路上。
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