WO2024016517A1 - 立体封装结构及其制作方法 - Google Patents

立体封装结构及其制作方法 Download PDF

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Publication number
WO2024016517A1
WO2024016517A1 PCT/CN2022/129806 CN2022129806W WO2024016517A1 WO 2024016517 A1 WO2024016517 A1 WO 2024016517A1 CN 2022129806 W CN2022129806 W CN 2022129806W WO 2024016517 A1 WO2024016517 A1 WO 2024016517A1
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chip
conductive circuit
circuit layer
substrate
flip
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PCT/CN2022/129806
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English (en)
French (fr)
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朱凯
黄立湘
缪桦
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深南电路股份有限公司
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Publication of WO2024016517A1 publication Critical patent/WO2024016517A1/zh

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Definitions

  • the present application relates to the field of semiconductor packaging, and in particular, to a three-dimensional packaging structure and a manufacturing method thereof.
  • PoP package on package
  • the main idea is to stack and package (or flip) a memory chip on top of a logic chip.
  • Passive components are mounted on the top of the chip.
  • the first type of method is based on traditional packaging technology, that is, after the chip is plastic-sealed on the packaging substrate, it is used as the bottom package, and then holes are drilled in the plastic layer of the bottom package, and interconnection is achieved by filling the holes with conductive paste, and then in The top of the bottom package is flipped onto the packaged top package.
  • the second type of method is based on advanced packaging technology.
  • a seed layer is made on a temporary carrier, and then a dry film is electroplated to form copper pillars, and the seed layer is etched. In this way, a three-dimensional interconnection structure is obtained for further mounting.
  • the chip is finally plastic-sealed and ground to expose the copper pillars, thus obtaining a three-dimensional interconnection structure.
  • the bottom package is produced, and then the bottom package is welded to the printed circuit board, and the top package is welded to the bottom package.
  • the third type of method is also based on advanced packaging technology.
  • through holes are processed on an organic resin core board for printed circuit boards, then electroplating is used to interconnect both sides of the organic resin core board, and then through slots are processed at designated positions.
  • tape is applied in sequence, and the chip is attached to the tape in the through slot, and finally the chip is plastic-sealed, thus obtaining a three-dimensional interconnection structure.
  • the bottom package is produced, and then the bottom package is welded to the printed circuit board, and the top package is welded to the bottom package.
  • the inventor realized that in all the above methods, since the top package is generally a packaged chip, and the thickness of the top package is thicker, there are lower packaging density, low density of the three-dimensional interconnection structure, and difficulty in manufacturing. Problems include high cost and low precision of circuits on the chip surface.
  • a three-dimensional packaging structure and its manufacturing method are provided to solve the existing problems of low packaging density, low density of three-dimensional interconnection structure, high production cost, and low precision of circuits on the chip surface in the existing technology.
  • Embodiments of the present application provide a method for manufacturing a three-dimensional packaging structure.
  • the manufacturing method includes:
  • Conduct circuit fabrication on the pad side and non-pad side of the substrate embedded with the preset chip to form a conductive circuit layer Install a flip-chip bare chip on one of the conductive circuit layers and plastic seal it, and install it on the other conductive circuit layer. Ball planting; wherein the conductive circuit layer is connected to the interconnection metal pillar, and the conductive circuit layer includes a first conductive circuit layer and a second conductive circuit layer.
  • the method for making a three-dimensional packaging structure provided by this application three-dimensionally packages bare chips together, which can further reduce the thickness of the package body and increase the packaging density compared to stacked packaging.
  • the use of organic resin substrates to assist chip molding can not only make interconnection metal pillars with high density, low cost and high yield, but also improve the mechanical strength of the chip molding layer, which is especially suitable for large-size advanced packaging. In addition, it can also reduce the amount of plastic packaging material and reduce the material cost of plastic packaging.
  • the use of organic resin substrates to assist chip molding can improve the anti-warping ability of the package, which is beneficial to realizing larger-sized packages and improving the integration of packaged products. Using a temporary carrier to assist in molding the chip.
  • choosing a temporary carrier with small thermal expansion and isotropy can significantly improve the predictability of chip position deviation during chip molding, the position accuracy after chip molding, and the conductivity of the chip pad side. Alignment accuracy of circuit and chip.
  • Temporary carriers have been used many times to assist circuit production. Specifically, choosing a high-flatness temporary carrier and combining it with grinding technology can obtain a high-flatness surface, which is beneficial to the production of high-precision conductive circuits and improves chip packaging density.
  • the embodiment of the present application provides a three-dimensional packaging structure, which includes:
  • a substrate of organic resin material the substrate has a through hole, and interconnecting metal pillars are electroplated in the through hole;
  • the substrate has a through slot, and a preset chip is embedded and plastic-sealed in the through slot;
  • Conductive circuit layers are provided on both sides of the substrate, and the conductive circuit layers are connected to the interconnection metal pillars; a flip-chip bare chip is installed on one of the conductive circuit layers and plastic-sealed, and the other conductive circuit layer is implanted with ball.
  • the three-dimensional packaging structure Compared with the conventional stacking packaging technology, the three-dimensional packaging structure provided by this application uses bare chip stacking packaging in the structure, and the packaging density is higher.
  • This three-dimensional packaging structure has the advantages of high density of conductive circuits, small chip drift, and good predictability. In addition, it also has the advantages of low production cost of interconnected metal columns, short flow distance of plastic sealing materials, low difficulty in processing and transportation, and good warpage resistance.
  • Figure 1 is a flow chart of a method for manufacturing a three-dimensional packaging structure provided by an embodiment of the present application
  • Figure 2-1 is a schematic diagram of processing through holes on a substrate according to an embodiment of the present application
  • Figure 2-2 is a schematic diagram of through-hole plating on a substrate provided by an embodiment of the present application.
  • Figure 2-3 is a schematic diagram of processing a through groove on a substrate according to an embodiment of the present application.
  • Figures 2-4 are schematic diagrams of pasting adhesive glue on a substrate according to an embodiment of the present application.
  • Figure 2-5 is a schematic diagram after removing the adhesive glue in the through groove on the substrate according to an embodiment of the present application
  • Figure 2-6 is a schematic diagram of pasting the first temporary carrier on the substrate through adhesive glue according to an embodiment of the present application
  • Figures 2-7 are schematic diagrams of pasting the preset chip in the slot on the first temporary carrier according to an embodiment of the present application
  • Figure 2-8 is a schematic diagram of plastically sealing a preset chip in a through slot according to an embodiment of the present application
  • Figure 2-9 is a schematic diagram of grinding the preset chip plastic packaging layer according to an embodiment of the present application.
  • Figure 2-10 is a schematic diagram of forming a first conductive circuit on the surface of a substrate according to an embodiment of the present application
  • Figure 2-11 is a schematic diagram of flip-chip bare chip on the first conductive line provided by an embodiment of the present application
  • Figure 2-12 is a schematic diagram of filling the bottom of the flip-chip bare chip of the first conductive circuit with filler and plastic sealing according to an embodiment of the present application;
  • Figure 2-13 is a schematic diagram of attaching a second temporary carrier to the side of a flip-chip bare chip and removing the first temporary carrier according to an embodiment of the present application;
  • Figure 2-14 is a schematic diagram of grinding on the side of the substrate with the first temporary carrier removed according to an embodiment of the present application
  • Figure 2-15 is a schematic diagram of fabricating a second conductive circuit layer on the side of the substrate after removing the first temporary carrier according to an embodiment of the present application;
  • Figure 2-16 is a schematic diagram of ball planting on the second conductive circuit layer on the substrate according to an embodiment of the present application
  • Figure 3-1 is a schematic diagram of grinding the first conductive circuit layer according to another embodiment of the present application.
  • Figure 3-2 is a schematic diagram of attaching a second temporary carrier to the first conductive circuit layer and removing the first temporary carrier according to another embodiment of the present application;
  • Figure 3-3 is a schematic diagram of attaching a second temporary carrier on the first conductive circuit layer and removing the first temporary carrier according to another embodiment of the present application;
  • Figure 3-4 is a schematic diagram of grinding the second conductive circuit layer provided by another embodiment of the present application.
  • Figure 3-5 is a schematic diagram of a flip-chip bare chip on the second conductive circuit layer provided by another embodiment of the present application;
  • Figure 3-6 is a schematic diagram of a molded bare chip on the second conductive circuit layer provided by another embodiment of the present application.
  • Figures 3-7 are schematic diagrams of ball planting on the first conductive line according to another embodiment of the present application.
  • 1 is the organic resin substrate
  • 2 is the through hole
  • 3 is the interconnection metal pillar
  • 4 is the through groove
  • 5 is the adhesive glue
  • 6 is the first temporary carrier
  • 7 is the chip
  • 8 is the attached film
  • 9 is Plastic encapsulation material
  • 10 is the first conductive circuit layer
  • 11 is the bare chip
  • 12 is the micro bump
  • 13 is the filler
  • 14 is the second conductive circuit
  • 15 is the second temporary carrier
  • 16 is the BGA solder ball.
  • FIG. 1 is a flow chart of a method for manufacturing a three-dimensional packaging structure provided by an embodiment of the present application.
  • the method includes:
  • S101 Provide a substrate of organic resin material, process through holes on the substrate, and perform electroplating in the through holes to form interconnected metal pillars.
  • a substrate 1 of organic resin material is provided, a through hole 2 is processed in the substrate 1, and electroplating is performed in the through hole 2 to form an interconnection metal pillar 3.
  • a substrate 1 of organic resin material is provided, a through hole 2 is processed in the substrate 1, and electroplating is performed in the through hole 2 to form an interconnection metal pillar 3.
  • electroplating is performed in the through hole 2 to form an interconnection metal pillar 3.
  • a substrate 1 of organic resin material is provided, and through holes 2 are processed on the substrate 1 at positions where interconnection metal pillars 3 need to be made;
  • the surface of the substrate 1 is completely covered with a copper layer, that is, a metal layer.
  • an organic resin substrate 1 is selected.
  • the organic resin substrate 1 can be an organic resin substrate 1 with a surface covered with copper foil.
  • the organic resin substrate 1 is processed at a preset position where the interconnection metal pillars 3 need to be made.
  • Through hole 2 The method of processing the through hole 2 on the organic resin substrate 1 can be to use a mechanical drill to drill the through hole 2 on the organic resin substrate 1 , or to use a laser to irradiate the organic resin substrate 1 to create the through hole 2 .
  • the inner wall of the through hole needs to be made with a seed layer.
  • seed layer making methods commonly used in the industry are:
  • the metal is generally one or two of copper, Ti, Ni, Cr, and Au.
  • the common one is Ti/Cu.
  • Electroless copper plating uses a reducing agent for catalytic reduction (the catalyst is Pd), and a metallic copper layer will be attached to the surface and hole walls.
  • the preferred order is electroless copper plating > sputtering/evaporation > adsorption of conductive material.
  • the electroplated through hole 2 refers to electroplating the through hole 2 of the organic resin substrate 1.
  • the electroplating material can be metallic copper.
  • the electroplating method is: using DC electroplating or pulse electroplating to fill the through hole 2 of the organic resin substrate 1 with metal. Interconnecting metal pillars 3 are formed.
  • a through groove 4 is processed on the organic resin substrate 1 where the preset chip 7 needs to be buried.
  • the size of the through groove 4 is larger than the size of the preset chip.
  • the space of the through slot 4 can accommodate one chip or two or more chips.
  • the method of processing the through groove 4 on the organic resin substrate 1 may be to use a laser to process the organic resin substrate 1 so that the organic resin substrate 1 exposes the through groove 4; or mechanical processing may be used to expose the organic resin substrate 1 to the through groove 4. .
  • "embedding the preset chip in the through-slot and plastic-sealing it” specifically includes:
  • An adhesive film 8 is used on the non-pad side of the preset chip 7 to replace the original tape, and the preset chip 7 is mounted on the first temporary carrier 6 with good thermal expansion coefficient matching and good uniformity, thus avoiding the original adhesive tape.
  • the large difference in thermal expansion coefficient of the tapes causes the problem of large drift of the preset chip 7.
  • the fixing effect of the chip attach film using resin curing fixation method is better than that of the tape whose viscosity is greatly affected by temperature.
  • the adhesive glue 5 is a double-sided adhesive glue, one side is used to be attached to one side of the organic resin substrate 1 , and the other side is used to be bonded to the first temporary carrier 6 .
  • the adhesive 5 serves to better fix the organic resin substrate 1 on the first temporary carrier 6 .
  • the preset chip 7 in the through-slot is plastic-sealed, which specifically includes:
  • the plastic molding material 9 is filled in the gap between the groove wall of the organic resin substrate 1 and the preset chip 7 and covers the upper surface of the organic resin substrate 1 .
  • the plastic molding compound must also fill the gaps between the preset chips.
  • Plastic sealant 9 also known as epoxy sealant, is a packaging material for electronic components. It is made of epoxy resin and phenolic resin as the base resin, silica powder as the filler, and a variety of additives. It is an existing technology.
  • the plastic sealant 9 can be granular, liquid or film type, and the sealing method can be compression molding or vacuum lamination. When vacuum lamination is used, only film-type epoxy sealant can be used.
  • a release layer is provided on the side of the first temporary carrier 6 close to the organic resin substrate 1, and the adhesive film is attached to the release layer.
  • the release layer can be a photosensitive debonding release layer or a heat-sensitive debonding release layer, preferably a photosensitive debonding release layer.
  • the purpose of setting the release layer is to facilitate the separation of the organic resin substrate 1 and the adhesive film 8 from the first temporary carrier.
  • the release layer can ensure that the double-sided tape (adhesive glue) and the cured adhesive film 8 are separated from the first temporary carrier. Peeling will not cause the first temporary carrier to break, adhesive residue, chip attach film to break, etc. due to the huge stress during peeling.
  • S103 Conduct circuit production on the pad side and the non-pad side of the substrate with the preset chip embedded to form a conductive circuit layer. Install the flip-chip bare chip on one of the conductive circuit layers and plastic seal it, and install it on the other conductive circuit layer. Ball planting; wherein, the conductive circuit layer is connected to the interconnection metal pillar, and the conductive circuit layer includes a first conductive circuit layer and a second conductive circuit layer.
  • the pad side in this article refers to the pad side of the preset chip
  • the non-pad side in this article also refers to the non-pad side of the preset chip
  • Step (1) as shown in Figure 2-9, grind the pad side of the substrate 1 to expose the pad of the preset chip 7; conduct circuit fabrication on the pad side of the ground substrate 1 to form a first conductive circuit layer 10;
  • the pad side of the plastic-sealed organic resin substrate 1 is polished to expose the pad of the predetermined chip.
  • grinding can use mechanical grinding to grind away the plastic sealing material and metal layer on the upper surface of the bonding pad side of the predetermined chip, so that all the metal layers on the bonding pad side surface of the organic resin substrate 1 are ground away and the solder joints on the surface of the predetermined chip are exposed. plate. Because the surface of the organic resin substrate 1 has high flatness, a highly flat surface can be obtained after grinding the organic resin substrate 1 , which is beneficial to the production of fine circuits.
  • forming the first conductive circuit 10 on the pad side of the ground organic resin substrate 1 specifically includes:
  • the stacking method is used to make several cyclic conductive circuits on the pad side of the preset chip, and each time the semi-additive method is used to produce the first connection line with a preset number of layers.
  • the stacking method is used to perform several cycles on the pad side of the preset chip to produce a target number of conductive circuit layers.
  • the conductive circuit layer includes conductive circuits and insulating media.
  • the semi-additive method is preferred for the production of conductive lines.
  • the photoresist material is selected according to the fineness of the conductive lines. Liquid photosensitive glue is preferred for lines below 8 ⁇ m, and dry film is preferred for lines 8 ⁇ m and above. Select the insulating medium according to the fineness of the conductive lines. Photosensitive polyimide is preferred for lines below 8 ⁇ m, ABF (Ajinomoto build-up film) is preferred for lines 8 ⁇ m and above, and glass fiber cloth reinforced for lines 50 ⁇ m and above. Epoxy resin.
  • the process of forming the first conductive circuit layer 10 is an existing technology and will not be described again here.
  • a surface treatment layer can also be formed on the side of the first conductive circuit layer on the side of the buried chip pad that is far away from the buried chip pad.
  • the preferred method for making the surface treatment layer is electroless nickel gold, and optional electroplating nickel gold, immersion silver, organic solder mask, and spray tin are optional.
  • Step (2) install the flip-chip bare chip 11 on the first conductive circuit layer 10. As shown in Figure 2-12, fill the bottom of the flip-chip bare chip 11 with the filler 13 and plastic seal it. Flip-chip bare chip 11;
  • the pad of the bare chip 11 is installed on the first conductive circuit layer 10 .
  • a non-conductive adhesive film is used to pre-attach the flip-chip bare chip, and then the thermal pressure bonding method is preferably used for mounting. Install the bare chip to achieve the function of using conductive adhesive film material to fill the bottom of the chip.
  • the flip-chip bare chip 11 is plastic-sealed with a plastic sealing material 9.
  • the plastic sealing material 9 is filled above the first conductive circuit layer 10 to form a plastic sealing layer.
  • the height of the plastic sealing layer is not lower than the height of the flip-chip bare chip.
  • the plastic sealing method is preferably compression molding, and the plastic sealant can be an epoxy sealant, preferably granular or liquid sealant, and film-type sealant can also be used.
  • the plastic sealing method can also be vacuum lamination. When vacuum lamination is used, only film-type epoxy plastic sealants can be used.
  • Step (3) attach the second temporary carrier 15 to the plastic side of the flip-chip bare chip
  • the first temporary carrier 6 and the second temporary carrier 15 are hard carriers, and the hard carrier is one of a glass carrier, a stainless steel carrier, or a silicon wafer carrier. kind.
  • the second conductive circuit layer 14 When forming the second conductive circuit layer 14 on the surface of the substrate on the non-pad side of the buried chip, add a second temporary carrier 15 on the pad side of the buried chip, that is, above the first conductive circuit layer 10, and The surface of the substrate on both sides is ground to obtain a highly flat surface to increase the density of conductive circuits embedded on the non-pad side of the chip, thereby increasing the overall packaging density of the package. Of course, this is also to adapt to the relatively increased demand for conductive lines in actual chip (transistor) density in the package.
  • Step (4) remove the first temporary carrier 6, grind and remove the non-pad side of the substrate, that is, the copper layer, and conduct circuit fabrication on the non-pad side of the substrate to form the second conductive circuit layer 14;
  • the multilayer method is used to fabricate a target number of conductive circuit layers on the non-pad side of the embedded chip through multiple cycles.
  • the conductive circuit layer includes conductive circuits and insulating media.
  • the semi-additive method is preferred for making conductive lines.
  • the photoresist material is selected according to the fineness of the conductive lines.
  • Liquid photosensitive glue is preferred for lines below 8 ⁇ m, and dry film is preferred for lines 8 ⁇ m and above.
  • the insulating medium is selected according to the fineness of the conductive lines. For lines below 8 ⁇ m, dry film is preferred.
  • Photosensitive polyimide is preferred for the following lines, ABF is preferred for lines of 8 ⁇ m and above, and glass fiber cloth reinforced epoxy resin can be selected for lines of 50 ⁇ m and above.
  • the process of forming the second conductive circuit layer 14 is an existing technology and will not be described again here.
  • Step (5) remove the second temporary carrier 15, and plant balls on the second conductive circuit layer 14 to form BGA solder balls 16.
  • it includes: releasing the second temporary carrier 15 on the flip-chip side, debonding the method according to the type of release layer, and removing the remaining adhesive layer. Then, balls are planted on the second conductive circuit layer on the non-pad side of the buried chip away from the surface of the buried chip to form BGA (Ball Gird Array, ball grid array package) solder balls 16. Balls are planted on the surface to form BGA solder balls 16. In order to solder the three-dimensional packaging structure to a printed circuit board or other chip surface.
  • BGA All Gird Array, ball grid array package
  • ball implantation is performed on the conductive circuit layer with the surface treatment layer.
  • conductive circuit layers are formed on the pad side and the non-pad side of the substrate on which the preset chip is embedded, and a flip-chip bare chip is installed on one of the conductive circuit layers and plastic-sealed.
  • the details of ball planting on another conductive circuit layer include:
  • Step (1) as shown in Figure 3-1, grind the pad side of the substrate 1 until the pad of the preset chip 7 is exposed; perform circuit fabrication on the pad side of the polished substrate 1 to form a first conductive circuit layer 10;
  • step 1 the steps between embedding the preset chip on the substrate and forming the first conductive circuit layer on the substrate are the same as step (1) in the previous embodiment.
  • step 2-1 to Figure 2-10 the steps between embedding the preset chip on the substrate and forming the first conductive circuit layer on the substrate are the same as step (1) in the previous embodiment.
  • Figure 2-1 to Figure 2-10 the steps between embedding the preset chip on the substrate and forming the first conductive circuit layer on the substrate are the same as step (1) in the previous embodiment.
  • Figure 2-1 to Figure 2-10 see Figure 2-1 to Figure 2-10 and the corresponding The relevant records will not be repeated in this step.
  • Step (2) attach the second temporary carrier 15 on the first conductive circuit layer 10, and remove the first temporary carrier 6; then, as shown in Figure 3-4, remove by grinding On the non-pad side of the substrate behind the first temporary carrier, as shown in Figure 3-5, circuit fabrication is performed on the non-pad side of the substrate to form a second conductive circuit layer;
  • the second temporary carrier 15 includes: attaching the second temporary carrier 15 to the upper surface of the first conductive circuit layer 10, removing the first temporary carrier 6, grinding off the adhesive and the metal layer on the surface of the organic resin substrate 1, and grinding off the preset Thickness of the attach film embedded in the non-pad side of the chip.
  • Circuit fabrication is performed on the non-pad side of the substrate 1 to form the second conductive circuit layer 14 .
  • the production of the second conductive circuit layer 14 belongs to the existing technology and will not be described again here.
  • Step (3) install the flip-chip bare chip 11 on the second conductive circuit layer 14, as shown in Figure 3-6, fill the bottom of the flip-chip bare chip 11 with the filler 13, and plastic seal Flip chip bare chip 11;
  • the method includes: the pad of the bare chip 11 is connected to the second conductive circuit layer 14 through the micro bumps 12, the gap between the bare chip 11 and the second conductive circuit layer 14 is filled with filler, and the plastic sealing material 9 is used to flip the bare chip.
  • the plastic sealant 9 is filled on the side of the second conductive circuit layer 14 away from the non-pad side of the embedded chip to form a plastic sealant layer.
  • the height of the plastic sealant layer is not lower than the height of the flip-chip bare chip.
  • Step (4) as shown in FIG. 3-7 , remove the second temporary carrier 15 and plant balls on the first conductive circuit layer 10 to form BGA solder balls 16 .
  • the second temporary carrier 15 is removed, and balls are planted on the first conductive circuit layer 10 to form BGA solder balls 16.
  • the purpose of ball planting is to solder the three-dimensional packaging structure to the printed circuit board or other chip surface. .
  • the flip chip is located on the non-pad side of the buried chip.
  • higher density lines and more solder balls can be arranged on the pad side of the buried chip (when the solder balls are located on the non-pad side of the buried chip, their number is affected by Limited to the density of interconnected copper pillars), a package with a higher overall chip (transistor) density can be obtained, and in particular, a higher transistor density of buried chips or more chips can be used.
  • the method for making a three-dimensional packaging structure provided by this application three-dimensionally packages bare chips together, which can further reduce the thickness of the package body and increase the packaging density compared to stacked packaging.
  • the use of organic resin substrates to assist chip molding can not only make interconnection metal pillars with high density, low cost and high yield, but also improve the mechanical strength of the chip molding layer, which is especially suitable for large-size advanced packaging. In addition, it can also reduce the amount of plastic packaging material and reduce the material cost of plastic packaging.
  • the use of organic resin substrates to assist chip molding can improve the anti-warping ability of the package, which is beneficial to realizing larger-sized packages and improving the integration of packaged products. Using a temporary carrier to assist in molding the chip.
  • choosing a temporary carrier with small thermal expansion and isotropy can significantly improve the predictability of the chip position deviation during chip molding, the position accuracy after chip molding, and the chip pad side. Alignment accuracy of conductive lines and chips.
  • Temporary carriers have been used many times to assist circuit production. Specifically, choosing a high-flatness temporary carrier and combining it with grinding technology can obtain a high-flatness surface, which is beneficial to the production of high-precision conductive circuits and improves chip packaging density.
  • An embodiment of the present application provides a schematic diagram of a three-dimensional packaging structure.
  • the three-dimensional packaging structure includes:
  • a substrate of organic resin material the substrate has a through hole, and interconnecting metal pillars are electroplated in the through hole;
  • the substrate has a through slot, and a preset chip is embedded and plastic-sealed in the through slot;
  • Conductive circuit layers are provided on both sides of the substrate, and the conductive circuit layers are connected to interconnecting metal pillars; a flip-chip bare chip is installed on one of the conductive circuit layers and plastic-sealed, and balls are planted on the other conductive circuit layer.
  • a first conductive circuit layer 10 is provided on the pad side of the substrate 1 with the preset chip 7 embedded; a first conductive circuit layer 10 is provided on the non-pad side of the substrate 1 with the preset chip 7 embedded.
  • the first conductive circuit layer 10 and the second conductive circuit layer 14 are connected to the interconnection metal pillars 3;
  • the flip-chip bare chip 11 is mounted on the first conductive circuit layer 10 and plastic-sealed.
  • the bottom of the flip-chip bare chip 11 is filled with filler 13; balls are planted on the second conductive circuit layer 14.
  • the substrate 1 is a substrate of organic resin material.
  • a plastic sealing material 9 is filled between the embedded preset chip 7 and the inner wall of the substrate.
  • a plastic sealing compound 9 is filled between the flip-chip bare chip 11 and the first conductive circuit layer 10.
  • the non-pad side of the embedded preset chip 7 is in contact with the second conductive circuit layer 10.
  • a first conductive circuit layer 10 is provided on the pad side of the substrate 1 with the preset chip 7 embedded; there is no soldering on the substrate 1 with the preset chip 7 embedded.
  • a second conductive circuit layer 14 is provided on the disk side;
  • the first conductive circuit layer 10 and the second conductive circuit layer 14 are connected to the interconnection metal pillars 3;
  • the flip-chip bare chip 11 is mounted on the second conductive circuit layer 14 and plastic-sealed.
  • the bottom of the flip-chip bare chip 11 is filled with filler 13; balls are planted on the first conductive circuit layer 10.
  • the filler 13 at the bottom of the flip-chip die is a non-conductive adhesive film or a capillary underfill adhesive.
  • the substrate 1 is a substrate made of organic resin material.
  • a plastic sealing material 9 is filled between the embedded preset chip 7 and the substrate groove wall.
  • a plastic sealing compound 9 is filled between the flip-chip bare chip 11 and the second conductive circuit layer 14.
  • the embedded preset chip 7 is filled with a plastic sealant 9. It is assumed that there is an adhesive film 8 between the non-pad side of the chip 7 and the second conductive circuit layer 14 .
  • the three-dimensional packaging structure provided by this application uses bare chip stacked packaging, which has a higher packaging density. It also has the advantages of high flatness of the temporary carrier, small chip drift, and good predictability. In addition, it also has the advantages of low production cost of interconnected metal columns, short flow distance of plastic sealing materials, low difficulty in processing and transportation, and good warpage resistance.

Abstract

本申请公开了一种立体封装结构及其制作方法，制作方法包括：提供有机树脂材料的基板，在基板上加工通孔，并在通孔内进行电镀，形成互连金属柱；在基板的设定位置处加工通槽，将预设芯片埋设在通槽内并塑封；在埋设有预设芯片的基板上焊盘侧和非焊盘侧分别进行线路制作形成导电线路层，在其中一个导电线路层上安装倒装裸芯片并塑封，在另一个导电线路层上植球；其中，导电线路层与互连金属柱连接，导电线路层包括第一导电线路层和第二导电线路层。本申请的立体封装结构封装厚度小，封装密度高，三维互连结构的密度高、制作成本低、芯片表面线路精细度高。

Description

立体封装结构及其制作方法
本申请以2022年7月21日提交的申请号为202210859669.0，名称为“立体封装结构及其制作方法”的中国发明申请为基础，并要求其优先权。
技术领域
本申请涉及半导体封装领域，尤其涉及一种立体封装结构及其制作方法。
背景技术
在现代芯片封装技术中，一个广泛应用的芯片封装技术就是堆叠封装(Package on Package，PoP)，其主要思路就是逻辑芯片顶部堆叠封装(或倒装)一个存储芯片，当然，也可以进一步在逻辑芯片顶部贴装被动元件。
芯片堆叠封装最大的一个技术挑战是底部封装体与顶部封装体的互连问题。目前，底部封装体与顶部封装体的互连主要采用三类方法：
第一类方法是基于传统封装技术，即在封装基板上塑封好芯片后，作为底部封装体，然后在底部封装体的塑封层钻孔，通过在孔内填塞导电膏来实现互连，然后在底部封装体的顶部倒装已经封装好的顶部封装体。
第二类方法是基于先进封装技术，首先，在一个临时载体上制作种子层，然后贴干膜电镀出铜柱，并蚀刻种子层，这样就得到了一个三维的互连结构，进一步地贴装芯片，最后塑封芯片，研磨露出铜柱，这样就得到了三维互连结构，制作获得底部封装体，然后再将底部封装体焊接再印刷电路板上，并在底部封装体上焊接顶部封装体。
第三类方法也是基于先进封装技术，首先，在一个印制电路板用的有机树脂芯板上加工通孔，然后电镀实现有机树脂芯板的两侧互连，然后在指定位置加工通槽，然后在依次贴胶带，并把芯片贴附在通槽内的胶带上，最后塑封芯片，这样得到了一个三维互连结构。制作获得底部封装体，然后再将底部封装体焊接再印刷电路板上，并在底部封装体上焊接顶部封装体。
发明人意识到，在上述所有方法中，由于顶部封装体一般是一个已经封装好的芯片，由于顶部封装体的厚度较厚，因此，存在封装密度较低，三维互连结构的密度低、制作成本高、芯片表面线路精细度不高等问题。
发明内容
基于此，提供一种立体封装结构及其制作方法，以解决现有技术存在的封装密度较低，三维互连结构的密度低、制作成本高、芯片表面线路精细度不高的问题。
本申请实施例提供了一种立体封装结构的制作方法，所述制作方法包括：
提供有机树脂材料的基板，在所述基板上加工通孔，并在所述通孔内进行电镀，形成互连金属柱；
在所述基板的设定位置处加工通槽，将预设芯片埋设在所述通槽内并塑封；
在埋设有所述预设芯片的基板上焊盘侧和非焊盘侧分别进行线路制作形成导电线路层，在其中一个导电线路层上安装倒装裸芯片并塑封，在另一个导电线路层上植球；其中，所述导电线路层与所述互连金属柱连接，所述导电线路层包括第一导电线路层和第二导电线路层。
本申请提供的立体封装结构的制作方法，将裸芯片立体封装在一起，相对于堆叠封装，可以进一步降低封装体厚度，提高封装密度。采用有机树脂基板辅助芯片塑封，既可以高密度、低成本以及高良率制作互连金属柱，又可以提高芯片塑封层的机械强度，尤其适用于大尺寸先进封装。除此之外，还可以减少塑封料的用量，降低塑封的材料成本。采用有机树脂基板辅助芯片塑封，可以提高封装体的抗翘曲能力，有利于实现更大尺寸的封装体和提高封装产品的集成度。采用临时载体辅助塑封芯片，具体来讲，选择热膨胀较小且各向同性的临时载体，可以显著提高芯片塑封时芯片位置偏移的可预测性、芯片塑封后的位置精度以及芯片焊盘侧导电线路与芯片的对位精度。多次采用临时载体辅助线路制作，具体来讲，选择高平整度的临时载体，结合研磨技术，可以得到高平整度的表面，有利于制作高精度导电线路，提高芯片封装密度。
本申请实施例提供了一种立体封装结构，所述结构包括：
有机树脂材料的基板，所述基板具有通孔，所述通孔内电镀有互连金属柱；
所述基板开有通槽，所述通槽内埋设并塑封有预设芯片；
所述基板的两侧分别设置有导电线路层，所述导电线路层与所述互连金属柱连接；在其中一个导电线路层上安装有倒装裸芯片并塑封，另一个导电线路层上植球。
本申请提供的立体封装结构，与常规堆叠封装技术相比，结构上使用裸芯片堆叠封装，封装密度更高。该立体封装结构同时具备了导电线路的密度高、芯片漂移小，可预测性好的优点。除此之外，还具备互连金属柱制作成本低、塑封料流胶距离短、加工转运难度低以及抗翘曲能力好的优点。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例的描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本申请一实施例提供的立体封装结构的制作方法的流程图；
图2-1是本申请一实施例提供的在基板上加工通孔示意图；
图2-2是本申请一实施例提供的在基板上通孔电镀示意图；
图2-3是本申请一实施例提供的在基板上加工通槽示意图；
图2-4是本申请一实施例提供的在基板上粘贴粘结胶示意图；
图2-5是本申请一实施例提供的将基板上通槽内粘结胶去除后的示意图；
图2-6是本申请一实施例提供的将基板上通过粘结胶粘贴第一临时载体的示意图；
图2-7是本申请一实施例提供的将预设芯片粘贴在第一临时载体上通槽内的示意图；
图2-8是本申请一实施例提供的将预设芯片塑封在通槽内的示意图；
图2-9是本申请一实施例提供的将预设芯片塑封层研磨的示意图；
图2-10是本申请一实施例提供的在基板表面形成第一导电线路示意图；
图2-11是本申请一实施例提供的在第一导电线路上倒装裸芯片示意图；
图2-12是本申请一实施例提供的在第一导电线路的倒装裸芯片底部填充填充剂并塑封示意图；
图2-13是本申请一实施例提供的在倒装裸芯片侧贴第二临时载体，并去除第一临时载体示意图；
图2-14是本申请一实施例提供的在基板移除第一临时载体侧进行研磨的示意图；
图2-15是本申请一实施例提供的在基板移除第一临时载体侧制作第二导电线路层示意图；
图2-16是本申请一实施例提供的在基板上第二导电线路层上植球示意图；
图3-1是本申请另一实施例提供的对第一导电线路层进行研磨的示意图；
图3-2是本申请另一实施例提供的第一导电线路层上贴附第二临时载体并去除第一临时载体的示意图；
图3-3是本申请另一实施例提供的第一导电线路层上贴附第二临时载体并去除第一临时载体的示意图；
图3-4是本申请另一实施例提供的第二导电线路层进行研磨的示意图；
图3-5是本申请另一实施例提供的第二导电线路层上倒装裸芯片的示意图；
图3-6是本申请另一实施例提供的第二导电线路层上塑封裸芯片的示意图；
图3-7是本申请另一实施例提供的在第一导电线路上植球的示意图。
其中，1为有机树脂基板，2为通孔，3为互连金属柱，4为通槽，5为粘结胶，6为第一临时载体，7为芯片，8为贴附膜，9为塑封料，10为第一导电线路层，11为裸芯片，12为微凸点，13为填充剂，14为第二导电线路，15为第二临时载体，16为BGA锡球。
具体实施方式
为了说明本申请的技术方案，下面通过具体实施例来进行说明。
参见图1，是本申请一实施例提供的立体封装结构的制作方法的流程图，所述方法包括：
S101、提供有机树脂材料的基板，在基板上加工通孔，并在通孔内进行电镀，形成互连金属柱。
参见图2-1和图2-2，在一示例中，“提供有机树脂材料的基板1，在基板1加工通孔2，并在通孔2内进行电镀，形成互连金属柱3”具体包括：
提供有机树脂材料的基板1，在基板1上需要制作互连金属柱3的位置加工通孔2；
制作种子层，并电镀通孔2，获得互连金属柱3，基板1表面完整覆盖铜层即金属层。
具体来讲，选取有机树脂基板1一张，作为优选地，有机树脂基板1可以为表面覆盖铜箔的有机树脂基板1，在有机树脂基板1需要制作互连金属柱3的预设位置处加工通孔2。在有机树脂基板1上加工通孔2的方法可以选用机械钻在有机树脂基板1上钻取通孔2，也可以采用激光来对有机树脂基板1进行照射出通孔2。
通孔内壁需要进行种子层制作，目前行业内常用的几种种子层制作方法为：
(1)溅射(PVD)或蒸镀(CVD)，这种情况下，表面和孔壁都会附着金属层，金属一般为铜、Ti、Ni、Cr、Au中的一种或两种，最常见的是Ti/Cu。
(2)化学镀铜，利用还原剂催化还原(催化剂是Pd)，在表面和孔壁都会附着金属铜层。
(3)吸附导电物，如石墨、炭黑、氧化石墨烯、高分子导电聚合物，只会在孔壁(没有铜)的位置吸附。
在本申请中，优选顺序为化学镀铜＞溅射/蒸镀＞吸附导电物。
电镀通孔2是指将有机树脂基板1的通孔2进行电镀，电镀材料可以为金属铜，电镀方式为：采用直流电镀或脉冲电镀来使得有机树脂基板1的通孔2内填充金属，来形成互连金属柱3。
S102、在基板的设定位置处加工通槽，将预设芯片埋设在通槽内并塑封。
参见图2-3至图2-8，在有机树脂基板1需要埋入预设芯片7的位置加工通槽4，通槽4的尺寸大于预设芯片的尺寸。可选地，通槽4的空间可以容纳一个芯片或两个及以上数量的芯片。在有机树脂基板1上加工通槽4的方式可以为采用激光对有机树脂基板1进行加工，使得有机树脂基板1露出通槽4；还可以采用机械加工的方式使得有机树脂基板1露出通槽4。
在一示例中，“将预设芯片埋设在通槽内并塑封”具体包括：
如图2-4所示，先将粘结胶粘贴在基板1一侧，然后如图2-5所示，将通槽下的粘结胶5去除；然后如图2-6所示，利用粘结胶5将基板1一侧粘结在第一临时载体6上；如图2-7所示，利用贴附膜8将所述预设芯片7贴附在第一临时载体6上的通槽4内，预设芯片7的焊盘远离第一临时载体6；塑封通槽内的预设芯片。
在预设芯片7的非焊盘侧采用贴附膜8来替代原本的胶带，将预设芯片7贴装到热膨胀系数匹配性好、均一性好的第一临时载体6上，规避了原有技术方案中胶带热膨胀系数差异大带来的预设芯片7大幅度漂移的问题，而且采用树脂固化固定方式的芯片贴附膜的固定效果也比粘度受温度影响大的胶带的固定效果更好。
在一示例中，粘结胶5为双面粘结胶，一面用于贴附于有机树脂基板1的一侧，另一面用于粘结在第一临时载体6上。粘结胶5的作为用将有机树脂基板1更好的固定于第一临时载体6上。
然后，如图2-8所示，塑封通槽内的预设芯片7，其具体包括：
将塑封料9填充于有机树脂基板1的通槽槽壁与预设芯片7之间的缝隙且覆盖有机树脂基板1的上表面。当一个通槽内放置两个以上预设芯片时，塑封料还要填充预设芯片之间的缝隙。
塑封料9也称环氧塑封料是电子元器件的封装材料,它是以环氧树脂、酚醛树脂为基体树脂,硅微粉为填料配合多种助剂加工制成的，为现有技术。
塑封料9可以为颗粒型、液态型或者薄膜型，塑封方式可以为压缩成型或真空贴膜，当采用真空贴膜塑封时，只能使用薄膜型环氧塑封料。
在一示例中，第一临时载体6靠近有机树脂基板1的一侧设有离型层，贴附膜贴附于离型层上。
离型层可以为光敏解键合离型层，还可以是热敏解键合离型层，优选光敏解键合离型层。
离型层设置的目的为方便有机树脂基板1和贴附膜8与第一临时载体剥离，离型层可以保证双面胶(粘结胶)和固化的贴附膜8从第一临时载体上剥离，不会因为剥离时巨大的应力而导致第一临时载体碎裂、粘结胶残留、芯片贴附膜碎裂等。
S103、在埋设有预设芯片的基板上焊盘侧和非焊盘侧分别进行线路制作形成导电线路层，在其中一个导电线路层上安装倒装裸芯片并塑封，在另一个导电线路层上植球；其中，导电线路层与互连金属柱连接，导电线路层包括第一导电线路层和第二导电线路层。
特别说明的是，文中焊盘侧均指的是预设芯片焊盘侧，文中非焊盘侧也均指的是预设芯片的非焊盘侧。
参见图2-9至图2-16，在一示例中，“在埋设有预设芯片的基板上焊盘侧和非焊盘侧分别进行线路制作形成导电线路层，在其中一个导电线路层上安装倒装裸芯片并塑封，在另一个导电线路层上植球”具体包括：
步骤(1)，如图2-9所示，研磨基板1的焊盘侧至露出预设芯片7的焊盘；在研磨后的基板1上焊盘侧进行线路制作，形成第一导电线路层10；
具体来讲，对塑封后的有机树脂基板1的焊盘侧进行研磨，以露出预设芯片的焊盘。其中，研磨可以采用机械研磨的方式，研磨掉预设芯片焊盘侧上表面的塑封料以及金属层，使得有机树脂基板1焊盘侧表面金属层全部被研磨掉且露出预设芯片表面的焊盘。因为有机树脂基板1表面的平整度高，因此，有机树脂基板1研磨过后可以得到高平整度的表面，这有利于制作精细的线路。
如图2-10所示，在研磨后的有机树脂基板1的焊盘侧制作形成第一导电线路10具体包括：
采用积层法在预设芯片的焊盘侧进行若干次循环导电线路制作，每次均采用半加成法进行制作，得到预设层数的第一连接线路。
采用积层法在预设芯片的焊盘侧进行若干次循环制作得到目标层数导电线路层，导电线路层包括导电线路、绝缘介质。导电线路的制作优选半加成法，根据导电线路精细程度选择光阻材料，8μm以下线路优选液态感光胶，8μm及以上线路优选干膜。根据导电线路精细程度选择绝缘介质，8μm以下线路优选感光聚酰亚胺，8μm及以上线路优选ABF(Ajinomoto build-up film，味之素堆积膜)，50μm及以上线路可以选择玻璃纤维布增强的环氧树脂。
制作形成第一导电线路层10的过程为现有技术，在此不再赘述。
在一示例中，为保证后续安装倒装裸芯片的可靠性，还可以在埋入芯片焊盘侧第一导电线路层远离埋入芯片焊盘的一面制作表面处理层。其中，表面处理层的制作方法优选化学镍金，可选电镀镍金、浸银、有机阻焊膜和喷锡。
步骤(2)，如图2-11所示，在第一导电线路层10上安装倒装裸芯片11，如图2-12所示，在倒装裸芯片11底部进行填充剂13填充，塑封倒装裸芯片11；
具体包括：裸芯片11的焊盘安装在第一导电线路层10上。当倒装裸芯片11凸点尺寸较小，倒装裸芯片尺寸较大时，采用非导电胶膜预先贴附在所述倒装裸芯片上，再优选热压键合方法贴装，安装倒装裸芯片，达到利用导电胶膜材料实现芯片底部填充的作用。
当倒装裸芯片凸点尺寸较大，且倒装裸芯片尺寸较小时，优选批量回流焊工艺安装芯片，并优选非导电胶膜或毛细管底部填充胶实现芯片底部填充。采用塑封料9对倒装裸芯片11塑封，塑封料9被填充于第一导电线路层10上方，形成塑封层，塑封层的高度不低于倒装裸芯片的高度。塑封方式优选压缩成型，塑封料可以为环氧塑封料，优选颗粒型和液态型的塑封料，也可以使用薄膜型的塑封料。塑封方式也可以是真空贴膜，其中，当使用真空贴膜塑封时，只能使用薄膜型环氧塑封料。
步骤(3)，如图2-13所示，在倒装裸芯片的塑封料一侧贴附第二临时载体15；
具体包括：在上述倒装裸芯片上方贴附第二临时载体15，第一临时载体6和第二临时载体15为硬质载体，硬质载体为玻璃载体、不锈钢载体或硅片载体中的一种。
在埋入芯片非焊盘侧的基板表面制作第二导电线路层14时，在埋入芯片焊盘侧即第一导线线路层10上方增加第二临时载体15，并对埋入芯片非焊盘侧的基板表面进行研磨，从而获得高平整度的表面，以提高埋入芯片非焊盘侧导电线路的密度，从而提高封装体整体的封装密度。当然，这也是为了适应于封装体中实际芯片(晶体管)密度相对提高对导电线路的需求。
步骤(4)，移除第一临时载体6，研磨移除第一临时载体6后基板的非焊盘侧即铜层，在基板的非焊盘侧进行线路制作形成第二导电线路层14；
具体包括：如图2-14所示，将第一临时载体6去掉，研磨移除第一临时载体6后基板1的非焊盘侧，研磨掉粘结层以及基板表面的金属层即铜层，此时，芯片焊盘侧仍有预设厚度的贴附膜。研磨基板的非焊盘侧时，在铜柱位置没有直径略大于铜柱的连接盘，这也有利于提高该侧导电线路的设计密度。
在一示例中，如图2-15所示，采用积层法在埋入芯片非焊盘侧多次循环制作得到目标层数导电线路层，导电线路层包括导电线路、绝缘介质。
在一示例中，导电线路制作优选半加成法，根据导电线路精细程度选择光阻材料，8μm以下线路优选液态感光胶、8μm及以上线路优选干膜；根据导电线路精细程度选择绝缘介质，8μm以下线路优选感光聚酰亚胺、8μm及以上线路优选ABF，50μm及以上线路可以选择玻璃纤维布增强的环氧树脂。
制作形成第二导电线路层14的过程为现有技术，在此不再赘述。
步骤(5)，如图2-16所示，移除第二临时载体15，在第二导电线路层14上植球，形成BGA锡球16。
具体包括：解除倒装芯片侧的第二临时载体15，解键合方式根据离型层类型决定，并除去残留的粘结层。然后在埋入芯片非焊盘侧的第二导电线路层远离埋入芯片的表面植球，形成BGA(Ball Gird Array，球栅阵列封装)锡球16，表面植球，形成BGA锡球16是为了将该立体封装结构焊接到印制电路板或其他芯片表面。
在埋入芯片焊盘侧直接倒装裸芯片并整体塑封裸芯片，而不是焊接已经封装好的芯片，这进一步降低了封装体的厚度，也可以提高整个封装体中的芯片密度(晶体管密度)。
在一示例中，在需要植球的导电线路层上制作表面处理层之后，是在制作有表面处理层的导电线路层上进行植球。
在另一示例中，在埋设有所述预设芯片的基板上焊盘侧和非焊盘侧分别进行线路制作形成导电线路层，在其中一个导电线路层上安装倒装裸芯片并塑封，在另一个导电线路层上植球具体包括：
步骤(1)，如图3-1所示，在研磨基板1的焊盘侧至露出预设芯片7的焊盘；在研磨后的基板1上焊盘侧进行线路制作，形成第一导电线路层10；
本步骤中，在基板上嵌入预设芯片并在基板上形成第一导电线路层之间的步骤与前述实施例中的步骤(1)相同，具体参见图2-1至图2-10及对应的相关记载，本步骤中不再赘述。
步骤(2)，如图3-2所示，在第一导电线路层10上贴附第二临时载体15，并移除第一临时载体6；然后如图3-4所示，研磨移除第一临时载体后基板的非焊盘侧，如图3-5所示，在基板的非焊盘侧进行线路制作形成第二导电线路层；
具体包括:在第一导电线路层10的上表面贴附第二临时载体15，将第一临时载体6移除，研磨掉粘结胶以及有机树脂基板1表面的金属层，并且研磨掉预设厚度的埋入芯片非焊盘侧的贴附膜。在基板1的非焊盘侧进行线路制作形成第二导电线路层14。制作第二导电线路层14属于现有技术，在此不再赘述。
步骤(3)，如图3-5所示，在第二导电线路层14上安装倒装裸芯片11，如图3-6所示，在倒装裸芯片11底部进行填充剂13填充，塑封倒装裸芯片11；
具体包括：裸芯片11的焊盘通过微凸点12与第二导电线路层14相连，裸芯片11与第二导电线路层14之间用填充剂进行填充，采用塑封料9对倒装裸芯片塑封，塑封料9被填充于第二导电线路层14远离埋入芯片非焊盘侧的一面，形成塑封层，塑封层的高度不低于倒装裸芯片的高度。
步骤(4)，如图3-7所示，移除第二临时载体15，在第一导电线路层10上植球，形成BGA锡球16。
具体来讲，将第二临时载体15去掉，在第一导电线路层10上植球，形成BGA锡球16，植球的目的是为了将该立体封装结构焊接到印制电路板或其他芯片表面。
倒装芯片位于埋入芯片的非焊盘侧，本示例在埋入芯片焊盘侧可以排布更高密度线路和更多锡球(锡球位于埋入芯片非焊盘侧时，其数量受限于互连铜柱的密度)，因此可以获得总体芯片(晶体管)密度更高的封装体，尤其是可以使用更高晶体管密度的埋入芯片或埋入更多的芯片。
本申请提供的立体封装结构的制作方法，将裸芯片立体封装在一起，相对于堆叠封装，可以进一步降低封装体厚度，提高封装密度。采用有机树脂基板辅助芯片塑封，既可以高密度、低成本以及高良率制作互连金属柱，又可以提高芯片塑封层的机械强度，尤其适用于大尺寸先进封装。除此之外，还可以减少塑封料的用量，降低塑封的材料成本。采用有机树脂基板辅助芯片塑封，可以提高封装体的抗翘曲能力，有利于实现更大尺寸的封装体和提高封装产品的集成度。采用临时载体辅助塑封芯片，具体来讲，选择热膨胀较小且各 向同性的临时载体，可以显著提高芯片塑封时芯片位置偏移的可预测性、芯片塑封后的位置精度，以及芯片焊盘侧导电线路与芯片的对位精度。多次采用临时载体辅助线路制作，具体来讲，选择高平整度的临时载体，结合研磨技术，可以得到高平整度的表面，有利于制作高精度导电线路，提高芯片封装密度。
本申请一实施例提供的立体封装结构的示意图，该立体封装结构包括：
有机树脂材料的基板，基板具有通孔，通孔内电镀有互连金属柱；
基板开有通槽，通槽内埋设并塑封有预设芯片；
基板的两侧分别设置有导电线路层，导电线路层与互连金属柱连接；在其中一个导电线路层上安装有倒装裸芯片并塑封，另一个导电线路层上植球。
在一示例中，参见图2-16，在埋设有预设芯片的基板1上焊盘侧设置有第一导电线路层10；在埋设有预设芯片7的基板1上非焊盘侧设置有第二导电线路层14；
第一导电线路层10和第二导电线路层14与互连金属柱3连接；
第一导电线路层10上安装倒装裸芯片11并塑封，在倒装裸芯片11底部填充有填充剂13；第二导电线路层14上植球。
基板1为有机树脂材料的基板。埋设的预设芯片7与基板内壁之间填充有塑封料9，倒装裸芯片11与第一导电线路层10之间填充有塑封料9，埋设的预设芯片7非焊盘侧与第二导电线路层14之间还存在贴附膜8。
在另一示例中，参见图3-7，在埋设有预设芯片7的基板1上焊盘侧设置有第一导电线路层10；在埋设有所述预设芯片7的基板1上非焊盘侧设置有第二导电线路层14；
第一导电线路层10和第二导电线路层14与互连金属柱3连接；
第二导电线路层14上安装倒装裸芯片11并塑封，在倒装裸芯片11底部填充有填充剂13；第一导电线路层10上植球。
在一示例中，倒装裸芯片底部的填充剂13为非导电胶膜或毛细管底部填充胶。
基板1为有机树脂材料的基板.埋设的预设芯片7与基板槽壁之间填充有塑封料9，倒装裸芯片11与第二导电线路层14之间填充有塑封料9，埋设的预设芯片7非焊盘侧与第二导电线路层14之间还存在贴附膜8。本申请提供的立体封装结构，与常规堆叠封装技术相比，结构上使用裸芯片堆叠封装，封装密度更高,同时具备了临时载体平整度高、芯片漂移小以及可预测性好的优点。除此之外，还具备互连金属柱制作成本低、塑封料流胶距离短、加工转运难度低以及抗翘曲能力好的优点。

Claims (20)

  1. 一种立体封装结构的制作方法，其中，所述制作方法包括：
    提供有机树脂材料的基板，在所述基板上加工通孔，并在所述通孔内进行电镀，形成互连金属柱；
    在所述基板的设定位置处加工通槽，将预设芯片埋设在所述通槽内并塑封；
    在埋设有所述预设芯片的基板上焊盘侧和非焊盘侧分别进行线路制作形成导电线路层，在其中一个导电线路层上安装倒装裸芯片并塑封，在另一个导电线路层上植球；其中，所述导电线路层与所述互连金属柱连接，所述导电线路层包括第一导电线路层和第二导电线路层。
  2. 根据权利要求1所述的立体封装结构的制作方法，其中，所述“提供有机树脂材料的基板，在所述基板加工通孔，并在所述通孔内进行电镀，形成互连金属柱”具体包括：
    提供有机树脂材料的基板，在所述基板上需要制作互连金属柱的位置加工通孔；
    制作种子层，并电镀通孔，获得互连金属柱，所述基板表面完整覆盖铜层。
  3. 根据权利要求1所述的立体封装结构的制作方法，其中，所述“将预设芯片埋设在所述通槽内并塑封”具体包括：
    利用粘结胶将所述基板一侧粘结在第一临时载体上；利用贴附膜将所述预设芯片贴附在所述第一临时载体上的通槽内，所述预设芯片的焊盘远离所述第一临时载体；
    塑封所述通槽内的所述预设芯片。
  4. 根据权利要求3所述的立体封装结构的制作方法，其中，所述“在埋设有所述预设芯片的基板上焊盘侧和非焊盘侧分别进行线路制作形成导电线路层，在其中一个导电线路层上安装倒装裸芯片并塑封，在另一个导电线路层上植球”具体包括：
    研磨所述基板的焊盘侧至露出所述预设芯片的焊盘；在所述预设芯片焊盘侧进行线路制作，形成第一导电线路层；
    在所述第一导电线路层上安装倒装裸芯片，在所述倒装裸芯片底部进行填充剂填充，塑封所述倒装裸芯片；
    在所述倒装裸芯片的塑封料一侧贴附第二临时载体；
    移除所述第一临时载体，研磨移除所述第一临时载体后所述预设芯片非焊盘侧，在所述预设芯片非焊盘侧进行线路制作形成第二导电线路层；
    移除第二临时载体，在所述第二导电线路层上植球。
  5. 根据权利要求3所述的立体封装结构的制作方法，其中，所述“在埋设有所述预设芯片的基板上焊盘侧和非焊盘侧分别进行线路制作形成导电线路层，在其中一个导电线路层上安装倒装裸芯片并塑封，在另一个导电线路层上植球”具体包括：
    研磨所述基板的焊盘侧至露出所述预设芯片的焊盘；在研磨后的所述基板上焊盘侧进行线路制作，形成第一导电线路层；
    在所述第一导电线路层上贴附第二临时载体，并移除所述第一临时载体；研磨移除所述第一临时载体后预设芯片的非焊盘侧，在所述预设芯片的非焊盘侧进行线路制作形成第二导电线路层；
    在所述第二导电线路层上安装所述倒装裸芯片，在所述倒装裸芯片底部进行填充剂填充，塑封所述倒装裸芯片；
    移除所述第二临时载体，在所述第一导电线路层上植球。
  6. 根据权利要求1所述的立体封装结构的制作方法，其中，所述“进行线路制作形成导电线路层”具体包括：
    采用积层法多次循环制作得到目标层数导电线路层，所述导电线路层包括导电线路和绝缘介质。
  7. 根据权利要求6所述的立体封装结构的制作方法，其中，所述导电线路采用半加成法制作，所述绝缘介质为感光聚酰亚胺、薄复合材料或环氧树脂中的一种。
  8. 根据权利要求1所述的立体封装结构的制作方法，其中，所述在其中一个导电线路层上安装倒装裸芯片并塑封之前还包括：
    在安装所述倒装裸芯片的导电线路层上制作表面处理层。
  9. 根据权利要求8所述的立体封装结构的制作方法，其中，所述在另一个导电线路层上植球具体包括：
    在制作有所述表面处理层的导电线路层上植球。
  10. 根据权利要求4所述的立体封装结构的制作方法，其中，所述第一临时载体和所述第二临时载体为硬质载体，所述硬质载体为玻璃载体、不锈钢载体或硅片载体中的一种。
  11. 根据权利要求4所述的立体封装结构的制作方法，其中，所述在其中一个导电线路层上安装倒装裸芯片具体包括：
    采用批量回流焊工艺进行贴装，安装倒装裸芯片；安装所述倒装裸芯片后，采用毛细管底部填充胶在所述倒装裸芯片底部进行填充。
  12. 根据权利要求4所述的立体封装结构的制作方法，其中，所述在其中一个导电线路层上安装倒装裸芯片具体包括：
    采用非导电胶膜预先贴附在所述倒装裸芯片上，再采用热压键合方法进行贴装，安装倒装裸芯片。
  13. 根据权利要求3所述的立体封装结构的制作方法，其中，塑封所述通槽内的所述预设芯片包括：
    将塑封料填充于所述通槽的槽壁与所述预设芯片之间的缝隙，且覆盖所述基板的上表面。
  14. 根据权利要求13所述的立体封装结构的制作方法，其中，所述塑封料采用压缩成型或真空贴膜的塑封方式，对所述通槽内的所述预设芯片进行塑封。
  15. 根据权利要求3所述的立体封装结构的制作方法，其中，所述第一临时载体上靠近所述基板的一侧设置有离型层，所述贴附膜贴附在所述离型层上。
  16. 根据权利要求15所述的立体封装结构的制作方法，其中，所述离型层为光敏解键合离型层或热敏解键合离型层。
  17. 一种立体封装结构，其中，包括：
    有机树脂材料的基板，所述基板具有通孔，所述通孔内电镀有互连金属柱；
    所述基板开有通槽，所述通槽内埋设并塑封有预设芯片；
    所述基板的两侧分别设置有导电线路层，所述导电线路层与所述互连金属柱连接；在其中一个导电线路层上安装有倒装裸芯片并塑封，另一个导电线路层上植球。
  18. 根据权利要求17所述的立体封装结构，其中，在埋设有所述预设芯片的基板上焊盘侧设置有第一导电线路层；在埋设有所述预设芯片的基板上非焊盘侧设置有第二导电线路层；
    所述第一导电线路层和所述第二导电线路层与所述互连金属柱连接；
    所述第一导电线路层上安装所述倒装裸芯片并塑封，在所述倒装裸芯片底部填充有填充剂；所述第二导电线路层上植球。
  19. 根据权利要求17所述的立体封装结构，其中，在埋设有所述预设芯片的基板上焊盘侧设置有第一导电线路层；在埋设有所述预设芯片的基板上非焊盘侧设置有第二导电线路层；
    所述第一导电线路层和所述第二导电线路层与所述互连金属柱连接；
    所述第二导电线路层上安装所述倒装裸芯片并塑封，在所述倒装裸芯片底部填充有填充剂；所述第一导电线路层上植球。
  20. 根据权利要求17所述的立体封装结构，其中，在所述通槽的槽壁与所述预设芯片之间的缝隙处填充有塑封料。
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CN111739860A (zh) * 2019-03-25 2020-10-02 英特尔公司 用于模块化半导体装置的基于无机物的嵌入式管芯层
CN114050111A (zh) * 2021-11-16 2022-02-15 江苏芯德半导体科技有限公司 一种扇出型封装方法及扇出型封装结构

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