CN102057485A - 基于薄片的半导体封装 - Google Patents

基于薄片的半导体封装 Download PDF

Info

Publication number
CN102057485A
CN102057485A CN2009801213036A CN200980121303A CN102057485A CN 102057485 A CN102057485 A CN 102057485A CN 2009801213036 A CN2009801213036 A CN 2009801213036A CN 200980121303 A CN200980121303 A CN 200980121303A CN 102057485 A CN102057485 A CN 102057485A
Authority
CN
China
Prior art keywords
sheet metal
carrier
panel
etching
molding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2009801213036A
Other languages
English (en)
Inventor
W·王
N·T·屠
J·贝延
D·钱
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Semiconductor Corp
Original Assignee
National Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corp filed Critical National Semiconductor Corp
Publication of CN102057485A publication Critical patent/CN102057485A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49579Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582Metallic layers on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/544Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68377Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/5442Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54426Marks applied to semiconductor devices or parts for alignment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54473Marks applied to semiconductor devices or parts for use after dicing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852Applying energy for connecting
    • H01L2224/85201Compression bonding
    • H01L2224/85205Ultrasonic bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • H01L2224/854Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85439Silver (Ag) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • H01L2224/854Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85455Nickel (Ni) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • H01L2224/854Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85463Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/85464Palladium (Pd) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00011Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01015Phosphorus [P]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01028Nickel [Ni]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0105Tin [Sn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01075Rhenium [Re]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12041LED
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/157Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49121Beam lead frame or beam lead device
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126Assembling bases
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155Manufacturing circuit on or in base
    • Y10T29/49156Manufacturing circuit on or in base with selective destruction of conductive paths
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/12All metal or with adjacent metals
    • Y10T428/12431Foil or filament smaller than 6 mils
    • Y10T428/12438Composite

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明涉及在集成电路封装中使用薄的薄片来形成电互连的方法和装置。在一个实施例中,薄片载体结构将部分导电薄片超声接合到金属载体来形成。接合的部分定义薄片载体结构中的面板。在一些实施例中,薄片载体结构被切割以形成多个隔离的面板,这些面板沿着它们的外围被密封。每一个隔离的面板可以具有和常规的引线框带或者面板差不多的大小。因此,现有的封装设备可以被用于增加小片、接合导线和模塑材料到面板。超声焊接帮助防止在这种处理步骤期间不需要的物质渗入薄片载体结构。在模塑的薄片载体结构的载体部分被移除之后,该结构被单体化成集成电路封装。一些实施例涉及使用部分或者全部前述操作的方法。其它实施例涉及新的封装装置。

Description

基于薄片的半导体封装
技术领域
本发明总体涉及集成电路(IC)的封装。更具体地,本发明涉及包含薄片的封装方法和装置(arrangement)。
背景技术
有多种用于封装集成电路(IC)小片(dice)的常规方法。举例来说,许多IC封装使用已经从金属薄片被压印(stamp)或者蚀刻的金属引线框来提供到外部器件的电直连。芯片(die)可以通过接合导线(bonding wire)、焊料块或者其它合适的电连接被电连接到引线框。通常,芯片和部分引线框使用模塑(molding)材料封装来保护芯片的有源面(active side)上的精密的电子部件,与此同时使被选定的部分引线框暴露来辅助到外部装置的电连接。
许多常规的引线框具有大约4-8毫英寸(mil)的厚度。进一步减小引线框的厚度有几种好处,包括能够减小整体封装大小和节省引线框金属。但是,通常越薄的引线框在封装过程中更加倾向于弯曲。诸如带基(backing tape)的支撑结构可以被应用于引线框来降低扭曲的风险。但是,这种结构可能会带来更高的成本。
在不同的时期,封装设计被提议采用金属薄片来取代引线框作为电互连结构。尽管已经开发了多种基于薄片的设计,但是没有一种在工业中达到被广泛接受的程度,部分原因是基于薄片的封装过程往往比常规的引线框封装更加昂贵,而部分原因是大多现有的封装设备不能很好地适用于这种基于薄片的封装设计。
尽管用于制造引线框和使用引线框技术封装集成电路的现有技术较为适用,但是仍需继续的努力来开发用于封装集成电路的更加有效率的设计和方法。
发明内容
所要求保护的发明涉及在集成电路封装中使用薄的薄片来形成电互连的方法和装置。在一个实施例中,薄片载体结构通过将部分导电薄片超声接合到金属载体来形成。接合的部分定义薄片载体结构中的面板。在一些实施例中,薄片载体结构被切割以形成多个隔离的面板,这些面板沿着它们的外围被密封。每一个隔离的面板可以具有和常规的引线框带或者面板差不多的大小。因此,现有的封装设备可以被用于增加小片、接合导线和模塑材料到面板。超声焊接帮助防止在这种处理步骤期间不需要的物质渗入薄片载体结构。在模塑的薄片载体结构的载体部分被移除之后,该结构被单体化(singulate)成集成电路封装。一些实施例涉及使用部分或者全部前述操作的方法。其它实施例涉及新的封装装置。
在本发明的一些方面中,描述了形成前述的薄片载体结构的方法。该方法包括超声接合部分金属薄片到载体。根据特定应用的需要,金属薄片和载体的各自的厚度可以改变。举例来说,薄片厚度的范围大约从0.5到2毫英寸以及载体厚度的范围大约从5到10毫英寸较为适用。超声接合的部分可以形成定义薄片载体结构中的面板的平行的焊接线。在一些实施例中,超声接合的部分围绕每个面板形成连续的周边。
其它金属可以被加入到薄片中以减少电迁移和辅助后面的导线接合。在一些实施例中,方法包括使用诸如银合金的金属对金属薄片的上表面进行点镀(spot plating)来形成多个器件区域。代替点镀,银的连续的层可以被涂覆到薄片的表面。在其它实施例中,镍、钯和/或金被涂覆到薄片的一面或者两面。还可以使用其它薄片金属化层。
在本发明的另一个方面中,描述了封装集成电路器件的方法。该方法涉及将多个小片附着到薄片载体结构上。薄片载体结构可以采取上述的薄片载体结构的形式,尽管这不是必须的。例如,薄片载体结构的一些实施例使用粘合剂来代替超声接合将薄片接合到载体。该方法还包括使用模塑材料封装部分金属薄片和小片,以及移除载体。在载体从模塑的薄片载体结构被移除之后,蚀刻薄片从而暴露一部分模塑材料。蚀刻定义薄片中的器件区域。每个器件区域被配置成电连接到集成电路芯片。在蚀刻步骤之后,该结构被单体化以形成集成电路封装。
还可能有其它特征。封装可以包括以连续带的形式涂覆模塑材料。在一些方面,金属薄片包括贱金属(铜)层和银涂覆层。在其它方面中,金属薄片包括贱金属层和一个或多个钯和镍层。这种层可以以相同的操作被蚀刻以隔离在每个器件区域上的触点引线和接合位置。在一些实施例中,在模塑的薄片被放置在可重用的蚀刻载体的空腔中之后进行蚀刻步骤。
本发明的另一个方面包括适用于封装集成电路小片的装置。该装置包括金属薄片,部分该金属薄片被超声接合到金属载体。这个金属载体结构可以有一个或多个上述的特征。
附图说明
本发明及其优势通过结合附图参考以下说明将更好地被理解,其中:
图1A是根据本发明的一个实施例的包括两个超声接合层(ultrasonically bonded layer)和多个面板的薄片载体(foil carrier)结构的图示俯视图。
图1B是根据本发明的一个实施例的在图1A中示出的其中一个面板的放大的图示俯视图。
图1C是在图1B中示出的面板上的其中一个器件区域(devicearea)的放大的图示俯视图。
图2是示出根据本发明的一个实施例的用于封装集成电路器件的过程的流程图。
图3A-3E是根据本发明的一个实施例的封装过程的各种阶段图示侧视图。
图4A是在图3E中示出的模塑的薄片结构在被放置在载体中之后的示例蚀刻载体的图示俯视图。
图4B是在蚀刻之后的图4A中示出的蚀刻载体和模塑的薄片结构的图示俯视图。
图4C是根据本发明的一个实施例的从图4B的蚀刻过程得到的器件区域的放大的图示俯视图。
图5A-5C是在蚀刻、电镀和单体化(singulation)之后,图3D中示出的模塑的薄片结构的图示侧视图。
图5D是根据本发明的一个实施例的单体化封装的图示侧视图。
图5E是在图5D中示出的单体化(singulated)封装的图示仰视图。
在附图中,相同的参考标记有时被用于表示相同的结构元件。还应当理解的是附图中的描绘是图示的并且不依比例决定。
具体实施方式
本发明总体涉及集成电路的封装。更具体地,本发明涉及用于使用薄的薄片来在集成电路封装中形成电互连的改进的、低成本的方法和装置。
薄的薄片给半导体制造业带来了一些挑战。如前所述,薄的薄片在封装过程的压力下有较大的弯曲倾向。另外,配置成处理引线框的现有的封装设备对处理薄的薄片的适应性通常较差,因为薄的薄片与常规的引线框大小不同并且更易碎。下文描述的本发明的各种实施例将应对这些挑战。
第一个描述的实施例涉及薄片载体结构100,该薄片载体结构100被设计成更加有效率地将薄的薄片集成到半导体封装过程中。薄片载体结构100是由沿着焊接线112超声接合到铝载体的铜薄片制成。薄片和载体还可以由其它合适的材料制成。焊接线112和投影的锯割区110(saw street)将该结构划分成多个面板104。
薄片载体结构100被设计成沿着投影的锯割区110切割。这种切割将产生多个隔离的面板。由于焊接线112延伸平行于每个锯割区110的两侧并且在每个锯割区110的两侧延伸,所以在切割操作之后,焊接线112将围绕每个隔离的面板形成连续、密封的周边。在这个实施例中,每个面板的大小和特性都适用于由现有的封装设备进行处理。因此,这种设备可以被用于蚀刻、单体化、加入小片、导线(wire)和模塑材料到每个面板。(这些处理步骤的例子将会结合图3A-3E、4A-4C和5A-5E在下文进行讨论)。由于每个面板使用超声接合密封,所以在上述处理步骤期间,阻止了不需要的物质进入面板的层之间。
超声接合的好处是足够强韧以能够承受由封装过程的后期阶段施加的应力,同时,在小片、导线和模塑材料被加入到薄片中之后,仍然允许容易地将载体从薄片分离。这里使用的术语“超声接合”包括任意合适的具有超声部件的接合技术,包括热超声接合(thermosonicbonding)。尽管超声接合较为适用,应当理解的是其它合适的接合技术可以被用于将薄片固定到载体。举例来说,可以使用各种合适的粘合剂。
在示出的实施例中,焊接线被限制在每个面板的外围的接合区域并且不进一步延伸到面板的中央或者内部。但是,应当理解的是,焊接线112可以以各种其它方式配置。例如,面板104可以通过单个较宽的焊接线代替成对的较薄焊接线被划分。如果锯割区沿着每个较宽的焊接线的中间延伸,那么得到的面板也将沿着它们的外围被密封。可替代地,可以提供另外的中间焊接线来有效地将面板划分成更小的密封的片段。例如,每个密封的片段可以包括器件区域的二维阵列或者更加像出现在各种常规的引线框带中的一些其它的器件区域的配置。
应当理解的是,薄片载体结构100中的薄片可以包括各种金属层。正如封装领域的技术人员所熟悉的,例如镍、钯或者银的金属层有时被涂覆于铜引线框上来解决各种问题,例如,减少电迁移和/或改进接合导线和引线框之间的电连接强度等等。在本发明中,薄片代替了引线框,并且可能希望涂覆相似的涂层到薄片。为了减少成本,这种金属化层有时可以在薄片被附着到载体结构之前被涂覆到薄片上。举例来说,如果在薄片载体结构100中的薄片是由铜制成的,那么可能希望使用镍和钯的层涂覆薄片的两面。在其它实施例中,薄片的上(暴露的)表面使用银或者银合金的层覆盖。可替代地,如图1B中所示的,薄片可以被点镀银。
图1B显示了根据本发明的一个实施例的面板104的放大的俯视图。面板104包括多个器件区域106,这些器件区域通过点镀银合金形成,尽管也可以使用其它合适的金属。图1C示出了器件区域106中的一个的放大的俯视图。点镀部分108形成接合位置的图案,适用于导线接合到集成电路芯片。这种点镀可以在薄片载体结构100沿着锯割区100切割之前或者之后发生。当接合导线随后在点镀部分108处被接合到薄片上时,银合金可以加强这种接合。
器件区域106可以采取多种不同的图案和配置。在示出的实施例中,点镀部分108定义多个接合位置,这些接合位置位于接近器件区域106外围处的环内。当然,也可以使用各种各样的其它接合位置图案。举例来说,如果需要向下接合(down bond)到类似芯片附着焊盘(attach pad)的放大的接地(或者其它)触点,那么也可以在器件区域106的中央提供合适的点镀。在另外的其它实施例中,多行接合位置或者各种各样的其它接合位置图案的任意一种可以被点镀在薄片上。
图2和3A-3E示出了根据本发明的一个实施例的用于封装集成电路器件的过程200。初始,在步骤202,提供包括薄片306和载体308的图3A的薄片载体结构300。薄片载体结构300可以采取从图1A的薄片载体结构100的切割下来的面板104的形式,尽管不需要这样。在示出的示例中,薄片306是铜薄片以及载体308由铝形成。在替代实施例中,可以使用不同的金属薄片来代替铜薄片以及使用不同的载体结构代替铝载体308。例如,载体可以可替代地由铜、钢、其它金属、诸如聚酰亚胺或者各种各样的其它合适的材料的非导电材料制得。在一些实施例中,薄片306通过超声接合被粘附到载体308,而在其它实施例中使用粘合剂或者其它合适的接合技术来将薄片306固定到载体308。
薄片载体结构300的尺寸可以进行各种变化来满足特定应用的需要。在一些实施例中,薄片载体结构300的大小接近典型的引线框带。薄片306和载体308的厚度也可以进行各种改变。在一些实施例中,薄片具有在大约0.5到2毫英寸的范围的厚度,薄片载体结构300具有在大约5到12毫英寸的范围的厚度。当使用铝载体时,在大约7到10毫英寸的范围的厚度较为适用。通常,有利的是让薄片载体结构的厚度大体上与标准的引线框的厚度匹配,使得适用于处理引线框的标准的封装设备可以被用于处理该结构。
初始,在步骤204,使用常规的芯片附着技术将小片318安装在薄片载体结构300上。在小片被附着之后,通过适当的手段(例如导线接合)将它们电连接到薄片。图3B示出了导线接合的结构。应当理解的是,所描述的方法的一个重要的优点在于在芯片附着和导线接合步骤中可以使用通常可用的芯片附着和导线接合设备。所得到的结构具有通过接合导线316电连接到薄片的多个小片。在示出的实施例中,在薄片306的两个表面上都提供了镍和钯的附加层。上部的钯层帮助更加稳固地将导线316固定在薄片中。
在步骤206和图3C中,使用模塑材料322封装小片308、导线316以及薄片载体面板301和铜层306的至少一部分,形成模塑的薄片载体结构324。在图3C示出的实施例中,模塑材料322被加入到单个连续的带中。即,模塑材料被相对均匀地涂覆在整个薄片306的模塑的部分上。注意这种类型的模塑在基于引线框的封装中并不常用。相反,在引线框带上承载的器件通常个别地模塑或者在子面板中模塑。模塑材料的连续带的好处将结合图3D、3E和步骤208进行讨论。
在步骤208,图3C的模塑的薄片载体结构324的载体部分被移除,得到图3D的模塑的薄片结构325。此时,模塑材料代替载体308为薄片提供结构支撑。应当理解的是,连续带模塑方法的优点在于它提供了对整个面板的良好的支撑从而带仍然可以以面板的形式被处理。相反,如果在模塑操作期间,在子面板之间提供模塑沟(molding gap),那么子面板在载体被移除后需要单独地被处理。
图3E显示了模塑的薄片结构305的外部视图。应当理解的是,尽管模塑的薄片结构325的上表面328基本上是平坦的,但这不是必须的。模塑的薄片结构325中的模塑材料322可以采取各种图案和形状,并且模塑材料334的深度可以随着模塑的薄片结构325的长度而改变。
在步骤209中,模塑的薄片结构325如图4A和4B所示被设置在蚀刻载体404中。图4A示出包含模塑的薄片结构325的蚀刻载体404的俯视图。在该示出的实施例中,蚀刻载体404包括对准孔402和配置成容纳模塑的薄片结构325的空腔406。蚀刻载体404被设计成容纳图3F的模塑的薄片结构325,使得模塑的薄片结构的上表面328被藏在空腔406中并且暴露出薄片306。蚀刻载体可以是可重用的并且优选地由铝制成,尽管也可以使用其它材料。
在步骤210,蚀刻薄片306。蚀刻移除了部分薄片306并且定义了如图4B所示的多个器件区域410。可以使用各种合适的蚀刻方法,包括等离子蚀刻。还可以使用其它合适的技术(例如锯割或者激光切割)来形成器件区域410。
一些实施例涉及利用母线(bus bars)来形成器件区域410以方便之后的在由薄片形成的电触点上的金属(例如锡或者焊料)的电镀。图4C图示示出这种器件区域。在该示出的实施例中,器件区域410具有芯片附着焊盘412、触点引线414和母线416。母线416电连接到焊盘和引线。母线416还可以形成在多个器件区域之间的导电链路。应当理解的是,器件区域410仅仅表示多个可能的配置中的一个。
图5A-5B提供在模塑的薄片结构325上的蚀刻处理的效果的图示侧视图。图5A是在蚀刻之前模塑的薄片结构325的图示侧视图。图5B示出了蚀刻方法如何移除部分薄片306,如何显露模塑材料322的区域以及如何形成触点引线414和芯片附着焊盘412。
如上所述,一些实施例考虑了图2的步骤211,该步骤包括将图5C焊接点508电镀到芯片附着焊盘412和触点引线414上。在步骤212,模塑的薄片结构325沿着图5C投影的锯割区302被单体化来形成半导体封装。模塑的薄片结构325可以使用各种技术被单体化,包括锯割和激光切割。图5D中示出了单体化的封装520的放大的侧视图。图5E中示出了封装的图示仰视图。仰视图示出了由模塑材料322围绕的芯片附着焊盘516和触点引线518。
尽管详细描述了本发明的仅仅一些实施例,应当理解的是,在不脱离本发明的精神和范围的情况下,可以以许多其它形式实施本发明。在之前的描述中,许多描述的引线框包括引线和/或触点,它们在这里常被称为触点引线。在本发明的上下文中,术语触点引线意在涵盖引线、触点和其它可能在引线框中出现的电互连结构。因此,本发明实施例应当被认为是示例性而不是限制性的,并且本发明不限于这里给出的细节,但可以在所附权利要求的范围内和等同于所附权利要求的范围修改。

Claims (19)

1.一种方法包括:
提供金属载体;
提供金属薄片;以及
超声接合部分所述金属薄片和所述金属载体,接合的部分在所述金属薄片中定义多个面板,所述多个面板适用于在集成电路的封装中用作薄片载体面板。
2.如权利要求1所述的方法,进一步包括使用银或者银合金来点镀所述金属薄片的表面以在每个面板内形成多个器件区域,每个器件区域适用于导线接合到集成电路芯片。
3.如权利要求1或2所述的方法,其中所述金属薄片是铜薄片,其具有在该金属薄片的上表面和下表面形成的镍层和钯层。
4.如前述任意一项权利要求所述的方法,其中,所述金属薄片的厚度在大约0.6和2毫英寸之间,以及所述载体的厚度在大约5和10毫英寸之间。
5.如前述任意一项权利要求所述的方法,其中,所述超声接合部分围绕所述多个面板的每一个形成连续的周边。
6.如前述任意一项权利要求所述的方法,进一步包括切割所述接合的金属薄片和金属载体以形成多个隔离的面板。
7.如权利要求6所述的方法,其中所述超声接合形成平行的焊接线以及其中所述切割步骤进一步包括沿着所述平行的焊接线并且在所述平行的焊接线之间切割。
8.一种用于封装集成电路器件的方法,包括:
提供薄片载体结构,该薄片载体结构包括粘合到载体的金属薄片;
附着多个小片到所述金属薄片;
使用模塑材料封装所述多个小片和所述金属薄片的至少一部分来形成模塑的薄片载体结构;
将所述载体从所述模塑的薄片载体结构移除以形成模塑的薄片结构;
在所述载体被移除之后蚀刻所述金属薄片以在所述金属薄片中定义多个器件区域,每个器件区域支撑所述多个小片的至少一个并且具有多个电触点,其中所述蚀刻使部分所述模塑材料暴露;以及
在蚀刻步骤之后,单体化所述模塑的薄片结构以提供多个封装的集成电路器件。
9.如权利要求8所述的方法,其中所述载体是金属载体以及部分所述金属薄片被超声接合到所述金属载体。
10.如权利要求8所述的方法,其中使用粘合剂将所述金属薄片附着到所述载体。
11.如权利要求8到10中任意一项所述的方法,其中,所述封装步骤包括将所述模塑材料涂覆到所述多个小片和所述部分所述金属薄片以在所述金属薄片上形成单个、连续模塑的带。
12.如权利要求8到11中任意一项所述的方法,其中:
所述金属薄片包括铜层和由银或银合金形成的第二层;
所述模塑材料接触所述银层;
所述蚀刻步骤包括蚀刻所述铜层和第二层两者来在每个器件区域上形成触点焊盘,并且让所述模塑材料在触点焊盘之间暴露;以及
所述第二层在每个触点焊盘上提供了导线接合位置。
13.如权利要求8到12中任意一项所述的方法,进一步包括将所述模塑的薄片结构放置在可重用的蚀刻载体的空腔中,所述可重用的蚀刻载体的空腔被配置成将所述金属薄片暴露给蚀刻过程。
14.如权利要求8到13中任意一项所述的方法,其中所述金属薄片包括具有用镍和钯覆盖的多个表面的金属层。
15.一种适用于封装集成电路小片的装置,包括:
金属载体;和
金属薄片,部分所述金属薄片被超声接合到所述金属载体,接合的部分在所述金属薄片中定义多个面板。
16.如权利要求15所述的装置,其中每个面板包括多个器件区域,每个器件区域被使用金属作点镀以形成适用于导线接合到集成电路芯片的电触点。
17.如权利要求15或16所述的装置,其中所述载体由铝制成以及所述薄片由铜制成。
18.如权利要求15到17中任意一项所述所述的装置,其中所述超声接合部分围绕所述多个面板的每一个形成连续的周边。
19.如权利要求15到18中任意一项所述所述的装置,其中所述超声接合部分形成定义所述多个面板的每一个的边界的平行的焊接线。
CN2009801213036A 2008-06-04 2009-05-11 基于薄片的半导体封装 Pending CN102057485A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/133335 2008-06-04
US12/133,335 US8375577B2 (en) 2008-06-04 2008-06-04 Method of making foil based semiconductor package
PCT/US2009/043503 WO2009148768A2 (en) 2008-06-04 2009-05-11 Foil based semiconductor package

Publications (1)

Publication Number Publication Date
CN102057485A true CN102057485A (zh) 2011-05-11

Family

ID=41398763

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2009801213036A Pending CN102057485A (zh) 2008-06-04 2009-05-11 基于薄片的半导体封装

Country Status (8)

Country Link
US (1) US8375577B2 (zh)
EP (1) EP2286451A4 (zh)
JP (1) JP5569910B2 (zh)
KR (1) KR101612976B1 (zh)
CN (1) CN102057485A (zh)
MY (1) MY152738A (zh)
TW (1) TWI484611B (zh)
WO (1) WO2009148768A2 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103219244A (zh) * 2012-01-18 2013-07-24 东琳精密股份有限公司 半导体的基板工序、封装方法、封装及系统级封装结构

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010513330A (ja) * 2006-12-22 2010-04-30 トーメン メディカル アーゲー 歯科インプラント及びその製造方法
DE102008000842A1 (de) * 2008-03-27 2009-10-01 Robert Bosch Gmbh Verfahren zur Herstellung einer elektronischen Baugruppe
US20100084748A1 (en) * 2008-06-04 2010-04-08 National Semiconductor Corporation Thin foil for use in packaging integrated circuits
US7836586B2 (en) * 2008-08-21 2010-11-23 National Semiconductor Corporation Thin foil semiconductor package
JP2009143234A (ja) * 2008-12-24 2009-07-02 Nippon Mining & Metals Co Ltd キャリア付金属箔
US8101470B2 (en) 2009-09-30 2012-01-24 National Semiconductor Corporation Foil based semiconductor package
US8377267B2 (en) * 2009-09-30 2013-02-19 National Semiconductor Corporation Foil plating for semiconductor packaging
JP5546363B2 (ja) * 2010-06-11 2014-07-09 ローム株式会社 半導体装置および半導体装置の製造方法
US8389334B2 (en) 2010-08-17 2013-03-05 National Semiconductor Corporation Foil-based method for packaging intergrated circuits
US10186458B2 (en) * 2012-07-05 2019-01-22 Infineon Technologies Ag Component and method of manufacturing a component using an ultrathin carrier
US10192849B2 (en) * 2014-02-10 2019-01-29 Infineon Technologies Ag Semiconductor modules with semiconductor dies bonded to a metal foil
CN104283524B (zh) * 2014-10-22 2017-07-14 应达利电子股份有限公司 一种压电石英晶体谐振器及其制作方法
JP2016139752A (ja) * 2015-01-29 2016-08-04 日立化成株式会社 半導体装置の製造方法
KR102592483B1 (ko) * 2018-10-10 2023-10-25 주식회사 루멘스 퀀텀닷 플레이트 조립체의 제조방법
US11362220B2 (en) 2018-04-06 2022-06-14 Sunpower Corporation Local metallization for semiconductor substrates using a laser beam
US11276785B2 (en) * 2018-04-06 2022-03-15 Sunpower Corporation Laser assisted metallization process for solar cell fabrication
US11664472B2 (en) 2018-04-06 2023-05-30 Maxeon Solar Pte. Ltd. Laser assisted metallization process for solar cell stringing
US11362234B2 (en) 2018-04-06 2022-06-14 Sunpower Corporation Local patterning and metallization of semiconductor structures using a laser beam
WO2019195804A1 (en) 2018-04-06 2019-10-10 Sunpower Corporation Laser assisted metallization process for solar cell circuit formation
US10515898B2 (en) * 2018-05-14 2019-12-24 Tdk Corporation Circuit board incorporating semiconductor IC and manufacturing method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09252014A (ja) * 1996-03-15 1997-09-22 Nissan Motor Co Ltd 半導体素子の製造方法
CN1323507A (zh) * 1998-09-14 2001-11-21 Via系统有限责任公司 多层印刷电路板组件、其制造方法及相关的多层印刷电路板
CN1337738A (zh) * 2000-08-09 2002-02-27 株式会社Kostat半导体 用于半导体封装处理的具有可注入导电区的带及其制造方法
JP2004058578A (ja) * 2002-07-31 2004-02-26 Hitachi Metals Ltd キャリア付き積層金属箔及びそれを用いたパッケージの製造方法

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4048438A (en) 1974-10-23 1977-09-13 Amp Incorporated Conductor patterned substrate providing stress release during direct attachment of integrated circuit chips
JPH0379040A (ja) * 1989-08-22 1991-04-04 Sumitomo Special Metals Co Ltd スポット状部分クラッド材の製造方法
JPH05145003A (ja) * 1991-11-21 1993-06-11 Sony Corp リードフレーム
US5308797A (en) 1992-11-24 1994-05-03 Texas Instruments Incorporated Leads for semiconductor chip assembly and method
JP3606275B2 (ja) * 1994-03-18 2005-01-05 日立化成工業株式会社 半導体パッケージ及びその製造方法
KR100437437B1 (ko) 1994-03-18 2004-06-25 히다치 가세고교 가부시끼가이샤 반도체 패키지의 제조법 및 반도체 패키지
JP3352084B2 (ja) * 1994-03-18 2002-12-03 日立化成工業株式会社 半導体素子搭載用基板及び半導体パッケージ
US6001671A (en) * 1996-04-18 1999-12-14 Tessera, Inc. Methods for manufacturing a semiconductor package having a sacrificial layer
US5942314A (en) * 1997-04-17 1999-08-24 Mitsui Mining & Smelting Co., Ltd. Ultrasonic welding of copper foil
AU7082798A (en) 1997-04-30 1998-11-24 Hitachi Chemical Company, Ltd. Board for mounting semiconductor element, method for manufacturing the same, andsemiconductor device
JP3521758B2 (ja) 1997-10-28 2004-04-19 セイコーエプソン株式会社 半導体装置の製造方法
KR20000071375A (ko) 1999-02-25 2000-11-25 윌리엄 비. 켐플러 땜납 볼을 모방한 융기를 갖는 집적 회로 소자 및 그 제조방법
US6451627B1 (en) * 1999-09-07 2002-09-17 Motorola, Inc. Semiconductor device and process for manufacturing and packaging a semiconductor device
JP2001127212A (ja) 1999-10-26 2001-05-11 Hitachi Ltd 半導体装置および半導体装置の製造方法
JP2001250887A (ja) * 2000-03-08 2001-09-14 Sanyo Electric Co Ltd 回路装置の製造方法
US6586676B2 (en) * 2000-05-15 2003-07-01 Texas Instruments Incorporated Plastic chip-scale package having integrated passive components
DE10031204A1 (de) 2000-06-27 2002-01-17 Infineon Technologies Ag Systemträger für Halbleiterchips und elektronische Bauteile sowie Herstellungsverfahren für einen Systemträger und für elektronische Bauteile
US6518161B1 (en) 2001-03-07 2003-02-11 Lsi Logic Corporation Method for manufacturing a dual chip in package with a flip chip die mounted on a wire bonded die
JP4852802B2 (ja) * 2001-06-19 2012-01-11 住友金属鉱山株式会社 リードフレーム
EP2312630A1 (en) * 2001-07-09 2011-04-20 Sumitomo Metal Mining Company Limited Leadframe and method of manufacturing the same
US6769174B2 (en) * 2002-07-26 2004-08-03 Stmicroeletronics, Inc. Leadframeless package structure and method
TW200411886A (en) 2002-12-26 2004-07-01 Advanced Semiconductor Eng An assembly method for a passive component
US20070176303A1 (en) 2005-12-27 2007-08-02 Makoto Murai Circuit device
TWI307130B (en) * 2006-06-20 2009-03-01 Advanced Semiconductor Eng Semiconductor package and manufacturing method thereof
US20100084748A1 (en) 2008-06-04 2010-04-08 National Semiconductor Corporation Thin foil for use in packaging integrated circuits
US7836586B2 (en) 2008-08-21 2010-11-23 National Semiconductor Corporation Thin foil semiconductor package

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09252014A (ja) * 1996-03-15 1997-09-22 Nissan Motor Co Ltd 半導体素子の製造方法
CN1323507A (zh) * 1998-09-14 2001-11-21 Via系统有限责任公司 多层印刷电路板组件、其制造方法及相关的多层印刷电路板
CN1337738A (zh) * 2000-08-09 2002-02-27 株式会社Kostat半导体 用于半导体封装处理的具有可注入导电区的带及其制造方法
JP2004058578A (ja) * 2002-07-31 2004-02-26 Hitachi Metals Ltd キャリア付き積層金属箔及びそれを用いたパッケージの製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103219244A (zh) * 2012-01-18 2013-07-24 东琳精密股份有限公司 半导体的基板工序、封装方法、封装及系统级封装结构
CN103219244B (zh) * 2012-01-18 2016-04-13 东琳精密股份有限公司 用于一半导体封装的系统级封装结构

Also Published As

Publication number Publication date
US20090305076A1 (en) 2009-12-10
MY152738A (en) 2014-11-28
TW201001658A (en) 2010-01-01
TWI484611B (zh) 2015-05-11
KR101612976B1 (ko) 2016-04-15
JP2011523213A (ja) 2011-08-04
WO2009148768A3 (en) 2010-03-04
KR20110015047A (ko) 2011-02-14
JP5569910B2 (ja) 2014-08-13
EP2286451A2 (en) 2011-02-23
EP2286451A4 (en) 2013-10-16
WO2009148768A2 (en) 2009-12-10
US8375577B2 (en) 2013-02-19

Similar Documents

Publication Publication Date Title
CN102057485A (zh) 基于薄片的半导体封装
US7439097B2 (en) Taped lead frames and methods of making and using the same in semiconductor packaging
TWI515837B (zh) 半導體裝置及其製造方法
US8890301B2 (en) Packaging and methods for packaging
KR100789348B1 (ko) 부분적으로 패터닝된 리드 프레임 및 이를 제조하는 방법및 반도체 패키징에서 이를 이용하는 방법
US20160118349A1 (en) Semiconductor package
US8133759B2 (en) Leadframe
TWI274409B (en) Process for manufacturing sawing type leadless semiconductor packages
TW201423917A (zh) 樹脂密封型半導體裝置及其製造方法
CN104025287A (zh) 半导体装置
JP2009105362A (ja) 半導体装置とその製造方法および半導体基板
TWI833739B (zh) 半導體封裝及製造其之方法
CN206584922U (zh) 预包封无导线可电镀引线框架封装结构
JP7144157B2 (ja) 半導体装置およびその製造方法
US10109564B2 (en) Wafer level chip scale semiconductor package
JP4418764B2 (ja) 樹脂封止型半導体パッケージの製造方法
JP2003158142A (ja) 半導体装置の製造方法
US20080258276A1 (en) Non-Leaded Semiconductor Package and a Method to Assemble the Same
US7582974B2 (en) Semiconductor device and method of manufacturing same
JP4570797B2 (ja) 半導体装置の製造方法
JP2019102697A (ja) 半導体装置およびその製造方法
JP2002164496A (ja) 半導体装置およびその製造方法
JP2003197845A (ja) リードフレーム及びこれを用いた半導体装置並びにその製造方法
TW201025463A (en) Manufacturing process of a leadless semiconductor package process and its structure
JP2002164497A (ja) 半導体装置およびその製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C12 Rejection of a patent application after its publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20110511