CN1337738A - 用于半导体封装处理的具有可注入导电区的带及其制造方法 - Google Patents
用于半导体封装处理的具有可注入导电区的带及其制造方法 Download PDFInfo
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Abstract
本发明提供了一种具有可注入导电区的带,它实现了一种新的结构,在该结构中有机的刚性基底在半导体封装处理中被从半导体封装件除去。该带包括一个带膜和附着在该带膜上的可注入导电区,该带膜可在封包处理之后与半导体封装件分离,且直到封包处理完成都起着通常的刚性基底的作用。本发明还提供了该带的制造方法。
Description
本发明涉及一种半导体封装组件,更具体地说,涉及一种具有可注入导电区的带,它在制造诸如球栅阵列(BGA)型封装的半导体封装过程中代替刚性基底,以及这种产品的制造方法。
近来,诸如个人计算机、蜂窝电话和可携式摄象机的电子产品变得尺寸越来越小而处理能力越来越大。因此,要求尺寸小、容量大且符合快速处理速度的半导体封装。因此,半导体封装件已经从包括双入线封装(DIP)的插入安装式转变成包括一个薄而小的出线封装(TSOP)、一个薄的四边形扁平封装(TQFP)和一个球栅阵列(BGA)的表面安装式。
在表面安装式中,BGA特别吸引人们的注意,因为它能够使半导体封装件的尺寸和重量大大地减小,并能够在芯片规模封装(CSP)中实现高质量和可靠性。
近来,多数半导体制造公司已经开发了CSP并用各自的名称公开了所开发的CSP。然而,CSP的结构是彼此非常类似的。一种BGA式封装是一种CSP。每一个传统的BGA封装都采用了诸如聚酰亚胺、双马来酰亚胺三嗪(BT)树脂或FR-4形成的刚性基底,而不是采用引线框,来作为半导体封装件体。在此,FR-4是通过硬化作为三聚氰胺化合物的中间物而产生的、被称为双氰胺的聚合物而制成的一种树脂。
在刚性基底中,电路图案起先被做在诸如聚酰亚胺的绝缘基底的前和后表面上。电路图案用具有优异的粘合强度的酚基的两面粘合剂或聚酰亚胺基的一面粘合剂牢固地粘合在绝缘基底上。刚性基底具有通过在绝缘基底上穿孔而形成的通孔,用以在电路图案之间进行互连,并且还包括用绝缘材料形成的焊料掩膜,以便利导线接合、外部连接端的连接和防止外部损坏。典型的BGA封装采用焊球或焊料凸起部作为外部连接端,而不是采用引线。
这种刚性基底,在半导体封装件组装完成之后,作为半导体封装件的一部分而保留在其内,因而它妨碍了半导体封装件的厚度的减小。有一段时间,在组装CSP中的改善的半导体封装件时,取消了刚性基底。然而,这种情况在进行导线接合、外部连接端的包装和连接上有很多的困难。
图1是采用刚性基底而不是采用引线框的典型的BGA封装的剖视图。以下的描述主要针对传统的BGA封装的结构的制造过程。
参见图1,在锯开处理中一个晶片被切成单个的芯片,因而制备了用于BGA封装的芯片2。芯片2在模连接处理中借助一种环氧树脂4接合到刚性基底10上。芯片2的接合台(未显示)在导线接合处理中通过金线6而与刚性基底10上的接合指相连。
在此,电路图案12被形成在刚性基底10上。形成在刚性基底10的前表面上的电路图案12通过通孔16连接到形成在刚性基底10的后表面上的诸如焊球台20的电路图案上。用于保护电路图案12并便利焊球即外部连接端的连接的焊料掩膜14和14’,分别被形成在刚性基底10的前和后表面上。构成刚性基底10的内部的绝缘基底18由BT树脂或诸如聚酰亚胺的塑料树脂制成。
随后,用环氧模制化合物8进行保护设置在刚性基底19的前表面上的金线6和芯片2的包装。随后,作为外部连接端的焊球22被连至刚性基底10的底部上的焊料台20。最后,成条的BGA封装在分割处理中被切成单个的BGA封装。
然而,根据传统技术的半导体封装件处理中采用的刚性基底具有以下问题。
首先,诸如形成在刚性基底10的顶部和底部上的电路图案12和20的中间连接器,和设置在芯片2与外部连接端22之间的通孔16,降低了BGA封装的电性能。
其次,构成刚性基底10的绝缘基底18在BGA封装组装完成之后仍然留在BGA封装内,这妨碍了减小半导体封装件的厚度。换言之,半导体封装件的厚度的减小受到了影响。
第三,由于需要进行形成焊料掩膜14和14’的处理以保证电路图案12之间的绝缘,制造变得复杂。
最后,刚性基底10是难于制造且价格高的。因此,BGA封装的组装成本高。
为了解决上述问题,本发明的一个目的,是提供一种具有可注入导电区的带,它能够被用来在半导体封装处理中代替刚性基底,且在半导体封装件组装之后不留在半导体封装件中。
本发明的另一个目的,是提供一种制造用于半导体封装处理的具有可注入导电区的带的方法。
因此,为了实现本发明的第一个目的,提供了一种用于半导体封装处理的带,它包括:一种带膜,在半导体封装件制造中,该带膜能够在封包处理之后与半导体封装件分离并在直到封包处理完成的过程中被用作引线框或基底;以及,附着在带膜上的可注入导电区,它们每一个都具有彼此相对的第一表面和第二表面,其中第一表面附在带膜上并与半导体封装件的外部连接端相连,且第二表面粘合到一种环氧模制化合物上,并在第二表面上进行导线接合。
该带膜包括在一个下部的带体和形成在该带体上的一个粘合层。在各个可注入导电区的第二表面上优选为形成有一个表面处理层。
该带膜用不与其他材料发生化学反应且在半导体封装件制造过程中不由于加热和加压而变形的材料制成。带膜可用聚合物、纸、金属或包括它们中的至少一种的复合物制成。
粘合层可以用诸如基于硅树脂的便于带膜与可注入导电区分离的粘合剂的构成。
可注入导电区优选为用铜或包括铜的合金制成,且优选的表面处理层是允许导线接合的材料层。
为了实现本发明的第二个目的,提供了制造用于半导体封装处理的具有可注入导电区的带的方法。该方法包括以下步骤:制备一种带膜,它直到封包处理完成都被用作引线框或基底,该带膜不被包含在半导体封装件内;以及,在带膜上形成可注入导电区。
该带膜包括一个带体和一个粘合层,且该粘合层用基于硅树脂的糊制成。
在一个实施例中,形成可注入导电区的步骤包括以下的子步骤:在带膜上叠置一个铜箔;在该铜箔上形成一个第一照相掩膜图案;在该第一照相掩膜图案的一个开放区上进行导线接合的表面处理;除去第一照相掩膜图案并形成一个第二照相掩膜图案;以及,利用第二照相掩膜图案进行一种蚀刻处理,从而只有可注入导电区能够被留在带膜上。
在另一实施例中,形成可注入导电区的步骤包括以下子步骤:在带膜上印刷可注入导电区;以及,在印刷的可注入导电区上进行用于导线接合的表面处理。
在另一个实施例中,用于形成可注入导电区的步骤包括以下子步骤:把在外部制成的可注入导电区拾取并放置到带膜上;以及,叠置带膜和可注入导电区。
在又一个实施例中,形成可注入导电区的步骤包括在带膜上淀积用于可注入导电区的材料层和在该材料层上形成图案。
在再一个实施例中,形成可注入导电区的步骤包括以下子步骤:在带膜上形成可注入导电区的籽层;以及,利用该籽层进行电镀。
根据本发明,采用了具有可注入导电区的带,而不是采用刚性基底,从而改善了半导体封装件的电性能并减小了半导体封装件的厚度。由于没有采用昂贵的刚性基底,制造成本能够得到降低,且能够实现方便而简化的制造。由于热辐射的路径被缩短,导热特性得到了改善。由于电路较短,电特性能够得到改善。另外,由于刚性基底与半导体封装件中的其他部分的热膨胀系数的不同而导致的应力问题能够得到限制。
通过以下结合附图对本发明的最佳实施例进行的详细描述,本发明的上述目的和优点将变得显而易见。在附图中:
图1是采用刚性基底而不是采用引线框的典型球栅阵列(BGA)封装的剖视图;
图2是根据本发明的采用具有可注入导电区的带来取代刚性基底的BGA封装的剖视图;
图3是流程图,显示了根据本发明的采用具有可注入导电区的带的半导体封装件的制造过程;
图4和5是根据本发明的具有可注入导电区的带的平面图;
图6和7是根据本发明的具有修正形状的可注入导电区的带的平面图;
图8是根据本发明的具有可注入导电区的带的部分剖视图;
图9至13是流程图,显示了根据本发明的具有用于半导体封装处理的可注入导电区的带的制造方法;以及
图14至16是平面图,显示了具有条形的可注入导电区的带的结构。
以下结合附图详细描述本发明的最佳实施例。在本说明书中,术语半导体封装件是在最广泛的意义上使用的,且不限于诸如球栅阵列(BGA)的具体半导体封装件。另外,具有可注入导电区的带不限于一种具体的形状。
本发明的精神和基本特征,能够以不同于在以下给出的最佳实施例中公布的方式的方式,而得到实现。例如,在本说明书的最佳实施例中,粘合层是用基于硅的粘合剂形成的,但可采用在半导体封装件组装中不在热和化学作用下发生变形和使可注入导电区能够被方便地从带体上分离的任何材料。另外,带体在最佳实施例中是用聚酰亚胺形成的,但可采用任何材料,只要该材料在半导体封装件组装中不因热和化学作用而变形。另外,在可注入导电区的一侧上形成了一种表面处理层,但如果导线接合能够在没有它的情况下进行,也可以不形成该表面处理层。因此,最佳实施例只是为了描述而公布的,而不是为了限定的目的。
根据本发明的具有可注入导电区的带在半导体封装处理中的应用
用于半导体封装处理的、具有可注入导电区的一种带,以完全不同于传统的刚性基底的应用方式的方式,被应用于半导体封装件的组装。以下首先结合图2和3描述具有可注入导电区的带是如何应用于半导体封装件的组装的。
图2是一种球栅阵列(BGA)封装的剖视图,该封装采用了根据本发明的具有可注入导电区的带来取代刚性基底。图3是流程图,显示了采用根据本发明的具有可注入导电区的带的半导体封装件的制造过程。
对根据本发明的半导体封装件(例如BGA封装)的结构的描述,将集中于半导体封装件的组装过程。在一种模连接处理中,一个芯片100用一种环氧树脂102连接到其上有可注入导电区的带膜110。该可注入导电区由用作散热器的可注入导电区114和用于外部连接端的连接的可注入导电区112构成。
在一种导线接合处理中,芯片100的接合台(未显示)通过金线106与可注入导电区112和114相连。在此,优选为是对各个可注入导电区112和114的一个第二表面进行用于导线接合的表面处理,该第二表面与可注入导电区112和114的一个第一表面相对,而该第一表面与带膜110相连。对于该表面处理,利用金、银或钯或它们的复合物制成的一个单层形成了一个表面处理层,以便利导线接合处理。
在导线接合完成之后,所产生的结构用一种环氧模制化合物104进行封包。在此,可注入导电区112和114的第二表面被粘合到该环氧模制化合物104上。由于在带膜110中包括了便利分离的粘合层(图8中的132),带膜110能够在封包完成之后沿着箭头的方向得到分离并从半导体封装件上除去。
其结果,可注入导电区112和114的第一表面得到暴露。作为外部连接端的焊球可被连接到该第一表面。一般地,半导体封装件的组装不是单个地进行的,而是以条为单位进行的,因而最后进行把条分成单个的BGA封装的分割处理。
因此,用于半导体封装处理的具有可注入导电区的带,直到封包处理,被用作刚性基底,并可随后被除去,从而使该带能够被应用于半导体封装件组装。该带的采用是与传统的刚性基底完全不同的一种思想。
根据本发明的用于半导体封装处理的具有可注入导电区的带的结构
图4和5是根据本发明的具有可注入导电区的带的平面图。参见图4,根据本发明的用于半导体封装处理并具有可注入导电区的带,包括一个带膜110和可注入导电区112A。带膜110的目的是在模连接处理、导线接合处理和封包处理中起传统的刚性基底的作用,并在封包处理之后从半导体封装件分离。为此,带膜110包括在表面上的一个粘合层(未显示),它容易分离。这种粘合层在概念上是与传统刚性基底采用的酚粘合剂或聚酰亚胺基的粘合剂不同的。传统上,形成了一种粘合剂以具有大的附着强度,以防止电路图案从绝缘基底脱离。然而本发明中采用的粘合层用硅基材料制成,它容易分离并不留残留。
对圆形的可注入导电区112A,外部连接端可被连接到粘合至带膜110的第一表面,且第二表面象传统技术中那样被用于导线接合。本发明只有可注入导电区,而没有传统刚性基底中采用的电路图案。另外,本发明不需要通孔作为芯片的接合台与外部连接端之间的中间连接器。
在该图中标号126表示芯片被连接的区域。在此,圆形的可注入导电区112A包括用作通过其向外辐射热量的散热器的可注入导电区,和用于外部连接端的连接的可注入导电区。
与其中作为散热器的可注入导电区和作为外部连接端的可注入导电区具有相同的结构的图4不同,在图5的实施例中,形成了单个的用于散热器的可注入导电区114,它比图4的散热器的总面积大,并具有与用于外部连接端的连接的可注入导电区112A不同的形状,因而改善了导热性。由于芯片的后表面与用作散热器的可注入导电区112之间的接触区在芯片被连接处较大,从芯片辐射来的热量能够更为有效地被从半导体封装件除去。
图6和7是根据本发明的带有具有修正形状的可注入导电区的带的平面图。与显示了用于外部连接端的连接的圆形可注入导电区的图4和5不同,图6和7显示了用于外部连接端的连接的矩形可注入导电区112B。可注入导电区112B的形状可被修正成任何形状,只要能够正常地进行导线接合和外部连接端的连接。虽然在图4至7的每一个中都显示了用于单个半导体封装件组装的具有可注入导电区的带,在实际的制造过程中采用了具有沿着行和列具有多个带的条,以便利多个半导体封装件的组装。显而易见的是,这种条的形状可得到修正,以适应半导体封装件制造公司的设备。
图8是根据本发明的具有可注入导电区的带的部分剖视图。参见图8,根据本发明的一种带包括带膜110和可注入导电区112和/或114。该带膜包括一个带体130和一个粘合层132。
带体130可用不因为热变形且不容易发生化学反应的任何材料制成,并在半导体封装件组装中被用来取代传统的引线框或刚性基底至封包处理完成。因此,诸如纸、聚合物、金属的单独材料或包括它们中的至少一种的复合物,可得到采用。用于带体130的有代表性的材料是聚合物中的聚酰亚胺膜。聚酰亚胺膜在-296℃至400℃的温度范围内保持其电和机械特性,并具有优异的耐化学性。然而,可以采用在半导体封装件组装过程中不转变的任何材料来代替聚酰亚胺膜。
由于粘合层132在封包处理之后应该容易从用环氧模制化合物封包的半导体封装件分离,它可用在半导体封装件组装中不容易变化的任何材料制成,而不是用具有优异粘合强度的材料制成。可作为粘合层132的材料有很多,但硅基的粘合剂是有代表性的例子。
在可注入导电区112’中,在导电区体140与粘合到带膜110的第一表面相对的一个第二表面上,形成了一个表面处理层142。表面处理层142是为了在导电区体140上进行导线接合而提供的。因此,表面处理层142可以用金、银、钯或包括这些材料中的至少一种的复合物制成。如果可以在没有表面处理层142的情况下进行导线接合,则可以不形成表面处理层142。在此,导电区体140是用铜或包括铜的合金制成的。
根据本发明的用于半导体封装处理的具有可注入导电区的带的制造方法
图9至13是流程图,显示了用于半导体封装处理的根据本发明的具有可注入导电区的带的制造方法。
第一实施例
图9是流程图,显示了根据本发明的第一实施例的用于半导体封装处理的具有可注入导电区的带的制造方法。参见图9,制备了一种带膜,它连接一种粘合层,该粘合层容易从在封包处理中用环氧模制化合物封包的半导体封装件分离。随后,在带膜上叠置了一个铜箔,该铜箔被用作可注入导电区体。在铜箔上形成了一个第一照相掩膜图案,它暴露出用于可注入导电区的区。在暴露的区上进行一种表面处理,以形成允许导线接合的表面处理层。随后,第一照相掩膜图案被除去。随后,在铜箔上形成一个第二照相掩膜图案,该图案暴露了用于可注入导电区的区以外的其余部分。利用该第二照相掩膜图案作为蚀刻掩膜,进行蚀刻处理,从而形成可注入导电区。
第二实施例
图10是流程图,显示了根据本发明的第二实施例的用于半导体封装处理的具有可注入导电区的带的制造方法。参见图10,制备了一种带膜,它包括一个粘合层,该粘合层能够容易地从在封包处理中用一种环氧模制化合物封包的半导体封装件分离。随后,在带膜上用导电金属糊印刷出可注入导电区。通过固化处理除去包含在导电金属糊中的挥发溶剂。最后,在印刷的可注入导电区上进行用于导线接合的表面处理。
第三实施例
图11是流程图,显示了根据本发明的第三实施例的用于半导体封装处理的具有可注入导电区的带的制造方法。参见图11,制备了一种带膜,它包括一个粘合层,该粘合层能够容易地从在封包处理中用一种环氧模制化合物封包的半导体封装件分离。与其他实施例不同,可注入导电区不是被形成在带膜上,而是在外部形成。例如,单个的可注入导电区是通过在压制机中进行冲压成形而预制的。这些可注入导电区随后利用拾取和放置机器被放置到带膜上。在完全放置了所有可注入导电区之后,带膜和可注入导电区被叠置。在完成了叠置之后,在可注入导电区的第二表面上进行表面处理。如果可注入导电区的第二表面已经在外界进行了表面处理,可不包括表面处理。
第四实施例
图12是流程图,显示了根据本发明的第四实施例的用于半导体封装处理的具有可注入导电区的带的制造方法。参见图12,制备了一种带膜,它包括一个粘合层,该粘合层能够容易地从在封包处理中用一种环氧模制化合物封包的半导体封装件分离。利用化学汽相淀积(CVD)法或物理汽相淀积(PVD)法(这些是制造半导体芯片的通常方法)在带膜上淀积用作可注入导电区体的一个薄膜,并随后用光刻在其上形成图案。在此,淀积薄膜并在其上形成图案的方法能够以各种方式得到修正。最后,在可注入导电区上进行表面处理。
第五实施例
图13是流程图,显示了根据本发明的第五实施例的用于半导体封装处理的具有可注入导电区的带的制造方法。参见图13,制备了一种带膜,它包括一个粘合层,该粘合层能够容易地从在封包处理中用一种环氧模制化合物封包的半导体封装件分离。随后,利用在制造半导体芯片时通常采用的光刻法在带膜上形成用于可注入导电区的籽层。随后,在具有籽层的带膜上进行电镀处理,以使籽层生长成可注入导电区。最后,在可注入导电区上进行用于导线接合的表面处理。
具有可注入导电区的带在一个条中的结构
图14至16是平面图,显示了具有可注入导电区的带在一个条中的结构。具有可注入导电区的带,当实际组装半导体封装件时,被形成在一个条中。根据制造者的设备,可形成各种类型的条。结合图14至16描述一种实施例。
图14是示意平面图,显示了根据本发明的一个实施例的具有可注入导电区的带所形成的条。参见图14,四个根据本发明的具有可注入导电区的带条150被提供在作为芯片规模封装件(CSP)制造中的传送装置的一个运送器154上。运送器154用金属或塑料聚合物制成。标号110表示了一个带膜,标号152表示了其中形成可注入导电区的一个区,且标号156表示了用于移动运送器154的孔。
图15是平面图,显示了图14所示的四个带条150中的一个。参见图15,可注入导电区112被形成在带条150上,从而能够形成每行五个和每列五个总共25个半导体封装件单元。标号160表示在分割处理中一个切割锯片通过的位置。
图16是图15的部分E的放大图。参见图16,用于单个半导体封装件的可注入导电区112得到显示,且各个可注入导电区112的形状可以以各种方式得到修正。如显示四个放大的可注入导电区的圆G所示,在各个可注入导电区112的整个表面上没有形成表面处理层142,但可以仅在容许导线接合所必需的区上形成表面处理层142。
由此,采用具有可注入导电区的带而代替刚性基底的本发明可实现以下的效果。
首先,本发明不需要诸如通孔的中间连接器和半导体封装件中的电路图案,从而改善了半导体封装件的电性能。
其次,根据本发明的具有可注入导电区的带在组装处理之后不留在半导体封装件内,因而减小了半导体封装件的厚度。
第三,本发明不采用传统上使用的昂贵的刚性基底,因而降低了半导体封装件的制造成本。
第四,本发明不要求形成通孔或焊料掩膜的处理,从而简化了带的制造。
第五,热从半导体芯片辐射出去的路径,通过采用用于散热器的可注入导电区,被缩短了,从而改善了半导体封装件的热辐射能力。
第六,传统上由于刚性基底与包括在半导体封装件中的其他周边部分的热膨胀系数差造成了半导体封装件中的大的应力。然而,本发明不包括刚性基底,因而解决了上述问题。
第七,在传统的分割处理中,当刚性基底为多层时,在把条分成单个的半导体封装件的锯开期间形成了裂缝或剥离之类的加工缺陷。然而,在采用具有可注入导电区的带的本发明中,上述的缺陷能够得到防止,且锯开能够方便地进行,因为在锯开的区域中只有环氧模制。因此,半导体封装件的成品率得到了提高。另外,分割处理中使用的锯片的消耗得到了降低。
第八,分割处理中的锯开处理可根据模的结构而予以取消。
虽然以上结合具体的实施例描述了本发明,但本领域的技术人员应该理解的是,在不脱离本发明的精神和范围的前提下可以对上述实施例进行修正。
Claims (23)
1.用于半导体封装处理的一种带,包括:
一个带膜,它可在封包处理之后从半导体封装件分离并直到封包处理完成被用作基底或引线框;以及
附着在带膜上的可注入导电区,每一个可注入导电区都具有相对的第一表面和第二表面,其中第一表面附在带膜上并与半导体封装件的一个外部连接端相连,且第二表面粘合到一种环氧模制化合物上,且在第二表面上进行导线接合。
2.根据权利要求1的带,其中带膜包括在下部的一个带体和形成在该带体上的一个粘合层。
3.根据权利要求1的带,其中该带膜是用在半导体封装件制造期间不因为热和压力而产生化学反应且不发生变化的材料制成的。
4.根据权利要求2的带,其中该带体是用选自聚合物、纸和金属中的一种材料或包括它们中的至少一种的复合物制成的。
5.根据权利要求4的带,其中聚合物是聚酰亚胺。
6.根据权利要求2的带,其中粘合层是便于带膜与可注入导电区的分离的硅树脂基粘合剂。
7.根据权利要求1的带,其中可注入导电区是用从由铜和包括铜的合金组成的组中选出的一种制成的。
8.根据权利要求1的带,其中可注入导电区的第二表面受到表面处理以进行导线接合。
9.根据权利要求8的带,其中用于导线接合的表面处理是通过形成一个膜来进行的,该膜由选自金、银、镍、钯或包括这些材料中的至少一种的复合物的材料制成的。
10.根据权利要求1的带,其中可注入导电区包括在与芯片的底部相连的部分的用作散热器的可注入导电区,和用于外部连接端的连接的可注入导电区。
11.用于半导体封装处理的具有可注入导电区的带的制造方法,该方法包括以下步骤:
制备一种带膜,该带膜直到封包处理完成都起着引线框或基底的作用,该带膜不被包含在半导体封装件内;以及
在带膜上形成可注入导电区。
12.根据权利要求11的方法,其中带膜包括一个带体和一个粘合层,该粘合层能够方便地与粘合到其上的一种材料分离。
13.根据权利要求12的方法,其中粘合层是用硅树脂基的糊形成的。
14.根据权利要求11的方法,其中形成可注入导电区的步骤包括以下子步骤:
在带膜上叠置一个铜箔;
在铜箔上形成一个第一照相掩膜图案;
在第一照相掩膜图案的一个开放区上进行用于导线接合的表面处理;
除去第一照相掩膜图案并形成一个第二照相掩膜图案;以及
利用第二照相掩膜图案进行一种蚀刻处理,从而使得只有可注入导电区被留在带膜上。
15.根据权利要求11的方法,其中形成可注入导电区的步骤包括以下的子步骤:
在带膜上印刷可注入导电区;以及
在印刷的可注入导电区上进行用于导线接合的表面处理。
16.根据权利要求15的方法,其中可注入导电区是用导电金属糊印刷的。
17.根据权利要求11的方法,其中形成可注入导电区的步骤包括以下的子步骤:
形成与带膜分离的可注入导电区;
把可注入导电区拾取并放置到带膜上;以及
叠置带膜和可注入导电区。
18.根据权利要求17的方法,其中各个可注入导电区的对着附着到带膜的另一表面的一个表面已经得到用于导线接合的表面处理。
19.根据权利要求17的方法,进一步包括在叠置了可注入导电区与带膜之后在可注入导电区的表面上进行用于导线接合的表面处理的步骤。
20.根据权利要求11的方法,其中形成可注入导电区的步骤是通过在带膜上淀积一个用于可注入导电区的材料层并在该材料层上形成图案而进行的。
21.根据权利要求20的方法,其中淀积是借助化学汽相淀积(CVD)法或物理汽相淀积(PVD)法而进行的。
22.根据权利要求20的方法,进一步包括在形成了可注入导电区之后在可注入导电区的表面上进行用于导线接合的表面处理的步骤。
23.根据权利要求11的方法,其中形成可注入导电区的步骤包括以下的子步骤:
在带膜上形成用于可注入导电区的籽层;以及
利用该籽层进行电镀。
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- 2000-08-09 KR KR10-2000-0046165A patent/KR100414479B1/ko not_active IP Right Cessation
- 2000-10-03 US US09/677,601 patent/US6534849B1/en not_active Expired - Fee Related
- 2000-10-11 SG SG200005830A patent/SG91302A1/en unknown
- 2000-10-20 CN CN00131635A patent/CN1337738A/zh active Pending
- 2000-10-20 EP EP00309245A patent/EP1180792A1/en not_active Withdrawn
- 2000-10-30 JP JP2000331169A patent/JP2002057246A/ja active Pending
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CN1918702B (zh) * | 2004-02-09 | 2010-05-26 | 飞思卡尔半导体公司 | 采用多孔载体的管芯包封 |
CN102057485A (zh) * | 2008-06-04 | 2011-05-11 | 国家半导体公司 | 基于薄片的半导体封装 |
CN104756239A (zh) * | 2012-08-08 | 2015-07-01 | 马维尔国际贸易有限公司 | 使用由载体铜箔支撑的薄铜箔制作封装体的方法 |
CN103474406A (zh) * | 2013-09-27 | 2013-12-25 | 华天科技(西安)有限公司 | 一种aaqfn框架产品无铜扁平封装件及其制作工艺 |
CN107293523A (zh) * | 2016-03-30 | 2017-10-24 | 苏州保尔迪瓦电子科技有限公司 | 一种智能功率模块及其制造方法 |
Also Published As
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EP1180792A1 (en) | 2002-02-20 |
US6534849B1 (en) | 2003-03-18 |
JP2002057246A (ja) | 2002-02-22 |
SG91302A1 (en) | 2002-09-17 |
US20020048948A1 (en) | 2002-04-25 |
US6507096B2 (en) | 2003-01-14 |
KR100414479B1 (ko) | 2004-01-07 |
KR20020012902A (ko) | 2002-02-20 |
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