CN1577815A - 高密度芯片尺寸封装及其制造方法 - Google Patents

高密度芯片尺寸封装及其制造方法 Download PDF

Info

Publication number
CN1577815A
CN1577815A CNA2003101141672A CN200310114167A CN1577815A CN 1577815 A CN1577815 A CN 1577815A CN A2003101141672 A CNA2003101141672 A CN A2003101141672A CN 200310114167 A CN200310114167 A CN 200310114167A CN 1577815 A CN1577815 A CN 1577815A
Authority
CN
China
Prior art keywords
circuit board
printed circuit
pcb
tube core
encapsulation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2003101141672A
Other languages
English (en)
Inventor
郑永熙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electro Mechanics Co Ltd
Original Assignee
Samsung Electro Mechanics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electro Mechanics Co Ltd filed Critical Samsung Electro Mechanics Co Ltd
Publication of CN1577815A publication Critical patent/CN1577815A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

在此公开了能提高电路密度和扩展可形成电路区的高密度芯片尺寸封装。高密度芯片尺寸封装包括具有在其上形成的电路图形的管芯，适合于在其上安装管芯的印刷电路板。印刷电路板具有管芯面积的100％至150％的面积，印刷电路板具有在其上形成的电路图形。在管芯上安装用于辐射来自管芯热量的散热片。以及在印刷电路板和散热片之间填充密封剂，用于可靠地连接印刷电路板和散热片，以及从外部屏蔽印刷电路板。

Description

高密度芯片尺寸封装及其制造方法
技术领域
本发明涉及能增加电路密度和扩展可形成电路区的高密度芯片尺寸封装，更具体涉及不需要在常规技术中当散热片粘附到封装时需要准备的空腔和使用液体密封剂的高密度芯片尺寸封装，以便提高电路密度，扩展可形成电路区，增强散热片的热辐射效率，且能应用于通过引线键合和倒装芯片技术安装的任何一种芯片。
背景技术
如所属领域的技术人员所公知，随着电子工业高度发展，电子设备变得更小，同时它们具有增大的容量。IC芯片的进步不可避免地导致半导体的I/O(输入/输出)数增加。当半导体的I/O数增加时，从工作的IC芯片产生大量的热量。为了消除这种由IC芯片产生的大量热量，已提出一种新的封装，例如超大BGA(球栅阵列)板和增强BGA(E-BGA)板，通过粘附一块用作散热片的金属板例如铜板到一般封装来获得这每一种板。金属板直接粘附到IC芯片，用于将IC芯片产生的热量辐射到外部。
E-BGA印刷电路板是不同于常规BGA印刷电路板的新型BGA印刷电路板。例如，E-BGA印刷电路板是主要用于图形芯片的板，通常安装在游戏机或计算机中。与常规BGA印刷电路板不同，E-BGA印刷电路板具有用于散热的散热片，该散热片通过粘结剂整个地粘附到印刷电路板的一侧。E-BGA印刷电路板的另一侧布置焊料凸块，焊料凸块用于安装芯片和与其它板或母板连接。在具有布置的焊料凸块的E-BGA印刷电路板的一侧还形成空腔，其中安装管芯(die)。
超大BGA是具有更复杂结构的E-BGA，其中层叠多个印刷电路板，以形成多个层，以及散热片粘附到超大BGA。
图1a和1b分别示出了增强BGA(E-BGA)和超大BGA(S-BGA)板的剖视图。
参考图1a，印刷电路板103通过粘合剂102安装在散热片101上。散热片101的中央形成一个空腔，其中安装管芯104。通过在印刷电路板103上提供连接管芯的电路图形和引线键合焊盘105的引线106完成印刷电路板103和管芯104之间的连接。引线键合结构和管芯104覆有用于保护引线键合结构和管芯104的电路图形的环氧模压化合物(EMC)。
如上所述，由于散热片101完全覆盖封装的底面，因此E-BGA封装具有优良的热辐射效率。但是，目前通常使用的BGA(球栅阵列)技术不可用于将E-BGA封装安装到其它板。代替使用BGA技术，必须采用使用引线的引线框技术将E-BGA封装安装到其它板。
图1b中示出了超大BGA(S-BGA)板。与上述E-BGA一样，超大BGA具有粘附到印刷电路板112底面的散热片111。但是，超大BGA不同于E-BGA，其中另一个印刷电路板114层叠在印刷电路板112上，这是超大BGA的特点。印刷电路板114通过粘结剂113粘附到印刷电路板112。封装的中央形成一个空腔，其中安装管芯115。印刷电路板112通过连接到引线键合焊盘117的引线119电连接到管芯115。同样，印刷电路板114通过连接到引线键合焊盘118的引线120电连接到管芯115。引线键合结构和管芯115覆有用于保护引线键合结构和管芯115的电路图形的环氧模压化合物(EMC)116。
如上所述，增强BGA和超大BGA印刷电路板提供优良的热辐射效率和高可靠性。另一方面，制造增强BGA印刷电路板或超大BGA印刷电路板的工艺是复杂的，以及形成精确的电路图形是困难的。
根据趋势提出了一种芯片尺寸封装(CSP)，以使电子工业中的各种产品更轻、更薄和更小。芯片尺寸封装是封装面积几乎等于管芯面积的封装，管芯安装在芯片尺寸封装中。常规封装具有大的封装面积，其中足以安装几个管芯，而芯片尺寸封装的封装面积不超过在芯片尺寸封装中安装的管芯面积的150％。此外，不通过使用常规的引线框，而是通过粘附几个焊球到封装的底面将芯片尺寸封装安装到其它基板。也就是说，通过使用所谓的BGA(球栅阵列)技术将芯片尺寸封装安装到其它基板，这是芯片尺寸封装的一个特点。
如上所述，尽管具有粘附到其表面的散热片的增强BGA印刷电路板或超大BGA印刷电路板提供优良的热辐射效率和高可靠性，但是用于制造增强BGA印刷电路板或超大BGA印刷电路板的工艺是复杂的，形成精确的电路图形是困难的。结果，难以将增强BGA印刷电路板或超大BGA印刷电路板应用于芯片尺寸封装。而且，由此增加制造增强BGA印刷电路板或超BGA印刷电路板的成本。由于这个缘故，随着C2BGA(传导冷却球栅阵列)已取得进展的结果，制造公司已考虑具有优良的热性能和可靠性的廉价板。C2BGA是具有散热片的板，散热片粘附到其表面，其中散热片通过焊料剂键合到板，以及通过与一般表面安装技术一样的回流工艺粘附到板。
图2a至2j示出了用于制造上述冷却传导GBA(C2BGA)工序的剖视图。
图2a是覆铜薄层压板201处理之前的剖视图。如图2a所示，绝缘层203涂敷有铜箔202。通常，覆铜薄层压板是包括绝缘层和在绝缘层上涂敷薄铜箔的薄迭层，薄迭层是用于制造印刷电路板的未加工基板。
覆铜薄层压板根据它的使用分为玻璃/环氧树脂覆铜薄层压板、耐热树脂覆铜薄层压板、纸/石炭酸覆铜薄层压板、高频覆铜薄层压板、韧性覆铜薄层压板(聚酰亚胺薄膜)以及化合物覆铜薄层压板。其中，玻璃/环氧树脂覆铜薄层压板主要用于制造双面印刷电路板和多层印刷电路板。
玻璃/环氧树脂覆铜薄层压板由通过使环氧树脂(树脂和硬化剂的混合物)渗入玻璃纤维获得的增强材料和铜箔构成。玻璃/环氧树脂覆铜薄层压板根据增强材料分类。例如，玻璃/环氧树脂覆铜薄层压板根据增强材料和抗热性可以分为FR-1至FR-5，这些是由NEMA(美国电气制造协会)规定的。上述五个等级之中，尽管具有增加玻璃瞬变温度的树脂性能的FR-5的需要正在增加，但等级FR-4使用最多。
如图2b所示，钻孔覆铜薄层压板201以形成电路层之间的电路连接需要的通孔204。覆铜薄层压板201例如可以通过机械打孔法或激光打孔法钻孔。
如图2c所示，覆铜薄层压板201通过非电解铜电镀法和电解铜电镀法电镀，以在板的表面上和通孔204的内壁上形成镀铜层205。首先进行非电解铜电镀法，然后进行电解铜电镀法。在进行电解铜电镀方法之前进行非电解铜电镀方法的理由是电解铜电镀法需要电，不能在绝缘层203上进行。换句话说，首先进行非电解铜电镀法，以形成电解铜电镀法需要的导电薄膜。但是，进行非电解铜电镀法是困难的和不经济的，形成电路图形的导电部分优选地通过电解铜电镀法形成。
如图2d所示，在通孔206中填充膏剂206，以保护形成在通孔内壁上的非电解镀铜层和电解镀铜层205，然后通过刻蚀形成电路图形。尽管根据印刷电路板的使用目的，可以使用任意的导电膏剂，但是通常使用绝缘油墨材料作为膏剂。导电膏剂是至少一种金属例如铜、银、金、锡和铅和有机粘合剂的混合物。但是，根据MLB的制造目的，可以省去如上所述的膏剂填充工序。
如图2e所示，穿过封装形成一个空腔207，其中安装管芯。空腔207例如可以通过机械打孔法或冲压法来形成。
如图2f所示，在除待连接到其它电路图形或其它板外的剩下部分上印刷抗焊剂208。
如图2g所示，用于电路连接的部分，例如引线或焊球，即，没有涂敷抗焊剂208露出的镀铜层205的部分用镍/金电镀，以形成镍/金电镀层209。当形成镍/金电镀层时，抗焊剂208用作电镀抗蚀剂。因此，镍/金电镀层209仅形成在没有印刷抗焊剂208的部分上。如之后所述，在镍/金电镀层209上形成为引线键合提供的引线键合焊盘。首先进行镍电镀，然后进行金电镀。结果，只有金电镀层露出。在镍电镀之后接着进行金电镀的理由是氧化露出的铜箔部分，这部分没有覆盖抗焊剂，增强待安装部分的焊接效率，以及获得良好的导电性。
随后，在封装的底面形成焊球210，用于将封装直接安装到其它基板。焊球210用来将本发明的封装直接安装到其它板。焊球210连接到在其它板提供的其它焊球，以便在板之间完成电连接。通过这种焊球210安装到其它板的板叫作BGA(球栅阵列)板。
如图2h所示，散热片211粘附到封装的底面。
如图2i所示，在散热片211的顶面涂敷焊料膏213。在涂敷的焊料膏213上安装管芯212。管芯212通过回流工序粘附到散热片211。随后，在镍/金电镀层209上形成键合焊盘214。键合焊盘214通过引线215连接到管芯212的电路图形。
如图2j所示，引线键合结构和管芯212覆有用于保护引线键合结构和管芯212露出的电路图形的环氧模压化合物(EMC)216。环氧模压化合物是固态材料，通过加热熔融。熔融的环氧模压化合物流到模具中，以获得希望形状的环氧模压化合物，环氧模压化合物最后覆盖在封装上。
如上所述，用于制造C2BGA的工序一般类似于制造普通板的工序。但是，根据制造C2BGA的工序，空腔形成在封装的中央，散热片安装在空腔中，因此减小形成焊球需要的有效面积与封装的总面积的比率，限制管脚数。
国际专利公开号WO02/13586，名称为“ADHESIVE BONDING OFPRINTED CIRCUIT BOARDS TO HEAT SINKS”公开了一种用于将从印刷电路板产生的热量有效地传递到散热片的结构。其中在印刷电路板和散热片之间的空隙(voids)中填充压敏粘接层和热固性粘接层。
韩国专利未审查公开号KR2001-0009153，名称为“PACKAGESTRUCTURE WITH HIGH HEAT RADIATION HEAT SPREADER FORTHIN SYSTEM AND METHOD OF MANUFACTURING THE SAME”公开了一种用于提高安装在用于计算机母板的插座中的芯片尺寸封装的热辐射效率的结构，其中散热片布置在芯片尺寸封装的顶部。散热片具有倾斜面，在倾斜面形成气孔和气缝，以便来自用于冷却母板的冷却风扇的气流通过气孔和气缝。但是，上述出版物公开的结构具有冷却风扇，限制了它的可适用范围。
发明内容
因此，本发明考虑了上述问题，本发明的目的是提供一种高密度芯片尺寸封装，采用适合于增加形成焊球需要的有效面积与封装的总面积比率和增加管脚数的热辐射结构，以及制造这种高密度芯片尺寸封装的方法。
本发明的另一个目的是提供一种高密度芯片尺寸封装，不包括在印刷电路板中安装管芯需要的空腔，由此增加形成焊球需要的有效面积和也增加管脚数，以及制造这种高密度芯片尺寸封装的方法。
本发明的再一个目的是提供一种高密度芯片尺寸封装，采用可应用于其中管芯通过引线键合和倒装芯片技术来安装的封装的热辐射结构，以及制造这种高密度芯片尺寸封装的方法。
本发明的再一个目的是提供一种高密度芯片尺寸封装，其中散热片通过热传导环氧树脂粘结剂粘附到管芯的顶面，由此增强管芯和散热片之间的热传递，以便平稳地辐射热量，以及制造这种高密度芯片尺寸封装的方法。
根据本发明的一个方面，通过准备高密度芯片尺寸封装可以完成上述及其它目的，该封装包括：其上形成有电路图形的管芯；用于在其上安装管芯的印刷电路板，印刷电路板具有管芯面积的100％至150％的面积，印刷电路板具有在其上形成的电路图形；安装在管芯上的散热片，用于辐射来自管芯的热量；以及在印刷电路板和散热片之间填充的密封剂，用于可靠地连接印刷电路板和散热片以及从外部屏蔽印刷电路板。
优选地，管芯通过热传导环氧树脂粘结剂粘附在印刷电路板上。
优选地，密封剂是环氧基液态密封剂。
优选地，管芯包括形成在其底表面的多个焊球，以便管芯通过焊球电连接到印刷电路板。
优选地，高密度芯片尺寸封装还包括在管芯和印刷电路板之间限定的空间中填充的液态密封剂。
优选地，印刷电路板具有在其底表面形成的焊料球，用于将具有在其上安装的芯片的印刷电路板安装到其它电路板。
根据本发明的另一个方面，提供一种制造高密度芯片尺寸封装的方法，该方法包括以下步骤：将具有在其上形成的电路图形的管芯安装到具有管芯面积的100％至150％的面积的印刷电路板上，印刷电路板具有在其上形成的电路图形；在管芯上安装用于辐射来自管芯的热量的散热片；在印刷电路板和散热片之间填充液态密封剂；以及固化在印刷电路板和散热片之间填充的液态密封剂。
优选地，在将散热片安装在管芯的步骤中通过热传导环氧树脂粘结剂将散热片粘接到管芯上。
优选地，填充液态密封剂的步骤包括除去来自填充的液态密封剂的空隙。
优选地，通过热固化工序进行固化液态密封剂的步骤。
优选地，将管芯安装到印刷电路板上的步骤包括：在管芯底面形成多个焊球；以便通过焊球电连接管芯和印刷电路板。
优选地，将管芯安装到印刷电路板上的步骤还包括：在管芯和印刷电路板之间限定的空间填充液态密封剂；以及除去来自填充的液态密封剂的空隙。
优选地，制造高密度芯片尺寸封装的方法还包括：在印刷电路板的底表面形成焊球，以便将其上具有管芯的印刷电路板安装到其它印刷电路板上。
附图说明
从下面结合附图的详细说明将更清楚地理解本发明的上述及其它目的、特点和其它优点。
图1a和Ib分别示出了增强BGA(E-BGA)和超大BGA(S-BGA)板的剖视图。
图2a至2j示出了用于制造常规冷却传导GBA(C2BGA)的工序的剖视图；
图3a至3i示出了根据本发明的优选实施例，采用热辐射结构制造高密度芯片尺寸封装的工序的剖视图，其中通过引线键合技术将管芯安装在封装上；以及
图4a至4i示出了根据本发明的另一个优选实施例，采用热辐射结构制造高密度芯片尺寸封装的工序的剖视图，其中通过倒装芯片技术将管芯安装在封装上。
具体实施方式
图3a至3i示出了根据本发明的优选实施例，采用热辐射结构制造高密度芯片尺寸封装的工序的剖视图，其中通过引线键合技术将管芯安装在封装上。
图3a是覆铜薄层压板301的剖视图，是用于本发明的高密度芯片尺寸封装的基板。如图3a所示，绝缘层303覆有铜箔302。有各种覆铜薄层压板。但是，主要使用由通过使环氧树脂(树脂和硬化剂的混合物)渗入玻璃纤维获得的增强材料和铜箔构成的玻璃/环氧树脂覆铜薄层压板。特别，命名为FR-4的覆铜薄层压板最常使用。FR-4覆铜薄层压板用作本发明的覆铜薄层压板，尽管本发明不受覆铜薄层压板的种类限制。
如图3b所示，钻孔覆铜薄层压板301，以形成电路层之间电路连接需要的通孔304。尽管例如可以通过机械打孔法或激光打孔法钻孔覆铜薄层压板301，但是当形成相对小的通孔时优选地使用激光打孔法。
如图3c所示，通过非电解铜电镀法和电解铜电镀法电镀覆铜薄层压板301。首先通过非电解铜电镀法形成薄镀铜层，然后通过电解铜电镀法在板的外面和通孔304的内壁形成导电镀层305。随后，在通孔306中填充绝缘膏剂。如图3c所示的电镀层305包括电镀层和非电镀层。
如图3d所示，在通孔206中填充用于保护在通孔304的内壁上形成的非电解铜电镀和电解镀铜电镀层305的膏剂206，然后通过刻蚀，在电镀层305上形成电路图形。如下完成通过刻蚀形成的电路图形：涂敷抗腐剂，例如干膜，通过曝光和显影形成抗蚀剂图形，通过蚀刻液除去除电路图形外的剩下部分。
如图3e所示，在除待连接到焊球和引线部分的其它剩下部分印刷抗焊剂307。
如图3f所示，用于电路连接的部分，例如引线或焊球，即不涂敷抗焊剂307且因此露出镀铜层305的部分用镍/金电镀，以形成镍/金电镀层308。当形成镍/金电镀层308时，如图3e所示的抗焊剂307用作电镀抗蚀剂。因此，仅在没有印刷抗焊剂307的部分上形成镍/金电镀层308。如下所述，在镍/金电镀层308上形成为引线键合提供的引线键合焊盘。首先进行镍电镀，然后进行金电镀。结果，只有金电镀层露出。在镍电镀之后接着进行金电镀的理由是氧化露出的铜箔部分，这部分没有覆盖抗焊剂，增强待安装部分的焊接效率，获得良好的导电性。
随后，在封装的底面形成焊球309，用于将封装直接安装到其它基板。焊球309用来将本发明的封装直接安装到其它板。焊球309连接到在其它板提供的其它焊球，以便在板之间完成电连接。也就是说，通过所谓的BGA(球栅阵列)技术将本发明的高密度芯片尺寸封装安装在另一个板上。
如图3g所示，在抗焊剂层307上涂敷粘结剂310，管芯311安装在粘结剂310上。随后，在镍/金电镀层308上形成为引线键合提供的引线键合焊盘312。引线键合焊盘312通过引线313连接到管芯311的电路图形，以便管芯的电路电连接到封装的电路。覆铜薄层压板301的面积封装中安装的管芯311的面积的100％至150％，优选地100％至120％，覆铜薄层压板301是用于本发明的封装基板。
如图3h所示，在管芯311上涂敷环氧树脂粘结剂314，其上粘接散热片315。在本发明的高密度芯片尺寸封装中，散热片315直接安装在管芯311上，散热片315通过环氧树脂粘结剂314可靠地粘附到管芯311。因此，实现平稳的热辐射。
如图3i所示，不仅在封装基板和散热片315之间的封装基板上露出的电路层上而且在抗焊剂层307上涂敷用于从外部保护露出的电路层和抗焊剂层307的液态密封剂316。随后，从液态密封剂316除去空隙，通过使用加热热固化液态密封剂316，这是液态密封剂316的固化工序。热固化的密封剂316用来保护内电路免受外部损坏因素例如湿度或碰撞影响。
通常用来保护内电路免受外部损害因素影响的EMC(环氧模压化合物)是固态，不是液态。因此，当EMC涂敷到封装时，给封装带来物理碰撞。另一方面，当使用液态密封剂时，这种物理碰撞是可以避免的。
如上所述，用于满足封装最小化提供的芯片尺寸封装(CSP)的特征在于：封装的面积是安装在其上的管芯(芯片)面积的100％至150％，以及其中高密度芯片尺寸封装通过焊球309直接安装在另一个板上。本发明的高密度芯片尺寸封装如图3a至3h所示，可以制造高密度和减小尺寸而不减小热辐射效率的封装。
图4a至4i示出了根据本发明的另一个优选实施例，采用热辐射结构制造高密度芯片尺寸封装的工序的剖视图，其中通过倒装芯片技术将管芯安装在封装上。
图4a是覆铜薄层压板401的剖视图，覆铜薄层压板401是用于本发明的高密度芯片尺寸封装的基板。用于本发明的该实施例的板与图3a所示的板相同。因此，尽管本发明不受上述覆铜薄层压板限制，但是命名为FR-4的覆铜薄层压板用作本发明的覆铜薄层压板。如图4a所示，绝缘层403覆有铜箔402。
如图4b所示，钻孔覆铜薄层压板401，以形成电路层之间的电路连接需要的通孔404。尽管可以例如通过机械打孔法或激光打孔法钻孔覆铜薄层压板401，但是当形成相对小的通孔时，优选地使用激光打孔法。
如图4c所示，通过非电解铜电镀法和电解铜电镀法完全电镀覆铜薄层压板401。首先通过非电解铜电镀法形成薄镀铜层，然后通过电解铜电镀法在板的外面和通孔404的内壁形成导电镀层405。随后，在通孔406中填充绝缘膏剂406。如图4c所示的电镀层405包括电解电镀层和非电解电镀层。
如图4d所示，通过刻蚀在围绕板的导电电镀层405上形成电路图形。如下完成通过刻蚀形成的电路图形：涂覆抗蚀剂，比如干膜，通过曝光和显影形成抗蚀剂图形，通过刻蚀液除去除电路图形外的剩下部分。
如图4e所示，在除待连接焊球和引线的部分外的剩下部分上，即，在除形成用于电路连接的焊球焊盘和引线键合焊盘部分外的剩下部分上印刷抗焊剂407，保护形成在电镀层405上的电路图形。
如图4f所示，用于电路连接的部分，例如引线或焊球，即未涂敷抗焊剂407且因此露出镀铜层405的部分用镍/金电镀，以形成镍/金电镀层408。当形成镍/金电镀层408时，如图4e所示的抗焊剂407用作电镀抗蚀剂。因此，仅在没有印刷抗焊剂407的部分上形成镍/金电镀层408。首先进行镍电镀，然后进行金电镀。结果，只有金电镀层露出。在镍电镀之后接着进行金电镀的理由是氧化露出的铜箔部分，这部分没有覆盖抗焊剂，增强待安装部分的焊接效率，以及获得良好的导电性。
随后，在封装的底面形成焊球409，用于将封装直接安装到其他基板。焊球409用来将本发明的封装直接安装在其它的板上。焊球409连接到在其它板上提供的其它焊球，以便在本发明的封装和其它板之间完成电连接。也就是说，通过所谓的BGA(球栅阵列)技术将本发明的高密度芯片尺寸封装安装在另一个板上。
如图4g所示，在抗焊剂层407上安装具有在其底面形成的焊球411的管芯410。在管芯410和抗焊剂层407之间，即，未布置焊球411的空间中填充液态下填充密封剂412，热固化密封剂以可靠地连接管芯410和抗焊剂层407。覆铜薄层压板401的面积是封装中安装的管芯410的100％至150％，优选地100％至120％。
如图4h所示，在管芯410上涂敷环氧树脂粘结剂413，其上粘接散热片414。在本发明的高密度芯片尺寸封装中，散热片414直接安装在管芯410上，散热片414通过环氧树脂粘结剂413可靠地粘附到管芯410，用与参考图3a至3i描述的工序一样的方法。因此，完成平稳的热辐射。
如图4i所示，不仅在封装基板和散热片414之间的封装基板上露出的电路层上而且在抗焊剂层407上涂敷用于从外部屏蔽露出的电路层和抗焊剂层407的液态密封剂316。随后，从液态密封剂415除去空隙，通过使用加热热固化液态密封剂415，这是液态密封剂415的固化工序。优选地，密封剂415是环氧基液态密封剂。
热固化的密封剂415用来保护内电路免受外部损坏因素例如湿度或碰撞影响。可以和参考图4h描述的液态下填充密封剂412一样，在散热片414和封装之间限定的空间中填充液态密封剂415，。
如上所述，本发明提供一种高密度芯片尺寸封装，采用适合于增加形成焊球需要的有效面积与封装的总面积的比率和增加管脚数而不减少热辐射效率的热辐射结构。
本发明的高密度芯片尺寸封装不包括在印刷电路板中安装管芯需要的空腔，由此增加形成焊球需要的有效面积以及也增加管脚数。
而且，本发明提供一种采用热辐射结构的高密度芯片尺寸封装，可适用于通过引线键合和倒装芯片技术安装管芯而不减少热辐射效率的封装。
此外，散热片通过导热环氧树脂粘结剂粘附到管芯的顶面，结果管芯和散热片之间热传递，因此平稳地辐射热量。
尽管为了说明已公开了本发明的优选实施例，但是本领域的普通技术人员应当理解：在不脱离所附的权利要求所公开的本发明的范围和精神的条件下，可以进行各种修改、增加和替换。

Claims (7)

1.一种高密度芯片尺寸封装，包括：
其上形成有电路图形的管芯；
其上适合于安装管芯的印刷电路板，印刷电路板具有管芯面积的100％至150％的面积，印刷电路板具有在其上形成的电路图形；
安装在管芯上的散热片，用于辐射来自管芯的热量；
以及在印刷电路板和散热片之间填充的密封剂，用于可靠地连接印刷电路板和散热片以及从外部屏蔽印刷电路板。
2.如权利要求1所述的封装，其中管芯通过热传导环氧树脂粘结剂粘附在印刷电路板上。
3.如权利要求1所述的封装，其中密封剂是环氧液态密封剂。
4.如权利要求1所述的封装，其中印刷电路板包括引线键合焊盘，以便管芯通过用于连接管芯和引线键合焊盘的引线电连接到印刷电路板。
5.如权利要求1所述的封装，其中管芯包括在其底面形成的多个焊球，以便管芯通过焊球电连接到印刷电路板。
6.如权利要求5所述的封装，还包括在管芯和印刷电路板之间限定的空间中填充的液态密封剂。
7.如权利要求1所述的封装，其中印刷电路板具有在其底面形成的焊球，用于将具有在其上安装的管芯的印刷电路板安装到其它印刷电路板上。
CNA2003101141672A 2003-06-28 2003-11-06 高密度芯片尺寸封装及其制造方法 Pending CN1577815A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020030042935A KR20050001930A (ko) 2003-06-28 2003-06-28 고밀도 칩 스케일 패키지 및 그 제조 방법
KR42935/2003 2003-06-28

Publications (1)

Publication Number Publication Date
CN1577815A true CN1577815A (zh) 2005-02-09

Family

ID=33536356

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2003101141672A Pending CN1577815A (zh) 2003-06-28 2003-11-06 高密度芯片尺寸封装及其制造方法

Country Status (5)

Country Link
US (1) US20040262746A1 (zh)
JP (1) JP2005019937A (zh)
KR (1) KR20050001930A (zh)
CN (1) CN1577815A (zh)
TW (1) TW200501854A (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103794575A (zh) * 2014-01-24 2014-05-14 清华大学 一种封装结构及封装方法
CN101584044B (zh) * 2006-12-12 2014-12-17 艾格瑞系统有限公司 集成电路封装体和用于在集成电路封装体中散热的方法
CN105555013A (zh) * 2014-10-23 2016-05-04 三星电子株式会社 制造印刷电路板组件的方法
CN106449513A (zh) * 2016-11-11 2017-02-22 华南理工大学 一种防过热csp荧光膜片模压装置及方法
CN107093588A (zh) * 2017-04-21 2017-08-25 中航（重庆）微电子有限公司 一种芯片双面垂直封装结构及封装方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7166906B2 (en) * 2004-05-21 2007-01-23 Samsung Electronics Co., Ltd. Package with barrier wall and method for manufacturing the same
JP4431901B2 (ja) * 2007-01-19 2010-03-17 セイコーエプソン株式会社 半導体装置
US7998791B2 (en) * 2008-02-01 2011-08-16 National Semiconductor Corporation Panel level methods and systems for packaging integrated circuits with integrated heat sinks
JP6008582B2 (ja) * 2012-05-28 2016-10-19 新光電気工業株式会社 半導体パッケージ、放熱板及びその製造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5285352A (en) * 1992-07-15 1994-02-08 Motorola, Inc. Pad array semiconductor device with thermal conductor and process for making the same
JP3454888B2 (ja) * 1993-11-24 2003-10-06 富士通株式会社 電子部品ユニット及びその製造方法
JP3056960B2 (ja) * 1993-12-27 2000-06-26 株式会社東芝 半導体装置及びｂｇａパッケージ
KR970005712B1 (ko) * 1994-01-11 1997-04-19 삼성전자 주식회사 고 열방출용 반도체 패키지
US5528457A (en) * 1994-12-21 1996-06-18 Gennum Corporation Method and structure for balancing encapsulation stresses in a hybrid circuit assembly
JPH09306954A (ja) * 1996-05-20 1997-11-28 Hitachi Ltd 半導体装置及びその実装方法並びに実装構造体
US6225695B1 (en) * 1997-06-05 2001-05-01 Lsi Logic Corporation Grooved semiconductor die for flip-chip heat sink attachment
US5977626A (en) * 1998-08-12 1999-11-02 Industrial Technology Research Institute Thermally and electrically enhanced PBGA package
US6146921A (en) * 1998-09-16 2000-11-14 Intel Corporation Cavity mold cap BGA package with post mold thermally conductive epoxy attach heat sink
US6739497B2 (en) * 2002-05-13 2004-05-25 International Busines Machines Corporation SMT passive device noflow underfill methodology and structure

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101584044B (zh) * 2006-12-12 2014-12-17 艾格瑞系统有限公司 集成电路封装体和用于在集成电路封装体中散热的方法
CN103794575A (zh) * 2014-01-24 2014-05-14 清华大学 一种封装结构及封装方法
CN108615711A (zh) * 2014-01-24 2018-10-02 清华大学 一种基于模板的封装结构及封装方法
CN105555013A (zh) * 2014-10-23 2016-05-04 三星电子株式会社 制造印刷电路板组件的方法
US10426041B2 (en) 2014-10-23 2019-09-24 Samsung Electronics Co., Ltd Method of manufacturing printed-circuit board assembly
CN105555013B (zh) * 2014-10-23 2020-09-08 三星电子株式会社 制造印刷电路板组件的方法
CN106449513A (zh) * 2016-11-11 2017-02-22 华南理工大学 一种防过热csp荧光膜片模压装置及方法
CN107093588A (zh) * 2017-04-21 2017-08-25 中航（重庆）微电子有限公司 一种芯片双面垂直封装结构及封装方法
CN107093588B (zh) * 2017-04-21 2019-09-03 华润微电子（重庆）有限公司 一种芯片双面垂直封装结构及封装方法

Also Published As

Publication number Publication date
JP2005019937A (ja) 2005-01-20
KR20050001930A (ko) 2005-01-07
TW200501854A (en) 2005-01-01
US20040262746A1 (en) 2004-12-30

Similar Documents

Publication Publication Date Title
CN1230894C (zh) 半导体封装及其制造方法
US7948076B2 (en) Semiconductor chip assembly with post/base heat spreader and vertical signal routing
US8378372B2 (en) Semiconductor chip assembly with post/base heat spreader and horizontal signal routing
US8163603B2 (en) Method of making a semiconductor chip assembly with a post/base heat spreader and a substrate using grinding
KR100327491B1 (ko) 프린트배선판 및 그 제조방법
US8841171B2 (en) Method of making stackable semiconductor assembly with bump/flange heat spreader and dual build-up circuitry
US20120126401A1 (en) Stackable semiconductor assembly with bump/base/flange heat spreader and electromagnetic shielding
CN1352804A (zh) 高密度电子封装及其制造方法
US8269336B2 (en) Semiconductor chip assembly with post/base heat spreader and signal post
JP4730426B2 (ja) 実装基板及び半導体モジュール
CN1525544A (zh) 利用无引线电镀工艺制造的封装基片及其制造方法
CN1797758A (zh) 具有半－刻蚀键合焊盘和切割电镀线的bga封装及其制造方法
US20140291001A1 (en) Method of making hybrid wiring board with built-in stiffener and interposer and hybrid wiring board manufactured thereby
US8895380B2 (en) Method of making semiconductor assembly with built-in stiffener and semiconductor assembly manufactured thereby
US8415703B2 (en) Semiconductor chip assembly with post/base/flange heat spreader and cavity in flange
US8148747B2 (en) Semiconductor chip assembly with post/base/cap heat spreader
CN1509134A (zh) 电路装置、电路模块及电路装置的制造方法
CN1577815A (zh) 高密度芯片尺寸封装及其制造方法
JP2021044530A (ja) 埋め込み部品のパッケージ構造及びその製造方法
US8110446B2 (en) Method of making a semiconductor chip assembly with a post/base heat spreader and a conductive trace
CN210575901U (zh) 具有高散热性的板级扇出封装结构
US20100052005A1 (en) Semiconductor chip assembly with post/base heat spreader and conductive trace
CN1591805A (zh) 热增强型球栅阵列集成电路封装基板制造方法及封装基板
CN101064259A (zh) 半导体封装件及其芯片承载结构与制法
IES20030458A2 (en) Electronics circuit manufacture

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication