CN1352804A - 高密度电子封装及其制造方法 - Google Patents

高密度电子封装及其制造方法 Download PDF

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Publication number
CN1352804A
CN1352804A CN00807754A CN00807754A CN1352804A CN 1352804 A CN1352804 A CN 1352804A CN 00807754 A CN00807754 A CN 00807754A CN 00807754 A CN00807754 A CN 00807754A CN 1352804 A CN1352804 A CN 1352804A
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China
Prior art keywords
flexible dielectric
dielectric adhesive
plug
conductor
flexible
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CN00807754A
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English (en)
Inventor
凯文·K·T·钟
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Amerasia International Technology Inc
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Amerasia International Technology Inc
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Publication of CN1352804A publication Critical patent/CN1352804A/zh
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
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    • B32B37/00—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding
    • B32B37/14—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the properties of the layers
    • B32B37/16—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the properties of the layers with all layers existing as coherent layers before laminating
    • B32B37/20—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the properties of the layers with all layers existing as coherent layers before laminating involving the assembly of continuous webs only
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    • B32B3/02—Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shape; Layered products comprising a layer having particular features of form characterised by features of form at particular places, e.g. in edge regions
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Abstract

高密度电子封装(100,100″,300,300′)包括一个低弹性模量的挠性粘合剂内插件衬底(110,210,310,330,500),电子器件(120,320,620,622,624,626)如半导体芯片或管芯或其它元件附着其上。挠性粘合剂内插件衬底(110,210,310,330,500)包括一片或一层其中有穿孔的分子挠性粘合剂(111,211,311,331,520,530),在该片或层中建立连接到电子器件(120,320,620,622,624,626)连接端子的导体通道(112,212,312,315,335,550,618)。对挠性粘合剂片(111,211,311,331,520,530)一个表面上的薄层金属箔(113,213,313,510,540)形成图案以提供连接端子并电连接到导体通道(112,212,312,315,335,550,618)。电子器件(120,320,620,622,624,626)可以被一个盖(130)或一种连接到挠性粘合剂内插件衬底(110,210,310,330,500)和/或电子器件(120,320,620,622,624,626)的密封剂(137)覆盖。电子封装(300)可以包括多个电子器件(320－1,320－2,320－3)和电互连的各个挠性粘合剂内插件(310－1,310－2,310－3,330－1,330－2,330－3)。

Description

高密度电子封装及其制造方法
                        技术领域
本发明涉及一种电子器件封装，并尤其涉及一种包括挠性衬底的电子器件封装，挠性衬底包含一种低弹性模量的挠性介电粘合剂。
                        背景技术
随着半导体集成电路技术的发展，大大提高了可以制作在单个半导体芯片上的电路数量和操作速度，由于连接芯片的输入和输出端子数量的增大以及这些连接端子之间间隔或间距的减小使得有效利用这些集成电路变得更加困难。在连接端子的数量超过常规的机械封装中能方便经济地得到的数量的时候，连接问题变得更加严重。
解决此类问题的一个方法是使用安装在下面(next-lever)电路板上的半导体芯片，连接端子接触并连接到相应的端子，即所谓的“倒装”安装。此倒装技术要求下面电路板上的连接端子与半导体芯片上的连接端子有相同的大小和相同的间距。特别是，半导体芯片连接的间距变得比常规的机械封装上和安装半导体芯片的电子线路板上可得到的间距细很多。另外，当暴露于热循环、通常由于互连其间的焊料的刚性而加重应力时，半导体芯片和下面电路板之间热膨胀的差异产生热感应力，导致互连的失败或降质。
解决此类问题的还有一个办法是在半导体芯片和下面的电路板之间采用一个中间衬底以吸收一些热感应力，并还使得能够分开与半导体芯片的连接，从而允许有一个能与常规的印刷电路板技术兼容的大连接尺寸和间距。如果中间衬底实际上大于半导体芯片的尺寸，则小尺寸芯片的优点将丧失，同样丧失的是提高了以极高的工作频率工作的能力的短导线长度的优点。虽然这可通过减小中间衬底的尺寸并采用能够细化线条宽度的下面衬底技术而得到改善，但中间衬底的刚性又造成了一些困难。中间衬底的周长不大于安置其上的半导体芯片的周长20％情况下的电子封装通常被称作“芯片尺度的器件封装”，尽管通常把较大的器件封装也称作“芯片尺度的器件封装”。
刚性中间衬底的难度在制造称之为“挠性”的特殊材料的衬底，如薄聚酰亚胺和其它所谓的“挠性”常规衬底，在其上可以通过常规的方法形成印刷导线和电镀穿孔。但是，这种衬底材料不是真正的挠性材料，而只是有较大的柔性，因为它不具有很低的弹性模量，由较高弹性模量的较薄材料制成。常规的材料如聚酰亚胺片具有较高的弹性模量，如大于70,000kg/cm2(1,000,000psi)的模量。另外，这种材料的使用和常规的制造方法导致不期望的高成本，并且可能需要执行更困难或昂贵的组装过程。
另外，通常优选防湿气进入的闭合腔器件封装，如通常用在高可靠性、军用、航天和医疗电子应用中以及光学器件和对频率敏感的通讯器件的密封器件封装。器件封装的防湿气进入的能力或允许湿气易于出去的能力对于操作可靠性是很重要的。
由于金属和/或陶瓷器件封装、用于密封器件封装盖的较慢的方法和较高的劳动量，使得常规的密封腔型器件封装非常昂贵。加盖的腔式器件封装比陶瓷器件封装便宜很多，但比灌封包封(encapsulated package)的器件封装如模铸的环氧树脂或模铸的塑料胶片包封的器件封装仍然贵很多，而这些类型的器件封装在商业电子应用中的比例大约为95-99％。甚至使用精密的分配设备，由于分配封装剂精确量所固有的缓慢过程，顶滴灌封封装(glob-top encapsulated)的器件封装比模铸的器件封装贵很多。具体地说，与只有US$0.01-0.05(不包括加工)材料成本的模铸环氧树脂器件封装相比，密封腔型器件封装可有US$0.90-1.00或更大的材料成本，并且常规的带有分布粘合剂的加盖器件封装可具有US$0.20-0.40的材料成本。
因此，需要一种这样的电子封装，即适于高密度(即芯片尺度的)器件封装，并且避免了常规的模铸器件封装的技术缺陷，没有常规的密封器件封装的高成本。
                        发明内容
为此目的，本发明包括一种具有用于连接到衬底的连接端子的电子封装，其中电子封装至少包括一个电子器件，所述的电子器件上具有多个连接端子，一个挠性介电粘合剂内插件(interposer)，和用于把电子器件的连接端子连接到某一特定的导体通道(via)的装置。挠性介电粘合剂内插件至少包括一层弹性模量小于35,000kg/cm2(大约500,000psi)的挠性介电粘合剂，多个经挠性介电粘合剂层的导体通道，其中多个导体通道中的至少某些对应于电子器件某些连接端子以及挠性介电粘合剂层一个表面上的金属箔，其中金属箔上被形成图案并与导体通道中的一个电连接。多个导体通道和形成有图案的金属箔中的一个包括用于连接到衬底的连接端子。
根据本发明的另一方面，多个电子器件的电子封装包括多个电子器件，每个电子器件上具有一种多个连接端子的图案，多个挠性介电粘合剂内插件，每个内插件与多个电子器件中的至少一个相连，还包括用于把多个电子器件的每一个的连接端子连接到与其相关的挠性介电粘合剂内插件的一个特定导体通道的装置。每个挠性介电粘合剂内插件至少包括一层弹性模量小于大约35,000kg/cm的挠性介电粘合剂层，多个经过挠性介电粘合剂层的导体通道，其中至少多个导体通道中的某些对应于多个电子器件中相连的某些连接端子和挠性介电粘合剂层一个表面上的金属箔，其中金属箔上被形成图案并与导体通道中的某些电连接。多条导体通道中的至少一个和形成有图案的金属箔包括用于把挠性介电粘合剂内插件连接到外部器件的外接端子。多个挠性介电粘合剂内插件彼此相邻放置并还包括用于把多个挠性介电粘合剂内插件的每一个的外接端子连接到多个挠性介电粘合剂内插件中相邻的一个内插件的外接端子的装置。
另外，用于制作电子封装的方法包括：
提供一个金属箔片；
在金属箔片的一个表面上设置至少一层弹性模量约小于35,000kg/cm(大约500,000psi)的挠性介电粘合剂，挠性介电粘合剂层中具有多个通孔；
在金属箔上建立导体材料以填充通孔，由此在其中形成导体通道；
对金属箔形成图案以形成电连接到挠性介电粘合剂层中导体通道的连接端子和导体的图案；
电镀至少一个导体通道和形成有图案的金属箔的连接端子，以提供外接端子；和
电连接至少一个电子器件的连接端子与对应的一条导体通道。
                        附图说明
通过参考下列附图，对本发明优选实施例的详细描述将有更容易更好的理解，其中附图包括：
图1和2是根据本发明连接到下面的衬底的电子封装的实施例截面图；
图3A和3B是与图1-2所述实施例中的内插件一起使用的“扇出(fan-out)”连接端子图案的简图；
图4和5是根据本发明分别连接到下面衬底的图1和2所示电子封装另一
实施例的截面图；
图6是根据图1所示本发明的电子封装实施例的表示附加细节的截面图；
图7是图6所示实施例中与内插件一起使用的扇出连接端子图案的简图；
图8A，8B和8C是介绍制作图1-7中有关种类的内插件的截面图；
图9A和9B分别是根据本发明并采用多层介电材料的内插件的平面及截面图；
图10和10B分别是根据本发明的用于堆叠电子封装的多个内插件的布局平面和截面图；
图11和12分别是根据本发明的采用多个内插件的叠置式电子封装的另一种布局截面图；
图13-18，13A13B，15A和16A是根据本发明制作挠性粘合剂内插件的各个阶段的截面图；
图19和20分别是采用根据本发明的挠性粘合剂内插件的卡的分解图和截面图。
                        具体实施方式
电子封装受热感应力和湿密封的影响。每个器件封装包括一个半导体芯片或管芯(die)，通过管芯胶粘贴到中间叠层衬底如FR4叠层。细金或铝键合线(bond wire)把半导体芯片的连接端子连接到衬底上对应的导体，而该衬底通过可以是一种焊料或导电粘合剂的连接被连接到下面衬底上的导体。半导体芯片和键合线典型地是通过模铸密封剂封装或用一个提供机械支撑及湿气阻挡的盖子盖住。
由于用于这种模块中的不同材料的热膨胀系数(CTE)和高弹性模量(ME)即刚性的差异产生机械应力。硅半导体管芯有约3ppm/℃的CTE，粘合剂具有约40ppm/℃的CTE，衬底具有约17ppm/℃的CTE，密封剂具有约30ppm/℃的CTE。硅半导体管芯有约700,000-1,400,000kg/cm2(约10,000,000-20,000,000psi)的ME，粘合剂具有约70,000kg/cm2(约1,000,000psi)的ME，衬底和密封剂具有约140,000kg/cm2(约2,000,000psi)的ME。原则上，主要在粘合剂中以及芯片和衬底之间粘合剂界面中产生应力，并且在密封剂中达到较小的程度。应力的大小依赖于CTE之差、粘合剂和密封剂的固化温度以及粘合剂和密封剂的弹性模量等大小。
对电子封装的湿法密封有两个思想流派。一个流派是允许湿气容易且迅速地从器件封装中脱出，这通常也意味着自由进入器件封装，而另一个流派是制造尽可能严密的气封。如果密封剂允许湿气较慢地进入器件封装，则湿气也会较慢地脱出。如果在粘合剂与半导体芯片或衬底之间的界面处、或密封剂和半导体芯片之间的界面处有任何层离，湿气会进入其中，并且甚至在器件封装的外部大气回到一种干燥或低湿度状态和/或温度状态之后也趋于在其中保留一段时间。
另外，半导体芯片可在没有连接键合线的连接端子的区域中有一个施加到其上表面的湿气阻挡涂层，该涂层还可防止腐蚀或氧化。
另一方面，通过采用一种固有地或分子地挠性“内插件”或中间衬底，可以避免现有器件封装中产生的应力，并且可以经济地制造可靠的电子封装，包括芯片尺度的器件封装。固有挠性或分子挠性材料是一种由于其分子结构而挠性的材料，而不仅是因为已经形成一个非常薄的薄片。钢、铝和玻璃如果做得非常薄，则可以弯曲，但没有一个是固有挠性的。此处使用的挠性意指材料的弹性模量约小于35,000kg/cm2(500,000psi)并且能承受长度的30％伸长而不断裂。因而常规的衬底材料如弹性模量约为140,000kg/cm2(2,000,000psi)的FR4叠层、弹性模量约为140,000kg/cm2(2,000,000psi)的聚酰亚胺和双马来酰亚胺-三嗪不是在此所指的挠性材料。
图1是根据本发明的电子封装100连接到下面的衬底140的实施例侧截面图。器件封装100包括一个挠性内插件110，电子器件如半导体芯片120附着其上。芯片120下表面上的连接端子通过连接124直接连接到内插件110的连接端子112，连接124最好是一种导电挠性粘合剂连接。在希望除通过连接124所提供的对芯片120的支撑以外的支撑时，采用挠性介电填充粘合剂126填充芯片120和内插件110之间不被挠性连接124填充的空间。内插件110上的连接端子114对应于内插件反面上的连接端子112，提供用于器件封装100和下面电路衬底140上的导体之间的连接134的连接端子，最好是金属。连接134可以是常规的焊料连接或导电粘合剂，如同在所有的焊球阵列的器件封装中一样，并且在器件封装100和下面的衬底140之间不需要一种填充材料。
最好挠性粘合剂内插件110包括一个位于金属箔层上的挠性介电粘合剂层，金属箔例如是铜、镍、铝或其它导电金属及它们的合金，随后在该层上蚀刻确定连接端子114的图案。挠性介电层中的穿孔用导体材料填充，如挠性导体粘合剂或金属，从而提供对连接端子112的电连接。内插件110的挠性粘合剂具有一种约小于35,000kg/cm2(约500,000psi)的弹性模量，并且最好约小于14,000kg/cm2(约200,000psi)，最好约为7,000kg/cm2(约100,000psi)，约为1,400kg/cm2(约20,000psi)更好。合适的挠性介电粘合剂例如包括如ESP7450型可丝网印刷的挠性热固介电粘合剂和UVS7450型可光刻挠性热固介电粘合剂，二者具有约1,400kg/cm2(约20,000psi)的弹性模量和约100ppm/℃的CTE，可从位于Princeton，New jersey的AI技术公司得到。可以用于填充内插件110介电层中的穿孔或形成连接124的合适的挠性导电粘合剂包括ESP8450和ESP8550挠性导电热固粘合剂，也可以从AI技术公司得到。下面将详细描述挠性内插件110及其制造方法。
通过粘合剂把盖或罩130附着到内插件110以封闭芯片120并提供对其的机械保护。在需要另外的机械支撑时可以用挠性粘合垫132把盖130的内表面和芯片120的上表面连接到一起。根据需要，盖130可以是塑料、玻璃、陶瓷或金属。在希望除去芯片120中的热量时，盖130可以用导热材料制造，如铜、黄铜、钢或铝，并且挠性粘合剂132可以包括导热颗粒以提供芯片120和盖130之间的热连接，热量可以从中耗散。在希望光被允许通过盖130并入射到芯片120上时，盖130或至少其顶部可以是透过所需波长的光的。另外，可以在挠性粘合剂内插件110上选择性地设置一个金属边118以使内插件110的与盖130连接的周围区域变硬。
另外，因为挠性粘合剂内插件110是分子挠性的，所以连接124最好是金属焊料连接，如已知的并广泛用在电子器件的倒装安装中的那样。在希望除由焊料连接124提供对芯片120的支撑以外的支撑时，用挠性介电粘合剂或刚性介电填充物126填充没有被连接124填满的芯片120和内插件110之间的空间。内插件连接端子114提供在器件封装100和下面电路衬底140之间的用于BGA焊料的连接端子或导体粘合剂连接134；在器件封装100和下面衬底140之间不要求填充。
注意到，在芯片120被附着到挠性粘合剂内插件110之前，形成各个连接124的封装100的挠性粘合剂凸块(bump)和器件封装的焊料凸块可以沉积在或施加到芯片120上，既可以在半导体管芯水平，也可以在半导体晶片水平，或者可以施用到内插件110的连接端子112。
图2是根据本发明连接到下面的衬底110的电子封装100″的实施例截面图。器件封装100″如同器件封装100，包括挠性内插件110和与其附贴的电子器件或芯片120，而且还带有通过键合线125连接到内插件110连接端子112′的芯片120上的连接端子。键合线124最好是细金或铝线，如公知的广泛用在电子器件中的那样。连接端子112可以由标准的引线框架金属形成，如铜、镍或可伐合金，也可以在芯片120之下形成附着管芯的焊接凸点。芯片120通过挠性或刚性的管芯附着粘合剂126′连接到挠性粘合剂内插件110。内插件连接端子114提供器件封装100′和下面电路衬底140上的导体之间用于BGA焊料的连接端子或导体粘合剂连接134，没有未填充的情形。连接到内插件110的盖130提供对芯片120的机械保护。可以选择性地采用挠性粘合垫132以对芯片120提供附加的机械支撑和覆盖，还可以选择性地提供金属边118以加强，正如以上所述。
注意到，因为图1-2所示器件封装100、100″的挠性粘合剂内插件110如以上限定的那样为分子挠性，所以连接124和连接134二者或其中一个可以是金属焊料连接，如公知的并广泛用在电子器件倒装安装中的所谓的“C4”焊料连接，没有危及所提供的电子连接的整体性和可靠性的热感应力，尽管焊料有非常刚性的性质，如大约700,000kg/cm2(大约10,000,000psi)的弹性模量和大约20-25ppm/℃的CTE。
虽然图1-2所示器件封装100、100″的挠性内插件110允许湿气进入到由盖130、芯片120和挠性内插件110限定的腔体136内，湿气也较容易地从腔136内脱出，但是，如果湿气存在于腔136内并且温度下降，则湿气可能会凝结在腔体136内内插件110、芯片120和盖130的表面上。这种凝结的湿气的存在会导致某些材料的腐蚀或氧化，如形成各种导体和连接端子的金属。这种凝结大部分发生在芯片120不工作时，即不被供电时。当芯片120被供电时，很可能由此产生的热量将提高芯片120的温度并且避免在芯片120上凝结。因而，最坏的情况是凝结也只是断续地发生并且在不供电的状态下发生。
例如当在图1所示的倒装配置中把半导体芯片120连接到挠性粘合剂内插件110时，未填满的介电粘合剂126保护芯片120和挠性粘合剂内插件110的连接端子免于凝结湿气。另外，当预见到湿气进入腔体136中时，最好未填满的介电粘合剂126是疏水的，以便进一步减小在芯片120和挠性粘合剂内插件110的连接端子上形成水汽凝结的可能性。类似地，当安装半导体芯片120以用于图2所示的键合线连接时，暴露芯片120的连接端子并且可以用一个适当的保护涂层128覆盖芯片120，最好是挠性疏水涂层，以便减小腐蚀的可能性。用于这种未填满(underfill)和涂层的疏水粘合剂包括CP7135、CP7130和ESP7450型挠性疏水介电粘合剂，可以从AI技术公司获得，其中载体介质典型地是一种无极性的疏水聚合物。
还注意到，当盖130包括一种围绕边缘的粘结到挠性粘合剂内插件110的预施加粘合剂时，可以在一个流水线过程中组装器件封装100、100″，如通过标准的拾取-放置(pickup-place)元件安装设备。虽然这种盖130可以以几种方式设置，包括把粘合剂喷洒到每个盖或罩上，或对每个盖或罩施用粘合剂预制，但粘合剂预制盖和罩，如在美国专利申请(1999年1月19日提交的申请号为US09/232,936)名为“Method Of Making An Adhesive Preform Lid，As For An Electronic Device”中所述，以及层叠的粘合剂盖和罩，如美国专利申请(1999年6月21日提交的申请号为09/337,453)名为“Method Of MakingAn Laminated Adhesive Lid，As For An Electronic Device”也非常适于器件封装100和100″。利用这种低成本的盖和罩以及流水线处理，根据本发明的器件封装的成本可以与顶滴及模铸灌封器件封装的成本相比。
图3和3B是与图1-2所述实施例中的挠性粘合剂内插件110(部分示出)一起使用的示例性“扇出”连接端子图案的简图。半导体芯片120通过常规的方法制备，允许在其中形成非常精细的特征，如大约1μm或更大的尺度，包括非常小尺寸的导体和非常密地间隔的连接端子。但是这些特征太细小而无法与典型的低成本常规的下面的衬底140，如FR4印刷电路板兼容，FR4印刷电路板典型的特征为至少为50μm(约2mils)或更大。因为对应于半导体芯片120连接端子图案的挠性粘合剂内插件110的连接端子112的图案不需要与对应于下面衬底140上连接端子图案的挠性粘合剂内插件110的连接端子114的图案相同，可以用连接端子112、114以及导体113的扇出形布局来分开连接端子112和114，以分别完成半导体芯片120上的连接端子与下面衬底140上的连接端子之间的连接。
在图3中，例如半导体芯片120的连接端子连接的端子112a-112f可以是直径为50μm(约2mils)，间距(中心与中心的间隔)为100μm(约4mils)，处于内插件110挠性粘合剂层111的第一表面上，示出的层111被部分地除去。下面衬底140的连接端子连接到的连接端子114a-114f可以是直径为100μm(约4mils)，间距(中心与中心的间隔)为300μm(约12mils)，处于内插件110挠性粘合剂层111的第二和相对表面上。导体113连接端子112和114中对应的一个，如连接端子112a和114a，112b和114b等，并且可以非常细，如大约25-50μm宽，并且有变化的长度以将连接端子114进一步隔开。导体113处于一个连续的长度内，移动连接端子114a与连接端子112a相距大约0.5mm(约20mils)，连接端子114b与连接端子112b相距大约1mm(约40mils)，连接端子114c与连接端子112c相距大约1.5mm(约60mils)。经挠性粘合剂层111的导体通道115可以比连接端子114小很多，如50μm(约2mils)直径。
虽然导体113在图3A中示于挠性粘合剂层111的远表面上并且经导体通道115连接到连接端子114，但导体113可以处于挠性粘合剂层111的近表面上并经导体通道115连接到连接端子112。挠性粘合剂层111耐溶剂和其它用在形成导体113、连接端子114和导体通道115的化学材料的腐蚀。另外，注意到内插件110上的连接端子114的位置可以处于半导体芯片120的周围以外，也可以处于芯片120的周围以内，或可以处于芯片120的周围以内和以外，即可以位于挠性粘合剂内插件114上的任何位置。
在图3中，例如另一种扇出形布局不仅相对于连接端子112扩展如图3A所示的连接端子114的大小和间隔，而且还提供连接端子112和114成为镜象图案，这对把以图2所示的方式安置的半导体芯片应用到图1所示器件封装中尤其有用，在图1中，芯片以倒装的方式安置，从下面衬底140的方向看，其连接端子的图案颠倒。此颠倒通过导体113的图案消除，其中导体把半导体芯片120(示为虚线)左边上的连接端子112与内插件110右部上的对应连接端子114连接，并且还把半导体芯片120右边上的连接端子112与内插件110左部上的对应连接端子114连接。在图3B所示的实例中，连接端子114很大且为矩形，在连接端子114与外部导体开始电接触时有用，并且如同在接触型卡或标签中一样，可以用于入/出存取，识别个人或设备或其它的物体、信用卡、借记卡和电话卡等。
前述器件封装100、100′的其它优点还在于它们采用易于得到，价格合理的材料，并且可以利用标准的“拾取-放置”设备制造，以便把半导体芯片120和盖130附着到一个固有的快速组装线配置上，并且固有地具备低成本的优点，如不超过常规的低成本模铸电子封装的成本两倍。
图4和5是根据本发明分别连接到下面衬底140的图1和2所示电子封装100、100″另一实施例的截面图，其中腔136中基本上用密封剂137填充。在这种情况下，盖或罩130可以用作包封的形板或模具，并且可以再被保留或除去；或者，可以除去盖130并使用包封模具。应注意到，用于在电子器件周围模制封装物的设备和其它基础结构是已知的并且可以得到，因此可以以较低的成本用在本发明中。可以对具有一系列在其上成一条直线(一维排列)的电子器件的“带”和连续卷、或在其宽度上具有固定数量的电子器件(二维排列)的“板”或宽的连续卷进行模制，类似于常规的引线框架器件封装的模制。同样在这种一维或二维器件阵列上执行焊料球134的设置和加工。带、连续卷、板或其它的分布可以在其中采用对准孔以适当地定位器件封装100和100″的各个特征。另外，已知模制的器件封装对湿气进入的抵抗力，并且可以通过这一事实改进，即湿气可以经内插件110的挠性粘合剂脱出，这将降低由于表面安装技术(SMT)器件封装的焊接期间的加热所致的截留湿气的膨胀效果，有时后称作“爆米花”效果。半导体芯片120以倒装方式安装时，最好用导电疏水挠性材料作为芯片120和内插件110之间的连接，从而进一步抵制湿气，并且疏水粘合剂填充物126同样最好是疏水粘合剂。
适于做封装物137的材料包括标准刚性封装物，如已知的环氧树脂和用于模制和顶滴包封的液体环氧树脂化合物，具有大约30ppm/℃或更小的CTE，较高的弹性模量，如大约140,000kg/cm2(约2,000,000)。
图6是类似于根据图1所示器件封装100的电子封装实施例的另外的详解截面图。电子器件(芯片或管芯)120通过挠性导电粘合剂连接124以及可选择的挠性介电填充粘合剂126以倒装的方式安置到挠性粘合剂内插件110上，挠性粘合剂内插件110包括挠性粘合剂层111和一种在其上提供导体113的金属层。挠性粘合剂层111具有穿孔，该穿孔是导体通孔112，可以用与金属导体113相同的金属电镀，如铜或铜合金，也可以是与连接124相同类型的挠性导电粘合剂。对金属层形成图案，如通过光刻或印刷，提供导体通道124和金属连接端子114之间的导体113，在导体上形成焊料球或焊料凸块连接端子134。
在一种形式中，图6的器件封装100，芯片120大约25-500μm(约1-20mils)厚，并且更典型地约为250-500μm(约10-20mils)厚，并且挠性粘合剂层111的厚度约为75-250μm(约3-10mils)，带有大约50-250μm(约2-10mils)厚的铜导体114和连接端子114。适于用作内插件110的挠性介电粘合剂包括ESP7450和CC7450型挠性热固粘合剂和UVS7450型挠性热固粘合剂，适于与常规的UV光阻材料和光刻化学试剂和溶剂一起使用，每种粘合剂都是一种可从位于Princeton，New Jersey的AI技术公司得到的聚合物粘合剂或者其它合适的挠性粘合剂，每种都具有适当的特性，如低介电常数、低介电损耗、良好的温度稳定性、对湿气的低敏感性等。镀铜的导体通孔112大约50-100μm(约2-4mils)的直径，与导体连接124一样。适于连接124的导电粘合剂包括PSS8150 SOLDER-SUB型粘合剂或ESS8450 SOLDER-SUB型粘合剂，每种都是可以从AI技术公司得到的热固导电聚合物粘合剂，或是其他合适的挠性导电粘合剂，其可以理想地降低在诸如焊接焊料连接134以及在芯片120的环境或功率耗散操作中由于器件封装的温度所产生的热感应力。合适的填充粘合剂126包括也可以从AI技术公司获得的MEE7650-5挠性介电聚合物粘合剂。焊料凸块134的直径约为125-250μm(约5-10mils)，回流后高度有所降低。盖130典型的厚度约为0.5-0.75mm(约20-30mils)，可以用与填充粘合剂126采用的粘合剂相同的粘合剂附着到挠性粘合剂内插件110。可选择的粘合剂界面132可以是一种介电粘合剂，如需要额外的机械支撑的ESP7450型或ESP7670型，也可以是诸如PSS8150 SOLDER-SUB型粘合剂或PSS8450 SOLDER-SUB型导电粘合剂，也需要芯片120和罩130之间的电连接，或者还可以是导热粘合剂，如可从AI技术公司获得的ESP7455型和ESP7675型导热介电热固粘合剂。盖130可以是塑料或金属，并且最好是金属，希望它最好是既导热又导电，除非是既导热又导电的塑料。
注意到，挠性粘合剂内插件110很适合通过半导体芯片120的连接端子之间的间隔分开芯片120的连接端子和下面衬底140的连接端子，如图6所示，因而导体通道124之间比连接端子114和焊料凸块134之间的间隔更接近，如同周边连接或焊球阵列(BGA)器件中的一样。图7是图6所示实施例以及在图1-2和4-5所示实施例中与挠性粘合剂内插件110一起使用的扇出形连接端子图案的简图，该连接端子可适应标准的、常规的或非标准的连接端子图案。例如，图7表示的芯片120(如虚线所示)具有位于其连接端子周围连接到导体通孔112如112a、112b等的连接端子，通过导体113连接到对应的连接端子114，如114a、114b等，这些连接端子分别位于两个同心矩形图案或连接端子的阵列R1和R2。导体通孔112大约有75μm(约3mils)的直径和150μm(约6mil)的间距，并经75μm(约3mil)宽的导体113连接到对应的连接端子114。如果是在图案R1上，连接端子114大约有125-250μm(约5-10mil)的直径和与导体113为1mm(约40mil)的间距，如果在图案R2上，则间距为2mm(或80mil)或更大。
除以上所述的电子封装100、100′和100″采用挠性粘合剂内插件110的优点之外，挠性粘合剂内插件110通过这样一种有利的方法制造，即避免多项与制造常规的印刷电路板有关的昂贵操作，如在衬底上钻孔并在衬底材料中形成电镀的导体孔，单独制造多个必须层叠在一起以形成多层印刷电路板的不同印刷电路板等等。而且，挠性粘合剂内插件110是真正挠性的，因为用于其中的粘合剂是分子挠性，即具有较低的弹性模量，并且不是仅因为较薄如在常规的所谓挠性衬底材料的情况下那样。结果，可以采用允许非常细的连接端子以及间隔非常小即细间距的导体的方法形成挠性粘合剂内插件110。
典型的挠性粘合剂内插件可以如下制作。提供一个薄金属片或金属箔，由该金属片或金属箔形成内插件110一侧上的连接端子。金属箔可以是铜或铜合金(如铍铜)，镍或镍合金，铝或铝合金，或其它合适的导电金属，并且最好是12.5-125μm(约0.5-5mils)厚的铜合金，20-50μm(约1-2mils)的厚度最为典型。可以制备金属箔表面以提高粘合剂在那儿的黏附性，如通过磨擦，或通过诸如化学蚀刻或等离子体蚀刻以及其它的合适方法。金属箔上应该可以形成图案，如通过蚀刻，并且应该可以软焊或被涂敷一种可软焊的材料，如以下所述的一种涂层。挠性粘合剂层111沉着在金属箔上，如通过丝网印刷、模版印刷、贴上剥离，或通过层叠干的或B阶段(B-stage)的粘合剂片，或是其它合适的方法，典型的厚度大约是50-250μm(约2-10mils)。粘合剂层111具有通过丝网印刷、模版印刷或其它印刷过程、或通过激光钻孔、机械钻孔、机械冲孔、管芯切割、光刻、等离子体蚀刻或其它合适的方法形成的穿孔，穿孔的位置对应于半导体芯片120连接到内插件110的连接端子的位置。最好用机械冲孔、管芯切割和丝网印刷形成直径约为100μm(约4mils)或更大的穿孔，并且最好用印刷、光刻、等离子体蚀刻或激光钻孔等方法形成直径约小于100μm(约4mils)的穿孔。这种通过机械装置的穿孔形成最好在干的或B阶段的挠性粘合剂片被层叠到金属箔上之前进行，并且最好在其中形成位置关系对准孔以提供挠性粘合剂片与后续处理操作中采用的模板、丝网、掩膜和其它层对齐，其中后续处理操作例如是蚀刻或其它掩模操作。在通过挠性粘合剂层111的等离子体蚀刻形成穿孔的地方，可以暂时地把金属蚀刻掩膜附着到其上，但通过一个油脂薄层或合适的低温粘合剂保持与挠性粘合剂层111分开，挠性粘合剂层111例如是MB7060型低融化流动温度的粘合剂，在大约60℃时释解，该粘合剂可以从AI技术公司得到。通过油脂或低温粘合剂提供的分离有利地减少或避免由于等离子体蚀刻或加热临时挠性粘合剂以除去金属蚀刻掩膜所导致的挠性粘合剂层111被加热，挠性粘合剂层111被加热会不理想地将其固化或局部固化。
用于挠性粘合剂内插件的层111的优选挠性粘合剂包括可以从AI技术公司得到的ESP7450和UVS7450型，它们具有下列表中列出的特征和特性：
  特征或参数 限度值 ESP7450粘合剂 UVS7450粘合剂
  介电常数 ＜6.0 ＜4.0 ＜4.0
  介电损耗 ＜0.1@＞60Hz. ＜0.05 ＜0.05
  介电强度 ＞19,700V/mm(＞500V/mil) ＞29,600V/mm(＞750V/mil) ＞29,600V/mm(＞750V/mil)
  弹性模量 ＜70,000kg/cm2(＜500,000psi) 1,400kg/cm2(20,000psi) 1,400kg/cm2(20,000psi)
断裂前的伸长 ＞30％ 100％@25℃ 100％@25℃
玻璃化转变温度 ＜0℃ ＜-20℃ ＜-20℃
对铜的黏附性 ＞1.07dyne/cm(＞6.01b/in) ＞1.43dyne/cm(＞8.0lb/in) ＞1.43dyne/cm(＞8.0lb/in)
湿气吸收度 ＜0.5％ ＜0.5％ ＜0.5％
化学耐腐蚀性(铜蚀刻溶液) 合格 合格，浸泡8小时 合格，浸泡8小时
溶剂耐腐蚀性(流动清洁操作) 合格 合格，浸泡8小时 合格，浸泡8小时
热稳定性和衰变TGA ＜10％的重量损耗℃@＞300℃ ＜10％的重量损耗℃@＞400℃ ＜10％的重量损耗℃@＞400℃
热膨胀系数 100ppm/℃ 100ppm/℃
虽然优选大约19,700V/mm(约500V/mil)的介电强度，但对于可操作性而言，只有11,800V/mm(约300V/mil)是必需的。
粘合剂层111是B阶段的和/或充分固化的(即局部或全部)，从而保持附着到金属箔并保持不受下列的影响：(1)之后使用的以把导体113和连接端子114的图案蚀刻成金属箔，并且用于施加，显影和除去用于确定被蚀刻在金属箔中的图案的光阻材料的化学蚀刻试剂或溶剂，无论是酸性还是碱性，和(2)电镀或沉积金属到挠性导体粘合剂以填充带有导体通道124的挠性粘合剂层111的穿孔。通过把金属电镀到穿孔内以形成基本上填充穿孔的导体通孔112的建立过程把导体材料填充到穿孔中，最好通过把与金属箔(例如铜或铜合金)相同金属的电镀到穿孔内以形成导体通孔112，或通过导电组合物如导体粘合剂，如填充有银或其它合适的导体颗粒的挠性导体粘合剂，例如可从AI技术公司获得的PSS8150型粘合剂沉积到穿孔中。
最好这种导电挠性粘合剂具有处于与层111的挠性介电粘合剂相同范围的弹性模量。例如，任何一种粘合剂的弹性模量最好不超过另外一种粘合剂的弹性模量的三到五倍。擦去介电粘合剂层111表面上通道导体112以外泄漏或溢出的任何导体粘合剂。挠性导体粘合剂如都可以从AI技术公司获得的PSS8150热固粘合剂、ME8155型、ME8650-XT型、ESP8450和ESP8550型热固粘合剂，不会影响用于介电层111的ESP7450和UVS7450型热固介电粘合剂。最好在用导电粘合剂填充穿孔之前通过电镀合适的抗氧化金属如镍-金、金、钯等来涂敷穿孔底面处的金属层113的暴露金属。应注意到，既可以在形成导体通孔112之前也可以在形成导体通孔112之后对金属箔层113形成图案。
通过常规的光刻过程对金属箔层113形成图案以产生端子114，端子114或是覆盖导体通孔112，或是与导体通孔112移开并通过导体113与那儿连接；或两种情况都有。因为一般地希望蚀刻特征的宽度与金属箔的厚度之比至少为2∶1，所以薄金属箔113使得能够得到更细的连接端子和导体。例如，可以用25μm(1mil)厚的铜箔得到大约50μm(2mil)宽的特征和间距。可以通过如电镀给金属箔113和导体通孔112施加一个涂层，如银、金、镍、钯、镍-金、镍-钯或其它精细金属的层，也可以是它们的合金层，从而减少氧化、金属迁移和/或内部金属的衰变。对于导体通孔112和连接端子114优选镍-金、镍-钯电镀涂层，约5μm厚的镍被约0.1μm厚的金或钯覆盖，尤其当连接124和134分别是挠性导电粘合剂时。
对连接端子114和导体113上形成图案之后，可以用一层挠性介电粘合剂覆盖导体113以防无意中的电连接，如焊料桥连。挠性介电粘合剂可以与用于挠性粘合剂层111的粘合剂相同，也可以是另一种类型，如可以被形成图案并被部分地除去的挠性光聚合物。在通过丝网印刷、模版印刷或其它允许图案沉着的方法沉积这种挠性介电粘合剂的地方，连接端子114的图案不能被方便地覆盖。虽然在很多情况下电子器件120和下面衬底140上连接端子的图案是预先确定的并且因此导体通孔112、连接端子114、导体113的图案必需与其适应，但当有能力确定电子器件120上和下面衬底140上连接端子的各个图案时，连接端子114和导体113的布局可以简化。
图8A、8B和8C是图1-7中所述类型的内插件110的制作过程侧截面图。图8A表示一种金属片或金属箔113，该金属箔或片113至少配置有两个相关对准孔119，相关对准孔用于在制作挠性粘合剂内插件110期间与金属箔113对齐不同的模板、丝网以及各个其他层。在通过模版印刷、丝网印刷或其它方式把挠性粘合剂层111施加到金属箔113上时，掩模，模板和丝网每个包括一组例如通过从中穿过的对准销与金属箔113的相关对准孔119类似的相关对准孔。用在挠性粘合剂沉积中以形成挠性粘合剂层111-1、111-2的掩膜、模板和/或丝网限定其中的穿孔117。当希望挠性粘合剂层111-1有额外的厚度时，在烘干或B阶段挠性粘合剂层111-1之后进行第二沉积以形成具有与层111-1相同图案和穿孔的挠性粘合剂层111-2。
在挠性粘合剂层111-1为一个层叠到金属箔113的烘干的B阶段的或部分固化的挠性介电粘合剂薄片或薄膜时，这种薄片或薄膜可以具有已经形成在其中的穿孔117，如通过钻孔、冲孔、管芯切割、激光切割等方法形成，或者可以通过激光切割或激光钻孔在层叠之后形成穿孔117。薄片111-1有利地包括一组对应于金属箔113的相关对准孔的对准孔，通过例如对准销对准。
最好通过把金属镀到金属箔113暴露在那儿的背侧上而在穿孔117中形成导体通孔112，从而基本上填充穿孔117，如图8B和8C所述。电镀导体通孔112最好是与金属箔113相同的金属，最好是铜或铜合金。通过例如常规的光刻法对金属箔113形成图案以限定导体和连接端子113。最好把抗氧化层112a-112脚114a-114f沉积到导体通孔112和导体以及连接端子113上，既可以在金属箔113形成图案之前，也可以在形成图案之后，但最好是形成图案之后。可以沉积银、金、锡、镍、镍-金、镍-钯和其它抗氧化金属，最好通过电镀的方法，从而提供对导电粘合剂的合适的焊接力和/或粘合力。依据形成在金属箔113中的图案，形成在挠性粘合剂内插件110的导电连接可以是“直通”连接，如图8B所述，也可以提供“扇出”或再分配形的连接端子图案，如图8C所述，其当电子器件120的连接端子的尺寸或间距太细而不能与常规的电子衬底140直通连接时较为方便。
或者，挠性粘合剂内插件110的介电层111′可以由一片高温介电材料形成，例如一种常规的介电衬底材料，如FR4，聚酰亚胺、聚酯、表面改型的四氟乙烯、聚苯撑硫等，由于这些材料建立的物理特性以及它们公知的尺寸稳定性和精确度，其中导体通孔112的最小尺寸足够大，例如至少为100μm(约4mils)，所以会导致很容易被接受。应注意到，其优点是甚至当采用薄的高温常规的介电层111′时，挠性粘合剂层111的本征挠性或分子挠性仍如所述保持有效。在这种情况下，高温介电材料片会有一组与金属箔113匹配的相关导孔，用于恰当的对准和穿孔的预切割。衬底111′上可以有常规的金属导体，用于提供“扇出”形连接等。
图9A是本发明挠性粘合剂内插件210的另一实施例平面图，其中该内插件采用多层挠性介电粘合剂211。其上表面(图9A中可见的表面)上的连接端子212的6×6阵列用包围1、2或3数字的实圆环线表示，数字1、2或3表示根据“直通”导体通道直接通向下方的挠性介电粘合剂层211的层数。连接端子212的6×6阵列例如连接到36个连接端子的电子器件上紧密相隔的细间距连接端子的对应阵列，电子器件例如是半导体芯片或其它的电子元件。挠性粘合剂内插件210的底面或反面上的连接端子214的扇出形阵列用虚圆环线表示，每个连接端子通过一个虚线213表示的电导体连接到对应的一个连接端子212。连接端子阵列214例如连接到下面的电子衬底(未示出)。通过这样的标记，较下方的字母后缀a-f表示6×6连接端子阵列的行，数字后缀表示该项以上的挠性粘合剂的层数。例如导体213-1处于第一和第二粘合剂层211-1和211-2之间。典型的212和214代表导体通道212上的抗氧化金属涂层，如镍-金或镍-钯。
图9B是图9A所述挠性粘合剂内插件的截面图，特别表示介电材料的多层211-1、211-2、211-3的使用。通过分别直接穿过第一、第二和第三挠性粘合剂层212-1、212-2、211-3的导体通道212-123提供连接端子212a和212b之间的示例性导体连接。通过分别直接穿过第一和第二挠性粘合剂层212-1、212-2的导体通道212-12、位于第二和第三挠性粘合剂层211-2和211-3之间界面处的导体213-2和直通第三挠性粘合剂层211-3的导体通道212-3提供连接端子212b和212-4b之间的示例性导体连接。通过直通第一挠性粘合剂层212-1的导体通道212-1、位于第一和第二挠性粘合剂层211-1和211-2之间界面处的导体213-1以及直通第二和第三挠性粘合剂层211-2和211-3的导体通道212-23提供连接端子212f和214f之间的示例性导体连接。
在图9A和9B所示的实施例中，导体通道212可以镀上金属或导电粘合剂，如上所述。导体213可以是适于被电镀的导电挠性粘合剂，如可从AI技术公司获得的ESP8450型挠性导电热固粘合剂，或者可以是一种被电镀的金属导体，如铜、镍、银、金、镍-金、镍-钯等。就挠性粘合剂内插件而言，挠性介电粘合剂层211-1、211-2、211-3与上述的挠性粘合剂类似。
在典型的制造程序中，在金属层上沉积或在金属层上层叠带有穿孔的挠性粘合剂层211-1。在穿过挠性粘合剂层211-1的穿孔中给通道导体212-1电镀上与金属层相同的金属，如铜。导体213-1被沉积到挠性粘合剂层211-1上，并且如果是挠性粘合剂，则被烘干或B阶段并被电镀。把带有穿孔的挠性介电粘合剂层211-2印刷到金属层上或层叠在其上。给通道导体212-2上电镀与穿过挠性粘合剂层211-2的穿孔中金属层相同的金属。把导体213沉积到挠性粘合剂层211-2上，并且如果是挠性粘合剂，则将其烘干或B形式分段，并再电镀。在其上印制带有穿孔的挠性粘合剂层211-3，或者可以层叠其上。给通道导体212-3上电镀与挠性粘合剂层211-3中的穿孔中金属层相同的金属。在前述过程中可以在任何方便的时候在金属层上形成图案。连接端子212a-212f和214上电镀如上所述的抗氧化金属。为了延伸通道导体212穿过一层或多层，可以在同一时间对一层或多层电镀，这样可能方便一些。应注意到，类似于内插件210的多层挠性粘合剂内插件可以包括较多或较少数量的粘合剂层211-1、211-2，以及挠性粘合剂层，并且可以包括其它配置和/或连接端子212a、212b…214a、214b的图案，在某些特定的应用中导体通道212和导体212可能也是需要或方便的。
图10A为根据本发明的多层叠置内插件310、330的示例性设置的平面图，图10B为截面图，这对于电子封装的叠置有用。在图10A中，挠性粘合剂内插件310的中心部分可以从挠性内插件330的中央开孔或腔体333看见。挠性粘合剂内插件310为矩形，并在其上具有直通导体通道312、315阵列，在每个导体通道的每一端有一个连接端子，例如通过抗氧化金属的沉积而提供。挠性粘合剂内插件310、330包括挠性介电粘合剂的各个层311、331、金属箔层和导体通道312、315、335以及抗氧化连接端子涂层，它们以相似的方式形成，并采用与以上就挠性粘合剂内插件110、210等所描述的材料相似的材料。如上所述，挠性粘合剂内插件330是一种轴环形(collar)分布，互连并分开两个平面的挠性内插件310作为一叠内插件的一部分，包含不同的或类似地位于或包进各个轴环型挠性粘合剂轴环内插件330的中心腔中的电子器件。
挠性粘合剂内插件310的连接端子/导体通道312、315包括位于中心的48个连接端子/通道312的6×8阵列，这些连接端子/通道用于连接到如半导体芯片或其它电子元件的电子器件的连接端子阵列，并且位于周围的72个连接端子/通道315的阵列用于连接到位于一叠类似内插件中内插件310之上或之下的邻近的挠性粘合剂内插件。一般地，连接端子/导体通道312的大小和间距(中心到中心的间隔)小于连接端子/通道315的大小和间距，如图10B中的示例性实施例所示，但不是必需的。典型的连接端子/通道315可以分布并间隔成与其它标准的连接端子的轮廓一致，如可以由标准组织或制造商规定。连接端子/导体通道312中的一个经导体313电连接到一个具体的连接端子/通道315，其中导体313通过如上结合图1-8所述对金属层图案而形成。因而，挠性粘合剂内插件310基本上与前述的挠性粘合剂内插件110相同，并且如果在细节上如尺寸和连接端子的数量及布局上有不同，但在形式和功能上类似。
挠性粘合剂内插件330有一个位于周围的包围中心腔333的72个直通连接端子/通道335的阵列，其中可以安置诸如半导体芯片或其它电子元件的电子器件。连接端子/通道335与挠性粘合剂内插件310的72个直通连接端子/通道315一对一地对应。一个直通连接端子/通道315通过连接332电连接到叠置的内插件310、330的一个对应的连接端子/通道335，其中连接332可以是焊料或导电粘合剂，这可以从如图10b的截面图中了解。一个或多个电子器件的连接端子典型地是通过焊料连接到连接端子/通道312并且定位于挠性粘合剂轴环330的腔333内。应注意到只需要48个连接端子/通道315、335连接到与电子器件相连的48个连接端子/通道312，其余的24个连接端子可以用于另外的信号路径或电子信号的直通路径，如果需要、希望或方便，还可以用于其它的功能。
在根据图10A和10B的典型配置中，挠性内插件310约为50-150μm(约2-6mils)厚，并且挠性内插件330与将要安置在腔333中的电子器件一样厚或稍厚，典型地约为50-750μm(约2-30mils)。电子器件320通过焊料连接324连接或连接332、334为焊料连接时，选择内插件310、320的挠性介电粘合剂材料要耐受熔化焊料所需的温度，如大约300℃下持续5分钟，即长于熔化和回流焊料连接所需的时间，基本上不改变其很重要的特性，如小于50％的变化。
图11是根据本发明的采用多个挠性粘合剂内插件310、330的用于多个电子器件320的叠置封装330的示例性设置的截面图。在封装300的第一层中，如结合图10A和10B所述的平面挠性粘合剂内插件310-1和轴环形挠性粘合剂内插件330-1具有安置于腔333-1中的电子器件330-1。平面内插件310-1最好通过焊料连接332在安装电子元件320-1之前地连接到轴环内插件330-1，但也可以通过合适的导体粘合剂连接。电子器件320-1的连接端子通过连接324、最好是焊料、但也可以是导体粘合剂连接到挠性粘合剂内插件310-1的连接端子312。
在器件封装320的第二层中，如同第一层中一样，如结合图10A和10B所述的平面挠性粘合剂内插件310-2和轴环形挠性粘合剂内插件330-2具有安置于腔333-2中的电子器件330-2。平面内插件310-2最好通过焊料连接332在安装电子元件320-2之前连接到轴环内插件330-2，但也可以通过合适的导体粘合剂连接。电子器件320-2的连接端子通过连接324、最好是焊料、但也可以是导体粘合剂地连接到挠性粘合剂内插件310-2的连接端子312。器件封装300的第一和第二层通过平面挠性粘合剂内插件310-2和轴环形挠性粘合剂内插件330-1的相应连接端子之间的电连接332连接到一起。
按照类似地方式，平面挠性粘合剂内插件310-3、轴环形挠性粘合剂内插件330-3和电子器件320-3通过连接332连接到挠性内插件330-2，完成例中的三层叠置的器件封装300。如上所述，金属箔上形成图案的导体313和挠性粘合剂内插件310、330建立的导体通道315、335分别最好是铜或铜合金，并且最好用镍和金或镍和钯涂敷以抗氧化并提高焊接能力。应注意到，根据本发明可以在这种器件封装中采用或多或少的层，并且所有的层可以被组装并且之后成为一叠，或者也可以各自组装，只要对组装操作方便。在任何一种情况下，在叠置器件封装300相反端的暴露的内插件310和330在导体通道315、335的端部每个都有暴露的可焊接的连接端子316、336，这些连接端子适于连接电子器件320的器件封装的附加层或把器件封装300连接到下面的衬底340。
包含多个电子器件320和多个挠性粘合剂内插件310、330的器件封装300连接到下面的衬底340，如印刷电路板、陶瓷衬底或其它衬底，其中多个挠性粘合剂内插件310、330可以是平面内插件310或轴环形内插件330。通过可以是焊料或是导体粘合剂的连接334把电子封装300电连接以及机械连接到下面衬底340。
图12是图11所示多个电子器件的叠置器件封装300的另一种示例性布局300′的截面图。在叠置的器件封装300′中，叠置器件封装300被倒置并且挠性粘合剂内插件330-3的连接端子336通过连接332、最好是焊料、但也可以是导体粘合剂连接到平面挠性粘合剂内插件330-4上。平面内插件310-4的暴露面具有一种连接端子的图案，该图案可以与平面内插件310-1、310-2、310-3中的一种或多种的图案相同，或者可以不同，如上述金属箔形成的导体图案重分布。这些连接端子用于把器件封装330′经连接334连接到下面衬底340，连接334可以是焊料，也可以是导体粘合剂。器件封装300和300′可以任选地包封在包封材料(未示出)中，如可从AI技术公司获得的MEE7650-5型挠性介电粘合剂。或者，虽然优选上述挠性粘合剂材料，但可以由常规的印刷电路板材料形成圆轴环形内插件330-1、330-2、330-3，特别是当其布局简单时。
因为在断裂之前挠性粘合剂至少具有30％的伸长，并且例中类型的粘合剂在断裂之前具有100％或更多的伸长，所以本发明的挠性内插件很容易地绕电子器件折叠，无需物理折叠线特征(physical fold-line features)，并且对于内插件的给定厚度，具有比常规的材料如聚酰亚胺、聚酯等小的半径。可以自选地在保护和/或包封层中包封完成的叠置器件封装300、300′，最好象用于层311的挠性粘合剂一样。另外，还可以自选地从覆盖最顶层器件封装的挠性粘合剂内插件310的特定连接端子中省去焊料球332，因为那儿不需要连接，但是可能希望通过简单地制作所有类似的器件封装而简化库存和装配。另一方面，在叠置器件封装300、300′的一个或多个器件封装中，一个或多个挠性内插件310可能不同，同样包含其中的一个或多个电子器件320也可能不同。
上述的挠性粘合剂内插件可以按照图13-18所示的方法制造，并且其各种变更叙述如下，挠性粘合剂内插件500具有两层或多层由金属箔形成的导体。提供一片金属箔510，并且最好在其中的图案中有两个或多个相关导孔514，导孔用于将金属箔510与各个掩膜、丝网、模板夹层等用在挠性粘合剂内插件500和/或其制造过程中的片、层对齐。在图13中，沉积适当厚度的第一层挠性介电粘合剂520并将其层叠到金属箔510上，并在其中有一个开口522的图案，导体通道将随后形成在其中。已沉积的挠性粘合剂层B阶段并烘干到可以接触以备连接，但是如果要在其上沉积或层叠额外的层，则最好固化层520。可以用一种带图案的光阻层涂覆金属箔510，有图案的光阻层限定之后将要形成的导体图案，如通过光刻或其它过程，或者可以把这种光阻材料应用的后面的过程中。
图14表示沉积或层叠在至少已经B阶段或烘干并且最好固化的挠性粘合剂层520上的类似地第二层挠性粘合剂530。如果挠性粘合剂的厚度厚于可以单次沉积可以施加的厚度，则采用第二层挠性粘合剂530，即可以把两层或多层挠性粘合剂一层在另一层上放置以获得所需的挠性粘合剂厚度。第二层挠性粘合剂530上具有一种对应于层520的开口图案522的开口图案532。最后一层挠性粘合剂、即本例中的第二层挠性粘合剂530最好被B阶段或烘干。应注意到，可以沉积任何数量的挠性介电粘合剂层，每一层最好在沉积下一层之前被固化，除了最顶层只需要被B阶段或烘干，由此得到任何厚度的挠性粘合剂。
制备图15所示的第二片金属箔540，在其上具有对应于挠性粘合剂层520、530中穿孔图案522、532的开口图案542，并且最好具有同样与金属箔510的相关导孔514图案对应的相关导孔544图案。开口542和导孔544可以通过任何常规的方法形成，包括利用常规的光阻材料的光刻和化学蚀刻或其它蚀刻。最好开口542的直径比穿孔522、532的直径稍小，如5-50％，并且可以用有图案的光阻层预涂覆金属箔510，在其中限定之后将要通过光刻或其它过程形成的导体图案，或者可以在后面的过程中施加这种光阻层。图中的金属箔540接近于金属箔510和挠性粘合剂层520、530定位，并且在箭头548所示的方向沿中线546移动，直到与层530接触并连接，这些诸如通过把金属箔548和B阶段的粘合剂530层叠在加热的辊之间，加热的辊对它们进行加热直到粘合剂层530熔化并与其压在一起，直到熔融的粘合剂530流到金属箔540并与其连接，之后冷却或固化，产生如图16所示的结构。
用导体材料填充穿孔522、532、542以形成图17所示的导体通道550。把导体通道550电镀到金属箔510的侧面，在金属箔上粘合剂层520、530存在于穿孔522、532、542中，并且建立镀层以用导体材料550填充穿孔522、532、542。最好把铜镀到穿孔522、532、542中，直到建立的镀层达到金属箔540的水平并在金属箔510和金属箔540之间实现电连接。一旦通孔导体550的镀层实现金属箔510和540之间的电连接，则把额外的金属薄层镀到金属箔540上。在两个金属箔410、540建立适当连接的状态下停止电镀或者可以继续完成穿孔542的填充。在金属箔540被预涂覆有图案的光阻层时，只有金属箔540上开口542和保留为光刻导体处于的位置有电镀的金属生成。
通过象光学蚀刻这样的方法在金属箔510、540上形成图案，从而确定导体上的图案，这样形成的每个导体至少连接到一个导体通道550，由此产生按照本发明的挠性粘合剂内插件500，基本上如图17所示示例性实施例中的那样，并且适于用于采用在此描述的挠性粘合剂内插件的器件封装实施例中。
另外，最好至少对通道导体550的暴露端电镀一种抗氧化金属，最好是镍-金或镍-钯层560、570，如图18所示。把电镀的金属层570镀到通道导体550的暴露端，并且把电镀的金属层电镀到金属箔510的暴露面上挠性粘合剂内插件500中通道导体550位于的地点。另外，最好还用抗氧化金属电镀从蚀刻金属箔510和540而得到的导体图案(印刷电路轨迹，图中看不到)。或者也可以利用有图案的光阻操作把抗氧化金属层560、570以导体的光刻后将要保留的图案施加到金属箔510、540上，在金属箔510、540被光刻以确定导体图案之前实施金属化。
应注意到，如果还需要额外的导体层，则可以把额外的挠性介电粘合剂层沉积到金属箔540上，并且可以根据上述的方法把其中带有穿孔的额外金属箔层叠到此额外的粘合剂层，由此使得挠性粘合剂内插件500可以包括两、三、四或更多的通过导体通道以所需的方案互连的带有图案的金属箔层。重要的是还注意到连接邻近金属箔片的导体通道的分布图案对于每对相邻的金属箔层可以不同，并且光刻在每个金属箔的导体图案可以与蚀刻在任何其它金属箔层中的图案不同，由此允许有适用于多种不同应用中的多种不同的挠性粘合剂内插件。
最好用铜或铜合金作为金属箔510、540。可从AI技术公司获得的CC7450型挠性热固介电粘合剂适用于挠性粘合剂层520和530，它们典型地以大约150-300μm(约6-12mils)的湿厚度沉积，并且最典型的值是225μm(约9mils)，它们典型的烘干和/固化厚度约为150μm(约6mils)。穿孔522、532、542直径的典型值处于25μm-2.5mm(约21-100mils)的范，对于穿孔522、532的典型直径值约为300μm(约12mils)，对于稍小穿孔542的典型直径值约为250μm(约10mils)。金属箔540被实施加热或施压的加热辊以80℃-150℃的典型温度层叠到挠性粘合剂层530上。
图15A和16A是图13-18所示各种方法变形的截面图，并且具体如图15和16所示。在图15A中的方法与图15中方法的不同之处在于导体通道550′分别建立在挠性介电粘合剂层520、530中的穿孔522、532中，如以上参照图17所述，但是是在金属箔540层叠到挠性介电粘合剂层之前。如通过上述的电镀建立的导体通道550′只达到等于或稍低于粘合剂层530暴露表面的水平。之后，把金属箔540层叠到粘合剂层530，如参照图16所述，此时产生图16A所示的结构。在此点上，导体通道550′可以或不可以与金属箔540电连接，并且用导体材料填充尺寸稍小的开口542。建立的导体通道550′进一步以导体材料填充金属箔540中的开口542并实现金属箔540和金属箔510之间的导体连接，如上所述，又产生图17所示的结构，并且优选用AC电源的电镀去减小或消除两层金属箔之间的氧化的可能性。对金属箔510、540形成图案并蚀刻，形成电导体图案，并且最好如上所述把抗氧化层560、570施加其上。
注意到，在挠性粘合剂内插件500的几何形状导致会干扰把导体金属电镀到通道开口522、532和/或542中的阴影或遮挡效果时，如穿孔的最后深度大于或远大于其直径时，前述制造挠性粘合剂内插件500的方法的另一种变形可能很有利。在此例中，挠性粘合剂层520可以沉积到金属箔510上并且把导体金属电镀到穿孔522中，最好达到稍低于层520的暴露面的水平，如上所述。在层520上沉积第二层挠性粘合剂530并把导体金属电镀到穿孔532中，以便在之前建立的层520的穿孔522中进一步建立导体材料，最好达到稍低于层530的暴露面的水平。可以以此方式建立任何所需数量的挠性粘合剂层。最好在沉积下一层之前固化每个挠性粘合剂层，最上层的挠性粘合剂保持B阶段并被烘干以用于与金属箔540层叠。通过此种方式可以形成长度穿过两层或多层挠性粘合剂的导体通道550，其长度长于导体通道的直径，如100μm(约4mils)的直径和200μm(约8mils)或更大的长度。
另外，可以通过用于沉积这些层的丝网或模板以外的工具分别在挠性粘合剂层520、530中有利地形成穿孔522、532，如最小穿孔522、532的直径为50-75μm(约2-3mils)，非常小，间距为100-175μm(约4-6mils)。因而可以形成如图13A和13B所示的具有图13所示穿孔图案522的挠性粘合剂层520。如通过模版印刷把易于移除的材料的暂时粘合剂凸块512的图案沉积到金属箔510上，如图13A所示，可以是金属箔的一条带、网或面。暂时凸块512与穿孔522的图案相同，即处于保留穿孔的每个位置，并且每个暂时凸块512与限定的穿孔522的直径相同。视情况而定，凸块512被沉积、烘干或B阶段，并且当凸块被烘干或B阶段时是一种将粘合到金属箔510的材料。因而，用于具有给定直径的穿孔522的暂时凸块512以相同的直径沉积，并且湿厚度大约等于或小于金属箔510的直径。凸块512的高度随着烘干或B阶段而降低，并因此以大于挠性粘合剂层520所需厚度的厚度沉积。
因而，例如在125μm(约5mils)厚度的挠性粘合剂层520中用于给定直径为50-75μm(约2-3mils)的穿孔522的暂时凸块512以相同的直径50-75μm(约2-3mils)沉积并且湿厚度约等于直径即75μm(约3mils)。粘合剂凸块512的高度随着B阶段降低，典型地约为湿厚度的60％，以致于当B阶段时75μm(约3mils)高度的凸块降低到约50μm(约2mils)的高度。可以通过对易于消除的材料层的连续沉积和B阶段建立所需厚度的凸块512，直到获得提供所需高度所必需的层数。合适的易于消除的材料包括光阻材料、类似于毛发凝胶的水基聚合物以及可溶粘合剂，如MB7100型热塑粘合剂(可溶于溶剂油)、WB7120型粘合剂(可溶于聚乙烯醇)和CP7130型热塑粘合剂(可溶于溶剂油)，都可以从AI技术公司获得。选择用于凸块512的合适材料，虽然这些材料溶于特定的溶剂，但还是看重它们不溶于用在形成挠性介电粘合剂层520的溶剂中的特性。
把挠性介电粘合剂沉积或向下拉到金属箔510上，其湿厚度类似于暂时凸块512的高度，但其厚度可稍大或稍小。合适的挠性粘合剂包括可从AI技术公司获得的CC7450型热固粘合剂，它具有基本上高于暂时凸块512的MB7100和CP7130型粘合剂的表面能，并且将有一种拉离凸块512从而使暂时凸块512脱离介电层520并易于用于将其去除的自然趋势。或者，可以把厚度等于或小于凸块512高度的薄膜或B阶段粘合剂片层叠到金属箔510。例如，可以在70-90℃的温度下把B阶段的CC7450粘合剂薄膜或片层叠到金属箔510，不使凸块512变形或坍塌，因为MB7100和CP7130型粘合剂在大约100-110℃的稍高温度下熔化。这样产生图13B所示的结构。选择适合于挠性介电粘合剂层520的材料，该种材料虽然可溶于特定的溶剂，但具有不溶于凸块512材料所使用的溶剂的特性。
然后根据需要B阶段或固化挠性粘合剂层520以抵御用于去除暂时凸块512的溶剂并粘结到金属箔510上。如果需要介电层较厚，则可以通过连续沉积暂时凸块512和/或挠性粘合剂层520以达到所需的厚度，并且根据需要在下一次连续沉积之前烘干或B阶段所使用的材料。例如，如果凸块512为125μm高，则湿粘合剂层520的厚度125μm在被B阶段时最终将缩到75μm，并且此第二应用用于达到约125μm的所需厚度。可以用另外的应用来提供更大的厚度，并且希望最后一层或最顶层粘合剂不被固化，但是被B阶段以便于随后再向其上层叠金属箔。
用诸如溶剂油或其它与用在CC7450型挠性介电粘合剂层520、530中的极性溶剂不兼容的非极性溶剂、或当把水基材料用于凸块512时的水或热水、或当用光阻材料时的典型的去除溶液消除凸块512。挠性粘合剂内插件500的其余处理如结合图16-18所描述的那样。
前述方法适于单独制造挠性粘合剂内插件500或适于同时制造数个内插件500，与金属箔510、540和/或挠性粘合剂层520、530的张或带用在批处理过程或连续处理过程中一样。在批处理中，使用前述一种或多种材料的一个或多个张、如25×31cm(约10×12英寸)或31×50cm(约12×20英寸)，并且通过挠性粘合剂层520、520的丝网和/或模板沉积在其中和其上形成多个内插件500。在连续过程中，使用如12.5-25cm(约5-10英寸)宽的带或条并且沿各个层被滚形沉积其上或层叠其上的方向移动。带或条具有沿其一个或两个边缘的驱动链轮孔，用于沿控制的方式运动。当在张或带上形成多个挠性粘合剂内插件500之后，可以切开以产生各个内插件500。
或者还应注意到，最好在用抗氧化材料如贵金属金、钯、镍-金等涂敷穿孔底部的暴露金属之后，通过用挠性导体粘合剂填充穿孔来形成通道导体。
虽然以上述实施例对本发明进行了描述，但由下列权利要求限定的本发明范围和实质之内的各种改型对于本领域的技术人员也是显而易见的。例如，虽然包含在各种器件封装实施例内的电子器件在此描绘为半导体芯片或管芯，如集成电路等，但这些器件也可包括其它类型的电子元件，如电阻、电容、电感以及这些器件的网络和它们的组合，还用多个半导体芯片或管芯，可以是单独的，也可以是与其它元件的组合。在图19的分解图中和图20的侧截面图中，“智慧卡”600采用根据本发明的挠性粘合剂内插件610。内插件610包括一个挠性介电粘合剂芯612，在芯的一侧上有一个被图案化为穿过挠性粘合剂层612的导体通道616之间的导体614的金属箔，在另一侧上有一个被图案化为连接端子618图案的金属箔。如集成电路620和元件622、624、626、还可以是集成电路、电阻、电容、电感、二极管、晶体管等的一个或多个电子器件用它们各自电连接到通道导体616的连接端子通过如焊料或导体粘合剂电连接到内插件610，包括电子器件及其安装的总高度典型地小于0.5mm(约20mils)。第一覆盖片630、如聚氯乙烯(PVC)片覆盖到内插件610上并通过一层粘合剂634与内插件连接。覆盖片630中有一个开口，连接端子618位于其中可从外部接触卡600，如接触型智慧卡中所希望的那样，其中连接端子618与阅读装置的对应连接端子电连接。第二PVC覆盖片640覆盖挠性粘合剂内插件610的另一面以保护其上的电子元件620-626，电子元件被一种粘合剂或其它的把覆盖片640连接到挠性粘合剂内插件610的密封剂650包围。
在把多个层用在如图9A和9B所述的挠性介电粘合剂内插件中时，很明显，在不脱离本发明概念的或制造具体实施例的方法的前提下，在某些特例中可以方便地用或多或少的粘合剂层实现复杂的或简单的扇出形图案。同样，这种扇出形图案可以用在挠性粘合剂内插件的任何一个实施例中，包括那些如图17、18和20所示的具有多个金属导体箔层的情形。在图20的放大图中展示了另一种智慧卡600，其中挠性粘合剂内插件660用于提供和/或电子器件620和连接端子618′之间的扇出形额外的导体连接。内插件660包括挠性粘合剂层662和提供连接端子664的有图案的金属箔，它们通过焊料或导体粘合剂668连接到挠性粘合剂内插件610的对应连接端子619。
根据本发明的挠性粘合剂内插件可以在其连接端子上具有焊料或导体粘合剂凸块，以便于半导体芯片和其它电子器件与其的连接，并且和/或用具有预施加的环氧填充粘合剂，如AI科技的ESP7675型，和/或预施加的粘合剂膜，如AI科技的ESP7450型，用于粘结其它的器件，如整形框架或覆盖片等。
另外，本发明的电子器件封装可以与其它常规的安装技术合用，如焊球阵列(BGA)技术和管脚阵列(PGA)技术。在这种情况下，把根据本发明的器件封装安装到常规的BGA或PGA可焊接衬底，该衬底反过来又以常规的BGA或PGA方式连接到下面的衬底。

Claims (53)

1.一种具有用于连接到衬底的连接端子的电子封装，包括：
至少一个电子器件，所述的电子器件上具有多个连接端子；
一个挠性介电粘合剂内插件，包括：
至少一层弹性模量小于35,000kg/cm2(大约500,000psi)的挠性介电粘合剂，
多个经挠性介电粘合剂层的导体通道，所述多个导体通道处于的分布图案与电子器件和衬底之一的连接端子的分布图案相对应，其中多个导体通道中的至少某一些对应于电子器件的一些连接端子，和
处于挠性介电粘合剂层一个表面上的金属箔，其中金属箔上被形成图案并与导体通道中的一些电连接，
其中多个导体通道和形成有图案的金属箔其中的一个包括用于连接到衬底的连接端子；和
用于把所述电子器件的连接端子连接到所述导体通道特定的某些上的设施。
2.如权利要求1所述的电子封装，其特征在于所述多个导体通道处于一种对应于电子器件连接端子的分布图案的分布图案之中，其中所述有图案的金属箔从所述电子器件的连接端子图案扇出到衬底的连接端子图案。
3.如权利要求2所述的电子封装，其特征在于用于连接的设施包括用于把电子器件的一些邻近对应的连接端子连接到某一特定导体通道的焊料或导电粘合剂之一的连接。
4.如权利要求1所述的电子封装，其特征在于多个导体通道处于一种对应于衬底的连接端子的分布图案的分布图案之中，其中有图案的金属箔从衬底的连接端子图案扇出到与所述电子器件的连接端子图案相关的图案。
5.如权利要求4所述的电子封装，其特征在于电子封装以其连接端子从远端连接到所述挠性介电粘合剂内插件，并且所述用于连接的设施包括在电子器件的连接端子和所述导体通道之间连接的导线。
6.如权利要求1所述的电子封装，还包括一个保护式的外壳，该外壳包围所述电子器件，并且至少沿其周边连接到挠性介电粘合剂内插件。
7.如权利要求6所述的电子封装，其特征在于保护式的外壳是一种将其边缘连接到挠性介电粘合剂内插件周边的覆盖物以及包围电子器件并至少沿其周边连接到挠性介电粘合剂内插件的密封剂中的一种。
8.如权利要求6所述的电子封装，其特征在于保护式的外壳包括一种将其边缘连接到挠性介电粘合剂内插件周边并通过挠性粘合剂连接到挠性介电粘合剂内插件远处的电子器件表面的覆盖物。
9.如权利要求1所述的电子封装，其特征在于挠性介电粘合剂具有小于7,000kg/cm2(大约100,000psi)的弹性模量。
10.如权利要求1所述的电子封装，其特征在于挠性介电粘合剂具有小于1,400kg/cm2(大约20,000psi)的弹性模量。
11.如权利要求1所述的电子封装，还包括一种连接电子器件和挠性介电粘合剂内插件的填充粘合剂。
12.如权利要求11所述的电子封装，其特征在于填充粘合剂包括具有约小于35,000kg/cm2(大约500,000psi)的弹性模量的挠性介电粘合剂。
13.如权利要求1所述的电子封装，其特征在于导体通道由电镀到至少一层挠性介电粘合剂中的孔中的金属建立。
14.一种用于多个电子器件的电子封装，包括：
多个电子器件，每个电子器件上具有一种多个连接端子的分布图案；
多个挠性介电粘合剂内插件，每个至少与多个电子器件中的一个相连，内插件包括：
至少一层弹性模量约小于35,000kg/cm2(大约500,000psi)的挠性介电粘合剂，
多个经挠性介电粘合剂层的导体通道，多个导体通道处于一种分布图案中，其中多个导体通道中的至少某一些对应于所述多个电子器件的相关一个的一些连接端子，和
处于挠性介电粘合剂层一个表面上的金属箔，其中金属箔上被形成图案并与导体通道中的一些电连接，
其中多个导体通道和形成有图案的金属箔其中的至少一个包括用于把挠性介电粘合剂内插件连接到外部器件的外接端子；和
用于把多个电子器件的每一个的连接端子连接到与其相连的挠性介电粘合剂内插件的某些特定的导体通道的设施，
其中多个挠性介电粘合剂内插件彼此相邻，并且还包括：
用于把多个挠性介电粘合剂内插件的每个的外接端子连接到多个挠性介电粘合剂内插件中相邻的一个的外接端子的设施。
15.如权利要求14所述的电子封装，其特征在于每个挠性介电粘合剂内插件包容与其相连的多个电子器件中的一个。
16.如权利要求15所述的电子封装，其特征在于多个挠性介电粘合剂内插件中的至少一个还至少包括多条导体通道中的特定的一些条，该些条通道对应于多个电子器件中的一个的连接端子，其中电子器件与多个挠性介电粘合剂内插件中相邻的一个相连。
17.如权利要求16所述的电子封装，其特征在于与多个挠性介电粘合剂内插件中至少一个相连的电子器件的连接端子的图案和与多个挠性介电粘合剂内插件中与其相邻的一个相连的电子器件的连接端子的图案相似，并且其中多个挠性介电粘合剂内插件中的至少一个的所述多个导体通道中的某些和其另外某些以彼此相似以及相对于与其相连的各电子器件相似的图案排列。
18.如权利要求14所述的电子封装，其特征在于多个挠性介电粘合剂内插件中的至少一个包括多条导体通道中的至少一些条，该些通道对应于多个电子器件中与多个挠性介电内插件中相邻的一个相连的一个的连接端子。
19.如权利要求14所述的电子封装，其特征在于用于连接外接端子的设施至少包括一个进一步的挠性介电粘合剂内插件，该内插件插在多个挠性介电粘合剂内插件的两个相邻内插件之间，所述的挠性介电粘合剂内插件至少有一层弹性模量小于35,000kg/cm2(大约500,000psi)的挠性介电粘合剂，和多条经挠性介电粘合剂层的导体通道，多个导体通道处于一种分布图案中，该分布图案对应于多个挠性介电粘合剂内插件的相邻两个内插件的导体通道。
20.如权利要求19所述的电子封装，其特征在于所述的进一步的挠性介电粘合剂内插件中有一个至少与多个电子器件中和两个相邻挠性介电粘合剂内插件中的一个相连的一个电子器件一样大的腔，并且其中所述的进一步的挠性介电粘合剂内插件和两个相邻挠性介电粘合剂内插件中的一个与腔内连接的多个电子器件中的一个并列。
21.如权利要求14所述的电子封装，其特征在于所述用于与外接端子连接的设施至少包括一个进一步的挠性介电粘合剂内插件，该内插件插在多个挠性介电粘合剂内插件的两个相邻内插件之间，其中有多条导体通道穿过，其图案对应于多个挠性介电粘合剂内插件的相邻两个的导体通道之一些的图案，其中所述的进一步的挠性介电粘合剂内插件中有一个至少与多个电子器件中和两个相邻挠性介电粘合剂内插件中的一个相连的一个电子器件一样大的腔，并且其中所述的进一步的挠性介电粘合剂内插件和两个相邻挠性介电粘合剂内插件中的一个与腔内连接的多个电子器件中的一个并列。
22.如权利要求14所述的电子封装，其特征在于多个挠性介电粘合剂内插件中至少一个的带有图案的金属箔从与其相连的电子器件的连接端子的图案扇出到衬底的连接端子的图案。
23.如权利要求14所述的电子封装，其特征在于用于连接的设施包括用于把电子器件的一些对应的连接端子连接到某些特定导体通道的焊料或导电粘合剂的连接。
24.如权利要求14所述的电子封装，还包括一种包封材料，用于包封多个电子器件和挠性介电粘合剂内插件，并且至少粘结到挠性介电粘合剂内插件上。
25.如权利要求14所述的电子封装，其特征在于挠性介电粘合剂具有小于7,000kg/cm2(大约100,000psi)的弹性模量。
26.如权利要求14所述的电子封装，其特征在于挠性介电粘合剂具有小于1,400kg/cm2(大约20,000psi)的弹性模量。
27.如权利要求14所述的电子封装，其特征在于导体通道由电镀到至少一层挠性介电粘合剂中的孔中的金属建立。
28.一种挠性介电粘合剂内插件，包括：
多层挠性介电粘合剂，该挠性介电粘合剂具有约小于35,000kg/cm2(大约500,000psi)的弹性模量；
多条穿过每个挠性介电粘合剂层的导体通道，在每层挠性介电粘合剂中的多条导体通道处于一种对应于至少相邻挠性介电粘合剂层的多条导体通道图案的一部分的分布图案中；和
一个处于至少两层挠性介电粘合剂层之间的金属箔，其中金属箔上被形成图案并与至少两层挠性介电粘合剂的每一个中的一些条导体通道电连接。
29.如权利要求28所述的电子封装，其特征在于导体通道由电镀金属建立。
30.如权利要求28所述的电子封装，其特征在于挠性介电粘合剂具有小于7,000kg/cm2(大约100,000psi)的弹性模量。
31.如权利要求28所述的电子封装，其特征在于挠性介电粘合剂具有小于1,400kg/cm2(大约20,000psi)的弹性模量。
32.如权利要求28所述的电子封装，其特征在于至少与一个电子器件组合，该电子器件上具有多个连接到第一多层挠性介电粘合剂的某一些特定导体通道的连接端子。
33.一种用于多个电子器件的电子封装，包括：
多个电子模块，每个电子模块的第一和第二相对表面上具有多个外接端子的预定图案，其特征在于每个电子模块包括：
一个在其上具有连接端子图案的电子器件；
一个第一挠性介电粘合剂内插件，包括：
至少一层挠性介电粘合剂，该挠性介电粘合剂具有约小于35,000kg/cm2(大约500,000psi)的弹性模量；
多条穿过所述挠性介电粘合剂层的导体通道，多条导体通道处于一种分布图案中，其中至少多条导体通道的第一部分对应于电子器件的连接端子，并且至少多条导体通道的第二部分对应于多个外接端子的一种预定的分布图案，
用于把电子器件的对应的一些连接端子电连接到多条导体通道的对应的第一部分的设施；
处于至少一层挠性介电粘合剂的一个表面上的金属箔，其中金属箔上形成图案，提供相应的第一部分和第二部分导体通道之间的电导体；
一个其中具有中心开口的第二介电内插件，其中第一挠性介电粘合剂内插件和第二介电内插件彼此相邻，电子器件设置在第二介电内插件的中心开口中，第二介电内插件包括多条处于一定分布图案中的导体通道，其中多条导体通道中的至少第一部分对应于多个外接端子的预定分布图案，和
用于把第一挠性介电粘合剂内插件的第二部分导体通道电连接到第二介电内插件的对应的第一部分导体通道的设施，其中第一挠性介电粘合剂内插件的第二部分导体通道的未连接端和第二介电内插件的第一部分导体通道的未连接端提供外接端子，和
用于把多个电子模块中每个的各个第一表面上的外接端子电连接到一个相邻电子模块的第二表面上外接端子的设施，其中多个电子模块彼此相邻定位且电连接。
34.如权利要求33所述的电子封装，其特征在于多个挠性介电粘合剂内插件中至少一个的带有图案的金属箔从与其相连的电子器件的连接端子的图案扇出到衬底的连接端子的图案。
35.如权利要求33所述的电子封装，其特征在于用于连接电子器件的对应连接端子的设施包括用于把电子器件的一些对应的连接端子连接到第一部分导体通道的焊料或导电粘合剂的连接。
36.如权利要求33所述的电子封装，其特征在于用于电连接第二部分导体通道的设施包括把第一挠性介电粘合剂内插件的第二部分导体通道连接到相邻的第二介电内插件的对应的第一部分导体通道的焊料和导电粘合剂之一的连接。
37.如权利要求33所述的电子封装，其特征在于用于连接外接端子的设施包括焊料和导电粘合剂其中的一种连接。
38.如权利要求33所述的电子封装，其特征在于挠性介电粘合剂具有小于7,000kg/cm2(大约100,000psi)的弹性模量。
39.如权利要求33所述的电子封装，其特征在于挠性介电粘合剂具有小于1,400kg/cm2(大约20,000psi)的弹性模量。
40.如权利要求33所述的电子封装，其特征在于导体通道由电镀到至少一层挠性介电粘合剂中的孔中的金属建立。
41.如权利要求33所述的电子封装，其特征在于第二介电内插件至少包括一层挠性介电粘合剂，该粘合剂具有约小于35,000kg/cm2(大约500,000psi)的弹性模量，其中多条导体通道穿过挠性介电粘合剂。
42.如权利要求41所述的电子封装，其特征在于挠性介电粘合剂具有小于7,000kg/cm2(大约100,000psi)的弹性模量。
43.如权利要求41所述的电子封装，其特征在于挠性介电粘合剂具有小于1,400kg/cm2(大约20,000psi)的弹性模量。
44.如权利要求41所述的电子封装，其特征在于导体通道由电镀到至少一层挠性介电粘合剂中的孔中的金属建立。
45.如权利要求33所述的电子封装，还包括一种包封材料，用于包封电子器件、第一挠性介电粘合剂内插件和第二介电内插件。
46.一种制作用于电子器件的电子封装的方法，包括：
提供一个金属箔片；
在金属箔片的一个表面上设置至少一层弹性模量约小于35,000kg/cm2(大约500,000psi)的挠性介电粘合剂，挠性介电粘合剂层中具有多个通孔；
在金属箔上建立导体材料以填充通孔，由此在其中形成导体通道；
对金属箔形成图案以形成连接端子和电连接到挠性介电粘合剂层中导体通道的导体的图案；
电镀至少一个导体通道和形成有图案的金属箔的连接端子，以提供外接端子；和
电连接至少一个电子器件的连接端子与对应的导体通道。
47.如权利要求46所述的方法，其特征在于提供至少一层挠性介电粘合剂包括在金属箔片上沉积一层挠性介电粘合剂。
48.如权利要求46所述的方法，其特征在于提供至少一层挠性介电粘合剂包括把挠性介电粘合剂片层叠到金属箔片上。
49.如权利要求46所述的方法，还包括在把挠性介电粘合剂片层叠到金属箔片之前和之后在挠性介电粘合剂片中形成穿孔。
50.如权利要求46所述的方法，其特征在于建立导体材料包括把金属电镀到穿孔中的金属箔上。
51.如权利要求46所述的方法，还包括在对金属箔形成图案之后，在金属箔片的至少没有一层挠性介电粘合剂的表面上提供至少一个第二层挠性介电粘合剂，该粘合剂的弹性模量约小于35,000kg/cm2(大约500,000psi)，挠性介电粘合剂的至少第二层中具有多个穿孔；并且在金属箔上建立导体材料以填充挠性介电粘合剂的至少第二层中的穿孔，由此在其中形成导体通道。
52.如权利要求46所述的方法，还包括至少在一层挠性介电粘合剂上提供一个第二金属箔片，第二金属箔片中具有一种对应于至少一层挠性介电粘合剂的穿孔的开口图案。
53.如权利要求52所述的方法，还包括在至少一层挠性介电粘合剂中的导体通道上建立导体材料，从而填充金属箔中的穿孔，由此在两片金属箔之间形成导体通道。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100461994C (zh) * 2005-05-25 2009-02-11 财团法人工业技术研究院 热增益型薄型化电子构装
CN1868048B (zh) * 2003-09-09 2011-06-01 菲科公司 使用柔性压力元件来密封电子部件的方法和装置
CN102593046A (zh) * 2010-12-22 2012-07-18 通用电气公司 制造半导体器件封装件的方法
CN102751204A (zh) * 2012-07-16 2012-10-24 江阴长电先进封装有限公司 一种扇出型圆片级芯片封装方法
CN104392969A (zh) * 2014-10-13 2015-03-04 华东光电集成器件研究所 一种多芯片集成电路抗冲击封装结构
CN104685624A (zh) * 2012-07-31 2015-06-03 英帆萨斯公司 重组晶圆级微电子封装
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
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US9728527B2 (en) 2013-11-22 2017-08-08 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
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US9812402B2 (en) 2015-10-12 2017-11-07 Invensas Corporation Wire bond wires for interference shielding
US9837330B2 (en) 2014-01-17 2017-12-05 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US9842745B2 (en) 2012-02-17 2017-12-12 Invensas Corporation Heat spreading substrate with embedded interconnects
US9852969B2 (en) 2013-11-22 2017-12-26 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US9953914B2 (en) 2012-05-22 2018-04-24 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US10008477B2 (en) 2013-09-16 2018-06-26 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US10008469B2 (en) 2015-04-30 2018-06-26 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US10026717B2 (en) 2013-11-22 2018-07-17 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US10062661B2 (en) 2011-05-03 2018-08-28 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US10128216B2 (en) 2010-07-19 2018-11-13 Tessera, Inc. Stackable molded microelectronic packages
CN108885708A (zh) * 2016-03-24 2018-11-23 维普公司 制造智能卡的方法
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US10297582B2 (en) 2012-08-03 2019-05-21 Invensas Corporation BVA interposer
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
CN110194435A (zh) * 2018-02-26 2019-09-03 Tdk电子股份有限公司 电子设备
US10460958B2 (en) 2013-08-07 2019-10-29 Invensas Corporation Method of manufacturing embedded packaging with preformed vias
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires

Families Citing this family (247)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6205654B1 (en) * 1992-12-11 2001-03-27 Staktek Group L.P. Method of manufacturing a surface mount package
US6717819B1 (en) * 1999-06-01 2004-04-06 Amerasia International Technology, Inc. Solderable flexible adhesive interposer as for an electronic package, and method for making same
US7553904B2 (en) 1999-08-04 2009-06-30 Hybrid Plastics, Inc. High use temperature nanocomposite resins
FI112288B (fi) * 2000-01-17 2003-11-14 Rafsec Oy Menetelmä älytarrasyöttörainan valmistamiseksi
JP2001223323A (ja) * 2000-02-10 2001-08-17 Mitsubishi Electric Corp 半導体装置
US6580031B2 (en) * 2000-03-14 2003-06-17 Amerasia International Technology, Inc. Method for making a flexible circuit interposer having high-aspect ratio conductors
US6400015B1 (en) * 2000-03-31 2002-06-04 Intel Corporation Method of creating shielded structures to protect semiconductor devices
FI112287B (fi) * 2000-03-31 2003-11-14 Rafsec Oy Menetelmä tuoteanturin muodostamiseksi ja tuoteanturi
SE516254C2 (sv) * 2000-04-26 2001-12-10 Ericsson Telefon Ab L M Förfarande för att bilda ett ledande lager på en halvledaranordning
US6642613B1 (en) * 2000-05-09 2003-11-04 National Semiconductor Corporation Techniques for joining an opto-electronic module to a semiconductor package
FI111881B (fi) * 2000-06-06 2003-09-30 Rafsec Oy Älykorttiraina ja menetelmä sen valmistamiseksi
US6611053B2 (en) * 2000-06-08 2003-08-26 Micron Technology, Inc. Protective structure for bond wires
US6404043B1 (en) * 2000-06-21 2002-06-11 Dense-Pac Microsystems, Inc. Panel stacking of BGA devices to form three-dimensional modules
US6812048B1 (en) * 2000-07-31 2004-11-02 Eaglestone Partners I, Llc Method for manufacturing a wafer-interposer assembly
JP3405456B2 (ja) * 2000-09-11 2003-05-12 沖電気工業株式会社 半導体装置，半導体装置の製造方法，スタック型半導体装置及びスタック型半導体装置の製造方法
US6686657B1 (en) * 2000-11-07 2004-02-03 Eaglestone Partners I, Llc Interposer for improved handling of semiconductor wafers and method of use of same
JP4635329B2 (ja) * 2000-12-01 2011-02-23 凸版印刷株式会社 配線回路基板の製造方法
FI112121B (fi) * 2000-12-11 2003-10-31 Rafsec Oy Älytarraraina, menetelmä sen valmistamiseksi, menetelmä kantorainan valmistamiseksi ja älytarrarainan älytarran rakenneosa
US6529022B2 (en) * 2000-12-15 2003-03-04 Eaglestone Pareners I, Llc Wafer testing interposer for a conventional package
US20020076854A1 (en) * 2000-12-15 2002-06-20 Pierce John L. System, method and apparatus for constructing a semiconductor wafer-interposer using B-Stage laminates
US6524885B2 (en) * 2000-12-15 2003-02-25 Eaglestone Partners I, Llc Method, apparatus and system for building an interposer onto a semiconductor wafer using laser techniques
US20020111029A1 (en) * 2001-02-12 2002-08-15 Johnson Morgan T. Laser micromachining and electrical structures formed thereby
US6879492B2 (en) * 2001-03-28 2005-04-12 International Business Machines Corporation Hyperbga buildup laminate
US7115986B2 (en) * 2001-05-02 2006-10-03 Micron Technology, Inc. Flexible ball grid array chip scale packages
FI112550B (fi) * 2001-05-31 2003-12-15 Rafsec Oy Älytarra ja älytarraraina
JP2002357633A (ja) * 2001-05-31 2002-12-13 Hitachi Ltd 半導体装置の製造方法およびそれに用いられる半導体選別装置
FI117331B (fi) * 2001-07-04 2006-09-15 Rafsec Oy Menetelmä ruiskuvaletun tuotteen valmistamiseksi
US6627984B2 (en) * 2001-07-24 2003-09-30 Dense-Pac Microsystems, Inc. Chip stack with differing chip package types
SG122743A1 (en) * 2001-08-21 2006-06-29 Micron Technology Inc Microelectronic devices and methods of manufacture
US20030041966A1 (en) * 2001-08-31 2003-03-06 International Business Machines Corporation Method of joining laminates for z-axis interconnection
JP2003110091A (ja) * 2001-09-28 2003-04-11 Toshiba Corp 半導体装置及び半導体装置の製造方法
US7045890B2 (en) * 2001-09-28 2006-05-16 Intel Corporation Heat spreader and stiffener having a stiffener extension
US7173329B2 (en) * 2001-09-28 2007-02-06 Intel Corporation Package stiffener
KR20030029743A (ko) * 2001-10-10 2003-04-16 삼성전자주식회사 플랙서블한 이중 배선기판을 이용한 적층 패키지
US7485951B2 (en) * 2001-10-26 2009-02-03 Entorian Technologies, Lp Modularized die stacking system and method
US7656678B2 (en) 2001-10-26 2010-02-02 Entorian Technologies, Lp Stacked module systems
US7053478B2 (en) * 2001-10-26 2006-05-30 Staktek Group L.P. Pitch change and chip scale stacking system
US6914324B2 (en) * 2001-10-26 2005-07-05 Staktek Group L.P. Memory expansion and chip scale stacking system and method
US20060255446A1 (en) * 2001-10-26 2006-11-16 Staktek Group, L.P. Stacked modules and method
US7026708B2 (en) * 2001-10-26 2006-04-11 Staktek Group L.P. Low profile chip scale stacking system and method
US20030234443A1 (en) * 2001-10-26 2003-12-25 Staktek Group, L.P. Low profile stacking system and method
US6956284B2 (en) * 2001-10-26 2005-10-18 Staktek Group L.P. Integrated circuit stacking system and method
US20050009234A1 (en) * 2001-10-26 2005-01-13 Staktek Group, L.P. Stacked module systems and methods for CSP packages
US6576992B1 (en) * 2001-10-26 2003-06-10 Staktek Group L.P. Chip scale stacking system and method
US20050056921A1 (en) * 2003-09-15 2005-03-17 Staktek Group L.P. Stacked module systems and methods
US6940729B2 (en) * 2001-10-26 2005-09-06 Staktek Group L.P. Integrated circuit stacking system and method
US6873059B2 (en) * 2001-11-13 2005-03-29 Texas Instruments Incorporated Semiconductor package with metal foil attachment film
US7081373B2 (en) * 2001-12-14 2006-07-25 Staktek Group, L.P. CSP chip stack with flex circuit
US6599778B2 (en) * 2001-12-19 2003-07-29 International Business Machines Corporation Chip and wafer integration process using vertical connections
FI119401B (fi) * 2001-12-21 2008-10-31 Upm Raflatac Oy Älytarraraina ja menetelmä sen valmistamiseksi
SG104293A1 (en) * 2002-01-09 2004-06-21 Micron Technology Inc Elimination of rdl using tape base flip chip on flex for die stacking
EP1489657A4 (en) * 2002-02-06 2011-06-29 Ibiden Co Ltd SEMICONDUCTOR CHIP MOUNTING PLATE, METHOD FOR THE PRODUCTION THEREOF AND SEMICONDUCTOR MODULE
US7154171B1 (en) * 2002-02-22 2006-12-26 Amkor Technology, Inc. Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor
SG115456A1 (en) * 2002-03-04 2005-10-28 Micron Technology Inc Semiconductor die packages with recessed interconnecting structures and methods for assembling the same
SG115459A1 (en) * 2002-03-04 2005-10-28 Micron Technology Inc Flip chip packaging using recessed interposer terminals
SG115455A1 (en) * 2002-03-04 2005-10-28 Micron Technology Inc Methods for assembly and packaging of flip chip configured dice with interposer
SG121707A1 (en) * 2002-03-04 2006-05-26 Micron Technology Inc Method and apparatus for flip-chip packaging providing testing capability
US6975035B2 (en) * 2002-03-04 2005-12-13 Micron Technology, Inc. Method and apparatus for dielectric filling of flip chip on interposer assembly
SG111935A1 (en) 2002-03-04 2005-06-29 Micron Technology Inc Interposer configured to reduce the profiles of semiconductor device assemblies and packages including the same and methods
JP2003318337A (ja) * 2002-04-22 2003-11-07 Toshiba Corp 電子機器
KR100460062B1 (ko) 2002-04-23 2004-12-04 주식회사 하이닉스반도체 멀티 칩 패키지 및 그 제조 방법
SG111069A1 (en) * 2002-06-18 2005-05-30 Micron Technology Inc Semiconductor devices including peripherally located bond pads, assemblies, packages, and methods
SG107595A1 (en) 2002-06-18 2004-12-29 Micron Technology Inc Semiconductor devices and semiconductor device components with peripherally located, castellated contacts, assembles and packages including such semiconductor devices or packages and associated methods
US20050167817A1 (en) * 2002-08-05 2005-08-04 Tessera, Inc. Microelectronic adaptors, assemblies and methods
US20040036170A1 (en) * 2002-08-20 2004-02-26 Lee Teck Kheng Double bumping of flexible substrate for first and second level interconnects
DE10238581B4 (de) * 2002-08-22 2008-11-27 Qimonda Ag Halbleiterbauelement
TW563232B (en) * 2002-08-23 2003-11-21 Via Tech Inc Chip scale package and method of fabricating the same
US6885102B2 (en) * 2002-08-26 2005-04-26 Intel Corporation Electronic assembly having a more dense arrangement of contacts that allows for routing of traces to the contacts
JP4085788B2 (ja) * 2002-08-30 2008-05-14 日本電気株式会社 半導体装置及びその製造方法、回路基板、電子機器
JP4081666B2 (ja) * 2002-09-24 2008-04-30 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
JP4208840B2 (ja) * 2002-12-17 2009-01-14 富士通マイクロエレクトロニクス株式会社 半導体装置
US7224280B2 (en) * 2002-12-31 2007-05-29 Avery Dennison Corporation RFID device and method of forming
KR100623015B1 (ko) 2003-11-05 2006-09-18 주식회사 유니세미콘 스택 패키지 및 그 제조방법
US6869825B2 (en) * 2002-12-31 2005-03-22 Intel Corporation Folded BGA package design with shortened communication paths and more electrical routing flexibility
KR100621991B1 (ko) * 2003-01-03 2006-09-13 삼성전자주식회사 칩 스케일 적층 패키지
CA2455024A1 (en) * 2003-01-30 2004-07-30 Endicott Interconnect Technologies, Inc. Stacked chip electronic package having laminate carrier and method of making same
US20040156177A1 (en) * 2003-02-12 2004-08-12 Matsushita Electric Industrial Co., Ltd. Package of electronic components and method for producing the same
TW200507218A (en) * 2003-03-31 2005-02-16 North Corp Layout circuit substrate, manufacturing method of layout circuit substrate, and circuit module
US7239024B2 (en) * 2003-04-04 2007-07-03 Thomas Joel Massingill Semiconductor package with recess for die
JP4416432B2 (ja) * 2003-05-12 2010-02-17 シチズン電子株式会社 電源回路装置
JP2004363573A (ja) * 2003-05-15 2004-12-24 Kumamoto Technology & Industry Foundation 半導体チップ実装体およびその製造方法
US20090014897A1 (en) * 2003-05-15 2009-01-15 Kumamoto Technology & Industry Foundation Semiconductor chip package and method of manufacturing the same
US20040245615A1 (en) * 2003-06-03 2004-12-09 Staktek Group, L.P. Point to point memory expansion system and method
US6870257B2 (en) * 2003-06-04 2005-03-22 Intel Corporation Power delivery through a flex tape in decoupled I/O-power hybrid substrate
US6992376B2 (en) * 2003-07-17 2006-01-31 Intel Corporation Electronic package having a folded package substrate
WO2005022965A2 (en) * 2003-08-29 2005-03-10 Thermalworks, Inc. Expansion constrained die stack
US7542304B2 (en) * 2003-09-15 2009-06-02 Entorian Technologies, Lp Memory expansion and integrated circuit stacking system and method
KR20060079219A (ko) * 2003-09-16 2006-07-05 코닌클리즈케 필립스 일렉트로닉스 엔.브이. 전자 디바이스, 이의 제조 방법 및 반제품
SG120123A1 (en) * 2003-09-30 2006-03-28 Micron Technology Inc Castellated chip-scale packages and methods for fabricating the same
US20090085011A1 (en) * 2003-12-18 2009-04-02 Lichtenhan Joseph D Neutron shielding composition
US7126829B1 (en) * 2004-02-09 2006-10-24 Pericom Semiconductor Corp. Adapter board for stacking Ball-Grid-Array (BGA) chips
US20050196604A1 (en) * 2004-03-05 2005-09-08 Unifoil Corporation Metallization process and product produced thereby
US7436060B2 (en) * 2004-06-09 2008-10-14 Lsi Corporation Semiconductor package and process utilizing pre-formed mold cap and heatspreader assembly
US7208346B2 (en) * 2004-06-14 2007-04-24 David Lee Methods of forming interposers on surfaces of dies of a wafer
JP4285339B2 (ja) * 2004-06-15 2009-06-24 パナソニック株式会社 回路モジュールおよび回路モジュールの製造方法
US20050282355A1 (en) * 2004-06-18 2005-12-22 Edwards David N High density bonding of electrical devices
US7112877B2 (en) * 2004-06-28 2006-09-26 General Electric Company High density package with wrap around interconnect
JP4353861B2 (ja) 2004-06-30 2009-10-28 Ｎｅｃエレクトロニクス株式会社 半導体装置
US20060033187A1 (en) * 2004-08-12 2006-02-16 Staktek Group, L.P. Rugged CSP module system and method
JP2006073683A (ja) * 2004-08-31 2006-03-16 Sony Corp 回路デバイス及び回路デバイスの製造方法
US7443023B2 (en) 2004-09-03 2008-10-28 Entorian Technologies, Lp High capacity thin module system
US7423885B2 (en) * 2004-09-03 2008-09-09 Entorian Technologies, Lp Die module system
US7760513B2 (en) 2004-09-03 2010-07-20 Entorian Technologies Lp Modified core for circuit module system and method
US8072058B2 (en) * 2004-10-25 2011-12-06 Amkor Technology, Inc. Semiconductor package having a plurality input/output members
CN101053079A (zh) 2004-11-03 2007-10-10 德塞拉股份有限公司 堆叠式封装的改进
FI20041525A (fi) * 2004-11-26 2006-03-17 Imbera Electronics Oy Elektroniikkamoduuli ja menetelmä sen valmistamiseksi
US20060118933A1 (en) * 2004-12-07 2006-06-08 Tessera, Inc. Stackable frames for packaging microelectronic devices
US7656047B2 (en) * 2005-01-05 2010-02-02 Advanced Semiconductor Engineering, Inc. Semiconductor device package and manufacturing method
US7633170B2 (en) * 2005-01-05 2009-12-15 Advanced Semiconductor Engineering, Inc. Semiconductor device package and manufacturing method thereof
US7309914B2 (en) * 2005-01-20 2007-12-18 Staktek Group L.P. Inverted CSP stacking system and method
WO2006088270A1 (en) * 2005-02-15 2006-08-24 Unisemicon Co., Ltd. Stacked package and method of fabricating the same
US7743963B1 (en) * 2005-03-01 2010-06-29 Amerasia International Technology, Inc. Solderable lid or cover for an electronic circuit
US20060250780A1 (en) * 2005-05-06 2006-11-09 Staktek Group L.P. System component interposer
KR100721353B1 (ko) * 2005-07-08 2007-05-25 삼성전자주식회사 칩 삽입형 매개기판의 구조와 제조 방법, 이를 이용한 이종칩의 웨이퍼 레벨 적층 구조 및 패키지 구조
US20070080441A1 (en) * 2005-08-18 2007-04-12 Scott Kirkman Thermal expansion compensation graded IC package
TWI261350B (en) * 2005-09-02 2006-09-01 Wintek Corp Electronic member with conductive connection structure
US8476591B2 (en) * 2005-09-21 2013-07-02 Analog Devices, Inc. Radiation sensor device and method
US7897920B2 (en) * 2005-09-21 2011-03-01 Analog Devices, Inc. Radiation sensor device and method
US7462939B2 (en) * 2005-10-20 2008-12-09 Honeywell International Inc. Interposer for compliant interfacial coupling
FI20051228L (sv) * 2005-12-01 2007-07-27 Zipic Oy Komponentlåda med mikrokrets
US8067253B2 (en) * 2005-12-21 2011-11-29 Avery Dennison Corporation Electrical device and method of manufacturing electrical devices using film embossing techniques to embed integrated circuits into film
US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
US20070187818A1 (en) * 2006-02-15 2007-08-16 Texas Instruments Incorporated Package on package design a combination of laminate and tape substrate
WO2007102358A1 (ja) * 2006-03-07 2007-09-13 Nec Corporation 電子デバイスパッケージ、モジュール、および電子機器
JP2007250764A (ja) * 2006-03-15 2007-09-27 Elpida Memory Inc 半導体装置及びその製造方法
JP2006237628A (ja) * 2006-04-14 2006-09-07 Sharp Corp 積層型半導体パッケージ用多層基板およびその製造方法
US7554198B2 (en) * 2006-06-29 2009-06-30 Intel Corporation Flexible joint methodology to attach a die on an organic substrate
US20080002384A1 (en) * 2006-06-30 2008-01-03 Motorola, Inc. Apparatus for providing radio frequency shielding and heat dissipation for electronic components
DE102006032073B4 (de) * 2006-07-11 2016-07-07 Intel Deutschland Gmbh Elektrisch leitfähiger Verbund aus einem Bauelement und einer Trägerplatte
US7888185B2 (en) * 2006-08-17 2011-02-15 Micron Technology, Inc. Semiconductor device assemblies and systems including at least one conductive pathway extending around a side of at least one semiconductor device
SG176498A1 (en) * 2006-08-18 2011-12-29 Hybrid Plastics Inc Nanoscopic assurance coating for lead-free solders
US7425758B2 (en) 2006-08-28 2008-09-16 Micron Technology, Inc. Metal core foldover package structures
US7417310B2 (en) 2006-11-02 2008-08-26 Entorian Technologies, Lp Circuit module having force resistant construction
EP2097725B1 (en) * 2006-12-27 2019-08-28 Analog Devices, Inc. Control aperture for an ir sensor
KR100829614B1 (ko) * 2006-12-29 2008-05-14 삼성전자주식회사 반도체 스택 패키지 및 그의 제조 방법
JP2010519769A (ja) * 2007-02-21 2010-06-03 ラムバス・インコーポレーテッド 高速メモリパッケージ
US7926173B2 (en) * 2007-07-05 2011-04-19 Occam Portfolio Llc Method of making a circuit assembly
US7841080B2 (en) * 2007-05-30 2010-11-30 Intel Corporation Multi-chip packaging using an interposer with through-vias
US7982137B2 (en) * 2007-06-27 2011-07-19 Hamilton Sundstrand Corporation Circuit board with an attached die and intermediate interposer
DE102007038514A1 (de) * 2007-08-16 2009-02-19 Robert Bosch Gmbh Elektrische Schaltungsanordnung und Verfahren zur Herstellung einer elektrischen Schaltungsanordnung
KR20090033605A (ko) * 2007-10-01 2009-04-06 삼성전자주식회사 적층형 반도체 패키지, 그 형성방법 및 이를 구비하는전자장치
KR101143837B1 (ko) * 2007-10-15 2012-07-12 삼성테크윈 주식회사 전자 소자를 내장하는 회로기판 및 회로기판의 제조 방법
US7906860B2 (en) * 2007-10-26 2011-03-15 Infineon Technologies Ag Semiconductor device
US8212339B2 (en) 2008-02-05 2012-07-03 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US8350367B2 (en) * 2008-02-05 2013-01-08 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US7989928B2 (en) * 2008-02-05 2011-08-02 Advanced Semiconductor Engineering Inc. Semiconductor device packages with electromagnetic interference shielding
US8022511B2 (en) * 2008-02-05 2011-09-20 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
JP5012612B2 (ja) * 2008-03-26 2012-08-29 日本電気株式会社 半導体デバイスの実装構造体及び実装構造体を用いた電子機器
US7880244B2 (en) * 2008-04-15 2011-02-01 Analog Devices, Inc. Wafer level CSP sensor
WO2009142591A1 (en) * 2008-05-20 2009-11-26 Swecard International Sa Smart card manufacture
US7727808B2 (en) * 2008-06-13 2010-06-01 General Electric Company Ultra thin die electronic package
US7829981B2 (en) * 2008-07-21 2010-11-09 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US8410584B2 (en) * 2008-08-08 2013-04-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US9893004B2 (en) * 2011-07-27 2018-02-13 Broadpak Corporation Semiconductor interposer integration
US9818680B2 (en) 2011-07-27 2017-11-14 Broadpak Corporation Scalable semiconductor interposer integration
US10026720B2 (en) 2015-05-20 2018-07-17 Broadpak Corporation Semiconductor structure and a method of making thereof
US8014166B2 (en) 2008-09-06 2011-09-06 Broadpak Corporation Stacking integrated circuits containing serializer and deserializer blocks using through silicon via
US20100110656A1 (en) 2008-10-31 2010-05-06 Advanced Semiconductor Engineering, Inc. Chip package and manufacturing method thereof
US8472199B2 (en) 2008-11-13 2013-06-25 Mosaid Technologies Incorporated System including a plurality of encapsulated semiconductor chips
US20100207257A1 (en) * 2009-02-17 2010-08-19 Advanced Semiconductor Engineering, Inc. Semiconductor package and manufacturing method thereof
US8110902B2 (en) * 2009-02-19 2012-02-07 Advanced Semiconductor Engineering, Inc. Chip package and manufacturing method thereof
US8212340B2 (en) 2009-07-13 2012-07-03 Advanced Semiconductor Engineering, Inc. Chip package and manufacturing method thereof
US20110108999A1 (en) * 2009-11-06 2011-05-12 Nalla Ravi K Microelectronic package and method of manufacturing same
US8030750B2 (en) * 2009-11-19 2011-10-04 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US8378466B2 (en) * 2009-11-19 2013-02-19 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with electromagnetic interference shielding
US8368185B2 (en) 2009-11-19 2013-02-05 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
TWM397596U (en) * 2010-03-22 2011-02-01 Mao Bang Electronic Co Ltd Integrated circuit chip card
TWI411075B (zh) 2010-03-22 2013-10-01 Advanced Semiconductor Eng 半導體封裝件及其製造方法
KR101078743B1 (ko) * 2010-04-14 2011-11-02 주식회사 하이닉스반도체 스택 패키지
KR101067109B1 (ko) * 2010-04-26 2011-09-26 삼성전기주식회사 전자부품 내장형 인쇄회로기판 및 그 제조방법
JP2014502033A (ja) 2010-06-08 2014-01-23 アメレイジア、インターナショナル テクノロジー、インク． 太陽電池の相互接続、そのモジュール、パネル及び方法
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US8847376B2 (en) 2010-07-23 2014-09-30 Tessera, Inc. Microelectronic elements with post-assembly planarization
TWI540698B (zh) 2010-08-02 2016-07-01 日月光半導體製造股份有限公司 半導體封裝件與其製造方法
TWI426587B (zh) * 2010-08-12 2014-02-11 矽品精密工業股份有限公司 晶片尺寸封裝件及其製法
US9007273B2 (en) 2010-09-09 2015-04-14 Advances Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
KR101075241B1 (ko) 2010-11-15 2011-11-01 테세라, 인코포레이티드 유전체 부재에 단자를 구비하는 마이크로전자 패키지
US20120146206A1 (en) 2010-12-13 2012-06-14 Tessera Research Llc Pin attachment
US9406658B2 (en) 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof
US8363418B2 (en) 2011-04-18 2013-01-29 Morgan/Weiss Technologies Inc. Above motherboard interposer with peripheral circuits
US8618659B2 (en) 2011-05-03 2013-12-31 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US8513817B2 (en) 2011-07-12 2013-08-20 Invensas Corporation Memory module in a package
US8502390B2 (en) 2011-07-12 2013-08-06 Tessera, Inc. De-skewed multi-die packages
US8823165B2 (en) 2011-07-12 2014-09-02 Invensas Corporation Memory module in a package
EP2562692B1 (en) 2011-08-25 2013-10-09 Textilma Ag RFID chip module
US8659140B2 (en) 2011-10-03 2014-02-25 Invensas Corporation Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate
US8659141B2 (en) 2011-10-03 2014-02-25 Invensas Corporation Stub minimization using duplicate sets of terminals for wirebond assemblies without windows
JP2014528652A (ja) 2011-10-03 2014-10-27 インヴェンサス・コーポレイション パッケージの中心から端子グリッドをオフセットすることによるスタブ最小化
WO2013052372A2 (en) * 2011-10-03 2013-04-11 Invensas Corporation Stub minimization for multi-die wirebond assemblies with parallel windows
US8659142B2 (en) 2011-10-03 2014-02-25 Invensas Corporation Stub minimization for wirebond assemblies without windows
JP5947904B2 (ja) 2011-10-03 2016-07-06 インヴェンサス・コーポレイション 直交するウインドウを有するマルチダイ・ワイヤボンド・アセンブリのためのスタブ最小化
US8345441B1 (en) 2011-10-03 2013-01-01 Invensas Corporation Stub minimization for multi-die wirebond assemblies with parallel windows
US8441111B2 (en) 2011-10-03 2013-05-14 Invensas Corporation Stub minimization for multi-die wirebond assemblies with parallel windows
US8436457B2 (en) * 2011-10-03 2013-05-07 Invensas Corporation Stub minimization for multi-die wirebond assemblies with parallel windows
US8610260B2 (en) 2011-10-03 2013-12-17 Invensas Corporation Stub minimization for assemblies without wirebonds to package substrate
US8541883B2 (en) 2011-11-29 2013-09-24 Advanced Semiconductor Engineering, Inc. Semiconductor device having shielded conductive vias
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9594999B2 (en) 2012-04-03 2017-03-14 X-Card Holdings, Llc Information carrying card comprising crosslinked polymer composition, and method of making the same
US9122968B2 (en) * 2012-04-03 2015-09-01 X-Card Holdings, Llc Information carrying card comprising a cross-linked polymer composition, and method of making the same
US8937376B2 (en) 2012-04-16 2015-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor packages with heat dissipation structures and related methods
US8786060B2 (en) 2012-05-04 2014-07-22 Advanced Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
US8704341B2 (en) 2012-05-15 2014-04-22 Advanced Semiconductor Engineering, Inc. Semiconductor packages with thermal dissipation structures and EMI shielding
US8653634B2 (en) 2012-06-11 2014-02-18 Advanced Semiconductor Engineering, Inc. EMI-shielded semiconductor devices and methods of making
US20140005527A1 (en) * 2012-06-29 2014-01-02 General Electric Company Method and system for dynamic referencing and registration used with surgical and interventional procedures
JP5728437B2 (ja) * 2012-07-17 2015-06-03 長野計器株式会社 物理量測定装置及び物理量測定装置の製造方法
US9153542B2 (en) 2012-08-01 2015-10-06 Advanced Semiconductor Engineering, Inc. Semiconductor package having an antenna and manufacturing method thereof
US9368477B2 (en) 2012-08-27 2016-06-14 Invensas Corporation Co-support circuit panel and microelectronic packages
US8848391B2 (en) 2012-08-27 2014-09-30 Invensas Corporation Co-support component and microelectronic assembly
US8848392B2 (en) 2012-08-27 2014-09-30 Invensas Corporation Co-support module and microelectronic assembly
US8787034B2 (en) 2012-08-27 2014-07-22 Invensas Corporation Co-support system and microelectronic assembly
US8975738B2 (en) 2012-11-12 2015-03-10 Invensas Corporation Structure for microelectronic packaging with terminals on dielectric mass
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US11907791B2 (en) 2013-01-18 2024-02-20 Amatech Group Lijited Smart cards with metal layer(s) and methods of manufacture
US11392817B2 (en) * 2013-01-18 2022-07-19 Amatech Group Limited Smart cards with metal layer(s) and methods of manufacture
US9362187B2 (en) * 2013-01-18 2016-06-07 Infineon Technologies Ag Chip package having terminal pads of different form factors
US9136254B2 (en) 2013-02-01 2015-09-15 Invensas Corporation Microelectronic package having wire bond vias and stiffening layer
US9978688B2 (en) 2013-02-28 2018-05-22 Advanced Semiconductor Engineering, Inc. Semiconductor package having a waveguide antenna and manufacturing method thereof
US20140264808A1 (en) * 2013-03-15 2014-09-18 Andreas Wolter Chip arrangements, chip packages, and a method for manufacturing a chip arrangement
WO2014149926A1 (en) 2013-03-15 2014-09-25 X-Card Holdings, Llc Methods of making a core layer for an information carrying card, and resulting products
US9070423B2 (en) 2013-06-11 2015-06-30 Invensas Corporation Single package dual channel memory with co-support
CN103400825B (zh) 2013-07-31 2016-05-18 日月光半导体制造股份有限公司 半导体封装件及其制造方法
US9123555B2 (en) 2013-10-25 2015-09-01 Invensas Corporation Co-support for XFD packaging
US9698079B2 (en) 2014-01-03 2017-07-04 Taiwan Semiconductor Manufacturing Company, Ltd. Barrier structures between external electrical connectors
US9646917B2 (en) 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
US9281296B2 (en) 2014-07-31 2016-03-08 Invensas Corporation Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design
US20160064299A1 (en) * 2014-08-29 2016-03-03 Nishant Lakhera Structure and method to minimize warpage of packaged semiconductor devices
US9691437B2 (en) 2014-09-25 2017-06-27 Invensas Corporation Compact microelectronic assembly having reduced spacing between controller and memory packages
CN104673108B (zh) * 2015-03-19 2016-09-14 中国电子科技集团公司第四十四研究所 在封闭壳体内设置绝缘胶的方法
US9484080B1 (en) 2015-11-09 2016-11-01 Invensas Corporation High-bandwidth memory application with controlled impedance loading
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US20170263565A1 (en) * 2016-03-14 2017-09-14 Stmicroelectronics Pte Ltd Integrated circuit (ic) package with a grounded electrically conductive shield layer and associated methods
US9679613B1 (en) 2016-05-06 2017-06-13 Invensas Corporation TFD I/O partition for high-speed, high-density applications
TWI646641B (zh) * 2016-08-24 2019-01-01 同欣電子工業股份有限公司 Waterproof package module and waterproof packaging process
US10199356B2 (en) 2017-02-24 2019-02-05 Micron Technology, Inc. Semiconductor device assembles with electrically functional heat transfer structures
US10090282B1 (en) 2017-06-13 2018-10-02 Micron Technology, Inc. Semiconductor device assemblies with lids including circuit elements
US10096576B1 (en) 2017-06-13 2018-10-09 Micron Technology, Inc. Semiconductor device assemblies with annular interposers
US10681814B2 (en) * 2017-09-08 2020-06-09 Kemet Electronics Corporation High density multi-component packages
JP6905438B2 (ja) 2017-09-22 2021-07-21 株式会社フジクラ 無線通信モジュール
RU2659726C1 (ru) * 2017-10-05 2018-07-03 Российская Федерация, от имени которой выступает Государственная корпорация по космической деятельности "РОСКОСМОС" Микромодуль
CN109727530A (zh) * 2017-10-31 2019-05-07 昆山工研院新型平板显示技术中心有限公司 柔性显示模组及柔性显示模组制备方法
US11211369B2 (en) * 2018-03-05 2021-12-28 Octavo Systems Llc Service module for SIP devices
EP3762871A4 (en) 2018-03-07 2021-11-10 X-Card Holdings, LLC METAL CARD
US10763203B1 (en) * 2019-02-08 2020-09-01 Nxp B.V. Conductive trace design for smart card
US11222855B2 (en) 2019-09-05 2022-01-11 Skyworks Solutions, Inc. Moisture barrier for bond pads and integrated circuit having the same
KR20220062192A (ko) * 2020-11-06 2022-05-16 삼성디스플레이 주식회사 기판 적층 구조 및 기판 절단 방법

Family Cites Families (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3555364A (en) 1968-01-31 1971-01-12 Drexel Inst Of Technology Microelectronic modules and assemblies
US4734825A (en) 1986-09-05 1988-03-29 Motorola Inc. Integrated circuit stackable package
US5192716A (en) 1989-01-25 1993-03-09 Polylithics, Inc. Method of making a extended integration semiconductor structure
US5148266A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies having interposer and flexible lead
US5148265A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies with fan-in leads
US5043794A (en) 1990-09-24 1991-08-27 At&T Bell Laboratories Integrated circuit package and compact assemblies thereof
US5679977A (en) 1990-09-24 1997-10-21 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US5172303A (en) 1990-11-23 1992-12-15 Motorola, Inc. Electronic component assembly
JP3004071B2 (ja) 1991-04-16 2000-01-31 日本特殊陶業株式会社 集積回路用パッケージ
US5367764A (en) 1991-12-31 1994-11-29 Tessera, Inc. Method of making a multi-layer circuit assembly
US5282312A (en) 1991-12-31 1994-02-01 Tessera, Inc. Multi-layer circuit construction methods with customization features
US5483421A (en) * 1992-03-09 1996-01-09 International Business Machines Corporation IC chip attachment
JP3105089B2 (ja) 1992-09-11 2000-10-30 株式会社東芝 半導体装置
US5371654A (en) 1992-10-19 1994-12-06 International Business Machines Corporation Three dimensional high performance interconnection package
US5375041A (en) 1992-12-02 1994-12-20 Intel Corporation Ra-tab array bump tab tape based I.C. package
WO1994018701A1 (en) * 1993-02-05 1994-08-18 W.L. Gore & Associates, Inc. Stress-resistant semiconductor chip-circuit board interconnect
US5548091A (en) 1993-10-26 1996-08-20 Tessera, Inc. Semiconductor chip connection components with adhesives and methods for bonding to the chip
US5386341A (en) 1993-11-01 1995-01-31 Motorola, Inc. Flexible substrate folded in a U-shape with a rigidizer plate located in the notch of the U-shape
US5455390A (en) 1994-02-01 1995-10-03 Tessera, Inc. Microelectronics unit mounting with multiple lead bonding
US5734555A (en) 1994-03-30 1998-03-31 Intel Corporation Shared socket multi-chip module and/or piggyback pin grid array package
JPH088389A (ja) 1994-04-20 1996-01-12 Fujitsu Ltd 半導体装置及び半導体装置ユニット
MY112145A (en) 1994-07-11 2001-04-30 Ibm Direct attachment of heat sink attached directly to flip chip using flexible epoxy
US5665473A (en) * 1994-09-16 1997-09-09 Tokuyama Corporation Package for mounting a semiconductor device
US5915170A (en) 1994-09-20 1999-06-22 Tessera, Inc. Multiple part compliant interface for packaging of a semiconductor chip and method therefor
US5929517A (en) 1994-12-29 1999-07-27 Tessera, Inc. Compliant integrated circuit package and method of fabricating the same
US5783870A (en) 1995-03-16 1998-07-21 National Semiconductor Corporation Method for connecting packages of a stacked ball grid array structure
US5777379A (en) 1995-08-18 1998-07-07 Tessera, Inc. Semiconductor assemblies with reinforced peripheral regions
US5861666A (en) 1995-08-30 1999-01-19 Tessera, Inc. Stacked chip assembly
TW353223B (en) 1995-10-10 1999-02-21 Acc Microelectronics Corp Semiconductor board providing high signal pin utilization
US5798564A (en) 1995-12-21 1998-08-25 Texas Instruments Incorporated Multiple chip module apparatus having dual sided substrate
AU5720998A (en) 1996-12-13 1998-07-03 Tessera, Inc. Electrical connection with inwardly deformable contacts
WO1998044564A1 (en) 1997-04-02 1998-10-08 Tessera, Inc. Chip with internal signal routing in external element
RU2133523C1 (ru) 1997-11-03 1999-07-20 Закрытое акционерное общество "Техно-ТМ" Трехмерный электронный модуль
US5901041A (en) 1997-12-02 1999-05-04 Northern Telecom Limited Flexible integrated circuit package
US5926369A (en) 1998-01-22 1999-07-20 International Business Machines Corporation Vertically integrated multi-chip circuit package with heat-sink support
US6108210A (en) * 1998-04-24 2000-08-22 Amerasia International Technology, Inc. Flip chip devices with flexible conductive adhesive

Cited By (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1868048B (zh) * 2003-09-09 2011-06-01 菲科公司 使用柔性压力元件来密封电子部件的方法和装置
CN100461994C (zh) * 2005-05-25 2009-02-11 财团法人工业技术研究院 热增益型薄型化电子构装
US10128216B2 (en) 2010-07-19 2018-11-13 Tessera, Inc. Stackable molded microelectronic packages
CN102593046A (zh) * 2010-12-22 2012-07-18 通用电气公司 制造半导体器件封装件的方法
CN102593046B (zh) * 2010-12-22 2015-08-26 通用电气公司 制造半导体器件封装件的方法
US10062661B2 (en) 2011-05-03 2018-08-28 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US10593643B2 (en) 2011-05-03 2020-03-17 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US11424211B2 (en) 2011-05-03 2022-08-23 Tessera Llc Package-on-package assembly with wire bonds to encapsulation surface
US10756049B2 (en) 2011-10-17 2020-08-25 Invensas Corporation Package-on-package assembly with wire bond vias
US11735563B2 (en) 2011-10-17 2023-08-22 Invensas Llc Package-on-package assembly with wire bond vias
US11189595B2 (en) 2011-10-17 2021-11-30 Invensas Corporation Package-on-package assembly with wire bond vias
US9761558B2 (en) 2011-10-17 2017-09-12 Invensas Corporation Package-on-package assembly with wire bond vias
US9842745B2 (en) 2012-02-17 2017-12-12 Invensas Corporation Heat spreading substrate with embedded interconnects
US9691679B2 (en) 2012-02-24 2017-06-27 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US10510659B2 (en) 2012-05-22 2019-12-17 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9953914B2 (en) 2012-05-22 2018-04-24 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US10170412B2 (en) 2012-05-22 2019-01-01 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
CN102751204A (zh) * 2012-07-16 2012-10-24 江阴长电先进封装有限公司 一种扇出型圆片级芯片封装方法
CN102751204B (zh) * 2012-07-16 2014-10-15 江阴长电先进封装有限公司 一种扇出型圆片级芯片封装方法
CN104685624A (zh) * 2012-07-31 2015-06-03 英帆萨斯公司 重组晶圆级微电子封装
US9917073B2 (en) 2012-07-31 2018-03-13 Invensas Corporation Reconstituted wafer-level package dram with conductive interconnects formed in encapsulant at periphery of the package
CN104685624B (zh) * 2012-07-31 2018-02-02 英帆萨斯公司 重组晶圆级微电子封装
US10297582B2 (en) 2012-08-03 2019-05-21 Invensas Corporation BVA interposer
US10460958B2 (en) 2013-08-07 2019-10-29 Invensas Corporation Method of manufacturing embedded packaging with preformed vias
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US10008477B2 (en) 2013-09-16 2018-06-26 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US10629567B2 (en) 2013-11-22 2020-04-21 Invensas Corporation Multiple plated via arrays of different wire heights on same substrate
USRE49987E1 (en) 2013-11-22 2024-05-28 Invensas Llc Multiple plated via arrays of different wire heights on a same substrate
US9728527B2 (en) 2013-11-22 2017-08-08 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US10026717B2 (en) 2013-11-22 2018-07-17 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9852969B2 (en) 2013-11-22 2017-12-26 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US10290613B2 (en) 2013-11-22 2019-05-14 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9837330B2 (en) 2014-01-17 2017-12-05 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US11990382B2 (en) 2014-01-17 2024-05-21 Adeia Semiconductor Technologies Llc Fine pitch BVA using reconstituted wafer with area array accessible for testing
US11404338B2 (en) 2014-01-17 2022-08-02 Invensas Corporation Fine pitch bva using reconstituted wafer with area array accessible for testing
US10529636B2 (en) 2014-01-17 2020-01-07 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
CN104392969A (zh) * 2014-10-13 2015-03-04 华东光电集成器件研究所 一种多芯片集成电路抗冲击封装结构
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US10806036B2 (en) 2015-03-05 2020-10-13 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US10008469B2 (en) 2015-04-30 2018-06-26 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US10115678B2 (en) 2015-10-12 2018-10-30 Invensas Corporation Wire bond wires for interference shielding
US11462483B2 (en) 2015-10-12 2022-10-04 Invensas Llc Wire bond wires for interference shielding
US10559537B2 (en) 2015-10-12 2020-02-11 Invensas Corporation Wire bond wires for interference shielding
US9812402B2 (en) 2015-10-12 2017-11-07 Invensas Corporation Wire bond wires for interference shielding
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US10043779B2 (en) 2015-11-17 2018-08-07 Invensas Corporation Packaged microelectronic device for a package-on-package device
US10325877B2 (en) 2015-12-30 2019-06-18 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
CN108885708A (zh) * 2016-03-24 2018-11-23 维普公司 制造智能卡的方法
US10658302B2 (en) 2016-07-29 2020-05-19 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
CN110194435A (zh) * 2018-02-26 2019-09-03 Tdk电子股份有限公司 电子设备

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