CN1381889A - 集成电路封装及其制作工艺 - Google Patents

集成电路封装及其制作工艺 Download PDF

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CN1381889A
CN1381889A CN02120367A CN02120367A CN1381889A CN 1381889 A CN1381889 A CN 1381889A CN 02120367 A CN02120367 A CN 02120367A CN 02120367 A CN02120367 A CN 02120367A CN 1381889 A CN1381889 A CN 1381889A
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chip
integrated circuit
encapsulation
substrate
layer
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CN100389494C (zh
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陈国祚
宫振越
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Via Technologies Inc
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Abstract

一种集成电路(Integrated Circuit,IC)封装及其制作工艺,其特征在于将芯片贴附于基板的表面,或者贴附于一凹陷于基板表层、至少一图案化线路层及多个填充有导电材料的贯孔,使芯片的主动表面上的焊垫可经过贯孔与图案化线路层相电性连接。当应用于球格数组式(Ball Grid Array,BGA)封装时,更可将多个焊球分别配置于图案化线路层的多个焊球垫上,使得芯片可依序透过增层电路层的线路层及焊球,而与外界相电性连接。

Description

集成电路封装及其制作工艺
技术领域
本发明是有关于一种集成电路(Integrated Circuit，IC)封装及其制作工艺，且特别是有关于一种以增层电路(Build-Up Circuit)取代公知的基板(Substrate)的集成电路封装及其制作工艺。
背景技术
近年来，随着电子技术的日新月异，高科技电子产业的相继问世，使得更人性化、功能更佳的电子产品不断地推陈出新。然而各种产品无不朝向轻、薄、短、小的趋势设计，以提供更便利的使用。电子产品的制造一直到完成，集成电路(IC)封装扮演着相当重要的角色，而集成电路(IC)封装的型态有多种，比如是双边引脚封装(DualIn-line Package，DIP)的形式、球格数组(Ball Grid Array，BGA)的封装形式、贴带自动接合(Tape Automatic Bonding)封装形式等，每种封装形式均具有其特殊性。
球格数组式(Ball Grid Array，BGA)封装利用焊球(Solder Ball)布满整个基板(Substrate)的底面积的方式，来取代传统的金属导线架(Lead frame)的引脚。其以打线(Wire Bonding)或覆晶(Flip Chip)的方式，将芯片的接点连接至基板上的接点，并利用基板的内部绕线将接点分散至基板表面，再通过导孔(via)连接到基板底面，最后将焊球分别植接(Planting)基板底面的接点。由于球格数组式封装可利用整个基板的底面积作为接点的布置，故具有高脚数(High PinCount)的优势。此外，在回焊(Reflow)作业时，焊球熔解后的表面张力可产生自我校准(Self Alignment)的现象，故焊球的对位精度要求不高，再加上接合强度好、优良的电气特性，使得球格数组式封装成为目前集成电路(IC)封装的主流之一。
请参考图1，其为公知的一种球格数组式封装的剖面图。球格数组式封装100将芯片200的背面贴附于基板110之上，并以打线(WireBonding)方式所形成的导线120，使得芯片200的焊垫(die pad)202与基板110的接点112相电性连接，接着以封装材料130包覆芯片200、导线120及接点112，再分别将焊球(solder ball)140植接于基板110的焊球垫114上，使得芯片200可依序透过导线120、基板110的内部线路116及焊球140，而与外界电路相电性连接。
另请参考图2，其为公知的另一种球格数组式封装的剖面图。与图1不同的是，球格数组式封装101利用覆晶(Flip Chip，F/C)的方式，先分别在芯片200的焊垫202上形成凸块(bump)204，并以凸块204直接接合于基板110的接点112，使得芯片200可依序透过凸块204、基板110的内部线路116及焊球140，而与外界电路相电性连接。
然而，公知的球格数组式封装中，若利用导线(wire)来连接芯片的焊垫至基板的接点，由于导线的电性阻抗(impedance)较高，将造成信号的时间延迟(time delay of signals)而降低芯片的性能(performance)。此外，若以覆晶的方式来连接芯片的焊垫至基板的接点，则必须额外在芯片的焊垫上形成凸块，并与基板的接点精确对位后相接合，如此将增加制作工艺步骤，而提高制造成本。
另外，在球格数组式封装中，由于欲封装的芯片均属于高脚数的芯片，因此无论是利用打线的方式，或是以覆晶的方式来电性连接芯片焊垫与基板的接点，均须使用具有微间距(Fine Pitch)接点的基板，才能符合高脚数芯片的要求。传统印刷电路板(Printed Circuit Board，PCB)的线宽(trace width)约为100微米，而接点与接点的间距(pitch)约为800～1200微米之间，然而，球格数组式封装所使用的微间距接点的基板，其线宽约为30微米，而焊垫与焊垫的间距约为150微米。因此与传统印刷电路板相较之下，此类微间距接点的基板制造成本较高，约略占球格数组式封装制造成本的至少二成以上，而适用于覆晶的封装基板其制造成本则更加昂贵。
发明内容
本发明的目的在于提供一种集成电路封装及其制作工艺，其可省略公知的基板及其与芯片之间的连接制作工艺，例如打线或覆晶制作工艺，同时符合原先应用于基板的接点间距，故可降低集成电路的封装成本，并可大幅提升芯片的运作效能，以及加速封装结构的散热速率。此外，在没有覆晶凸块的局限之下，芯片的运作效能将更容易提升。
基于本发明的目的，本发明提供一种集成电路封装，具有一基板及至少一芯片，其中芯片的背面贴附于基板之上，且芯片的主动表面(Active Surface)具有多个焊垫。此外，此封装还包括一增层电路层，其形成于基板之上，增层电路层具有至少一绝缘层、至少一图案化线路层及多个贯孔，其中绝缘层位于该主动表面及该图案化线路层之间，并且贯孔分别对应焊垫而贯穿绝缘层，并以导电材质填充于贯孔之中，而图案化线路层则透过导电材质与芯片的焊垫相电性连接。当本发明的集成电路封装应用于球格数组式封装时，上述的图案化线路层则更具有多个焊球垫，此外，此封装更在图案化线路层上配置有一保护层，其中保护层具有多个开口，用以分别暴露出图案化线路层的焊球垫，另外，此封装更可在上述的焊球垫上分别配置焊球。
为让本发明的上述目的、特征和优点能够明显易懂，下文特举一较佳实施例，并配合所附图标，作详细说明。
附图说明
图1为公知的一种球格数组式封装的剖面图；
图2为公知的另一种球格数组式封装的剖面图；
图3A～3I依序为本发明的较佳实施例的集成电路封装的流程剖面图；
图4A、图4B为形成导电材质及线路层的流程剖面图；
图5A、图5B为形成线路层的流程剖面图；
图6为本发明的较佳实施例的一种集成电路封装，其具有内部电路的基板的剖面图；
图7为本发明的较佳实施例的另一种集成电路封装，其具有平面型基板的剖面图。标号说明：
100、101：球格数组式封装              110：基板
112：接点                             114：焊球垫
116：内部线路                         120：导线
130：封装材料                         140：焊球
200：芯片                             202：焊垫
204：凸块
300、301：集成电路封装                310：基板
312：表面                             314：凹穴
316：内部线路                         320：绝缘层
322：贯孔                             330：薄金属层
340：金属层                           342：线路层
344：填充部                           346：焊球垫
348：导电材质                         350：保护层
360：焊球                             400：芯片
402：主动表面                         404：背面
406：焊垫                             408：粘胶
501：光阻层                           503：线路层
505：电容
具体实施方式
请参考图3A～图3I，其依序为本发明的较佳实施例的集成电路封装的流程图。如图3A所示，首先提供一基板310，其表面可选择性地具有一凹穴314，而凹穴314位于基板310上，并凹陷于基板310的表面312，此凹穴314的位置不限定位于基板310的正中央。此外，芯片400具有一主动表面402及对应的一背面404，并以其背面404贴附于凹穴314的底部，但芯片400的位置不限于在凹穴314的底部，也可位于基板310的表面312，并暴露出芯片400的主动表面402，而芯片400的主动表面(Active Surface)402则具有多个焊垫406，用以作为信号输出入接点，其中主动表面402乃是指芯片400的具有器件(device)的一面。另外，芯片400的贴附方式可以利用粘胶(paste)408粘贴于凹穴314的底部，其中粘胶408包括可导电的粘着物质，如银胶(silver paste)或导电胶，或者是以非导电性的粘着物质，如粘贴带(adhesive tape)取代粘胶408，而将芯片400贴附于凹穴314的底部。
如图3B所示，将芯片400贴附于基板310之后，接着形成一绝缘层320于基板310及芯片400之上，同时部分绝缘层320将被填充于芯片400及凹穴314之间，而形成绝缘层320的方法包括以旋转涂布(Spin Coating)、网版印刷(Screen Printing)及滚压涂布(RollerCoating)等方式，且绝缘层320的材质则包括感光介质(Photo-Imageable Dielectric，PID)、玻璃(glass)、树脂(resin)或其它可固化的材质。接着，如图3C所示，在形成绝缘层320之后，形成多个贯孔322于绝缘层320之中，用以暴露出芯片400的焊垫406，其中形成贯孔(via)322的方法则包括感光成孔(Photo-Via)、雷射烧孔(Laser Ablation)及等离子蚀孔(Plasma Etching)等方式。
如图3D所示，在绝缘层320及焊垫406之上，全面性形成一薄金属层330，用以作为电镀(Electroplating)用的种子层(Seed Layer)，例如以化学铜形成一铜箔层作为薄金属层330。接着，如图3E所示，例如以电镀的方式，全面性形成一金属层340于薄金属层330之上，同时填充贯孔322。之后，如图3F所示，将金属层340予以平坦化，此时金属层340可约略分成线路层342及填充部344，其中填充部344填满贯孔322，而将金属层340予以平坦化的方法则可以利用化学机械研磨(Chemical Mechanical Polishing，CMP)的方式。在表面平整度要求不高的情况下，此平坦化的流程可以省略。
如图3G所示，接着例如以微影蚀刻的方式，移除部分线路层342，通过图案化线路层342，使得图案化的线路层342及绝缘层320构成增层电路层(Build-up Circuit)370，并可重复上述步骤而形成多层增层电路层370，以符合所需的绕线布局设计。在非球格数组式封装时(例如形成的导线接脚直接与具有导线的胶卷型导线(Tape)以导电胶接合)则可省略保护层、焊球垫及焊球制作工艺。当集成电路封装300应用于球格数组式封装时，则如图3H所示，可利用网版印刷、涂布后微影(Photolithography)或是其它的方式，形成一图案化的保护层，例如一焊罩层(Solder Mask)，材质比如为防焊绿漆，用以暴露出部分线路层342而形成焊球垫346。再如图3I所示，分别将焊球360植接(Planting)在对应的焊球垫346上，而完成球格数组式的集成电路封装300。
如图3G所示，芯片400的背面404，在与基板310贴合时，虽力求与粘胶410对齐，但不必然要对齐，绝缘层320在未贯孔的部分及金属层340的表面，虽然保持平整对后续制作工艺较为有利，但也不必然都是平整的。再如图3I所示，焊球360的间距不必然是固定值，可依实际需要而调整，且线路层342可在芯片400的主动表面402与基板310的表面312间自由延伸。
如图3F所示，在制作工艺上，除了形成金属层340以作为线路层342及填充部344之外，也可利用两道制作工艺，将线路层342及填充部344分两次制作。因此，我们可以在图3D所示的制作工艺完成后，也就是在形成薄金属层330于绝缘层320及焊垫406上之后，可以如图4A所示，将一导电材质348填入贯孔322之中，其作用与图3F的金属层340的填充部344相同，而填入的方式可以使用网版印刷，至于导电材质348则可以运用导电胶，例如银胶、铜胶等。接着，如图4B所示，再全面性形成一线路层342于薄金属层330及导电材质348之上，而形成线路层342的方法可以使用电镀，此后的制作工艺步骤则与图3G～3I相同，于此不再重复赘述。
如图3G所示，形成线路层342的方法，可由图3D的步骤，先涂布上一光阻层501，并可以利用曝光及显影的方式来图案化此光阻层501，如图5A所示。接着，再以电镀的方式，在没有光阻的部分长出线路层503，如图5B所示。接着，移除光阻层50l，并加以短暂金属蚀刻，将光阻层501下的薄导电层330去除，即可得到图3G的图案化的线路层342，而此后的制作工艺步骤，同样如图3H～3I所示，于此不在重复赘述。
请参考图3I，基板310的材质可包括金属、玻璃及高分子聚合物(polymer)或其它材料。由于芯片400于运作时会产生高热，因此，当基板310的材质为金属或导热性佳的材料时，将可增加芯片400的导热散热速率，以提升芯片400的运作效能。另请参考图6，其为具有内部线路的基板的集成电路封装的剖面图。基板310也可具有一内部线路316，并可通过增加填充部344的设计，使得基板310的内部线路316可经过填充部344’，而电性连接芯片400的焊垫406或图案化的线路层342，因而使得球格式数组的集成电路封装301的绕线设计将具有更大的弹性空间。
此外，可于图3H之后，重复图3C～图3H的制作工艺，则可制作多层线路层342-1、342-2的电路，而此多出的线路层342-2，除了可使设计自由度变大之外，也可作为接地或电源平面，或于平面间产生电容505，用以作为调整产品的电特性之用。
请参考图7，其为本发明的较佳实施例的另一种具有集成电路封装，其具有平面型基板的剖面图。与图6相较之下，两者最主要的差别在于绝缘层320-1在芯片400的表面402与基板310的表面312的厚度不相同，其它的部分则类似，于此不再详述。此外，若选择绝缘层320厚度在芯片400的表面402与基板310的表面312相同时，则同样可以调整线路层342-1的厚度，或提高绝缘层320-1以上各层的平整度。
本发明的集成电路封装的特征先将芯片贴附于基板的凹穴底部或基板的表面，接着在基底及芯片上直接形成增层电路层，并将焊球配置于增层电路层的线路层的焊球垫，使得芯片得以依序透过增层电路层的内部绕线及焊球，而与外界相电性连接。
承上所述，当本发明的集成电路封装应用于球格数组式封装时，将可省略公知的球格数组式封装所需的具有微间距接点的基板，并可省略第一层级(Level 1)的电子构装，即以打线制作工艺或覆晶制作工艺，将芯片连接至封装基板的层级的封装，而直接以增层电路层的内部绕线直接连接芯片的焊垫及焊球，故可大幅降低导线连接或凸块连接所产生的较高的电性阻抗，而有助于提升芯片的运作效能。
综上所述，本发明的集成电路封装具有下列优点：
(1)本发明的集成电路封装将高密度的芯片焊垫直接以线路层延伸至芯片以外的区域，以直接做出可大到印刷电路板的焊垫(或焊球)的焊点间隔，可直接取代高脚数芯片的封装，故可大幅降低封装成本。
(2)本发明的集成电路封装在芯片上直接形成至少一增层电路层，在无须应用公知的具有微间距接点的基板之下，同样可制作出符合原先焊点的分布位置的集成电路封装。
(3)本发明的集成电路封装以其增层电路层取代公知的具有微间距接点的基板，因而省略公知成本较高的基板及其组装制作工艺，故可降低芯片的封装成本。
(4)本发明的集成电路封装直接以增层电路层的内部绕线直接连接芯片的焊垫及焊球，故可大幅降低例如打金线连接或凸块连接所产生的较高的电性阻抗，而有助于提升芯片的运作效能。
(5)当本发明的集成电路封装选用金属或导热性佳的材质作为容纳芯片的基板的材质时，由于基板以其凹穴包覆于芯片的外围，故有助于增加芯片的散热的效率，进而提升芯片的运作效能。若选用金属时，不但具上述的优点，且对于电磁干扰(Electro-MagneticInterference，EMI)的遮蔽效果甚佳，同时可利用此金属材质的基板作为接地功能，进而增进整体封装性能。
(6)本发明的集成电路封装可选用具有内部线路的基板，并将内部线路电性连接芯片的焊垫或增层电路层的线路层，使得集成电路封装的绕线设计将具有更大的弹性空间。
(7)本发明的集成电路封装的制作工艺可对单一晶粒进行增层线路的制作，也可以大面积的基板上同时粘着大量晶粒完成的器件(set)进行制作工艺处理，以大幅降低生产成本。
虽然本发明已以一较佳实施例公开如上，然其并非用以限定本发明，任何熟悉此技术者，在不脱离本发明的精神和范围内，当可作些许之更动与润饰，因此本发明的保护范围当视权利要求书为准。

Claims (30)

1、一种集成电路封装，其特征在于：至少包括：
一基板，具有一第一面；
至少一芯片，具有一主动表面及对应的一背面，其中该芯片以该背面贴附于该基板的该第一面，且该芯片更具有复数个焊垫，其为于该芯片的该主动表面；
一增层电路层，配置于该基板之上，该增层电路层具有至少一绝缘层、至少一图案化线路层及复数个贯孔，其中该绝缘层位于该主动表面及该图案化线路层之间，而该些贯孔分别对应该些焊垫而贯穿该绝缘层，且该些贯孔之中具有一导电材质，而该图案化线路层以该导电材质与该些焊垫相电性连接，且部分该图案化线路层延伸至该芯片的该主动表面上方以外的区域。
2、如权利要求1所述的集成电路封装，其特征在于：其中部分该绝缘层填充于该芯片及该基板之间。
3、如权利要求1所述的集成电路封装，其特征在于：其中该图案化线路层更具有复数个焊球垫，且该集成电路封装更包括复数个焊球，其分别配置于该些焊球垫之上。
4、如权利要求3所述的集成电路封装，其特征在于：更包括图案化的一保护层，其配置于该图案化线路层之上，且该保护层具有复数个开口，其分别暴露出该些焊球垫。
5、如权利要求1所述的集成电路封装，其特征在于：其中该绝缘层的材质包括感光介质、玻璃、树脂及可固化材料其中之一。
6、如权利要求1所述的集成电路封装，其特征在于：其中该基板更具有一内部线路。
7、如权利要求6所述的集成电路封装，其特征在于：其中该内部线路与该芯片的该些焊垫相电性连接。
8、一种集成电路封装的制作工艺，其特征在于：至少包括：
提供一基板，该基板具有一第一面；
提供至少一芯片，该芯片具有一主动表面及一背面，其中该芯片以该背面贴附于该基板的该第一面，且该芯片更具有复数个焊垫，其位于该芯片的该主动表面；
形成一增层电路层于该基板之上，其中该增层电路层具有至少一绝缘层、至少一图案化线路层及复数个贯孔，其中该绝缘层位于该主动表面及该图案化线路层之间，而该些贯孔分别对应该些焊垫而贯穿该绝缘层，且该些贯孔之中具有一导电材质，而该图案化线路层以该导电材质与该些焊垫相电性连接，且部分该图案化线路层延伸至该芯片的该主动表面上方以外的区域。
9、如权利要求8所述的集成电路封装的制作工艺，其特征在于：其中部分该绝缘层填充于该芯片及该基板之间。
10、如权利要求8所述的集成电路封装的制作工艺，其特征在于：还包括形成复数个焊球垫于该图案化线路层上。
11、如权利要求10所述的集成电路封装的制作工艺，其特征在于：还包括分别形成数个焊球于该些焊球垫上。
12、如权利要求8所述的集成电路封装的制作工艺，其特征在于：其中该绝缘层的材质包括感光介质、玻璃及树脂其中之一。
13、如权利要求8所述的集成电路封装的制作工艺，其特征在于：其中该基板还具有一内部电路。
14、如权利要求13所述的集成电路封装的制作工艺，其特征在于：其中该内部电路至少与该芯片的该些焊垫的一相电性连接。
15、一种集成电路封装，其特征在于：至少包括：
一基板，具有一第一面及至少一凹穴，其中该凹穴凹陷于该基板的该第一面；
至少一芯片，具有一主动表面及对应的一背面，其中该芯片以该背面贴附于该凹穴的底部，且该芯片更具有复数个焊垫，其为于该芯片的该主动表面；
一增层电路层，配置于该基板之上，该增层电路层具有至少一绝缘层、至少一图案化线路层及复数个贯孔，其中该绝缘层位于该主动表面及该图案化线路层之间，而该些贯孔分别对应该些焊垫而贯穿该绝缘层，且该些贯孔之中具有一导电材质，而该图案化线路层以该导电材质与该些焊垫相电性连接，且部分该图案化线路层延伸至该芯片的该主动表面上方以外的区域。
16、如权利要求15所述的集成电路封装，其特征在于：其中部分该绝缘层填充于该芯片及该凹穴之间。
17、如权利要求15所述的集成电路封装，其特征在于：其中部分该绝缘层填充于该芯片及该基板之间。
18、如权利要求15所述的集成电路封装，其特征在于：其中该图案化线路层更具有复数个焊球垫，且该集成电路封装更包括复数个焊球，其分别配置于该些焊球垫之上。
19、如权利要求18所述的集成电路封装，其特征在于：更包括图案化一保护层，其配置于该图案化线路层之上，且该保护层具有复数个开口，其分别暴露出该些焊球垫。
20、如权利要求15所述的集成电路封装，其特征在于：其中该绝缘层的材质包括感光介质、玻璃、树脂及可固化材料其中之一。
21、如权利要求15所述的集成电路封装，其特征在于：其中该基板更具有一内部线路。
22、如权利要求21所述的集成电路封装，其特征在于：其中该内部线路与该芯片的该些焊垫相电性连接。
23、一种集成电路封装的制作工艺，其特征在于：至少包括：
提供一基板，该基板具有一第一面及至少一凹穴，其中该凹穴凹陷于该基板的该第一面；
提供至少一芯片，该芯片具有一主动表面及一背面，其中该芯片以该背面贴附于该凹穴的底部，且该芯片更具有复数个焊垫，其位于该芯片的该主动表面；
形成一增层电路层于该基板之上，其中该增层电路层具有至少一绝缘层、至少一图案化线路层及复数个贯孔，其中该绝缘层位于该主动表面及该图案化线路层之间，而该些贯孔分别对应该些焊垫而贯穿该绝缘层，且该些贯孔之中具有一导电材质，而该图案化线路层以该导电材质与该些焊垫相电性连接，且部分该图案化线路层延伸至该芯片的该主动表面上方以外的区域。
24、如权利要求23所述的集成电路封装的制作工艺，其特征在于：还包括形成复数个焊球垫于该图案化线路层上。
25、如权利要求24所述的集成电路封装的制作工艺，其特征在于：还包括分别形成复数个焊球于该些焊球垫上。
26、如权利要求23所述的集成电路封装的制作工艺，其特征在于：其中部分该绝缘层填充于该芯片及该凹穴之间。
27、如权利要求23所述的集成电路封装的制作工艺，其持征在于：其中部分该绝缘层填充于该芯片及该基板之间。
28、如权利要求23所述的集成电路封装的制作工艺，其特征在于：其中该绝缘层的材质包括感光介质、玻璃及树脂其中之一。
29、如权利要求23所述的集成电路封装的制作工艺，其特征在于：其中该基板更具有一内部电路。
30、如权利要求29所述的集成电路封装的制作工艺，其特征在于：其中该内部电路至少与该芯片的该些焊垫的一相电性连接。
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